Journal of the Korean Physical Society, Vol. 38, No. 3, March 2001, pp.

220∼223

Application of Dynamic Pass-Transistor Logic to an 8-Bit Multiplier
Jong Duk Lee∗ , Yong Jin Yoon† , Kyoung Hwa Lee‡ and Byung-Gook Park
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, Seoul 151-742 (Received 12 April 2000) Dynamic pass-transistor logic (PTL), which combines pass-transistor logic with dynamic logic, is proposed for high-performance VLSI circuit design. The dynamic PTL holds the merits of fast evaluation characteristics as dynamic logic. Moreover, because a pre-charged scheme solves the weak logic ‘high’ problem of a static PTL, an additional level restoration circuit is not needed. An 8-bit multiplier is designed using dynamic PTL for the evaluation of its characteristics. The multiplier consists of a Booth’s partial product generator and a [4 : 2] compressor for a partial product reduction tree. For the comparison of performance, the multiplier is also designed using conventional static CMOS logic. An HSPICE simulation is carried out with the 0.25 µm CMOS device model parameters used in Samsung Electronics Co. From the simulation, the delay of multiplier is 206.2 psec, and the power consumption is 117.5 mW with a 3.3 V supply voltage, a 1 GHz operation and a 60 o C temperature. The results show that the multiplier designed by using dynamic PTL improves the speed by 2.5 times but consumes more power by 21 %; hence, the power delay product is improved by 50 % compared with a static CMOS.

I. INTRODUCTION Pass-transistor logic (PTL) was reported as another alternative logic that can enhance circuit performance [1]. Since PTL can propagate signals using both the source (or drain) and the gate, its high functionality can reduce the number of transistors in the critical path. As a PTL-based circuit can consist of only one type of MOS transistor (generally an nMOS transistor), it has a low node capacitance. As a result, PTL enables high-speed and low-power circuits. However, due to the threshold voltage drop, PTL has a weak logic ‘high’, so additional level restoration circuits are needed. As a result, the performance of PTL is degraded, and the circuit structure is more complicated. In this paper, a dynamic PTL that replaces the weak logic ’high’ with a pre-charged level is proposed. Because of the pre-charged scheme, dynamic PTL can operate without level restoration circuits, so the circuit performance can be improved. An 8-bit multiplier is designed using dynamic PTL, and the performance is verified by using an HSPICE simulation.
E-mail: jdlee@snu.ac.kr, Tel:+82-2-880-7268, Fax:+82-2-871-7323 † E-mail: mbyoon@smdl.snu.ac.kr, Tel:+82-2-880-7282, Fax:+82-2-871-7323 ‡ E-mail: keich@smdl.snu.ac.kr, Tel:+82-2-880-7282, Fax:+82-2-871-7323 -220∗

II. DESIGN USING DYNAMIC PASS-TRANSISTOR

Fig. 1. Two-input multiplexer circuit using (a) dynamic PTL scheme and (b) CPL. Dynamic PTL needs no level restoration.

there is a limit to reducing the number of transistors. (c) basic block by loop 2. LRS terminates its pre. Design of the multiplexer based Booth’s partial product generator. -221- Table 1. respectively. 3. Operation of multiplexer based partial product generator using Radix-4 Booth’s algorithm. 2. CPL is chosen because of its superior performance among the conventional static PTLs [2]. the ‘loop 1’ and ‘loop 2’ build basic transistor blocks of (b) and (c).charge state and it make the node enter into evaluation mode. III. a dynamic inverter is used. the logic function XOR using dynamic PTL is completed. However. 4. Local reset signal(LRS) generator for dynamic PTL. (b) basic block by loop 1. Additional level restoring circuits and a complementary output like CPL are not needed. Figure 1 shows the multiplexer circuit using dynamic PTL and complementary pass-transistor logic (CPL). because the DPL uses the same number of pMOS transistors as nMOS transistors. DESIGN OF 8-BIT MULTIPLIER USING Fig. Fig. The output nodes of dynamic PTL are pre-charged by a local reset (LRS) signal generated by the inputs and the system clock. By wiring these circuits simply. and (d) completed dynamic PTL 2. As shown in Figure 3. Example of minimized dynamic PTL implementation for 2-input XOR (a) loops on Karnough map. For the cascade connection of the dynamic PTL. Because the nMOS transistor of dynamic PTL operates only to discharge the nodes. For example to make XOR. When the input transits to ‘L’ from normal ‘H’ . there is no threshold voltage drop problem. One complementary inputs are logically dynamic ANDed with the system clock. DPL needs both nMOS transistors for neighbor ‘0’ group and pMOS transistors for neighbor ‘1’ group separately on the Karnaugh-map.input XOR. But dynamic PTL is looping only ‘0’ for nMOS transistor. The synthesis method of dynamic PTL is different from that of DPL. The inverter in the PTL scheme is necessary to de-couple the input/output signals and to re-generate the signal for every three or four pass transistors.Application of Dynamic Pass-Transistor Logic to an 8-bit Multiplier – Jong Duk Lee et al. . It needs four transistors to construct 2-input XOR. Multiplier Bit Pattern Bj+1 Bj Bj−1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Operation 0 A A 2A –2A –A –A 0 Patial Product 0 Ai Ai Ai−1 Ai−1 Ai Ai 1 Fig. Research on the synthesis of high speed PTL has been carried out using double pass-transistor logic (DPL) [3]. LRS generator circuit is displayed at Figure 2. and then they are discharged conditionally by input signals.

The compressed outputs. internal carries are not propagated to the next weight. the PPG selects a proper type of multiplicand A. the multiplexer-based PPG is illustrated. In this research [4 : 2] compressor scheme was chosen for the PPRT. 8. the fast reduction method is the key to high performance. AND-OR (A-O). By the skew of these signal pre-charged node may be discharged Fig. The input signals from previous pass transistor block may arrive at next block-PPRT. 38. Many papers report that a [4 : 2] compressor is the optimal leaf cell of a PPRT in the trade-off of design simplicity and wiring complexity [5]. Partial products may be reduced using one of the various compressor and counter Fig. DYNAMIC PTL The multiplier consists of a partial product generator (PPG) and a partial product reduction tree (PPRT). the multiplexer in the dotted region of Figure 4 is expressed by dynamic PTL. The pre-charge pMOS is not shown for simplicity in Figure 5. Therefore. The multiplexer-structured PPG has the merits that it generates partial products without Booth’s encoding circuits and can equalize the arrival times of all the partial products at the input of the next stage. 6. . Fig. fast reduction is possible. Partial product generator expressed by dynamic PTL. Because the internal output carry (‘CO’) is not a function of the input carry (‘CIN’) from the previous bit.-222- Journal of the Korean Physical Society. Negative partial products are made through 2’s complement. 3. Vol. Because a wider bit multiplier has a large partial product reduction tree (PPRT). Schematic diagram of the [4 : 2] compressor chosen for the multiplier.respectively. [4 : 2] compressor for the partial product reduction tree designed by using dynamic PTL. 5. and in figure 5. which consists of a 4-input XOR. Booth’s rule is arranged in Table 1. may become the inputs of the successive carry propagation adder or another compressor for the final multiplication results. schemes. In Figure 4. No. ‘X’ and ‘Y’. 7. OR-AND (O-A) and 2input multiplexer. Figure 6 shows the [4 : 2] compressor. Because the multiplexer structure is proper to PTL. According to the bit patterns of the multiplier B. the PPG is designed to generate a partial product through an 8 : 1 multiplexer under the rules of the radix-4 Booth’s algorithm [4]. Simulated delay of the 8-bit multiplier designed by using dynamic PTL and static CMOS logic. March 2001 Fig.

G. The power delay product is improved by 50 %. the dynamic PTL-based multiplier reveals a propagation delay of 206. REFERENCES [1] K. At a lower supply voltage of 2. and Sys.3 V 195. IV. Power (mW) 2.5 times faster than a static CMOS one. Flynn.5 V 3.2 602. Computer Arithmetic Algorithm (Prentice-Hall.05 48.0 nm / 0.5 V 3. The simulation of the 8-bit multiplier is carried out for dynamic PTL and static CMOS logic. ISRC-98-X-5505.2 nm / 0. respectively. on Computers 47. CONCLUSIONS Since dynamic PTL has the merits both of conventional PTL and dynamic logic. 1079 (1997). and high performance is expected. Logic Dynamic PTL Static CMOS Power (mV) 2. The delay and power consumption data for various supply voltages are summarized in Table 3.25 µm CMOS device model parameters used at Samsung Electronics Co. A. Dynamic PTL outperforms CPL both in power and delay. 32.5 V 3. Solid State Cir. Y. 792 (1996).input multiplexer designed by using dynamic PTL is verified through a simulation and is compared with static PTL-CPL. The dynamic PTL-based multiplier presents high performance compared with the static CMOS-based one. [3] V. 31.60 Time Delay (psec) 2.7 301.43 V and 6.47 1. 974 (1997). At a 3. IEEE J.33 117.3 V 103 87 127 109 -223- Dynamic PTL CPL Power × Delay (fJ) 2.3 V 20. ACKNOWLEDGMENTS This research was supported by a contract from the Inter-university Semiconductor Research Center to Samsung Electronics Co. Therefore. Because the dynamic PTL removes the overlap current through pMOS it has the fast evaluation characteristics of dynamic logic. An 8-bit multiplier that consists of a PPG and a PPRT is selected for evaluating the performance of dynamic PTL. The power delay product is improved by half.3 V 1. V. 1201 (1998). J.0 510. For preventing incorrect operation of the PPRT due to the skews of the PPG outputs the compressor is designed by pre-discharged dynamic PTL while the PPG is designed using a pre-charged dynamic PTL. which is verified using an HSPICE simulation.5 to a lower than VCC level. [5] H.99 Time Delay (psec) 2. Simulated results of the 8-bit multiplier designed by dynamic PTL with temperature of 60◦ and operation frequency of 1 GHz. The thickness of the gate oxide / threshold voltage of the pMOS and the nMOS are 6.5 times than the static CMOS.2 psec. Koren. a pre-discharge dynamic PTL with a dynamic inverter is also proposed.1 29.5 392.9 251. Simulated results of the 2-input multiplexer designed by dynamic PTL and CPL.7 Power × Delay (pJ) 2. Zimmermann and W. SIMULATION RESULTS An HSPICE simulation is carried out with the 0.4 206. IEEE Trans.90 3. 44. dynamic PTL is proved to be a highperformance circuit design logic. The detailed design of PPRT using the predischarged dynamic PTL scheme is illustrated in Figure 7. For a stable interface between the PPG and PPRT blocks. Al-Twaijary and M. the performance of the 2.28 96. Solid State Cir. it needs no additional restoration circuit. The results are depicted in Figure 8.7 24. the dynamic PTL-based multiplier consumes more power than a static CMOS one by 21%. The speed of the multiplier designed using dynamic PTL is faster by 2. Oklobdzija and B. First of all.3 V 290. IEEE J.3 V supply voltage. IEEE Trans.3 V 71. However.35 V. . Yano. [2] R.1 49. 1993). the improvement is decreased to 30 % because the effect of the threshold voltage drop in the pre-discharge scheme is more significant at low supply voltage. Sasaki. The simulation results are summarized in Table 2. Seki. on Cir. The dynamic PTL-based multiplexer improves both the power consumption and speed.5 V 3. Pre-discharge dynamic PTL scheme uses small discharging nMOSs to discharge the nodes by the LRS.-II: Analog and Digital Signal Processing. which is 2.5 V 3. Duchene. [4] I.Application of Dynamic Pass-Transistor Logic to an 8-bit Multiplier – Jong Duk Lee et al. Rikino and K.5 V.4 Table 3. under Grant No. Fichtner. Table 2.5 V 3.98 3. K.

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