L4

1/30/2009

PROGRAMMABLE LOGIC

1/30/2009

MZ-SED

L4/1

Why Programmable Logic?
• Facts:
– It is most economical to produce an IC in large volumes – Many designs required only small volumes of ICs

• Need an IC that can be:
– Produced in large volumes – Handle many designs required in small volumes

• A programmable logic part can be:
– made in large volumes – programmed to implement large numbers of different lowvolume designs

1/30/2009

MZ-SED

L4/2

Programmable Logic - More Advantages
• Many programmable logic devices are field-programmable, i. e., can be programmed outside of the manufacturing environment • Most programmable logic devices are erasable and reprogrammable.
– Allows “updating” a device or correction of errors – Allows reuse the device for a different design - the ultimate in re-usability! – Ideal for course laboratories

• Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs.
– Complete Intel Pentium designs were actually prototyped with specialized systems based on large numbers of VLSI programmable devices!

1/30/2009

MZ-SED

L4/3

MZ

1

Programming lost if chip power lost • Single-bit storage element – Non-Volatile • Erasable • Electrically erasable • Flash (as in Flash Memory) – Build lookup tables • Storage elements (as in a memory) – Transistor Switching Control • Stored charge on a floating transistor gate – Erasable – Electrically erasable – Flash (as in Flash Memory) • Storage elements (as in a memory) MZ-SED 1/30/2009 L4/6 MZ 2 .Cannot be erased and reprogrammed • Mask programming • Fuse • Antifuse Technology Characteristics • Reprogrammable – Volatile .L4 1/30/2009 Programming Technologies • Programming technologies are used to: – Control connections – Build lookup tables – Control transistor switching • The technologies – Control connections • • • • Mask programming Fuse Antifuse Single-bit storage element 1/30/2009 MZ-SED L4/4 Programming Technologies • The technologies (continued) – Build lookup tables • Storage elements (as in a memory) – Transistor Switching Control • Stored charge on a floating transistor gate – Erasable – Electrically erasable – Flash (as in Flash Memory) • Storage elements (as in a memory) 1/30/2009 MZ-SED L4/5 • Permanent .

a programmable array of AND gates feeding a programmable array of OR gates.L4 1/30/2009 Antifuse-Based FPGA antifuse polysilicon ONO dielectric n+ antifuse diffusion 2l Open by default.a fixed array of AND gates and a programmable array of OR gates • Programmable Array Logic (PAL) .a programmable array of AND gates feeding a fixed array of OR gates. closed by applying current pulse 1/30/2009 L4/7 MZ-SED Programmable Logic Array (PLA) x1 x2 xn Input buffers and inverters x1 x1 xn xn P1 AND plane OR plane Pk f1 fm General structure of a PLA 1/30/2009 MZ-SED L4/8 Programmable Configurations • Read Only Memory (ROM) .complex enough to be called “architectures” 1/30/2009 MZ-SED L4/9 MZ 3 . • Complex Programmable Logic Device (CPLD) /FieldProgrammable Gate Array (FPGA) . • Programmable Logic Array (PLA) .

– M output lines. • Fixed AND array with 2N outputs implementing all N-literal minterms. PAL and PLA Configurations Inputs Fixed AND array (decoder) Programmable Connections Programmable OR array Outputs 1/30/2009 (a) Programmable read-only memory (PROM) Inputs Programmable Connections Programmable AND array Fixed OR array Outputs (b) Programmable array logic (PAL) device Inputs Programmable Connections Programmable Programmable AND array Connections Programmable OR array Outputs (c) Programmable logic array (PLA) device 1/30/2009 MZ-SED L4/10 Array-Based Programmable Logic I5 I4 I3 I2 I1 I0 Programmable OR array I3 I2 I1 I0 Programmable OR array I5 I4 I3 I2 I1 I0 Fixed OR array Programmable AND array O 3O 2O 1O 0 Fixed AND array O3O2O1O0 Programmable AND array O 3O 2O 1O 0 PLA PROM Indicates programmable connection Indicates fixed connection PAL 1/30/2009 MZ-SED L4/11 Read Only Memory • Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have: – N input lines. and – 2N decoded minterms. 1/30/2009 MZ-SED L4/12 MZ 4 . • Programmable OR Array with M outputs lines to form up to M sum of minterm expressions.L4 ROM.

An “X” in the array corresponds to attaching the minterm to the OR • Read Example: For input (A2. no connection is made 1/30/2009 • Can be viewed as a memory with the inputs as addresses of data (output values). A0)? 1/30/2009 MZ-SED D7 D6 D5 D4 A2 D3 D2 A1 D1 A0 D0 X X X X X X X X X X F3 F2 F1 F0 L4/14 Programming a PROM 1 X2 X 1 X 0 : programmed node NA NA f1 f0 1/30/2009 MZ-SED L4/15 MZ 5 . • What are functions F3.F1. M= 4 output lines) • The fixed "AND" array is a “decoder” with 3 inputs and 8 outputs implementing minterms. a connection is made to the corresponding minterm for the corresponding output – If a 0.A0) = 011. F2 . F1 and F0 in terms of (A2.F0 ) = 0011. output is (F3. hence ROM or PROM names! 1/30/2009 MZ-SED L4/13 Read Only Memory Example • Example: A 8 X 4 ROM (N = 3 input lines.F2. A1. • The programmable "OR“ A array uses a single line to B represent all inputs to an C OR gate.L4 Read Only Memory • A program for a ROM or PROM is simply a multiple-output truth table – If a 1 entry.A1.

PAL may have too few inputs to the OR gates. adding POS functions – No multilevel circuit implementations in ROM (without external connections from output to input). 1/30/2009 • Advantages – For given internal complexity. 3-output PAL with fixed. a PAL can have larger N and M – Some PALs have outputs that can be complemented. having a programmable set of ANDs combined with fixed ORs.L4 Programmable Array Logic (PAL) • The PAL is the opposite of the ROM. PAL has outputs from OR terms as internal inputs to all AND terms. k macrocells 1/30/2009 MZ-SED MZ X X X X X X X X X F1 = A B + C F2 = A B C + AC + AB F3 = F4 = B F3 X X X XX X • 4-input. • Disadvantage – ROM guaranteed to implement any M functions of N inputs. 3-input OR terms • What are the equations for F1 through F4? 2 3 A F2 X Product 1 term X X X X F1 F4 L4/17 OUT macrocell L4/18 6 . j minterms/macrocell. making implementation of multi-level circuits easier. 1/30/2009 MZ-SED L4/16 Programmable Array Logic Example AND gates inputs 0 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 C 10 11 12 D 1/30/2009 MZ-SED 0 1 2 3 4 5 6 7 8 9 More Complex PAL programmable AND array (2 i 3 jk ) product terms k macrocells 1 j -wide OR array D Q j j CLK A B C i i inputs i inputs.

required – A PLA has all of its product terms connectable to all outputs. N. overcoming the problem of the limited inputs to the PAL Ors – Some PLAs have outputs that can be complemented. the product term count limits the application of a PLA. 3-output PLA with 4 product terms 1/30/2009 MZ-SED L4/21 MZ 7 . 1/30/2009 MZ-SED L4/20 Programmable Logic Array Example A B C X X 1 X X What are the equations for F1 & F2? Could the PLA implement the functions without the XOR gates? AB BC AC AB X X X X X 2 X Fuse blown Fuse intact X X 3 X X X 4 X C C B B AA 0 1 F1 F2 • 3-input. helping to fit it into a PLA. – Two-level multiple-output optimization is required to reduce the number of product terms in an implementation. adding POS functions 1/30/2009 1/30/2009 MZ-SED L4/19 Programmable Logic Array (PLA) • Disadvantages – Often. PLA requires external connections to do multi-level circuits.L4 Programmable Logic Array (PLA) • Compared to a ROM and a PAL. – Multi-level circuit capability available in PAL not available in PLA. • Advantages – A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs. a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs.

S6) 1/30/2009 MZ-SED f1 f2 L4/24 MZ 8 .+P6) MZ-SED f1 f2 L4/23 x1 x2 x3 x4 NOR plane VDD VDD S1 S2 S3 S4 S5 S6 NOR plane A NOR-NOR PLA used for product of sums (f = S1 S2….L4 PLA Implementation x2 x3 Programmable connections P1 OR plane 1/30/2009 x1 P2 P3 P4 AND plane 1/30/2009 Gate-level diagram of a PLA MZ-SED f1 f2 L4/22 x1 x2 x3 x4 NOR plane VDD VDD P1 P2 P3 P4 P5 P6 NOR plane 1/30/2009 A NOR-NOR PLA used for sum of products (f = P1 +P2+….

L4 x1 VDD P 1 P 2 P 3 P 4 P 5 P 6 NOR plane PAL programmed to implement the two functions of previous slide 1/30/2009 MZ-SED 1/30/2009 x2 x3 x4 f1 f2 L4/25 PLA Implementation (using programmable transistors) x1 x2 x3 NOR plane VDD VDD VDD S 1 VDD S 2 VDD S 3 NOR plane 1/30/2009 MZ-SED f1 f2 L4/26 Using EEPROM transistors to create a programmable plane x x x 1 2 n VDD S1 VDD S2 VDD Sk 1/30/2009 MZ-SED L4/27 MZ 9 .

1/30/2009 Ve = Ve ++++ ++++ +++++ + ++++++ ++++ + (b) A programmable switch (c) EEPROM transistor 1/30/2009 MZ-SED L4/28 Complex Programmable Logic Device (CPLD) I/O block I/O block PAL-like block PAL-like block Interconnection wires I/O block I/O block PAL-like block PAL-like block 1/30/2009 Structure of a complex programmable logic device (CPLD) MZ-SED L4/29 A section of a CPLD PAL-like block (details not shown) PAL-like block D Q D Q D Q 1/30/2009 MZ-SED L4/30 MZ 10 .L4 Using EEPROM transistors to create a programmable plane.

L4 EPLD Block Diagram Macrocell 1/30/2009 Primary inputs 1/30/2009 MZ-SED L4/31 2-Input Mux as programmable logic block Configuration A 0 0 0 0 X Y Y 1 1 1 B 0 X Y Y 0 0 1 0 0 1 S 0 1 1 X Y X X X Y 1 F= 0 X Y XY XY XY X +Y X Y 1 A B 0 F 1 S 1/30/2009 MZ-SED L4/32 Logic Cell of Actel Fuse-Based FPGA A B SA 1 C D SB S0 S1 1/30/2009 L4/33 1 Y 1 MZ-SED MZ 11 .

L4 Field-Programmable Gate Arrays (FPGAs) Look-Up Tables (LUTs) x1 0/1 0/1 0/1 0/1 x2 (a) Circuit for a two-input LUT 1/30/2009 f x1 x2 0 0 1 1 0 1 0 1 f1 1 0 0 1 (b) f 1 = x 1 x 2 + x 1 x 2 x1 1 0 0 1 x2 (c) Storage cell contents in the LUT f1 A two-input lookup table (LUT) 1/30/2009 MZ-SED L4/34 A three-input LUT x1 x2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 x3 1/30/2009 MZ-SED f L4/35 Inclusion of a flip-flop in an FPGA logic block Select Out In1 In2 In3 Clock LUT Flip-flop D Q 1/30/2009 MZ-SED L4/36 MZ 12 .

C 4 4 xx D4 D3 D2 D1 Logic function of xxx Logic function of xxx Logic function of xxx xx xx xx xx x x xxxx xxxx xxxx Bits control xxxx x xx x xx 1/30/2009 xx xx x Bits control xxxx x xx x x xx F4 F3 F2 F1 xx xx xx xx x xxxxx xx xx H P x Multiplexer Controlled by Configuration Program x Xilinx 4000 Series 1/30/2009 MZ-SED L4/37 FPGAs x3 f x1 x1 x2 x2 0 0 0 1 x2 f1 x3 0 1 0 0 f2 f1 f2 0 1 1 1 f A section of a programmed FPGA 1/30/2009 MZ-SED L4/38 FPGAs x3 f x1 x1 x2 x2 0 0 0 1 x2 f1 x3 0 1 0 0 f2 f1 f2 0 1 1 1 f A section of a programmed FPGA 1/30/2009 MZ-SED L4/39 MZ 13 ...L4 LUT-Based Logic Cell C1..

L4 A field-programmable gate array (FPGA) 1/30/2009 1/30/2009 MZ-SED L4/40 Array-Based Programmable Wiring Interconnect Point M Programmed interconnection Input/output pin Cell Horizontal tracks Vertical tracks 1/30/2009 MZ-SED L4/41 Pass-transistor switches in FPGAs x1 0 0 f 1 0 x2 1 Vf VA 1 1 SRAM 0 SRAM 0 SRAM (to other wires) 1/30/2009 MZ-SED L4/42 MZ 14 .

L4 1/30/2009 Restoring a high voltage level V DD SRAM 1 VA VB To logic block 1/30/2009 MZ-SED L4/43 Mesh-based Interconnect Network Switch Box Connect Box Interconnect Point 1/30/2009 MZ-SED L4/44 Transistor Implementation of Mesh 1/30/2009 MZ-SED L4/45 MZ 15 .

MZ-SED 1/30/2009 L4/48 MZ 16 .L4 Hierarchical Mesh Network 1/30/2009 Use overlayed mesh to support longer connections Reduced fanout and reduced resistance 1/30/2009 MZ-SED L4/46 CPLD packaging and programming (a) CPLD in a Quad Flat Pack (QFP) package To computer Printed circuit board (b) JTAG programming MZ-SED 1/30/2009 L4/47 Standard-Cell x1 x2 x3 f2 f1 A section of two rows in a standard-cell chip Select specific devices and interconnection. Logic gates are “standardized”. CAD tools layout and route wires. Trade offs versus Programable Logic Devices: less area/less power/higher clock frequency.

…) Routing channel requirements are reduced by presence of more interconnect layers L4/49 1/30/2009 MZ-SED Standard Cell — Example [Brodersen92] 1/30/2009 MZ-SED L4/50 Standard Cell – The New Generation Cell-structure hidden under interconnect layers 1/30/2009 MZ-SED L4/51 MZ 17 .L4 Cell-based Design (or standard cells) Feedthrough cell Logic cell 1/30/2009 Rows of cells Routing channel Functional module (RAM. multiplier.

L4 Sea-of-gates gate array 1/30/2009 1/30/2009 MZ-SED L4/52 The logic function f1 = x2x3+x1x3 in the gate array f1 x1 x2 x3 1/30/2009 MZ-SED L4/53 MZ 18 .

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