Ha Noi University of Science and Technology School of Electronics and Telecommunication

Report
Project name : Building PONG GAME on DE1 hardware foundation of Altera
Guiding lecturer : Phm Ngc Nam. : ng c Tn T3 Nguyn Minh c T3 ng Minh c T4 H Minh c T11 - 20070840 Nguyn Mnh t T2

Members

Content
1 2 Thankful expression ...................................................................................................... Overview ....................................................................................................................... 2.1 2.2 2.3 Purpose ..................................................................................................................... Basic foundation ...................................................................................................... Project requirement .................................................................................................. Functional requirement ..................................................................................... Non-functional requirement ..............................................................................

2.3.1 2.3.2 2.4 2.5 3

Particular works ....................................................................................................... Achivement ..............................................................................................................

Used technology ............................................................................................................ 3.1 3.2

DE1 Kit Hardware ......................................................................................................

Quartus II Sofware ...................................................................................................

Block diagram of the system ......................................................................................... 4.1 4.2 4.3 4.4 Keyboard .................................................................................................................. Display ..................................................................................................................... ROM......................................................................................................................... Processing unit .........................................................................................................

5 5

PS2 Keyboard ................................................................................................................ Block for receiving PS2 data .................................................................................... 5.1.1 5.1.2 5.2 Giao tip vt l cng PS2 .................................................................................. Khi nhn d liu PS2 ......................................................................................

Mch giao tip vi PS2 Keyboard ........................................................................... Tng quan v m ha bn phm ........................................................................

5.2.1

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5.2.2 6

Mch giao tip PS2 keyboard ...........................................................................

VGA............................................................................................................................... 6.1
Graphic .......................................................................................................................

6.1.1 6.1.2 6.2 6.2.1 6.2.2 6.3

Introduction ....................................................................................................... VGA Gate .......................................................................................................... iu hi n vi o ................................................................................................. M h ng VG ..........................................................................................

M h to pix ...................................................................................................

VGA text .................................................................................................................. Gii thiu ........................................................................................................... To t xt .............................................................................................................. Font ROM ......................................................................................................... M h to t xt T n .........................................................................................

6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 7 C 7.1

Font.....................................................................................................

c xy dng game .............................................................................................. Xy dng mn hnh new game ................................................................................ Layer nn ........................................................................................................... Text layer...........................................................................................................

7.1.1 7.1.2 7.2

Xy dng mn h i hnh ........................................................................................ Text.................................................................................................................... Header ............................................................................................................... B tng .......................................................................................................... Bng m i ........................................................................................................... Rn ....................................................................................................................

7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3

Khi no kt th tr h i? ........................................................................................

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7.4

Xy dng phn kt th tr h i .............................................................................. Mn hnh tnh i m ........................................................................................... Mn u i m v tn ngi h i .......................................................................

7.4.1 7.4.2 8 9

Kt lun.......................................................................................................................... Cc ti liu tham kh o ...................................................................................................

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1 Thankful expression
We would like to give thankful voice to lecturer Nam who guided and helped through the implementation process.

2 Overview
2.1 Purpose
Designing PONG GAME based on DE1 kit. Holding knowledge of DE1 hardware. Expanding programming capacity with C language.

2.2 Basic foundation

Basic knowledge on FPGA and C language. Experience for reading and seeking English or Vietnamese documents.

2.3 System requirement

2.3.1 Functional requirement
Its sign for 2 p y rs. Friendly interface and easy to play, using PS2 keyboard to play and VGA monitor to display game objects and score. Game has three level : Easy, Medium, Hard. The speed of the game would be raised according to each level. One player can select the levels in the list to play. If one person win 3 set, the person will be winner. Each set has 11 scores. The players can pause the game any tim A piece of music starts game. y pr ssing

2.3.2 Non-functional requirement

System is built on DE1 kit The system works at frequency of 50MHz.

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2.4 Particular work

..

2.5 Achievement
The game is basically completed with the friendly interface and not complex to play. Handling ball reflection is quite well.

2.6 Shortcoming
Som tim s, st rting g m is sti ow n .

3 Used technology
3.1 Hardware
3.1.1 DE1 Kit
DE1 board is a development tool has many features, the board allow the user to implement from simple circuits to complex projects. Particularly, the following hardware is provided on the DE1 board : t r Cy on II 2C20 FPG t r S ri Configur tion vi vi EPCS4

US

st r (on o r ) for progr mming n us r PI ontrol; both JTAG and Active

Serial (AS) programming modes are supported 512-Kbyte SRAM 8-Mbyte SDRAM 4-Mbyte Flash memory SD C r so t

4 push utton swit h s

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 10 togg swit h s 10 r us r LEDs

8 r n us r LEDs 50-MHz oscillator, 27-MHz oscillator and 24-MHz oscillator for clock sources 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks VG D C (4-bit resistor network) with VGA-out connector RS-232 transceiver and 9-pin connector PS/2 mous / y oard connector Two 40-pin Expansion Headers with resistor protection Pow r y ith r 7.5V DC pt r or US

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Figure 3.1.1 Kit DE1

3.2 C language
C is a popular language used for many embedded systems. We use the language to programme the NIOS II on the SoPC system.

4 Block Diagram

KEYBORAD

KEYBOARD CONTROLLER

VGA CONTROLLER

VGA MONITER

PONG MAIN

PONG CORE

AUDIO COTROLLER

IC CODEC

Figure 4. Block Diagram

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There four key parts in our project : VGA controller, PS2 controller, Audio controller and Pong main with input : PS2 keyboard, and output : VGA display, speaker. Data from keyboard to control balls and paddlers and the score calculation would be processed by the Pong main.

5 PS2 Keyboard
To control the direction of movement of the slider up and down, enter the level to start playing, pause the game or to save the name if the player scores high ... we have to use akeyboard. Currently the market has two types of keyboard is usb port keyboard and keyboard port ps2.Trong pong game made by the group selected the ps2 keyboard to use. We will turn to find out about this type of keyboard as well as design mass necessary to be able to receive data sent from the keyboard correctly.

5.1 Data Blocks received PS2

5.1.1 Physical Interfaces PS2 port
A PS2 port has four pins: data ps2d pin, clock pin ps2c and two pins are the source VCC and ground pin which power is provided by the host VCC. The data from the host keyboard to be transmitted over a serial data pin standard UART. The process begins with data transfer a start bit, 8 data bits, 1 parity bit and Figure 5.1 Port PS2
Start Bit (1 bit)

1 stop bit
Data Bits (8 bits) Odd Parity Bit (1 bit) Stop Bit (1 bit)

Figure 5.2 Description of a data block

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Clock of the keyboard is transmitted through the pin ps2c frequency range from 10kHz to 16.7 Khz, ps2d signal must be stable for at least 5us front and back up and down slopes of the signal ps2c. We can see this by describing the drawing:

Hnh 5.3

5.1.2 PS2 receiving data blocks

Order to collect data rather than a sampling design will use a detector circuit of the signal slopes down ps2c reference point. The input circuit includes receiving signals from ps2c ps2d and keyboard, the host clock signal, a system reset signal and a signal for receiving data from the keyboard. The output of the circuit will be the 8 bit data signal and a signal rx_done_tick. This signal is high at every clock cycle. We have received the block diagram of the circuit:
rx_en clk rst KEYBOARD ps2d ps2c Filter & Falling Edge ps2c clk Falling edge ps2_rx rx_done_tick dout (7 downto 0)

Figure 5.4 Block diagram of the circuit to receive data

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ASM receives block diagram of the data:

Idle

F Rx_en=1 and Fail_edge=1 T b<=ps2d (b>>1) n<= 9

dps

F Fail_edge=1

b<= ps2d & (b>>1)

n=0

n<=n-1 T

Load rx_done_tick <=1

Figure 5.5 ASM receiving vessel

Basically, the circuit works as follows: First in the standby mode, the circuit to check the slope of the clock signal of the PS2 and get a start bit. After identifying the start bit to 10 bit circuits will next include 8 data bits, 1 parity bit and 1 stop bit. End of the 8 bit data and move on hold.

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The circuit communicating with PS2 Keyboard

In this section we'll learn how to encode keyboard design and a circuit for decoding the commands sent from the keyboard to the Host.

5.1.3 Overview of the keyboard encoder

A keyboard is a matrix of keys. It embeds a microcontroller to regulate the operation of the keyboard. There are three modes of operation of the keys can occur are: When you press a key, then make the key code is transmitted. When we hold a large enough down time of about 0.5 s, the code will begin to make a repeat with a cycle speed of 100 ms identified. When you release the keys of the keyboard, the break code will be transmitted.

The figure below shows the code of the keys make the keyboard:

Figure 5.6 Keyboard

For the keyboard usually make its code size is 1 byte longer to extend the key size is from 2 to 4 byte for byte. PS2 keyboard will begin serialization code depending on the operation of the keyboard. For example, you press and release the first key A make code is sent to then break its code: 1C F0 1C For example key expansion up button: E0 75 F0 E0 75

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If you press a key long enough then release the make code will be sent several times: 1C 1C 1C .. F0 1C If multiple keys are pressed simultaneously, the code is sent in turn make code and break code of two keys. For example, you press two keys simultaneously, the Shift and A COE will be sent to: 12 1C F0 1C F0 12

5.1.4 PS2 keyboard interface circuit

PS2 keyboard interface circuits work to filter the main component obtained in scan code obtained after the operation, press and release the key. At the same time generate a signal to a controller can recognize what is key expansion (usually for the purpose of movement of the slider, select level players) what are often key (used to store players named in the case of high results, pause or start the game) There are two ways to record the main component in the scan code from the press release the key operation is started and start make code break code. In pong game that made the group has chosen to start group will make code more accurately because the command will be executed immediately after being imported to avoid delay to the key if we are using to catch break code. Block diagram of the circuit with a PS2 keyboard interface:

ps2c ps2d

ps2c ps2d

Key_code
dout got_tick done_tick w_data wr r_data rd

got_key

clk

PS2_rx

FSM to get make code

FIFO

Figure 5.7

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Spotlight in this circuit is the signal got_key. After the circuit receives data sent from the PS2 keyboard and output is a signal dout is done_tick signal. Output signal will be sent to an FSM circuit to determine the main components of the code that we need to collect to serve our purposes. Got_tick positive signal high when the circuit will determine the composition of FSM code to read, and write into the code for this in the Control Unit Fifo waiting for treatment. Chart FSM to start make code:

got_key = 0 ext_key = 1 done_tick = 1

wait

done_tick = 0

Check key
got_key = 0 brk_key = 1 brk_key = 0 brk_flag = 1

loop

Clear flag
brk_flag = 0 brk_flag = 1

Check flag
got_key = 0 brk_flag = 0

Read key

got_key = 1
Figure 5.8

FSM is designed to break code scan code instead of all keys pressed including extended keys. The advantage is that can get the right key when a key is pressed but the change is more complex circuits. This reading is E0 FSM will skip this code; Upon receiving F0 F0

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will ignore and bypass the code and immediately following its receipt. Thus, complete the task FSM received scan code. FSM do the job as follows: At first signal and brk_flag got_key by 0. When you receive a code from the receiver, it will have to check the extended code E0 or not, if it will ignore (got_key <= 0) and return to standby. If you are not E0, check to see if it is F0 or not. If the flag F0 is set to 1 and skip brk_flag this code and move on hold. If not the E0 and F0, this will check the flag brk_flag, if the one they will ignore the code, and delete flag brk_flag about 0. If is 0, then get this code. Then move on hold. For example, when you press and release the up arrow key will have the following code is transmitted in turn: E0 75 E0 F0 75 Upon receipt of first E0 values, this is wide open to be missed. Upon receipt of the next 75 value, this is not the E0 or F0, brk_flag flag and check for the value 0 => get this value => we get scan code E0 next skip. F0 next brk_flag flags ignored and set to 1. The value of the last 75, the flag brk_flag check for a value => ignore and delete this flag to 0.

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6 VGA
6.1 Graphics
6.1.1 Introduction
- VGA stands for "video graphics array", is a graphics standard introduced in late 1980 from the same type computer IBM PS / 2. In the following sections, we will discuss the interface 640 x 480 resolution with 8 basic colors of the screen CRT (cathode ray tube). - Below is a combination of color from the 3-bit VGA: red (R) 0 0 0 0 1 1 1 1 Green (G) 0 0 1 1 0 0 1 1 Blue (B) 0 1 0 1 0 1 0 1 Color black Blue Green Cyan red Magenta Gold White

6.1.2 VGA Port

- VGA port has five positive signals include sync signal horizontally and vertically, and v_sync h_sync and 3 for the third picture signal red, green, blue. - The picture is an analog signal, and video controller using a DAC converter to convert the digital signal level analog audio output desired. If a picture signal N-bit test signal may be converted to a similar level 2N. - In the discussion, we use color picture signal output 3bit so we'll get 2 ^ 3 = 8 basic colors as listed in the table .

6.2 Video controllers

A controller that creates the image sync signal and the output pixel data. Chart as follows:

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External data/control

rgb Pixel generation Pixel generation circuit circuit

pixel_x pixel_y video_on h_sync v_sync

VGA monitor

clock

VGA_sync VGA_sync

Figure 6.1: Block diagram of the VGA controller

Chart include: Synchronization circuit, denoted VGA_sync. Create pixel circuit "Pixel circuit generation." - Circuit VGA_sync creates synchronization signal and time signal.Signal h_sync and v_sync VGA port is connected to control the horizontal scanning mode and the vertical of controllers.Pixel_x and pixel_y is the output of the decoded signal from the buffer inside. The two signals to determine the location of the current pixel. VGA_synccung circuit generates a signal to determine video_on when do activate or disable signal displayed on the screen. - Circuit 3 pixel generation circuit generates picture signal rgb. Samples were corresponding to the coordinates of the current pixel and the signal data and external controls. - Circuit VGA synchronization - This circuit generates the synchronization signal h_sync horizontal and vertical synchronization v_sync. Of which: h_sync: indicate the time required for scanning a row. v_sync: indicate the time required for scanning the entire screen. - In the discussion we use the screen resolution is 640x480 pixels with a speed of 25MHz, which means that the process 1s 25M pixel screen. - Monitor the area include black members in the area around the screen and see the rectangle in the middle. The coordinate axes and the positive direction of the axis as shown below: -

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border Visible area

y h_video_on 0 h_sync 639 655 751 799

display Left border Right retrace border Left border

Figure 6.2: Diagram of horizontal scan time

6.2.1.1 Sync signal horizontally Diagrams-time scanning sync signal horizontally as shown 2. A signature h_sync signal is divided into four areas: Display area: is where the pixel is displayed on the screen. Area scan backwards: is where the electron beam volte-face towards the left side. Area boundary must:is the black area on the right, in the region this picture messaging is disabled is not displayed. The sea son: the black area is the same as the left and right border regions, in the region this competition the picture signal of breath is not displayed.

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6.2.1.2 sync signal in the vertical Map-time scanning sync signal vertically as follows:

v_video_on 0 v_sync 479 489 491 524

display Top border Bottom retrace border Top border

Figure 6.3: Diagrams of the time signal scanned vertically.

In which: Display area: is where the pixel is displayed on the screen. Area scan backwards: is where the electron beam volte-face towards the left

side. Border area on: is the black area above, in this region the picture messaging is disabled is not displayed. border below: black area is the same as the area below and above the boundary, in the region this competition the picture signal of breath is not displayed. 6.2.1.3 Speed pixel - Call p is the number of pixels in a horizontal row, l be positive in a horizontal screen and s is the number of displays in the 1 s test speed by pixel p * l * s. - Note: order to be not blinking screen test s must be greater than or equal to 24. - With a screen resolution 640x480 and displays the number of 1s is 60 images / s test p = 800 pixels / line, l = 525 line / screen, s = 60 screens / second tape speed 800x525x60 pix 25M pix / s.

6.2.2 Create pixel circuit

- Circuit generates a signal to create pixel color 3 - bit rgb to VGA port. Control signals and data indicate that external content to be displayed on the screen, and pixel_y pixel_x indicate your current pixel coordinates. There three types of pixel circuits created:

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 Map type bit - mapped. Map style tile - mapped. Map object model - mapped. - In the chart type bit - mapped, data displayed on the screen is stored in a memory cell. Each pixel is stored directly in memory that forms words memory (memory word) and signal pixel_x, pixel_y create memory cell address. A micro processor constantly updated graphical screen and write data to memory cells. A receiver for continuous read from the memory and transfers data to RGB. Chart bit - mapped commonly used to create color. Disadvantage when using this diagram is a waste of space. - To reduce memory requirements, people use chart style tile - mapped. In the diagram this model, we group a set of bits to form a tile (square tiles) and to treat each tile as a bit. Chart is usually used to create text. - Finally, the object model diagram - mapped is often used to create the objects. In the preserve, we trade on a combination of three ways to generate a complete screen. 6.2.2.1 Diagrams object model - mapped. Block diagram:

Data/control Video_on pixel_x pixel_y Object 1 Object 1 Generation circuit Generation circuit

rgb mux

rgb

Object 2 Object 2 Generation circuit Generation circuit

Object 3 Object 3 Generation circuit Generation circuit

Figure 6.4: Block diagram of the circuit object - mapped.

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- Block diagram including circuit creates the objects, a mux to select the objects displayed. Circuits perform the following functions: Hold down the coordinates of the object coordinates and comparing this with the current position and that pixel_x pixel_y provided. Hold down the coordinates of the object coordinates and comparing this with the current position and that pixel_x pixel_y provided. Only the color of the object signal. - Set mux check the signal on and identify information would be transmitted to the output signal rgb. 6.2.2.2 Diagrams style bit - mapped In this type of diagram, each pixel memory cells should constitute a drawback of this method is very religious memory. This approach does not require additional circuitry to switch the signal pixel_ x and pixel_y memory locations but much wasted memory. 6.2.2.3 Diagrams style tile - mapped Diagrams for this model is used to create text and will be discussed in Section 2.

6.3 VGA text

6.3.1 Introduction
- Diagrams style tile - mapped is used to create text and other characters. Each tile is considered as a super-pixel. Method build the characters are generally regarded as the tile and create a pixel circuit design using this method.

6.3.2 Create text

- When applying this method, each character is treated as a tile, the value of a ma tilebieu performances of a particular sample. We use the ASCII code 7 - bit characters. - Form of the tiles that make up your text font character sets. There are many kinds of fonts, but in the capacity of our discuss fontchu in size 8x16 (8 columns and 16 rows).

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00000000 00000000 00000000 00000000 00010000 00010000 00111000 00111000 01101100 01101100 11000110 11000110 11000110 11000110 11111110 11111110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

Figure 6.5: Model of characters and font characters

- Other characters include numbers, letters and flowers business letters, symbols, and many special graphics characters. - For screen resolution 640 x480, when using tile in size 8 x16, each horizontal row and each tile 80 is not just hang vertically just not enough 30 tile. Meanwhile we can see the screen resolution is 80 x 30.

6.3.3 Font ROM

To make that ASCII characters, we use font ROM. Suppose we made 128 first character of the ASCII table is the size of 211 x 8 ROM. Among them, 7 the highest weighted bit of 11 bit address used to identify characters, four weighted smallest bit is used to identify the row in a form of words. Figure 5 is a ROM address and content of the letter A. How do the following:
constant ADDR_WIDTH: integer :=ll; constant DATA_WIDTH: integer:=8; signal addr_reg: std_logic_vector (ADDR_WIDTH -1 downto 0); type rom_type is array (0 to 2**ADDR_WIDTH-l) -- ROM definition constant RUM: rom_type :=

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-- code

x00

(blank space)

00000000, -- 0 00000000, -- 1 00000000, -- 2 00000000, -- 3 00000000, -- 4 00000000, -- 5 00000000, -- 6 00000000, -- 7 00000000, -- 8 00000000, -- 9 00000000, -- a 00000000, -- b 00000000, -- c 00000000, -- d 00000000, -- e 00000000, -- f ... begin -- addr register to infer block RAM process (clk) begin if (clkevent and clk = 1) then addr-reg end end data end if ; process; <= ROM(to_integer(unsigned(addr_reg))) ; arch; <= addr;

6.3.4 Text to create a basic circuit

- Create pixel circuit generates the pixel values corresponding to the coordinates of the current pixel data and signals / controls outside. Create pixel circuit model based on measurements of tile - mapped two phases involved. In the first phase capacity of the high bit pixel_x and pixel_y to generate the code of a tile, and in the second period and the bit length encoding is to generate low value of the pixel.

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- Under this method, the screen is considered as a resolution of 80x30 tiles, each tile is a box the size of 8x16. First, pixel_x and pixel_y will indicate the location coordinates of the current tile.The circuit used to create character coordinates in conjunction with the data signal / control from the outside to create the value of tlie corresponding ASCII code. Next, this will make ASCII 7 bits of the address of the font ROM and the location of the sample in question. Combined with the lower 4 bits of the y coordinates to form the full address of the font ROM. The output of the ROM font corresponding to a row of an 8 bit samples, and the third bit is the smallest weight of x coordinates indicate the position of the pixel.

6.3.5 The rate of Font

Trong s i u ti m pp hng t th iu h nh h th pix . Ch ng hn, hng t th m r ng t font h th 8x16 n font th 16x32. th hin ng vi ny, hng t h n h ph i t pix 1 it v i it trng s nh nh t pix x v pix y. h

7 Cc bc xy dng game
S FSM c a game:

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Reset Enter = 0

Start
Enter = 1

Play
Fail = 1 Bigger = 0

Fail = 0

Game over
Bigger = 1

Enter = 1

Enter name

Hnh 7.1. FSM ca game

ASM c a game:

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New game

End game

Level <= 1

Del_count_ena <=1'

Level ++ T Level -T

Btn = up F F Btn = down F Btn = Enter T

End_count = 1 T Score_bigger = 1 T

Play

Enter Name

Snake_size <= 4 Score <= 0 Size_tick <= 0 Score_tick = 0 F F eat = 1 T Size_tick <= 1 Score_tick = 1 Fail = 1 T

Get_key <= 0 Get_name <= 1 F

Btn = Ent r T

Get_key <= 1

Get_name <= 1

Hnh 7.2 S ASM ca snake game

7.1 Xy dng mn hnh new game

Mn hnh new game:

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SNAKE GAME
Difficulty: Level 1 Level 2 Level 3 Level 4 Level 5

Hnh 7.3 Start screen

Box mu trng hi n th n phm

ng c chn hin ti. Dng phm mi tn n xung trn

di chuy n v tr c a box.

V thit k, c th chia m hnh new game lm 2 phn nh 2 y r: y r nn cha background mu xanh v box mu trng , top layer cha text.
RGB

Background & Select_box

RGB

0 1
Text_on

Start_RGB

Start text

ena

1-5 counter key

Hnh 7.4 S khi mn hnh new game

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7.1.1 Layer nn
Cha nn xanh v select_box mu trng:

SNAKE GAME
Difficulty: Level 1 Level 2 Level 3 Level 4 Level 5

Hnh 7.5 Start screen - background

Box mu trng c hi n th nh trong 5 v tr c ty thu c vo m position x

i t ng hnh ch nht, v tr c a n l m t

nh trc t ng ng vi 5 v tr c a cc level. N xu t hin u v ngi h i mun chn. x iu ny, ta s dng m t bin c a select_box. Khi ngi h i nh n phm mi tn n hoc

nh t

xung s m tng hoc gi m gi tr c a bin position ny dn n th y i v tr c a select_box. Bin position ny ng c s dng cho phn h i hnh nh th m s u vo x nh t di chuy n c a ch rn.

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Position = 1
Position = 1

Position = 2 Position = 3 Position = 4 Position = 5

Hnh 7.6 Ta box thay i theo bin Position

nh c a select_box s ph thu c vo gi tr c a bin level ny.

Phn vic tip theo l cho hi n th select_box mu trng ny ln trn nn mu x nh nh m t i t ng hnh ch nht th ng thng.

7.1.2 Text layer

Layer cha text c a mn hnh new game s c dng:

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SNAKE GAME
Difficulty: Level 1 Level 2 Level 3 Level 4 Level 5

Hnh 7.7 Start screen - text layer

Vic xy dng layer text ny khng c g phc tp, hon ton da trn kin thc v vic hi n th text ln mn hnh VGA. Ch t tr t ng ng c a select_box. c a cc m v s o ho ng vi cc v

7.2 Xy dng mn chi chnh

Mn hnh h i hnh ng:

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SPEED: 3

SCORE: 13

Hnh 7.8 Mn hnh chi chnh

N bao g m cc phn chnh: Text hi n th level hin ti c B tng gia mn hnh. Rn. M i. tr h i v m i m t c c ngi h i.

Header mu trng l khu vc hi n th text.

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Postion

Key board
ena
ena

Speed_counter

Step_tick move Ball_feed

Snake_size

Snake counter

Snake drive
Score_tick

Snake_Game Snake_posit graph Ball_posit

RGB

Snake_fail

read

random

0 1

Play_RGB

ena

Score counter Postion

score level

Level & score text

RGB

Text on

Hnh 7.9 S khi mn chi chnh

7.2.1 Text
Vic hi n th t xt v t lm top- y r bit phn trc. y hng t s i vo vic m s o hi n th level v score c ngi h i.

score

Level & score text level

RGB

Text on
Hnh 7.10S khi hin th text mn chi chnh

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SPEED: 3

SCORE: 13

Hnh 7.11 Layer text ca phn chi chnh

i m c

ngi h i

u th o i u d liu in ry 14 it. hi n th i m s:

i m s ny,

trc tin ta chuy n v dng BCD 16 bit thng qua b chuy n i BIN_2_BCD. C 4 bit c a tn hiu CD ny t ng ng vi 1 ch s c

Bin2BCD
14bit Binary 16bit BCD

Binary 00001000110010 BCD 0000010101110010 0 5 7 2

Hnh 7.12

572

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 a ch c a m t ch s trong ROM bng gi tr c a ch s hi n th c thc hin nh thng.

ng thm 48. T

vic

Hon ton t ng t i vi vic hi n th level.

7.2.2 Header
Vng header mu trng c to ra bng cch s dng thut to r nht th ng thng. i t ng hnh ch

7.2.3 Bc tng
to ra b tng hnh ch nht. S u ROM c hi n nhng v tr mun hi n th b tng, ta ch vic cho hi n bng cch load tng. ho vn t n s dng ROM to i t ng khng ph i

111100 111001 110011 100111 001111 111100 111001 110011 100111 001111 111100 111001 110011 100111 001111

Tng

Hnh 7.13 ROM tng

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7.2.4 Bng mi
Vic hi n th bng hon ton ging vi vic hi n th b tng. Sau mi ln rn n c bng m i s cn bng m i mi xu t hin v xu t hin m t v tr ngu nhin. to ra t ngu nhin ny, ta s dng 2 b m vi cc gi tr ln nh t ng vi 2 t t s l y 2 gi tr c a 2 b ln m lm m ny s m quay vng lin tc. Khi rn n m i s

nh t c a 2 chiu mn hnh. 2 b

sinh ra m t tn hiu yu cu sinh bng mi. Khi t

cho bng m i mi sinh ra. 2 gi tr ny ph thu c vo thi gian gia cc ln n ny

m i lin tip c a rn. V v kho ng thi gian ny l ngu nhin nn 2 gi tr t ng ngu nhin.

ena

Ball feed

Snake drive
Score_tick

read

random

N-1

Ball_X

M-2 M-1

Ball_Y

Read

Hnh 7.14 B sinh ta ngu nhin

Nu nh

ng m i mi sinh ra c t sinh r

nm trong phn thn thay th.

ng c hi n th c a rn

th m t qu bng mi s ph i

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Head Ball

New ball
Hnh 7.15 Bng nm trong thn rn

trnh vic qu bng mi sinh nm trong b tng, ta chn to trong b m sinh t ngu nhin cho bng.

c a bng ngay t

7.2.5 Rn
Vic hi n th t ng t c a rn ng hon ton ging vi m vi b tng, load ROM cho t ng t m t. C iu ch rn c chiu i th y i. x m nh m t tham s u vo t b tnh chiu di rn m oi nh m t m ng nhiu phn t, mi phn t ng vi nh v t tri c a mi t t ng

Chiu di c a ch rn

ta s xt sau ny. Ch rn

m t t c a rn. Trong mi phn t c cha t

ng c a rn. Ch nhng t no c ch s nh h n hiu di rn mi c hi n th :

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hi n th

Kh ng

hi n th

L-1

L: Chiu i rn N: Chiu i rn ti rn

Hnh 7.16 Hin th rn

Ta cn m t m ng m t chiu c chiu i t ng ng ng c c bt hay khng:

hi n th

cha tn hiu cho bit t t ng

Kh ng

hi n th

u Snak_on

L-1

Hnh 7.17 Hin th rn

Khi khi VGA qut mn hnh theo pixel_x v pixel_y, ta s ki m tra xem t c thu t rn no khng. Gi s t t rn ng qut nm trong m t t rn no . ki m tra tn hiu sn on t ng ng. Nu n bng 1 ta s load ROM v hi n th

hin ti , t s t rn

, ng c li th khng cho hi n th

Ty thu c vo ROM c pix ti m ng mu nn. Do

t rn m pix

c hi n th hay khng. Nu gi tr x

ROM t ng ng 1 th pix

s c gn gi tr RGB c a ch rn. Nu 0 th , ti mi t rn ta cn m t tn hiu nh pixel hin

c bt hay khng. => Ta cn m t m ng 1 chiu c cng chiu di vi ch rn

cha tn hiu bt pixel cho c ch rn:

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Pixel_x

Pixel_x

Pixel_y

1 1

1 1 1
t th i

0 1 1

Pixel_y

Sna_on(i) =0'

Sna_on(i) =1'

Hnh 7.18 ROM v bt tng pixel cho t rn

Nh hnh trn,

t c khi no c tn hiu Sna_on th i no

ng 1 th s xu t ra gi

tr RGB c a ch rn. m iu ny, ta or t t c cc bit c a tn hiu sna_on li vi nhau to ra tn hiu snake_on. => b t c khi no snake_on bng 1 th ho xu t gi tr RGB c a ch rn ra cng VGA:

Sna_on 0

Sna_on 1

Sna_on 2

Sna_on 3

Sna_on n-3

Sna_on n-2

Sna_on n-1

Snake_on

OR

OR

OR

OR

OR

OR

Hnh 7.19

iu khin rn di chuyn:

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M t h h rn. T t c c

n gi n

iu khi n rn di chuy n

h vi

iu khi n u c a nh v tri

t rn cn li s t ho t ng sau:

ng i th o u rn bng cch gn t

t ng tr

Top0 Left0 Left1

Top1 Left2

Top2 Left3

Top3 Left4

Top4 Left5

Top5

Head

Hnh 7.20 Di chuyn rn

Ta s dng m t tn hiu (step_tick) cp nht . Do ch nh t , hu

th ng o hi no th c

ch t

c a t li c iu

t. mi khi tn hiu step_tick 1th t a n cng cao th t ount r

u rn v

di chuy n c a rn cng th p. sinh ra tn hiu

di chuy n c a rn, ta dng m t b

step_tick. Gi tr cao nh t c a b cng cao th gi tr cao nh t c a b

m ph thu c vo level c

ngi h i. L v

m cng th p => chu k c a tn hiu step_tick

cng th p => rn di chuy n cng nhanh:

level

Step_tick

Counter
clk

clk Step_tick

Hnh 7.21 B sinh tn hiu di chuyn

iu khin u rn:

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ena

Co-ordinate of snake_head

Snake drive
Hnh 7.22 Khi iu khin u rn

u rn hng t

iu khi n bi 4 phm mi tn trn n phm. Khi nhn c tn hiu i h . trnh tnh

n phm u rn s di chuy n theo chiu m mi tn

trng nhn vo phm mi tn h ng c li vi hng di chuy n c a rn dn n u c a ch rn chui vo thn c a n ta cn m t bin cha chiu x l nhn phm b m. Do rn nh phn 2 bit ng i huy n c a ch rn 4 hng di chuy n trn mn hnh nn ta dng m t bin

m ha chiu di chuy n c a rn:

direc <= "00"; => di chuy n t tri sang ph i. direc <= "01"; => di chuy n t ph i sang tri. direc <= "10"; => di chuy n t trn xung i. direc <= "11"; => di chuy n t i ln trn.

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01

11
00
Hnh 7.23 Hng trn mn hnh

Khi nhn m t phm b m t bn phm- v d l "01110100" ( phm di chuy n sang ph i)ta s ki m tra phm g. Trong trng h p ny t phm mi tn s ng ph i. Tip theo ki m tr hng ng i huy n c a rn l chiu no. Nu 01 ph i sang tri

ng c chiu mi tn th s h ng ho php u c a rn di chuy n sang ph i m tip tc di chuy n sang tri.

10

Hng Hng

ng i huy n th r i

Hng h ng th

Hnh 7.24 iu hng u rn

Khi iu khi n u rn:

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7.3 Khi no kt thc tr chi?

Tr h i t th chnh n. Vi x nh rn m u v tng c thc hin n gi n bng cch ki m tra xem ta hi m u c a rn m vo tng ho m vo hnh phn thn c a

u c a rn c nm trong vng c a b tng hay khng. Vic ki m tra xem con rn c t n hnh n h y h ng ng c thc hin t ng t bng cch ki m tra t hay khng. u rn c trng vi t c t c bt c a con rn

Hnh 7.25 u rn nm trong thn

Do vic ki m tra rn m vo tng v t m hnh n hai tn hiu ring r nn s cn kt h p li bng php or.

c thc hin ring r, sinh ra

7.4 Xy dng phn kt thc tr chi

7.4.1 Mn hnh tnh im
Sau khi rn m vo tng hoc t m vo hnh n , tr h i t thc v s hin ra mn hnh tnh i m:

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SCORE: 120
Top 5: Player1: 560 Player2: 440 Player3: 360 Player4: 210 Player5: 100

Hnh 7.26 Mn hnh tnh im tr chi

Trn mn hnh s hi n th s i m c s t ng ng c u trong 1 m ng 5 phn t:

ngi h i hin ti. ng thi hi n th tn v i m . i m v tn c 5 ngi c

5 ngi c s i m cao nh t tr

score Score array

Score sreen

RGB

Name array
Hnh 7.27 Khi hin th im ngi chi

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Vic hi n th t xt, i m s ging nh phn hi n th

i m v v trong mn h i hnh.

7.4.2 Mn lu im v tn ngi chi

Mn hnh tn i m ch hi n th trong 3s. Sau 3s, nu i m s c h n ngi c u i vo trong top5, hn hnh u tn s c hi n th : ngi h i hin ti cao i m s th p nh t trong top5 th tn v i m s c a ngi h i hin ti s

ENTER YOUR NAME:

LONG_

Hnh 7.28 mn hnh lu tn

Mn hnh g m 2 phn : layer text v background cha text_box mu trng. V n hi n th ging cc phn n tr y v h n gi n.

Ta xt v n nhp tn t bn phm v x u tr tn ng i m s vo m ng. u tn phm ngi h i c nhp t bn phm ta s dng m ng 7 phn t, mi phn 1 phm c nh n, scan code SCII t ng ng thng qua b c chuy n ln host v chuy n thnh m

t 1 c

a ch c a 1 ch ci trong font_ROM. Mi hi

chuy n i SCAN2ASCII.

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Key board

2 ASCII
Hnh 7.29 Chuyn Scan code sang m ASCII

, m

SCII u vo trong m ng. Khi hi n th ch vi

c gi tr

a ch ROM t

trong m ng v load k t t ng ng. Khi nhn c phm backspace, mch s xa phn t tr 5 ngi h i i m s cao nh t. v gi tr 0 ( a ch c a

kho ng trng trong ROM). Khi nhn phm enter, m ng cha tn s c chn vo trong m ng 2 chiu cha tn c

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Player 1: 500 Player 2: 400 Player 3: 300 Present player: 250

Playe r 4: 2 00
Player 5: 100

Hnh 7.30 Lu im s ngi chi

8 Kt lun
Sau m t thng h lm vi , hng t i hon thnh sn g m trn it DE1. Th ng qu g m hon nh dng ti hng t i hc h i thm r t nhiu thut trong lp trnh VHDL ng nh nhng kinh nghim qu bu trong vic pht tri n ng dng trn FPGA. M thnh nhng vn cn r t nhiu vic ph i m game hon thin h n na. hon thin g m nh hi n th

SDRAM, audio cho game. Hy vng s u ti ny, nh m i s u s tip tc pht tri n

9 Cc ti liu tham kho

FPGA Prototyping VHDL Examples - Xilinx Spartan-3 version . PONG P.CHU

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Cng nhiu ngu n ti liu trn internet

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