You are on page 1of 166

The Pennsylvania State University The Graduate School Department of Computer Science and Engineering

A TIQ BASED CMOS FLASH A/D CONVERTER FOR SYSTEM-ON-CHIP APPLICATIONS

A Thesis in Computer Science and Engineering by Jincheol Yoo c 2003 Jincheol Yoo

Submitted in Partial Fulllment of the Requirements for the Degree of

Doctor of Philosophy May 2003

We approve the thesis of Jincheol Yoo.

Date of Signature

Kyusun Choi Assistant Professor of Computer Science and Engineering Thesis Adviser Chair of Committee

Mary Jane Irwin Distinguished Professor of Computer Science and Engineering

Vijaykrishnan Narayanan Assistant Professor of Computer Science and Engineering

Charles L. Croskey Professor of Electrical Engineering

Raj Acharya Professor of Computer Science and Engineering Head of the Department of Computer Science and Engineering

iii

Abstract

The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are becoming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. Moreover, SoC trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design. Thus, this thesis is to investigate high speed, low power, and low voltage CMOS ash ADCs for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded CMOS inverters as a comparator. The TIQ technique has been introduced in [53]. The TIQ technique proposed here has been developed for better implementation in SoC applications. Four issues are addressed to achieve high speed, low power consumption, and low voltage operation in the TIQ ash ADC. First, the high speed and low power TIQ ash ADC architecture is presented along with an optimal design method - called the systematic size variation (SSV) technique - for reducing the impacts of the process variation. Second, a new digital encoder called the fat tree encoder is introduced. The fat tree encoder replaces the ROM type encoder that is the speed bottleneck. Next, for low power applications, a power and resolution adaptive ash ADC (PRA-ADC) and a power management method in the TIQ ash ADC are presented to reduce/manage power consumption. Finally, a new voltage comparator, called the

iv Quantum Voltage (QV) comparator, for next generation deep sub-micron low voltage CMOS ash ADC is proposed. In addition to the above four issues, simulation results and fabrication results of the TIQ ash ADC are discussed. The preliminary results show that the TIQ ash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other ADCs.

Table of Contents

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xi

Acknowledgments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiv

Chapter 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 1.2 1.3 Challenges in Designing ADCs for SoC . . . . . . . . . . . . . . . . . Solid-State Technology . . . . . . . . . . . . . . . . . . . . . . . . . . Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 3 4

Chapter 2. A/D Converter Background . . . . . . . . . . . . . . . . . . . . . . . 2.1 ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Static Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.1 2.1.1.2 2.1.1.3 2.1.2 Oset and Gain Error . . . . . . . . . . . . . . . . . Dierential Non-Linearity Error (DNL) . . . . . . . Integral Non-Linearity Error (INL) . . . . . . . . . .

6 6 7 8 9 11 12 12 13 13 14

Dynamic Parameters . . . . . . . . . . . . . . . . . . . . . . . 2.1.2.1 2.1.2.2 2.1.2.3 2.1.2.4 Signal-to-Noise Ratio (SNR) . . . . . . . . . . . . . Signal-to-Noise and Distortion Ratio (SINAD) . . . Total Harmonic Distortion (THD) . . . . . . . . . . Eective Number of Bits (ENOB) . . . . . . . . . .

vi 2.1.2.5 2.2 Spurious-Free Dynamic Range (SFDR) . . . . . . . 14 14 16 19 20 22 23

ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . Successive Approximation ADC . . . . . . . . . . . . . . . . . ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of ADC Architectures . . . . . . . . . . . . . . . .

Chapter 3. TIQ Flash ADC 3.1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 27 27 29 30 31 31 33 33 37 38 39 41

TIQ Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 CMOS Inverter as a Comparator . . . . . . . . . . . . . . . . 3.1.1.1 3.1.1.2 3.1.1.3 3.1.2 Sensitivity to Process . . . . . . . . . . . . . . . . . Sensitivity to Temperature . . . . . . . . . . . . . . Sensitivity to Power Supply Voltage . . . . . . . . .

Comparator Generation and Selection Method . . . . . . . . 3.1.2.1 3.1.2.2 Random Size Variation (RSV) Technique . . . . . . Systematic Size Variation (SSV) Technique . . . . .

3.2 3.3

Gain Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC-to-BC Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 3.3.2 ROM Type Encoder . . . . . . . . . . . . . . . . . . . . . . . Fat Tree Encoder . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4. Experimental Results and Evaluations . . . . . . . . . . . . . . . . . 4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .

43 43

vii 4.1.1 TIQ Flash ADC Performance . . . . . . . . . . . . . . . . . . 4.1.1.1 4.1.1.2 4.1.1.3 4.1.2 4.1.3 4.2 Simulation Results of 0.25 m technology . . . . . . Simulation Results of 0.18 m technology . . . . . . Simulation Results of 0.50 m technology . . . . . . 45 49 56 60 64 68 70 71 76 78 81 83

Variation Eects on the RSV and SSV Techniques . . . . . . Fat Tree Encoder vs. ROM Type Encoders . . . . . . . . . .

Fabrication Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 4.2.2 Test Results of 0.25 m TIQ ash ADC Chips . . . . . . . . Test Results of 0.18 m TIQ ash ADC Chips . . . . . . . . 4.2.2.1 4.2.2.2 4.2.3 Noise eects on the ADCs . . . . . . . . . . . . . . . Fast Fourier Transform (FFT) Test Results . . . . .

Test Results of 0.50 m TIQ ash ADC Chips . . . . . . . .

Chapter 5. Low Power Applications with TIQ Comparator . . . . . . . . . . . . 5.1 The Power and Resolution Adaptive Flash ADC (PRA-ADC) . . . . 5.1.1 5.1.2 5.1.3 5.2 PRA-ADC Design and Layout . . . . . . . . . . . . . . . . . PRA-ADC Simulation Results . . . . . . . . . . . . . . . . .

84 84 85 90 93 93 95 97 99

Summary of the PRA-ADC . . . . . . . . . . . . . . . . . . .

A Power Management Method in the TIQ Flash ADC . . . . . . . . 5.2.1 5.2.2 5.2.3 Power Management Method . . . . . . . . . . . . . . . . . . . Power Simulation Results . . . . . . . . . . . . . . . . . . . . Summary of the Power Management Method . . . . . . . . .

Chapter 6. Low Voltage Operation in ADCs . . . . . . . . . . . . . . . . . . . .

101

viii 6.1 Low Voltage Operation with the TIQ ash ADC . . . . . . . . . . . 6.1.1 6.1.2 6.2 Power Analysis of the TIQ ash ADC . . . . . . . . . . . . . Voltage and Temperature Variations in 0.07 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 103 106 108 109 110 112 114 116

Quantum Voltage Comparator 6.2.1 6.2.2

Simple Transconductance Amplier . . . . . . . . . . . . . . . Flash ADC with QV comparator . . . . . . . . . . . . . . . . 6.2.2.1 6.2.2.2 The QV Comparator . . . . . . . . . . . . . . . . .

ADC Design with QV comparator . . . . . . . . . .

6.2.3

Simulation Results and Comparisons with TIQ Comparator . 6.2.3.1 Power Consumption Comparison with TIQ Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.2 Noise Comparisons with TIQ Comparator . . . . . .

118 119 119

6.2.4

Summary of the QV Comparator . . . . . . . . . . . . . . . .

Chapter 7. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

122

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

127

Appendix A. DNL and INL Calculating Program . . . . . . . . . . . . . . . . .

137

Appendix B. MOSIS Parametric Test Results for TSMC 0.25 m CMOS Run .

139

Appendix C. MOSIS Parametric Test Results for TSMC 0.18 m CMOS Run .

143

Appendix D. MOSIS Parametric Test Results for AMI C5 (0.50 m) Run . . . .

147

ix

List of Tables

2.1 4.1 4.2 4.3 4.4

Summary of ADC architectures . . . . . . . . . . . . . . . . . . . . . . . Comparator transistor sizes used in 0.25 m design . . . . . . . . . . . . Simulation results of 0.25 m TIQ ash ADCs . . . . . . . . . . . . . . Process variation result in an 8-bit TIQ ash ADC . . . . . . . . . . . . Temperature and power supply voltage variation results in the 8-bit TIQ ash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24 49 50 52

53 56 58 59 62 63 66

4.5 4.6 4.7 4.8 4.9

Simulation results of 0.18 m TIQ ash ADCs . . . . . . . . . . . . . . Variation results in a 0.18 m 8-bit TIQ ash ADC Absolute currents used by each component . . . . . . . . . . .

. . . . . . . . . . . . . . . .

Simulation results of the 8-bit 0.50 m TIQ ash ADC . . . . . . . . . . Variation results in a 0.50 m 8-bit TIQ ash ADC . . . . . . . . . . .

4.10 The eects of process variations and RSV and SSV design techniques . . 4.11 DNL and INL for temperature and power supply voltage variations using the RSV and SSV design techniques . . . . . . . . . . . . . . . . . . . . 4.12 Summary of the simulation results with two encoders . . . . . . . . . . . 4.13 Summary of 0.25 m chip test results . . . . . . . . . . . . . . . . . . . 4.14 ADC Signal delay test results . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Summary of 0.18 m chip test results . . . . . . . . . . . . . . . . . . . 5.1 Summary of the PRA-ADC simulation results . . . . . . . . . . . . . . .

67 69 72 74 78 90

x 5.2 6.1 6.2 6.3 6.4 Power simulation results of the 6-bit and 8-bit ADC . . . . . . . . . . . Summary of the simulation results in 0.07 m technology . . . . . . . . Comparisons with other low-voltage ADCs . . . . . . . . . . . . . . . . . Power analysis of the TIQ ash ADC by components . . . . . . . . . . . Power supply voltage and temperature variation results from the 0.07 m 8-bit TIQ ash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 6.6 6.7 7.1 Summary of the QVC ADC simulation results . . . . . . . . . . . . . . . Power Consumption Comparisons with TIQ Comparator . . . . . . . . . Power supply voltage and temperature variations results . . . . . . . . . Comparison the TIQ ash ADC with other ADCs . . . . . . . . . . . . 107 116 118 120 124 99 102 103 106

xi

List of Figures

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

Staircase transfer function of an ADC . . . . . . . . . . . . . . . . . . . Oset and gain errors, after [32] . . . . . . . . . . . . . . . . . . . . . . . Dierential non-linearity error (DNL) . . . . . . . . . . . . . . . . . . . Integral non-linearity error (INL) . . . . . . . . . . . . . . . . . . . . . . Tradeo between resolutions and sampling rates . . . . . . . . . . . . .

7 9 10 11 16 17 18 19 20 21 22 26 28

Block diagram of a ash ADC . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of an 8-bit sub-ranging ADC . . . . . . . . . . . . . . . . Block diagram of a pipelined ADC . . . . . . . . . . . . . . . . . . . . . Block diagram of a successive approximation (SAR) ADC . . . . . . . .

2.10 Reference voltage tree in a 3-bit SAR ADC . . . . . . . . . . . . . . . . 2.11 Block diagram of a ADC . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 Block diagram of the TIQ ash ADC . . . . . . . . . . . . . . . . . . . . Inverter schematic and VTC . . . . . . . . . . . . . . . . . . . . . . . . . The 3-D plot of the inverter switching threshold voltages, Vm , as the function of PMOS and NMOS transistor widths . . . . . . . . . . . . . . 3.4 3.5 3.6 3.7 3.8 Two 6-bit TIQ comparators produced by two design techniques . . . . . An example of the SSV technique . . . . . . . . . . . . . . . . . . . . . . Gain booster propagation delay result vs. gate length . . . . . . . . . . Gain booster voltage gain result vs. gate length . . . . . . . . . . . . . . The two steps for TC-to-BC encoder . . . . . . . . . . . . . . . . . . . .

32 34 36 37 38 39

xii 3.9 ROM type encoder of a 3-bit ADC . . . . . . . . . . . . . . . . . . . . . 40 41 44 46 47 48 50 54 55 60 62 65 68 70 71 75 76 77 79 80 82 83

3.10 Example of the 3-bit fat tree encoder . . . . . . . . . . . . . . . . . . . . 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Layout of a 8-bit TIQ ash ADC with fat tree encoder . . . . . . . . . . DC simulation results of a 6-bit TIQ ash ADC . . . . . . . . . . . . . . Transient results of a 9-bit TIQ ash ADC (1) . . . . . . . . . . . . . . Transient results of a 9-bit TIQ ash ADC (2) . . . . . . . . . . . . . . Chip layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power consumption in the 6-bit ADCs . . . . . . . . . . . . . . . . . . . FFT at fin =1 MHz in 6-bit ADC . . . . . . . . . . . . . . . . . . . . . . Relative currents used by each component . . . . . . . . . . . . . . . . . DNL and INL of the 8-bit TIQ ash ADC with 0.50 m . . . . . . . . .

4.10 DNLs and INLs of the two 6-bit TIQ comparator . . . . . . . . . . . . . 4.11 Two encoders in the TIQ ash ADC . . . . . . . . . . . . . . . . . . . . 4.12 Equipments for testing prototype chips . . . . . . . . . . . . . . . . . . . 4.13 Die photo of a chip fabricated with 0.25 m . . . . . . . . . . . . . . . . 4.14 Oscilloscope outputs of 0.25 m ADCs . . . . . . . . . . . . . . . . . . . 4.15 DNL and INL of the 6-bit low power based ADC . . . . . . . . . . . . . 4.16 Die photo of a chip fabricated with 0.18 m . . . . . . . . . . . . . . . . 4.17 Oscilloscope outputs of 0.18 m ADCs . . . . . . . . . . . . . . . . . . . 4.18 Noise eects on the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 FFT spectra of measured and ideal data . . . . . . . . . . . . . . . . . . 4.20 Die photo of a chip fabricated with 0.50 m . . . . . . . . . . . . . . . .

xiii 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Active mode or standby mode selector circuit . . . . . . . . . . . . . . . The power and resolution adaptive ADC . . . . . . . . . . . . . . . . . . The precision control logic . . . . . . . . . . . . . . . . . . . . . . . . . . VLSI layout of the PRA-ADC . . . . . . . . . . . . . . . . . . . . . . . . Power reduction comparison . . . . . . . . . . . . . . . . . . . . . . . . . Resolution switching and switching overhead time . . . . . . . . . . . . 86 87 88 89 91 92 96 98 100 104 105 109 111 113 115 117

Power management method with TIQ ash ADC . . . . . . . . . . . . . 6-bit ADC simulation result with power management method . . . . . . Power dissipation vs. frequency . . . . . . . . . . . . . . . . . . . . . . . SPICE simulation result with 0.07 m ADC . . . . . . . . . . . . . . . . Linearity errors of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . Schematic of the current mirror and the dierential pair [34] . . . . . . . ADC architecture using the QV comparator . . . . . . . . . . . . . . . . Schematic of the QV comparator and its voltage transfer characteristic . The 8-bit QVC ash ADC layout used two cascading QV comparators . The SPICE simulation result of the 8-bit QVC ash ADC . . . . . . . .

Summary chart of comparing the QVC ash ADC with the TIQ ash ADC 121

xiv

Acknowledgments

First of all, I would like to express my sincere thankfulness to my thesis advisor, Dr. Kyusun Choi, for his guidance, patience, encouragement, and support during my stay at Penn State. I would also like to thank the committee members, Dr. Mary Jane Irwin, Dr. Vijaykrishnan Narayanan, and Dr. Charles L. Croskey, for their time in reviewing my thesis. Next, I am thankful to the Korean Army and the Korea Military Academy for their nancial support and for giving me the chance to study abroad. Especially, I am grateful to Dr. Jang Koon Shin, the former Head of the Department of Computer Science at the Korea Military Academy, for his guidance when I prepared my PhD study. Thanks also go to Professor Eun Jae Choi, Dr. Min Young Ra, and Dr. Myoung Ho Oh for their valuable comments and encouragement. I specially appreciate Daegyu Lee, Jahan Ghaznavi and Dr. Jongsoo Kim, professor of the Department of Electrical Engineering at the University of Ulsan, for their help in chip design and fabrication and also Steven M. Brown for his proofreading of my thesis. My special thanks go to the other students in Microsystems Design Lab (MDL) and in Mixed Signal Chip Design Group for their friendship and all of their help. Also, I wish to thank the Device Group at UC Berkeley which provided the 0.07 m the Berkeley Predictive Technology Model (BPTM) SPICE model. I am also grateful to the Department of Computer Science and Engineering at Penn State for supporting me as a teaching assistant. I truly thank Vicki Keller for her

xv help and support. Also, I would like to thank all Korean students in the Department of Computer Science and Engineering at Penn State for their friendship and for sharing their time playing tennis and racket ball. During my stay at Penn State, I made my religious faith strengthen from the Bible study with members of Korean Catholic Community. My special thanks go to Fr. Youngchun Kim for leading that Bible study and for teaching me how to pray. I am indebted to the Almighty God during my study. Thanks God! Finally, my greatest thanks go to my family. I would like to thank my parents and my sister in Korea for their patience, support, and love during this long graduate study. As for my children, Hosoo Yoo and Jiwoo Yoo, I am very thankful to them for always believing in me. I would like to express my deepest gratitude to my wife, Seonghye Yoon who has generously and consistently provided me the endless support and love. This work was supported in part by Pittsburgh Digital Greenhouse (EDTD00-2) through a grant from the Commonwealth of Pennsylvania, Department of Community and Economic Development.

Chapter 1

Introduction

The minimum channel length of the transistor will be scaled down to 0.065 m in 2007 according to the roadmap of semiconductors [44]. In addition to this downscaling, todays system-on-chip (SoC) trend forces analog and mixed-signal integrated circuits (ICs) to be integrated with complex digital processors and memory on a single chip - called complete SoC or digital and mixed-signal (D/MS) SoC. At present, there are many demands on the complete SoC in wireless and broadband communications wireless networking (WLAN, voice/data communication, and Bluetooth), wired communication (WAN and LAN), and consumer electronics (DVD, MP3, digital cameras, video games, and so on). Therefore, as one of the mixed-signal ICs, analog-to-digital converters (ADCs) have to follow this complete SoC trend. This chapter introduces the challenges in designing ADCs and possible solid-state technologies for the complete SoC trend.

1.1

Challenges in Designing ADCs for SoC


There are many challenges for ADCs to be adaptable for SoC implementation

with current mixed-signal technology. The major considerations in designing ADCs for the complete SoC are high speed, low power, and low voltage.

2 In terms of high speed, presently 0.13 m CMOS technology allows processor speeds in excess of 2.4 GHz. However, the sampling speed of ADCs fabricated with an advanced BiCMOS process was around 200 mega samples per second (MSPS). Recently, one of the major ADC foundries has produced high speed ADCs with a bipolar process operating up to 1.5 giga samples per second (GSPS) [33] for digital oscilloscopes, digital RF/IF signal processing, direct RF down-conversion, and radar/ECM systems. This ADC produced by Maxim Integrated Products has enough speed for SoC implementation, but the price is too expensive because it uses bipolar solid-state technology. Both cost and high speed operation are limitations of the complete SoC. Accordingly, to remove the speed gap between a processor and an ADC in the complete SoC implementation, an ADC architecture must not only be fast but also cheap. The next challenge is low power consumption. In the portable device market, reducing the power consumption is one of the main issues. ADCs should be integrated with digital circuits on a single chip for the portable devices. All battery powered devices are now being designed to include low power techniques to prolong the battery life. Similarly, ADCs need a low power architecture or a low power technique. Low voltage operation is one of the dicult challenges in the mixed-signal ICs. The down-scaling of the minimum channel length to 0.065 m results in the reduction of the power supply voltage to 0.7 V . However, the minimum supply voltage for the analog circuits predicted in SIA Roadmap [44] does not follow the digital supply voltage reduction. A mixed-signal circuit designer faces a great challenge when designing an ADC that operates at low voltage because of the relatively high threshold voltage of the transistors. As a result, an ADC should be operated in a small voltage range.

3 The main motivation of this thesis is to design an ADC that will allow on-chip direct digitization of a wideband RF signal. One of the major challenges in developing the complete SoC product for the wireless digital network market is the integration of radio frequency (RF) analog circuit devices, which are mostly passive discrete devices. Eventually, we want to replace the passive devices with active devices. We also want to replace analog designs with full-digital implementations. To do this, a suitable ADC architecture, concentrating on high speed, for the complete SoC should be devised.

1.2

Solid-State Technology
The type of solid-state technology used to implement the converter also aects the

speed of an ADC. Three dierent types of solid-state technologies are currently used for high speed ADC implementations: CMOS technology, bipolar technology, and Gallium Arsenide (GaAs) technology. GaAs technology [6, 45, 46, 55] is the fastest of the three, and CMOS technology is the slowest. The fastest ADCs are implemented with ash type architecture using the GaAs technology. The current GaAs technology is not compatible with the silicon based CMOS technology, however, which makes it very dicult to realize the single-chip system solution targeted at by the current SoC trend. Bipolar technology [33] allows faster operation and is compatible with the CMOS technology. However, BiCMOS technology requires more processing steps and higher cost compared to standard CMOS technology. Therefore, mixed-signal circuit implementation using only the standard CMOS technology is the preferred choice for SoC products. Hence, we propose a high speed CMOS ash architecture [8, 52, 57, 70] with low power consumption, which is featuring the Threshold Inverter Quantization (TIQ)

4 technique. The TIQ technique allows greater ADC speed using the standard CMOS logic circuitry preferred for SoC implementation. The main advantage of the TIQ based CMOS ash ADC (TIQ ash ADC) design is a simpler comparator design. The idea is to use digital inverters as analog voltage comparators. This eliminates the need for high-gain dierential input voltage comparators that are inherently more complex and slower than the digital inverters. The TIQ ash ADC [67, 69, 64] also eliminates the need of reference voltages, which require a resistor ladder circuit. This simplicity in the comparator part provides both high speed and low power consumption at the same time. Moreover, it allows a complete ADC to be implemented using the standard CMOS logic technology, making the featured ADC ideal for a complete SoC implementation. On the other hand, the ADC input range varies due to process parameter changes from one fabrication to another, and the single ended inverter comparator is more susceptible to noise. These two criteria must be carefully considered to obtain a successful TIQ ash ADC implementation. The detailed architecture of the TIQ ash ADC will be described in Chapter 3.

1.3

Thesis Overview
This thesis is organized as 7 chapters. The rst chapter introduces the challenges

in designing ADCs for the complete SoC. Chapter 2 provides the necessary background on ADCs including ADC specications and several conventional ADC architectures. Chapter 3 rst investigates the CMOS inverter and then describes the proposed ash ADC utilizing TIQ comparator. Each component in the TIQ ash ADC will be explained in detail. Chapter 4 presents simulation results and measurements of the TIQ ash ADC.

5 Chapter 5 provides a new power and resolution adaptive ash ADC (PRA-ADC) and a power management method for the TIQ ash ADC for low power applications with the TIQ comparator. Chapter 6 introduces a new comparator, the Quantum Voltage (QV) comparator, for the next generation deep sub-micron low voltage CMOS ash ADC. Chapter 7 summarizes the work completed in this thesis and compares the TIQ ash ADC with other ADCs. Future work for the ADC is also described.

Chapter 2

A/D Converter Background

This chapter rst overviews commonly used ADC parameters to describe the performance of ADCs. Next, the most popular ADC architectures at the present time are introduced and compared to each other for design considerations of ADCs.

2.1

ADC Parameters
The parameters that show the performance of an ADC can be obtained from the

data sheets of the ADC [33, 54]. There are many parameters to understand the performance of an ADC, and often these parameters are poorly dened. To comprehend the meaning of them, we should check the standard for terminology and denitions of ADCs. Some relevant standards have been published by organizations such as IEEE [17], Texas Instruments [54], and Maxim Integrated Products [29]. These standards are very useful for estimating and comparing ADCs. Also, most published materials including books and papers concerned with ADCs use the parameters from the standards to describe the ADCs performance. Therefore, in this section some of major parameters, which are classied by two categories, static parameters and dynamic parameters, are dened for easier understanding of this thesis.

7 2.1.1 Static Parameters The static parameters describe the errors between the actual points and the ideal/theoretical points in the staircase transfer function of an ADC when it is converting DC signals. Figure 2.1 shows the staircase transfer function of an ADC. The actual characteristic does not match with the ideal characteristic in both the reference voltage and the width of horizontal steps, as shown in Figure 2.1. These dierences are essentially due to oset error, gain error, dierential non-linearity error (DNL), and integral non-linearity error (INL).

Output Code

111 110 101 100 011 010 001 000

Actual characteristic

Ideal characteristic

V1

V2

V3

V4

V5

V6

V7

Analog Reference Voltage

Fig. 2.1. Staircase transfer function of an ADC

8 2.1.1.1 Oset and Gain Error

The oset error, Eof f set , is dened [54] as the dierence between the nominal and actual oset points. The denitions of other materials [17, 29, 15, 9, 26, 36] are a little bit dierent, but the meaning of the oset error is always the same. Generally speaking, it means the dierence between the rst ideal reference voltage, Vmin in Figure 2.1, and the rst actual reference voltage. This oset error can be mathematically formalized. (Vmin Vmin ) VLSB

Eof f set =

(2.1)

where Vmin is the rst reference voltage of the actual characteristic, and VLSB is a quantization step. The gain error, Egain , is dened as the dierence between the nominal and actual gain point after the oset error has been eliminated. That is, it indicates the slope dierence between the lines - the dashed line shown in Figure 2.1 - after the oset error has been adjusted to zero. The equation of the gain error is as follows: (Vmax Vmin )

Egain =

(Vmax Vmin )

100

(2.2)

where Vmax and Vmax stand for the last reference voltages of the transfer function in the actual characteristic and the ideal characteristic, respectively. The gain error is usually presented by the percentage of the full scale range of the analog input voltage, VF SR = Vmax Vmin . The denitions of the oset and gain error are summarized in Figure 2.2, which is modied from the original gure [32].

9
Output Code

gain error Ideal line y = ax

Actual line y = cx + b offset error calibrated y = cx b offset error Analog Reference Voltage

Fig. 2.2. Oset and gain errors, after [32]

With the calibration of the oset error, there will be no missing output codes, but the transfer function will be shifted. However, the gain error calibration either reduces the dynamic voltage range in a positive gain error - the slope of the actual line is higher than the one of the ideal line - or loses some output codes in the case of a negative gain error. The calibration of the oset and gain error can be done by a microcontroller or a digital signal processor (DSP).

2.1.1.2

Dierential Non-Linearity Error (DNL)

The dierential non-linearity error (DNL) - sometimes this is simply called dierential linearity (DLE) - describes how far the actual step size is from the ideal step in the least signicant bit (LSB) unit, after elimination of the gain error. To measure the

10 DNL, the following equation [30] is used. V Vk DN L(k) = k+1 1 LSB VLSB

(2.3)

where VLSB = VF SR /2n 2 for an n-bit ash ADC. Therefore, the ideal value of step width is 1 LSB since its DNL is 0, according to Equation 2.3. Figure 2.3 shows the DNL in an example ADC. We can see two dierent DNLs in Figure 2.3. DNL(2) shows

Output Code

111 110 101 100 011 010 001 000 V1

Actual characteristic

DNL(2) = - 0.5 LSB Ideal characteristic

DNL(3) = + 1.5 LSB V2 V3 V4 V5 V6 V7 Analog Reference Voltage

Fig. 2.3. Dierential non-linearity error (DNL)

-0.5 LSB, which means the step width is half of the ideal LSB, but in this case we can still get no missing code. On the other hand, DNL(3) illustrates that there is no output code 100 because of its step width. Hence, there will be the possibility for an ADC to become non-monotonic if the DNL is greater than 1 LSB.

11 2.1.1.3 Integral Non-Linearity Error (INL)

In the DNL calculation, the DNL only deals with two adjacent actual reference voltages, no matter how far away from the ideal reference voltages. However, the integral non-linearity error (INL) - sometimes this is simply called integral linearity (ILE) - checks the dierence between the actual reference voltages and the ideal reference voltages at all transition points. Therefore, the INL shown in Figure 2.4 describes the overall shape of an ADC transfer characteristic from the straight line drawn between end points after

Output Code

111 110 101 100 011 010 001 000 V1

Actual characteristic

INL(3) = - 1.0 LSB Ideal characteristic

INL(2) = - 0.5 LSB V2 V3 V4 V5 V6 V7 Analog Reference Voltage

Fig. 2.4. Integral non-linearity error (INL)

both the oset error and the gain error are nullied. Equation 2.4 formally denes the

12 INL [30]. V Vmin IN L(k) = k k LSB VLSB

(2.4)

A program for calculating DNL and INL with Equation 2.3 and Equation 2.4 and for drawing their plots with MATLAB are shown in Appendix A.

2.1.2

Dynamic Parameters The static parameters are determined by DC Tests, but the dynamic parameters

are concerned with AC specications such as resolution, sampling frequency, input signal frequency, and so on. The main parameters to review are the signal-to-noise ratio (SNR), the signal-to-noise and distortion ratio (SINAD), the eective number of bits (ENOB), the total harmonic distortion (THD), and the spurious-free dynamic range (SFDR). These dynamic parameters are usually extracted from the Fast Fourier Transform (FFT) test - transforming time domain signals into the frequency domain to get the detailed signal analysis.

2.1.2.1

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio of signal power to noise power. With the SNR, we can easily know how much noise is in an ADC. Generally, the SNR is expressed in decibel (dB) as in the following equation [2]: ARM S, signal ARM S, noise

SN R = 20 log10

= 6.02n + 1.76 dB

(2.5)

13 where ARM S,signal and ARM S,noise are the root mean square (RMS) amplitude for the signal and the noise, respectively. The signal means the fundamental amplitude signal, and the noise does not include the signicant harmonics, which are usually from the second to the fth highest amplitudes. The detailed derivation of Equation 2.5 is described in [9]. This equation shows the theoretical limits of the SNR for n-bit resolution, for example, 50 dB is the maximum SNR for an ideal 8-bit ADC.

2.1.2.2

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD, SNDR, or TDE for total dynamic error [36]) is the ratio of signal power to noise power including the signicant harmonics. Since the SNR does not include the signicant harmonics, the SNR is usually larger than the SINAD. Mathematically, the SINAD is formalized as follows: ARM S, signal ARM S, noise+harmonics

SIN AD = 20 log10

dB

(2.6)

2.1.2.3

Total Harmonic Distortion (THD)

The total harmonic distortion (THD) is the ratio of noise power - only the signicant harmonics - to the signal power. This parameter is caused by the INL, since a sinusoid input signal will be distorted after passing through a non-linear transfer function. For this reason, harmonic tones will be created [36]. The THD can be expressed as ARM S, harmonics ARM S, signal

T HD = 20 log10

dB

(2.7)

14 2.1.2.4 Eective Number of Bits (ENOB)

The eective number of bits (ENOB) shows an ADCs performance at a specic input frequency. The ENOB is really related to the input frequency. If the input frequency is increased, then the ENOB is degraded because all of the noises are increased including the THD. The ENOB can be generally calculated with SINAD as shown in Equation 2.8 [29]. SIN AD 1.76 6.02

EN OB =

(2.8)

2.1.2.5

Spurious-Free Dynamic Range (SFDR)

The parameter that shows the dynamic range of an ADC is the spurious-free dynamic range (SFDR). The SFDR is the ratio of the signal power to the largest harmonic, the second signicant harmonic. It can be expressed as ARM S, signal ARM S, 2nd harmonic

SF DR = 20 log10

dB

(2.9)

We can compute the SFDR as the dierence between the amplitude of fundamental and the amplitude of second signicant harmonic in the FFT plot. This SFDR is the important factor in distinguishing the input signal from undesirable spurs.

2.2

ADC Architectures
At present, there exists a variety of ADCs with dierent architectures, resolu-

tions, sampling rates, power consumptions, and temperature ranges. These ADCs are

15 used in dierent applications - from mobile communication devices to measure equipment - according to the characteristics of ADCs. Since the performance - sampling rate, resolution, and power consumption - of an ADC is basically determined by its architecture, one single ADC type cannot cover all applications. For instance, ash (parallel) ADCs can be used in high speed and low resolution applications. Because of its parallel architecture, all conversions are done in one cycle with many comparators. On the other hand, a successive approximation ADC can be used in low-speed and high-resolution applications since the conversions are done in many cycles with only one comparator. Therefore, it is important to properly choose an ADC for each particular application. Among the variety of ADC architectures, there are four most popular ADC architectures presently used. These are as follows: Flash: The ash ADC operates at very high speed with lower resolution. It is also called a parallel ADC due to its parallel operation. Pipelined: The pipelined ADC can operate at a high speed, but it is slower than the ash. It covers a wide range of applications because of its exible resolution and speed. Successive approximation register (SAR): The SAR ADC is suitable for low power and medium-to-high resolution applications with medium speed. Sigma-delta (): The ADCs are used for high resolution and low speed applications.

16 Figure 2.5 shows the trade o between resolutions and sampling rates of the above popular ADC architectures. The application ranges for each architecture are also shown. In the following sections, the four popular ADC architectures are briey addressed.

Resoultion (bits)

Sigma-Delta 22 18 14 10 6 2 100 1K 10K 100K 1M


Industrial process control Portable instrumentation Smart transmitters Remote data acquisition Weigh scales Data / signal acquisition Pen digitizers & industrial controls Portable / battery-powered devices

SAR Pipelined

Flash
Video, HDTV Medical & CCD imaging xDSL, Cable modem, fast Ethernet

Direct RF Downconversion & RF / IF processing High speed data acquisition Digital Oscilloscopes & Radar / ECM systems Wideband Satellite receivers

10M

100M

1G

Sampling rate (Hz)

Fig. 2.5. Tradeo between resolutions and sampling rates

2.2.1

Flash ADC The ash ADC is known for its fastest speed compared to other ADC architec-

tures. Therefore, it is used for high-speed and very large bandwidth applications such as radar processing, digital oscilloscopes, high-density disk drives, and so on. The ash ADC is also known as the parallel ADC because of its parallel architecture. Figure 2.6 illustrates a typical ash ADC block diagram. As shown in Figure 2.6, this architecture needs 2n 1 comparators for an n-bit ADC; for example, a set of 63

17
Analog input V2 n -1 0

1 V2 n -2 1 V2 n -3 Encoder Binary output

1 V1

Fig. 2.6. Block diagram of a ash ADC

comparators are used for 6-bit ash ADC. Each comparator has a reference voltage that is provided by an external reference source. These reference voltages are equally spaced by VLSB from the largest reference voltage (V2n 1 in Figure 2.6) to the smallest reference voltage V1 . An analog input is connected to all comparators so that each comparator output is produced in one cycle. The digital output of the set of comparators - called the thermometer code - is changed into a binary code through the encoder. The ash ADC architecture has high speed conversion due to its parallel structure. However, the ash ADC needs a large number of comparators as the resolution increases. For instance, a 6-bit ash ADC needs 63 comparators, but 1023 comparators are needed for a 10-bit ash ADC. This exponentially increasing number of comparators requires a large die size and a large amount of power consumption. To compensate for the disadvantages of the ash architecture, a half-ash architecture (or sub-ranging

18 architecture) can be implemented with two half resolution ash ADCs and a digital-toanalog converter (DAC). Figure 2.7 shows the block diagram of an 8-bit sub-ranging ADC. The rst most signicant bits (MSBs) are obtained through the coarse 4-bit ash

Analog input

S/H

Coarse 4-bit Flash ADC

DAC

Fine 4-bit Flash ADC

Fist half MSBs (4 bits)

Rest half LSBs (4 bits)

Fig. 2.7. Block diagram of an 8-bit sub-ranging ADC

ADC. Then a residue is created and converted to an analog signal in the DAC. After subtracting the analog residual from the input signal, the last 4 LSBs can be obtained through the ne 4-bit ash ADC. Finally, we have obtained a full 8-bit binary output with two steps of conversion. Therefore, we can convert an analog signal with a total of 30 comparators instead of 255 comparators. There are advantages in architecture complexity and power consumption, but the speed is less than for the typical ash ADC. Also, both a sample-and-hold (S/H) circuit and DAC are necessary, while the S/H is not mandatory in the typical ash ADC.

19 2.2.2 Pipelined ADC The pipelined ADC architecture is a type of sub-ranging ADC introduced in the previous section. This architecture is implemented with at least two or more lowresolution ash ADCs as shown in Figure 2.8. Each stage has a S/H circuit to hold the amplied residue from the previous stage. Then, the input is fed to the low resolution ash ADC to generate a segmented binary output. Like the sub-ranging ADC, the segmented output is changed to an analog signal and is subtracted from the input. This residue is amplied in an amplier to send to the next stage. The segmented binary outputs from each stage are time-aligned with a shift register. The nal binary output is obtained after passing through digital error correction logic. This conversion process in the pipelined ADC is shown in Figure 2.8.

Amplified input

S/H

k-bit Flash ADC k-bit Analog input S/H Stage 1 k-bit Stage 2 k-bit

k-bit DAC

Stage m k-bit Shift register n-bit

Digital error correction logic n-bit

Fig. 2.8. Block diagram of a pipelined ADC

20 As shown in Figure 2.8, the internal ash ADCs have low resolution that depends on the application. Hence, the pipelined ADC can be applied from high speed applications with low resolution to low speed applications with high resolution. Also it can be modied for low power applications. This is why the pipelined ADC is very popular today.

2.2.3

Successive Approximation ADC The successive approximation register (SAR) - commonly called successive ap-

proximation converter - is widely used in industrial control applications and batterypowered applications because of its good balance between speed and power consumption. Figure 2.9 illustrates the architecture of the SAR ADC that consists of one comparator, a DAC, and a successive approximation register. The conversion algorithm is similar to

Vin Analog input S/H Vref

Successive Approximation Register (n -bit)

n -bit

n -bit DAC

Fig. 2.9. Block diagram of a successive approximation (SAR) ADC

the binary search algorithm. First, the reference voltage, Vref , provided by DAC is set

21 to the
VF SR to obtain the MSB. After getting the MSB, the SAR moves to the next 2

V SR bit with F4 or 3 VF SR depending on the result of the MSB. If the MSB is 1, then 4

Vref = 3 VF SR , otherwise Vref = 4

VF SR 4 . This sequence will continue until the LSB

is obtained. Figure 2.10 shows how the reference voltages are implemented in a 3-bit

binary output 111 V7 110 V6 101 V5 100 Vin V4 011 V3 010 V2 001 V1 V7 V6 V5 V4 V3 V2 000 V1

Fig. 2.10. Reference voltage tree in a 3-bit SAR ADC

SAR ADC. Note that V7 is the largest reference voltage, and V1 is the smallest reference voltage. To get a binary output, 3 comparisons are needed, while 7 comparisons are needed in the ash architecture. For a 10-bit resolution, the SAR only needs 10 comparisons with a single comparator, but the ash ADC needs 1023 comparisons with 1023 comparators. There are large savings in power consumption, but the SAR ADC needs n cycles for n-bit resolution, while the ash ADC and the pipeline ADC need 1 cycle

22 and m (number of stages) cycles, respectively. Therefore, this SAR architecture is very attractive for low power applications with a medium sampling rate.

2.2.4

ADC The ADC is also called an oversampling ADC. It consists of two main blocks.

One is the modulator that includes an integrator, a comparator, and a single-bit DAC. The other is a digital lter that changes the output to binary code with ltering. Its block diagram is shown in Figure 2.11. The output of the 1-bit DAC

Modulator
Analog input

f
Integrator

Digital filter

n -bit

1-bit DAC

Fig. 2.11. Block diagram of a ADC

is subtracted from the input signal, integrated, and then converted to a 1-bit binary output. This single bit again goes to the DAC to be processed. This closed-loop process is performed at a very high oversampled rate [4]. The ADC is very popular for low bandwidth with high resolution applications because of the capability of noise shaping

23 [4]. But, the latency is much greater than for the other ADC architectures, and this restricts the application of the ADC.

2.2.5

Summary of ADC Architectures The most popular ADC architectures have been reviewed in the previous sections.

The ash ADC architecture is the fastest, the SAR ADC architecture has been developed for low power applications, the ADC is very useful for high resolution applications, and the pipelined ADC can be applied for various applications depending on how the sub ash ADCs are organized. Each ADC architecture has tradeos among speed, resolution, and power consumption. In summary, Table 2.1 provides the characteristics of four popular ADC architectures [4, 31]. In the third column, sps stands for samples per second. The m shown in the forth column is the number of stages in the pipeline architecture, and n indicates the resolution of the ADC.

24

Table 2.1. Summary of ADC architectures

Architecture

Resolution (bits)

Speed (sps) 250M - 1G

Latency (cycle) 1

Comments

Flash

< 10

- extremely fast - high input bandwidth - highest power consumption - expensive - large die size

Pipelined

8 - 16

1M - 100M

- high throughput rate - low power consumption - on-chip self calibration - require 50 % duty cycles - needs minimum clock frequency

SAR

10 - 18

76K - 5M

- high resolution & accuracy - low power consumption - few external components - limited sampling rates - low input bandwidth

> 14

> 200K

large

- high resolution - high input bandwidth - digital on-chip ltering - external S/H - limited sampling rates

25

Chapter 3

TIQ Flash ADC

This chapter provides detailed information about the proposed TIQ ash ADC including its major components. Also important characteristics of the CMOS inverter are introduced for simulation and analysis of the TIQ ash ADC, which will be described in Chapter 4. The proposed ash ADC features the threshold inverter quantization (TIQ) technique for high speed and low power using standard CMOS technology that is compatible with microprocessor fabrication. Figure 3.1 shows the block diagram of the TIQ ash ADC. The use of two cascading inverters as a voltage comparator is the reason for the techniques name. The voltage comparators compare the input voltage with internal reference voltages, which are determined by the transistor sizes of the inverters. Hence, we do not need the resistor ladder circuit used in a conventional ash ADC shown in Figure 2.6. The gain boosters make sharper thresholds for comparator outputs and provide full a digital output voltage swing. The comparator outputs - the thermometer code are converted to a binary code in two steps through the 01 generator and the encoder as shown in Figure 3.1.

26

Analog Input Voltage max Vm

Thermometer Code

1-out-of-n Code

Binary Code

MSB

Vin

TIQ Comparator

Gain Booster

01 Generator

Encoder LSB

min Vm

Fig. 3.1. Block diagram of the TIQ ash ADC

27

3.1

TIQ Comparator
The comparator is the most important component in the ADC architecture. Its

role is to convert an input voltage (Vin ) into a logic 1 or 0 by comparing a reference voltage (Vref ) with the Vin . If Vin is greater than Vref , the output of the comparator is 1, otherwise 0. Commonly used comparator structures in CMOS ADC design are the fully dierential latch comparator [3] and dynamic comparator [70, 56]. The former is sometimes called a clocked comparator, and the latter is called a auto-zero comparator or chopper comparator. To achieve high speed, such comparators are usually implemented with bipolar transistor technology. For SoC implementation in this case, BiCMOS technology would be necessary to integrate both a high speed ADC and a digital signal process on the same substrate. The TIQ comparator uses two cascading CMOS inverters as a comparator for high speed and low power consumption. Tangel [53] used this TIQ comparator for implementing a high speed ash ADC. The proposed TIQ comparator that is described in this thesis has been developed not only for higher speed but also for higher resolution.

3.1.1

CMOS Inverter as a Comparator The inverter threshold (Vm ) is dened as the Vin = Vout in the VTC of an

inverter [41, 43]. Mathematically,

Vm =

r VDD VT p 1+r

+ VT n

with r =

kp kn

(3.1)

28 where VT p and VT n represent the threshold voltages of the PMOS and NMOS devices, respectively. Figure 3.2 shows the schematic of an inverter and its VTC from the simulation. At the rst inverter, the analog input signal quantization level is set by Vm

* hspice file created from inv.ext - technology: mmi25

2.6 2.4 2.2 2

Vb Vout1 Va Vin

Wp / Lp

Wp / Lp
Voltages (lin)

1.8 1.6 1.4 1.2 1 800m

Vin

Vout1 Wn / Ln

Vout Wn / Ln

600m 400m 200m 0 800m

Vout

Vin = Vout

600m

1 1.2 1.4 Voltage X (lin) (VOLTS)

1.6

1.8

(a) Inverter schematic diagram

(b) Inverter VTC

Fig. 3.2. Inverter schematic and VTC

depending on the W/L ratios of PMOS and NMOS. The second inverter is used to increase voltage gain and to prevent an unbalanced propagation delay. In Figure 3.2, the slope of Vout is shown larger than the one of Vout1 . The inverter threshold depends on the transistor sizes. The inverter VTC Va and Vb show the dierence from the VTC of Vout . With a xed length of the PMOS and NMOS devices, we can get desired values of Va and Vb by increasing only the width of the PMOS and NMOS transistors, respectively.

29 This result can be conrmed by the following equation of the inverter threshold [43].
p Wp n Wn

VDD VT p 1+
p Wp n Wn

+ VT n (3.2)

Vm =

where p and n are the electron and hole mobility, respectively. To derive Equation 3.2, we assume that both transistors are in the active region, the gate oxide thickness (Cox )for both transistors is the same, and the lengths of both transistors (Lp and Ln ) are also the same. From Equation 3.2, we know that Vm is shifted depending the transistor width ratio (Wp /Wn ). That is, increasing Wp makes Vm larger, and increasing Wn results in Vm being smaller on the VTC. This changing of the widths of the PMOS and NMOS devices with a xed transistor length is the idea of the TIQ comparator. We can use the inverter threshold voltage as an internal reference voltage to compare the input voltage. However, to use the CMOS inverter as a voltage comparator, we should check the sensitivity of Vm to other parameters, which are ignored in Equation 3.2, for correct operation of the TIQ ash ADC. In a mixed-signal design, the ignored parameters - threshold voltages of both transistors, electron and hole mobility, and power supply voltage - are not xed at a constant value. The following sections will discuss the sensitivity to process, temperature, and power supply voltage.

3.1.1.1

Sensitivity to Process

For implementing the TIQ comparator, the BSIM3 (HSPICE Level 49) MOS transistor model that includes about 93 parameters to dene a transistor behavior is

30 used. However in reality, there are many parameters. We cannot be sure that the simulation results with the BSIM3 MOS transistor model will be exactly matched with the measurement results. Therefore, we need a more complete transistor model for the inverter threshold sensitivity to reduce the gap between the simulation results and the measurement results. Moreover, if we apply another transistor model that was not used in our ADC design, the inverter threshold sensitivity will be critical in the TIQ comparator. Since process parameters change from one fabrication to another fabrication, the inverter threshold voltage will change. This situation is especially one of major problems for linearity errors of the TIQ comparator that uses Vm as a reference voltage.

3.1.1.2

Sensitivity to Temperature

The inverter threshold voltage also depends on temperature according to the following partial dierential equation [1]. Vm = T 1 1+ dVT n p Wp dT
p Wp n Wn d VT p

(3.3)

dT

n Wn

If the temperature is changed, then the eective mobility, channel length, and threshold voltage of the PMOS (VT p ) and NMOS (VT n ) devices will be aected. Therefore, the inverter threshold will be also changed. The inverter threshold variation with Equation 3.3 has been simulated in [49]. The simulation results show that large ratio of Wp /Wn is more sensitive to temperature variation. For temperature variation simulation, the range of temperature - from 40o C to 85o C will be applied in this thesis.

31 3.1.1.3 Sensitivity to Power Supply Voltage

Since the CMOS inverter has a single-ended input, it is more susceptible to power supply voltage noise than the dierential comparator. The partial dierential equation for power supply voltage [53] can be expressed by

Vm = VDD

1 1+
n Wn p Wp

(3.4)

Like Equation 3.2, the lengths of PMOS and NMOS devices are assumed to be equal. This equation also shows that the larger ratio of the Wp /Wn the more sensitive Vm is to power supply voltage variation. This fact has been proved by simulation [49]. Generally, a 5% power supply range is used in a commercial chip. This rejection ratio will be used in the power supply voltage variation simulation.

3.1.2

Comparator Generation and Selection Method The TIQ ash ADC requires 2n 1 dierent size comparators and we need to

eectively nd their sizes to correctly implement the TIQ comparators. However, choosing the needed Vm from many candidates for comparators and generating the selected comparators with a custom layout are dicult jobs. For example, a 10-bit ash ADC would need 1023 TIQ comparators, too many for manual layout designs, while other ADCs use a single comparator design and simply duplicate it for 2n 1 times. We have developed a customized program that automatically generates the TIQ comparators with an optimal selection approach.

32 A CMOS inverter consists of one PMOS and one NMOS transistor, with the inverter switching threshold voltage depending upon the transistor sizes. If one xes the length of both the PMOS and NMOS transistors at a constant size, one can obtain dierent inverter threshold voltages by simply varying the transistors widths. Figure 3.3 shows the 3-D plot of Vm as the function of PMOS and NMOS transistor widths.

2 1.8 1.6 Vm (V) 1.4 1.2 1 0.8 0.6 0 NMOS (um) 5 10 0 5 10 20 15 PMOS (um)

Fig. 3.3. The 3-D plot of the inverter switching threshold voltages, Vm , as the function of PMOS and NMOS transistor widths

To design an n-bit ADC, one needs 2n 1 equal quantization voltages, and one must decide on the maximum Vm and the minimum Vm . After deciding the maximum Vm and minimum Vm , one computes the LSB voltage step (VLSB ) by (max. Vm - min. Vm )/(2n 2). There are two dierent design methods [22, 66] for the TIQ comparator for the Vm values shown in Figure 3.3. One method, called the random size variation (RSV) technique, can obtain the 2n 1 reference voltages by selecting the inverter

33 width from the full range of the 3-D surface without considering the relation of adjacent comparators. This method is named zero DNL design method in [22, 66]. The other method, called the systematic size variation (SSV) technique, considers the relation of comparators in selection of the inverter size. This method is named non-zero DNL design method in [22, 66]. Detailed descriptions are given in the following sections.

3.1.2.1

Random Size Variation (RSV) Technique

The random size variation (RSV) technique simply chooses the Vm from the fullrange of the 3-D plot (around 2 million points). This algorithm selects the actual Vm that is the closest the ideal Vm , theoretical points that are exactly spaced by VLSB , regardless of the transistor size relationship with other comparators. This method needs much time to nd a Vm , because it checks all points of the 3-D plot. As a result, all of the internal reference voltages of the 2n 1 comparators are almost equally divided by VLSB . Hence, the DNL (dened by ((Vi+1 Vi )/VLSB ) 1) of this approach is almost zero. A 6-bit TIQ comparator layout produced by the RSV technique is shown in Figure 3.4(a). The increase or decrease of the transistor size is not systematic.

3.1.2.2

Systematic Size Variation (SSV) Technique

In the case of the systematic size variation (SSV) technique, the Vm is selected from a reduced-range of the 3-D plot. The diagonal line shown in Figure 3.3 is the ideal line for this approach. This approach keeps the systematic increasing/decreasing order of transistor sizes. But, the values along the diagonal line are in too small range to nd proper 2n 1 reference voltages. Therefore, the range is expanded around the diagonal

34

Vm63

Vm63

NMOS

NMOS

PMOS

PMOS

Vm1 Vm1 (a) A 6-bit TIQ comparator layout (b) A 6-bit TIQ comparator layout produced by the RSV technique produced by the SSV technique

Fig. 3.4. Two 6-bit TIQ comparators produced by two design techniques

35 line. We obtain the systematic increasing/decreasing comparator transistor sizes shown in Figure 3.4(b) by considering the relation of adjacent comparators. The SSV algorithm determines the best t Vm values around the diagonal line in Figure 3.3, keeping an increasing/decreasing order of transistor sizes. The algorithm also enforces the incremental transistor size step to a certain minimum width (W), which is initially given, for the maximum resolution of the given CMOS technology. The SSV technique uses the following four steps to generate the 2n 1 TIQ comparators: Step 1: Generating a set of inverter sizes roughly following the diagonal line. The maximum Vm , minimum Vm , and W are needed for this step. Step 2: Finding Vm of each inverter produced in Step 1 through HSPICE simulation. This step takes much more time. When we used 5 Sun-Blade 2000 machines at the same time, this step took around 4 hours for nding 28000 points. Step 3: Selecting a set of 2n 1 inverters among the inverters generated in Step 1, whose Vm voltages are the nearest to the ideal one, satisfying the following conditions simultaneously: Does each comparator keep the order of increasing/decreasing transistor sizes? Does the dierences between two adjacent comparators keep at least the W? Step 4: Generating a cell design of the TIQ comparators based on the selected set of inverters in Step 3. With this automatic generation, we can obtain the TIQ comparator layout in a few seconds A 6-bit TIQ comparator manual design takes around 4 hours.

36 Figure 3.5 shows an example of how the SSV technique generates a set of transistor sizes and chooses the best t (optimal) ones among them. From every possible combi-

PMOS

Fig. 3.5. An example of the SSV technique

nation of PMOS and NMOS transistor sizes, the program rst arranges them along the diagonal line. Next, the program selects the optimal combinations by looking up the Vm values of each combination resulted from the HSPICE simulation. The lled black dots are the selected combination of PMOS and NMOS transistor sizes for the TIQ inverters. The simulation results of both RSV technique and SSV technique will be represented in Section 4.1.2.

W W : Arranged combination : Selected combination NMOS

37

3.2

Gain Booster
Each gain booster consists of two cascading inverters with the same circuit as

the comparator, but the transistor sizes of each gain booster are small and identical. The gain booster is used to increase voltage gain of the output of a comparator so that it provides a full digital output voltage swing. Figure 3.6 and Figure 3.7 respectively show the propagation delay and voltage gain of the gain booster over transistor length variation.

6 5 Propagation delay (sec) 4 3 2 1

x 10

0 0

0.5

1.5 2 2.5 Transistor length (um)

3.5

Fig. 3.6. Gain booster propagation delay result vs. gate length

The propagation delays trend is almost exponentially proportional to the transistor length, but the voltage gain follows a logarithm function. Therefore both propagation

38
250

200

Voltage gain

150

100

50

0 0

2 3 Transistor length (um)

Fig. 3.7. Gain booster voltage gain result vs. gate length

delay and voltage gain should be considered together when we choose the size of the gain booster.

3.3

TC-to-BC Encoder
After the comparators produce a thermometer code (TC), the thermometer code

to binary code (TC-to-BC) encoder generally converts it to a binary code (BC) in two steps. The TC is converted to the 1-out-of-n code, using XOR logic. This code is then converted to BC. The two steps for TC-to-BC encoder are shown in Figure 3.8 The most common implementation of the TC-to-BC encoder has been the ROM/PLA circuits [39, 18], however, the TC-to-BC encoder is often the bottle neck of high sampling rate ash ADCs. Alternate encoder designs such as a Wallace tree encoder [19] for 1 GHz sampling rate ash ADC implemented with gallium arsenide (GaAs) technology, a

39
TC-to-BC Encoder Thermometer Code 0 0 1 1 1 1 1 1-out-of-n Code Generator 0 0 1 0 0 0 0 0 1-out-of-n Code Binary Code 1 0 1

ROM/PLA Encoder

Fig. 3.8. The two steps for TC-to-BC encoder

XOR encoder [61] for a 8 GHz rate ADC implementation with silicon-germanium (SiGe) bipolar technology, and a pipeline encoder [27] for a 5 GHz rate ADC implemented with the Josephson-junction super-conduction technology have been used. The following sections describe two encoders: a ROM type encoder and a fat tree encoder. The ROM type encoder is generally used in a ash ADC architecture. To increase the speed of the ash ADC, we propose a new TC-to-BC encoder, the fat tree encoder, that is highly suitable for a high speed and low power CMOS ash ADC.

3.3.1

ROM Type Encoder To convert a 1-out-of-n code to a BC, a ROM can be used. An optimized, with

respect to transistor sizes, NOR ROM circuit was developed to achieve high speed conversion as shown in Figure 3.9. In the TIQ ash ADC, the ROM speed is the predominant factor of the overall ADC speed because the signal delay of the ROM is algorithmically

40

V in V r7
TIQ Comp.
7

V r4 Vr3 Vr2 V r1

TIQ Comp.

TIQ Comp.

TIQ Comp.

TIQ Comp.

Buffer

out2

out1

out0

ROM type encoder

Fig. 3.9. ROM type encoder of a 3-bit ADC

41 O(N ), where N is the number of ROM inputs. Therefore, we need to improve the speed of the encoder with an alternative design, non-ROM type such as [19, 61, 27].

3.3.2

Fat Tree Encoder We propose the fat tree encoder to improve the encoder speed that is the bottle

neck of a ash ADC speed [23, 21]. The main advantage of the fat tree encoder over the other encoders is its high encoding speed and low power consumption. Figure 3.10 shows an example of the 3-bit fat tree encoder. The 1-out-of-8 code, which is the output of the 01 generator, is presented at the leaf nodes (from a7 to a0 ) of the tree. The 3-bit

a7 a6 a5 a4 a3 a2 a1 a0 du d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 1 0 0 0 0 0 0

1 0 0 0 0 0 0 0

d(2:0) 000 001 010 011 100 101 110 111

d2 = (a4 + a5) + (a6 + a7) d1 = (a2 + a3) + (a6 + a7) d0 = (a1 + a3) + (a5 + a7)

Fig. 3.10. Example of the 3-bit fat tree encoder

binary output (d2 , d1 , and d0 ) is located at the root of the tree. The output is obtained by a logical ORing of the leaf nodes depending on the truth table shown on the right

42 in Figure 3.10. When using only 2-input OR gates, 6 OR gate results go to the parent nodes, then nally 4 OR gate results (du , d2 , d1 , d0 ) are obtained. One of those 4 results, du , will be used for the next level of the tree. As shown in the tree, the number of edges increases from leaf to root. So, this new encoder type is named the fat tree encoder. The fat tree encoders signal delay is O(log2 N ) because of its tree architecture. Therefore, it is much faster than the ROM type encoder; for example, there are only 2 OR gate delays in case of 3-bit encoding. Also, all multiple OR gates can be changed to NOR and NAND gates for more ecient implementation. Moreover, the fat tree encoder can be easily pipelined at each height in the tree. Even though it has an advantage in terms of speed of the ADC, it is much more dicult to design and automatically generate than the ROM type encoder. Because the fat tree is 3-dimensional, design automation of the fat tree encoder is one of the challenges for an improved implementation of the TIQ ash ADC.

43

Chapter 4

Experimental Results and Evaluations

In this chapter, we present the experimental results and fabrication results of the TIQ ash ADCs. The TIQ ash ADCs have been designed with three dierent standard CMOS technologies - 0.25 m, 0.18m, and 0.50m - with both MAX and Magic CAD tools. The HSPICE models (BSIM3 level 49) have been used for the experimental simulations. Also, the TIQ ash ADCs have been fabricated three times through the MOSIS service. This chapter will rst show the simulation results then present the fabrication measurements.

4.1

Simulation Results
With three dierent CMOS technologies and three dierent resolutions: 6-bit,

8-bit, and 9-bit, a total of 20 TIQ ash ADCs have been designed, simulated, and fabricated. Also four more TIQ ash ADCs have been designed and simulated with the 0.07 m predictive model from the BPTM in the University of California at Berkeley [5]. Therefore, there are too many layouts and simulation results to show all of them in this thesis. Hence, only the necessary layouts and simulation results will be presented. The ADC layout is shown in Figure 4.1. This layout shows an 8-bit TIQ ash ADC with a fat tree encoder. The layouts of the other ADCs are similar to Figure 4.1 except that layout area diers. Some ADCs use a ROM type encoder instead of the fat

44

01 Generator

Fat Tree Encoder

TIQ Comparator

Gain Booster

Fig. 4.1. Layout of a 8-bit TIQ ash ADC with fat tree encoder

45 tree encoder. In these cases, more regular layouts are shown in the encoder part. The layout of a TIQ ash ADC with ROM type encoder is discussed in Section 4.1.3.

4.1.1

TIQ Flash ADC Performance As shown in Figure 3.2, the inverter threshold voltages (Vm ) vary with transistor

size. Figure 4.2 shows DC simulation results of a 6-bit TIQ ash ADC and shows the uniformity of 63 equally spaced inverter threshold voltage. For a transient operation, the simulation results of a 9-bit TIQ ash ADC with 0.25 m technology are shown in both Figure 4.3 and Figure 4.4. Since the LSB of the 9-bit ADC can not be distinguished

in a page, its simulation results is divided into two gures. Figure 4.3 shows the rst half of the simulation results and Figure 4.4 shows the last half of the simulation results. This 0.25 m 9-bit ADC was recently designed with a fat tree encoder for a fabrication. These gures demonstrate a sampling speed up to 1 GSPS without a missing binary code. The simulation results - sampling rate, power consumption, and layout - of TIQ ash ADCs with 3 dierent technologies are described in following sections.

46

2.6 2.4 2.2 2 1.8 1.6

max. Vm

Voltages (lin)

1.4 1.2 1 800m 600m 400m 200m 0

min. Vm

800m

1.2 1.4 Voltage X (lin) (VOLTS)

1.6

Fig. 4.2. DC simulation results of a 6-bit TIQ ash ADC

47

1.5 Vin d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 0 50n 100n 150n Time (lin) (TIME) 200n 250n 300n

Fig. 4.3. Transient results of a 9-bit TIQ ash ADC (1)

48

1.5 Vin d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 300n 350n 400n 450n Time (lin) (TIME) 500n 550n

Fig. 4.4. Transient results of a 9-bit TIQ ash ADC (2)

49 4.1.1.1 Simulation Results of 0.25 m technology

A total of six TIQ ash ADCs with 0.25 m CMOS technology have been designed with ROM type encoders for fabrication in the same run as shown in Figure 4.5. The transistor sizes used in designing the comparator and its inverter threshold voltage are shown Table 4.1. The min. comp and the max. comp entries shown in the second

Table 4.1. Comparator transistor sizes used in 0.25 m design

Length (m) 0.24

Comparator

Wp (m) 2.0 20.0 2.0 40.0 2.0 80.0

Wn (m) 10.0 1.0 20.0 1.0 40.0 1.0

Vm (V ) 0.74774305 1.64793472 0.67623762 1.62422083 0.60015062 1.66380054

min. comp max. comp

0.50

min.comp max. comp

1.00

min.Comp max. comp

column mean that the comparator has the smallest inverter threshold voltage and the largest inverter threshold voltage, respectively. All 6-bit, 8-bit, and 9-bit ADCs have same sizes of min. comp and max. comp if they have the same size of length. Table 4.2 summarizes the simulation results of TIQ ash ADCs with a 2.5 V power supply voltage. There are two versions of the ADCs for each resolution. The smaller comparator length is for high speed and the larger length is for low power. As the length

50

Fig. 4.5. Chip layout

Table 4.2. Simulation results of 0.25 m TIQ ash ADCs

Resolution (bits) 6 6 8 8 9 9

Comp. Length (m) 0.24 1.00 0.24 0.50 0.50 1.00

Area (mm2 ) 0.051 0.102 0.254 0.322 0.635 0.826

Max. Speed (MSPS) 1000 400 667 500 250 200

Avg. Power (mW ) 68.98 37.57 254.76 165.29 317.40 260.11

Total Energy (nJ) 4.41 6.01 97.83 84.63 650.00 665.88

51 of the comparators increase, the ADC consumes less power, but the speed degrades even if we increased the maximum width of the low power based ADCs comparator. For the 9-bit ADC, the minimum gate length was not used because of too much power consumption. In terms of ADC speed, low power based ADCs have 60%, 25%, and 20% degradation for the 6-bit, 8-bit, and 9-bit, respectively compared to the high speed versions. But, the ADCs reduced power consumption by 46% for the 6-bit, 35% for the 8-bit, and 19% for the 9-bit. Since the total energy during the conversion depends on both speed and power consumption of each ADC, the low power based ADCs does not always consume small energy compared to the high speed based ADCs. The linearity errors are 0.26 LSB of DNL and 0.23 LSB of INL for the 9-bit high speed based ADC. This is the worst case among the six TIQ ash ADCs.

Linearity Errors in 0.25 m Technology The most critical issue for the TIQ ash ADC might be process variation. The process variation simulation results demonstrate changes in the oset, gain, and linearity of the ADC input voltage range. Table 4.3 shows the process variation eects of an 8bit TIQ ash ADC designed with N94S process parameter. The maximum oset and gain variations from the N94S process are 7.8% and 3.3%, respectively. The full scale range of reference voltage shows a 9.4% maximum deviation, and the step among the reference voltages are 11.3% dierent from the designed process. However, the DNL is very consistent, within 0.1 LSB, compared with the INL because we used the SSV technique mentioned in Section 3.1.2.2 for designing the TIQ comparator.

52

Table 4.3. Process variation result in an 8-bit TIQ ash ADC

Process

min. Vm (V ) 0.74774 0.76576 0.70882 0.73098 0.73114 0.75399 0.73727 0.76846 0.73436 0.74635 0.73449 0.71114 0.70803 0.69004 0.78762 0.80580 7.76%

max. Vm (V ) 1.64793 1.66084 1.63864 1.60244 1.64028 1.62559 1.59411 1.63072 1.62822 1.63290 1.64926 1.63563 1.69926 1.59432 1.60307 1.70152 3.27%

VF SR (V ) 0.90019 0.89508 0.92982 0.87146 0.90914 0.87160 0.85684 0.86225 0.89386 0.88656 0.91477 0.92449 0.99124 0.90428 0.81545 0.89573 9.41%

VLSB (V ) 0.00354 0.00352 0.00366 0.00343 0.00358 0.00343 0.00337 0.00339 0.00352 0.00394 0.00360 0.00364 0.00390 0.00356 0.00321 0.00353 11.30%

DNL (LSB) 0.0396 0.0623 0.0747 0.1040 0.1013 0.0728 0.1066 0.0570 0.0703 0.0556 0.0529 0.0500 0.0785 0.0393 0.0835 0.0433

INL (LSB) 0.0295 1.6888 1.3783 2.6049 2.4323 1.2026 2.8842 0.9483 1.4102 1.4195 1.4407 0.5552 2.3330 0.4805 1.9656 0.5012

N94S T02D T04R T08P-epi T08P-ne T09A-epi T09A-ne T0BL-epi T0BL-ne T0BM T11Y-epi T11Y-ne TSMC- TSMC-fs TSMC-ss TSMC-sf max. dev.

53 Other issues for the TIQ ash ADC linearity errors are temperature and power supply voltage variations. These variation results in the 8-bit ADC are shown in Table 4.4. The comparator was designed with inverter threshold voltages from operating

Table 4.4. Temperature and power supply voltage variation results in the 8-bit TIQ ash ADC

Variations -40o C 27o C 85o C 2.375V (-5%) 2.625V (+5%) max. dev.

min. Vm (V ) 0.76707 0.74719 0.73210 0.72906 0.76598 2.59%

max. Vm (V ) 1.60842 1.64923 1.68785 1.54588 1.75084 6.25%

VF SR (V ) 0.84135 0.90205 0.95575 0.81682 0.98486 9.41%

VLSB (V ) 0.00331 0.00355 0.00376 0.00322 0.00388 9.61%

DNL (LSB) 0.0647 0.0396 0.0593 0.0455 0.0461

INL (LSB) 1.8118 0.0837 1.7988 0.5880 0.6106

at a 25o C temperature and a 2.5 V power supply voltage. Again, the net eects of the variation are oset, gain, and linearity changes, but the maximum deviation is not as large as the process variation except the INL. With the SSV technique, we can obtain reasonable values of DNL, but the INL is still a matter to consider for increasing the accuracy of the TIQ ash ADCs. The linearity errors due to process, temperature, and power supply voltage variations in 0.25 m CMOS technology are not a large problem for ADC performance according to the above simulation results. The designed TIQ ash ADCs keep their

54 sampling rate regardless of these variations. But, in 0.18 m CMOS technology, these variations degrade the ADC performance. The detailed description of these results will be presented in Section 4.1.1.2.

Power Consumption in 6-bit ADCs Figure 4.6 displays the power consumption in the 6-bit TIQ ash ADCs. Both

6-bit high speed ADC


80m

TPOWRD (lin)

60m

40m

6-bit low power ADC


20m

0 600m 800m 1 1.2 1.4 Voltage X (lin) (VOLTS) 1.6 1.8

Fig. 4.6. Power consumption in the 6-bit ADCs

plots show that a large amount of power is consumed in the middle of the conversion process. Since most of the comparators are turned on at the middle voltage, VF SR /2, during conversion, the power consumption lines look parabolic. Also, we can notice that more power is consumed at the beginning of converting - low input voltage - than at the

55 end of converting. The power consumption in the 8-bit and 9-bit ADC looks similar to Figure 4.6.

FFT test with 0.25 m 6-bit ADC The Fast Fourier Transform (FFT) test is a commonly used measure for the dynamic parameters of the ADCs. During the FFT test, the signal in the time domain is converted to a signal in the frequency domain. Figure 4.7 depicts the FFT simulation results for a 6-bit ADC. The 6-bit ADC FFT test with a 1 MHz sine wave signal exhibits

0 5 10 15

Amplitude(dB)

20 25 30 35 40 45 50 0 20

sample = 250 MHz, SNR = 43.85 dB SINAD = 33.17 dB THD = -36.17 dB SFDR = 37.93 dB

in = 1 MHz

40

60

80

100

120

140

Frequency(MHz)

Fig. 4.7. FFT at fin =1 MHz in 6-bit ADC

harmonics 37.93 dB (SFDR) below the fundamental frequency 1 MHz. The SINAD of 33.17 dB implies the ENOB is equal to 5.2 bits.

56 4.1.1.2 Simulation Results of 0.18 m technology

For the second fabrication, 0.18 m CMOS technology and a 1.8 V power supply voltage were used. A fat tree encoder was also designed for a 6-bit ADC to compare with ROM type encoder. The simulation results summarized in Table 4.5 show higher speed,

Table 4.5. Simulation results of 0.18 m TIQ ash ADCs

Resolution (bits) 6 6 6 w/ROM 6 w/FAT 8 8 9 9

Comp. Length (m) 0.18 0.50 1.00 1.00 FAT 0.50 1.00 1.00 1.50

Area (mm2 ) 0.037 0.045 0.074 0.069 0.165 0.272 0.537 0.595

Speed(1) (MSPS) 2000 1666 1111 1111 2000 1666 667 500

Speed(2) (MSPS) 1250 1000 667 714 1000 714 476 400

Power (mW ) 101.98 39.37 35.85 23.46 137.08 108.47 194.23 110.38

Energy (nJ) 3.26 1.51 2.06 1.35 17.55 16.66 149.17 113.03

smaller area, and lower power consumption than the results for 0.25 m technology. There are two ADC speeds shown in this table. The fourth column in Table 4.5 shows the maximum speed with the process parameters used in the design. However, the speed in the fth column indicates the speed after considering all process, temperature, and power supply voltage variations. Because of these variations, the speed is degraded by up to 57 % for the 8-bit low power based ADC. In the 0.18 m technology, these variations aect the speed of the TIQ ash ADC.

57 Linearity Errors in 0.18 m Technology As shown in Table 4.5, the process, temperature, and power supply voltage variations are problems for the performance of the 0.18 m ADCs, while these variations do not degrade the performance of the 0.25 m ADCs. Therefore, we need to check the variation eects in 0.18 m technology. The parameter variation results are shown in Table 4.6. The DNLs of the variation results with 0.18 m technology are all within 0.3 LSB which shows that the ADCs are monotonic. However, the maximum deviations from the results of process, TSMC-tt, which was used for the design, are very large compared to the 0.25 m technology variation results. These large values result in a large value of INL. The large INL means that the ADC has a possibility to be non-monotonic. As a result, the ADCs cannot be operated at the maximum sampling rates under these variations. From these variation results, we noticed that the process, temperature, and power supply voltage variations are a critical factor of the ADC performance as the gate length is made smaller. Again, we recognize that the SSV technique is very eective for reducing the DNL, but with small gate lengths the SSV technique cannot overcome the large value of INL. A design method for improving the INL is necessary for the TIQ ash ADC to correctly operate using the small length of CMOS technology.

Power Consumption in Each Component of the ADC The power consumption in a short-gate technology should be less than the one in a long-gate technology because of the reduction of power supply voltage, which is quadratically proportional to power consumption. The sixth column in Table 4.5 shows

58

Table 4.6. Variation results in a 0.18 m 8-bit TIQ ash ADC

Variations

min. Vm (V ) 0.61069 0.53818 0.51266 0.68121 0.70925 0.63725 0.64719 0.64070 0.65218 0.65618 0.65272 0.63870 0.64072 0.65168 0.64914 0.63122 0.59515 0.59516 0.62579 16.1% 7.1%

max. Vm (V ) 1.01191 1.02046 0.92721 1.00577 1.09709 1.03781 1.03766 1.03931 1.04176 1.04019 1.05780 1.03128 1.05136 1.04931 1.05872 0.97874 1.04430 0.95409 1.07056 8.4% 3.8%

VF SR (V ) 0.40122 0.48588 0.41455 0.32456 0.38784 0.40056 0.39047 0.39861 0.38958 0.38401 0.40508 0.39258 0.41064 0.39763 0.40958 0.34752 0.44915 0.35893 0.44477 21.1% 6.3%

VLSB (V ) 0.00158 0.00191 0.00163 0.00128 0.00153 0.00158 0.00154 0.00157 0.00153 0.00151 0.00159 0.00155 0.00162 0.00157 0.00161 0.00137 0.00177 0.00141 0.00175 20.9% 6.2%

DNL (LSB) 0.0899 0.1850 0.2086 0.1941 0.2774 0.2591 0.2761 0.2585 0.2912 0.2931 0.2757 0.2853 0.2706 0.2568 0.2569 0.3056 0.2768 0.2666 0.1414

INL (LSB) 0.0758 1.3156 1.1193 2.1702 1.2637 4.3487 4.9441 5.0830 6.9232 6.7843 6.6918 6.7023 6.9110 7.0116 7.3446 4.5929 3.2568 0.8621 0.6882

TSMC-tt TSMC- TSMC-fs TSMC-ss TSMC-sf T12K T14B T15J T16X T18H T1CH T22T T24I T26X T28M -40o C 85o C 1.71V (-5%) 1.89V (+5%) max. dev. avg. dev.

59 the average power consumption of the ADCs. The power consumption for the 0.18 m technology does not produce a large savings because the maximum transistor size in the comparator is at least 2.5 times for the PMOS and 1.5 times for the NMOS devices larger than the sizes in 0.25 m technology. The absolute currents and relative currents used by each component are shown in Table 4.7 and in Figure 4.8, respectively. The simulated

Table 4.7. Absolute currents used by each component

ADCs

Comparator (mA)

Gain booster (mA) 1.37 1.36 1.45 1.50 1.53 1.49 1.43

01 generator (mA) 0.68 0.68 0.68 1.05 0.73 0.74 0.74

Encoder (mA) 10.99 10.86 10.86 3.96 15.22 14.73 16.52

6b 0.18 6b 0.50 6b 1.00r 6b 1.00f 8b 0.50 8b 1.00 9b 1.00

75.07 27.94 23.53 17.46 85.00 72.57 138.81

maximum currents show the portion of power consumption in each ADC. As expected, the comparator consumes more than 60 % of the power. Figure 4.8 also illustrates that the comparator power portion is decreased as the gate length is made longer. Also, the resolution of the ADC eects the portion of the power consumption. For the same gate length, the higher resolution ADC consumes more power than the lower resolution

60

Fig. 4.8. Relative currents used by each component

ADC. The encoder section is the next major uses of power. Specically, the ROM type encoder (the 3rd one) consumes more power than the fat tree encoder (the 4th one). The power consumption of the gain booster, which is a minimum size of inverter, and the 01 generator are very small compared to the power of the comparator. Therefore, we should focus on the comparator for designing a low power ADC.

4.1.1.3

Simulation Results of 0.50 m technology

An 8-bit TIQ ash ADC has been designed with 0.50 m CMOS standard technology for the third fabrication. For this chip, the fat tree encoder was used to increase the speed of the TIQ ash ADC. In Section 4.1.1.2 the fat tree encoder was conrmed to be faster than the ROM type encoder. The fat tree encoder also has an advantage in power consumption.

61 Unlike the rst and second fabrication, no parameter values were supplied by the chip fabrication vendor. Therefore we needed to choose one parameter that could be less sensitive to the process variation. To choose the parameter set that was used in this design, we picked 10 SPICE parameters provided by MOSIS and calculated the average values of each inverter threshold voltage. After that, we chose the parameter model T22A because 255 inverter threshold voltages of the T22A were the closest to the average values. The simulation results of the 8-bit 0.50 m TIQ ash ADC are described in Table 4.8. As can be seen, the ADC size is larger than for the ADCs with 0.25 m and 0.18 m, but the ADC speed is faster than the speed of the 8-bit ADC with 0.25 m. Next, we optimized the size of both fat tree encoder and gain booster. The power consumption in this case is very large since the maximum width of PMOS and NMOS devices in the comparator has been increased at least four times compared to the ADCs with 0.25 m. In addition to this increasing the width, the inuence on the power consumption is the power supply voltage increasing from 2.5 V to 5.0 V . Figure 4.9 displays the DNL and INL of the 8-bit TIQ ash ADC designed with the T22A SPICE parameter set. Table 4.9 shows the variation of results with other SPICE models. The results are exactly as expected. In the 0.50 m CMOS technology, the inverter threshold voltages are less sensitive to process variations than for the previous smaller technologies. The simulations with other process models shows small deviations (within 1% in all parameters) including DNL and INL from the model used for the design. Especially, the DNL and INL of the other processes are less than 0.5 LSB, except for one - the T17Z INL. The DNLs are almost the same as the T22A model. There is only 3.2%

62

Table 4.8. Simulation results of the 8-bit 0.50 m TIQ ash ADC

Resolution CMOS tech. comparator length power supply max. speed avg. power total energy VF SR VLSB DNL INL ADC area

8 bit 0.50 m 1.50 m 5.0 V 500 MSPS 2.399 W 2.457 J 1.346 V - 2.613 V 0.005 V 0.2647 LSB 0.1726 LSB 1.722 mm2

0.5

0.5

0.25
DNL (LSB)

0.25
INL (LSB)

0.25

0.25

0.5 0

50

100 150 output code

200

250

0.5 0

50

100 150 output code

200

250

(a) DNL

(b) INL

Fig. 4.9. DNL and INL of the 8-bit TIQ ash ADC with 0.50 m

63

Table 4.9. Variation results in a 0.50 m 8-bit TIQ ash ADC

Process

min. Vm (V ) 1.34574 1.33873 1.34216 1.33868 1.35666 1.35208 1.33346 1.34862 1.35072 1.35827 0.93% 0.56%

max. Vm (V ) 2.61347 2.61190 2.61802 2.61317 2.63113 2.60971 2.59478 2.62063 2.60794 2.62137 0.72% 0.29%

VF SR (V ) 1.26773 1.27317 1.27586 1.27449 1.27447 1.25763 1.26132 1.27201 1.25722 1.26310 0.83% 0.55%

VLSB (V ) 0.00499 0.00501 0.00502 0.00502 0.00502 0.00495 0.00497 0.00501 0.00495 0.00497 0.80% 0.56%

DNL (LSB) 0.2647 0.2654 0.2687 0.2700 0.2723 0.2713 0.2720 0.2689 0.2731 0.2658

INL (LSB) 0.1726 0.3186 0.5883 0.1779 0.3649 0.2866 0.3867 0.3078 0.3328 0.2093

T22A T17G T17Z T1AW T1BD T1CK T21S T22Y T24H T24O max. dev. avg. dev.

64 maximum deviation. However, the deviations of the INLs are large, but they are still in a reasonable range when compared to the 0.25 m and 0.18 m results. By choosing the process that has an average inverter threshold voltage, we can get reasonable DNLs and INLs in spite of process variations. But, this method is not practical because there are too many processes to reasonably choose between them.

4.1.2

Variation Eects on the RSV and SSV Techniques This section deals with the simulation results from the two design methods intro-

duced in Section 3.1.2: the RSV and SSV techniques. Two 6-bit TIQ comparators have been designed with the 0.25 m TSMC-TT SPICE parameter set. One comparator was designed with the RSV technique and the other one with the SSV technique. Initially, the 6-bit comparator with the SSV technique had a larger value of DNL and INL. However, choosing inverter transistor sizes from the diagonal line shown in Figure 3.3 ensures the monotonic size increase and decrease of the PMOS and NMOS transistors (shown in Figure 3.4(b)), respectively. This makes the DNL and INL of the ADC to be less sensitive to the CMOS process variations. The 22 HSPICE parameters provided by MOSIS and ve TSMC parameters are used to check the eects of process variation. The simulation results of the Figure 4.10 and Table 4.10 show that the DNL and INL of the RSV technique are much more sensitive to process variation than those of the SSV technique. Considering process variations, the SSV technique can reduce

DNL and INL to 82.6% and 32.5% on average compared to those of RSV technique, respectively.

65

1 tsmctt tsmcff n94s


DNL (LSB)

1 tsmctt tsmcff n94s

0.5
DNL (LSB)

0.5

0.5

0.5

1 0

10

20 30 40 OUTPUT CODE

50

60

1 0

10

20 30 40 OUTPUT CODE

50

60

(a) DNLs of RSV technique


1.5 1 0.5
INL (LSB)

(b) DNLs of SSV technique


1.5

tsmctt tsmcff n94s


INL (LSB)

1 0.5 0

tsmctt tsmcff n94s

0.5 1 1.5 0

0.5 1 1.5 0

10

20 30 40 OUTPUT CODE

50

60

10

20 30 40 OUTPUT CODE

50

60

(c) INLs of RSV technique

(d) INLs of SSV technique

Fig. 4.10. DNLs and INLs of the two 6-bit TIQ comparator

66

Table 4.10. The eects of process variations and RSV and SSV design techniques

Process

DNL of RSV (LSB)

DNL of SSV (LSB) 0.0114 0.0414 0.0142 0.0158 0.0424 0.1028 0.0825 0.0790 0.0958 0.0872 0.0885 0.0431 0.0598 0.0832 0.0482 0.1055 0.0694 0.0687 0.0732 0.0840 0.0864 0.0458 0.0553 0.0436 0.0655 0.0533 0.0397

INL of RSV (LSB) 0.0013 0.5839 0.1140 0.1190 0.4954 1.1109 1.0058 0.7746 1.2349 1.0539 1.0335 0.5388 0.8105 0.6712 0.4142 1.1881 0.6809 0.5629 0.6464 0.8050 0.8417 0.5458 0.5122 0.3692 0.5564 0.7442 0.6181

INL of SSV (LSB) 0.0083 0.5265 0.1155 0.1164 0.4293 0.6823 0.6420 0.4836 0.7610 0.6096 0.6172 0.2581 0.3986 0.4954 0.3088 0.7065 0.4310 0.4220 0.4558 0.5284 0.5522 0.2530 0.3327 0.2762 0.3992 0.3982 0.3441

TSMC-TT TSMC- TSMC-fS TSMC-Sf TSMC-SS T08P-epi T08P-ne T09A-epi T09A-ne T0BL-epi T0BL-ne T11Y-epi T11Y-ne T13M-epi T13O-epi T14Y-epi T15H-epi T16R-epi T17A-epi T18I-epi T19o-epi T1AB-epi T1CJ-epi T21Q-epi T23C-epi T25T-epi T27H-epi

0.0023 0.1384 0.0134 0.0140 0.1399 0.9277 0.7054 0.9695 0.8278 1.0548 0.8946 0.9425 1.0289 1.1652 0.6815 0.9827 1.1302 0.8226 0.9733 1.0313 0.9317 0.9246 0.9578 0.5672 0.9806 0.8805 0.6261

67 Table 4.11 compares the RSV and SSV techniques for temperature and power supply voltage variations. For the temperature and power supply voltage variation, 43.5% reduction for DNL and 6.0% reduction for INL are achieved. Again, the key feature in the SSV technique is to maintain the monotonicity of transistor size changes so that the resulting ADC will have consistent DNL limits in spite of process, temperature, and power supply voltage variations.

Table 4.11. DNL and INL for temperature and power supply voltage variations using the RSV and SSV design techniques
Variations -40o C 85o C 2.375 V 2.625 V DNL of RSV (LSB) 0.0634 LSB 0.0617 LSB 0.0365 LSB 0.0309 LSB DNL of SSV (LSB) 0.0459 LSB 0.0353 LSB 0.0169 LSB 0.0155 LSB INL of RSV (LSB) 0.4449 LSB 0.4392 LSB 0.1450 LSB 0.1483 LSB INL of SSV (LSB) 0.4330 LSB 0.4324 LSB 0.1306 LSB 0.1337 LSB

The TIQ comparator design is based on the internal voltage reference determined by the transistor sizes. However, the internal voltage reference varies due to the CMOS process parameter variation during manufacturing. Such variations create limits on the linearity variation of the ADC. The SSV design technique of the TIQ comparator signicantly improves the linearity of the ADC in spite of the CMOS process variation. In particular, the DNL dependence on the CMOS process variation can be almost eliminated.

68 4.1.3 Fat Tree Encoder vs. ROM Type Encoders The concepts of the fat tree encoder and ROM type encoder were introduced in Section 3.3. In this section, we compare the two encoders in terms of their sampling rate and power consumption. For a more ecient implementation in CMOS, the OR gates shown in Figure 3.10 are replaced with NOR and NAND gates using DeMorgans theorems. To compare the two encoders, 0.18 m TIQ ash ADCs were designed with the fat tree encoder and the ROM type encoder, respectively. Two encoders are shown in the Figure 4.11. The only dierence between two ADCs in Figure 4.11 is the encoder. The simulation results with these two encoders are summarized in Table 4.12.

fat tree encoder

ROM type encoder

(a) Fat tree encoder layout

(b) ROM type encoder layout

Fig. 4.11. Two encoders in the TIQ ash ADC

69 Table 4.12. Summary of the simulation results with two encoders

Fat Tree Encoder sampling rate avg. power max. power total energy encoder transistor number encoder area 2.00 GSPS 22.70 mW 38.65 mW 0.73 nJ 485 0.0074 mm2

ROM Type Encoder 1.11 GSPS 32.64 mW 54.41 mW 1.88 nJ 222 0.0094 mm2

The speed of the ADC with the fat tree encoder is about 1.8 times faster than the speed of the ADC with the ROM type encoder. Concerning power consumption and area, the fat tree encoder can save 30.5% of the power, 61.2% of the energy, and 21.3% of the area. For the TIQ ash ADC, the ROM type encoder does not have a sense amplier and minimum size of the NMOS device. Instead, the sizes of NMOS and PMOS transistors in the ROM have been optimized for high speed operation. Therefore, the ROM type encoder consumes more power even if it has small number of transistors. Table 4.12 clearly demonstrates that the fat tree encoder is a better choice over the ROM type encoder in a SoC implementation. The disadvantage of the fat tree encoder is the diculty in its layout. As shown in Figure 4.11, the fat tree encoder is not as regular as the ROM type encoder. Hence, it takes much more time to design the fat tree encoder. For an eective design and implementation of the fat tree encoder, a systematic layout tool should be developed.

70

4.2

Fabrication Results
TIQ ash ADCs have been fabricated three times. The rst fabrication was done

with TSMC 0.25 m CMOS technology and packaged in a 40-pin dual inline package (DIP). The TSMC 0.18 m CMOS technology was used in the second fabrication and it was packaged in a 84-pin pin grid array (PGA). For the third fabrication, 0.50 m CMOS technology was used and packaged in a 40-pin DIP. The fabricated prototype chips have been tested with a 15MHz function generator (HP33120A), 100 MHz 2*16 channel oscilloscope (HP54645D), and a DC power supply (HP3631A), as shown in Figure 4.12.

15MHz Function Generator

DC Power Supply

100MHz Oscilloscope

Bread Board

0.25um Chips

Fig. 4.12. Equipments for testing prototype chips

71 4.2.1 Test Results of 0.25 m TIQ ash ADC Chips The rst fabricated chip contained six TIQ ash ADCs: two for 6-bits, two for 8-bits, and two for 9-bits. As mentioned in Section 4.1.1.1, we tried two dierent gate lengths for the comparator transistors in each resolution to compare the speed and the power consumption. Figure 4.13 shows the fabricated chip die photo (2.58 mm 2.58 mm). Since the 5 layers of metal covers most of the active area, the details of each ADC

8-bit 0.24um

8-bit 0.50um

9-bit 0.50um

9-bit 1.00um

6-bit 6-bit 0.24 1.00um um

Fig. 4.13. Die photo of a chip fabricated with 0.25 m

layout cannot be seen. The layout of the chip shown in Figure 4.5 is displayed after removal of the topmost metal layer that covers the active area.

72 A total of 25 prototype chips were received. The test results show that only the 6-bit low-power based ADC (comparator length equals to 1.00 m) operates with full precision without a missing code. However, the other ADCs work with reduced precision. Table 4.13 summarizes the test results of the rst fabricated ADCs. The second column

Table 4.13. Summary of 0.25 m chip test results

ADCs

of TRs

Comp. length (m)

Precision (bits) 4 6 5 7 6 8

Avg. Power (mW ) 109.38 35.25 170.50 121.25 200.38 179.63

Signal delay (ns) 3.799 21.404 7.249 18.612 27.762 83.595

6-bit

1000

0.24 1.00

8-bit

5174

0.24 0.50

9-bit

10555

0.50 1.00

shows the number of transistors used in each ADC. The precision of the ADCs are shown in the third column. These precisions are reduced due to the following reasons: Process limitation: Although layout dimension can be specied in 0.01 m steps, mask production and physical dimension control in 0.01 m is not possible. Considering this minimum feature size of 0.24 m, W in Section 3.1.2.2 was too small in the rst fabrication.

73 On chip power distribution: The pad frame design does not separate the analog power lines from the digital power lines. Digital circuits generate noise on the power supply line causing the sensitive analog comparators to chatter. Noise coupling to ADC input: The large capacity output pad drivers causes more noise on the power supply when the oscilloscope probe is connected. Also, the switching transitions at the output couple to the ADC input. The actual measured power for each ADC shows good matching with simulation results described in Table 4.2. Overall 10% - 20% less power consumption was measured than produced by the simulation results. This might be mainly due to an under estimation of the parasitics in simulation parameters. We cannot actually measure the conversion speed of the ADCs except for the 6bit low power based TIQ ash ADC because of the unanticipated noise. However, all of the ADCs correctly operate with 1 MHz square wave input. Therefore, the performance of the ADCs can be illustrated by the measured signal delays shown in Table 4.13 with this square wave input. The signal delay means the transition time from 000000 to 111111 in the case of the 6-bit ADC. The original ADC design and simulation has been done with TSMC-tt (simply called TSMC) process parameter set. The wafer test result was produced T14Y-lo-epi parameter set (simply called T14Y) shown in Appendix B. The signal delays of the ADCs are summarized in Table 4.14. Re-simulation with T14Y parameter shows the signal delay is 10% - 30% longer than for the designed parameter TSMC. However, the actual measurements on a prototype chip show at least a 50% longer signal delay. Several possible reasons are as follows:

74 Table 4.14. ADC Signal delay test results

ADCs input swing

Chip 15 0.0V -2.5V (ns)

Chip 15 0.6V -1.7V (ns) 5.562 37.861 7.487 17.574 31.211 106.862

TSMC 0.0V -2.5V (ns) 1.850 4.506 1.430 1.931 2.330 3.740

TSMC 0.6V -1.7V (ns) 2.011 6.481 1.520 2.244 2.629 4.437

T14Y 0.0V -2.5V (ns) 2.216 5.250 1.914 2.502 3.075 4.544

T14Y 0.6V -1.7V (ns) 2.383 8.186 2.012 2.914 3.483 5.775

6b024 6b100 8b024 8b050 9b050 9b100

3.924 21.562 7.787 18.662 27.712 82.062

A signicant under estimation of the load conditions The layout to circuit extraction being not too accurate The bandwidth of the signal source and measuring tools being limited The bread board conguration and power supply limits Table 4.14 describes the signal delays with a rail-to-rail swing input voltage (0.0V - 2.5V ) and ADC the full swing range (0.6V - 1.7V ). The signal delays with the ADC full swing input range are longer than for the rail-to-rail swing. The maximum observed conversion speed in the 6-bit low-power based TIQ ash ADC is 250 MSPS, as measured with a recently acquired 250 MHz mixed signal oscilloscope, but we anticipate being able to document higher-speed operation with better measuring equipment. Figure 4.14 shows a 20 KHz sine wave test result for the 6-bit

75

(a) 20 KHz sine wave test with power supply noise in 6-bit ADC

(b) 100 KHz saw wave test with 9-bit ADC

Fig. 4.14. Oscilloscope outputs of 0.25 m ADCs

76 ADC and a 100 KHz saw-tooth wave form test result for the 9-bit ADC. The process parameter variation produces less than 3% variation of min. Vm and is consistent among chips. The INL (1.20 LSB) and DNL (0.27 LSB) are signicantly larger for the test result than the simulation results. The measured INL and DNL for the 6-bit ADC are shown in Figure 4.15.

0.5 0.4 0.3 0.2


DNL (LSB) INL (LSB)

1.5

0.5

0.1 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 OUTPUT CODE 50 60

0.5

1.5 0

10

20

30 40 OUTPUT CODE

50

60

(a) Differential non-linearity

(b) Integral non-linearity

Fig. 4.15. DNL and INL of the 6-bit low power based ADC

4.2.2

Test Results of 0.18 m TIQ ash ADC Chips The second chip fabrication used the same die size as the rst fabrication. Since

0.18 m CMOS technology was used at this time, we could put more TIQ ash ADCs on the chip than the previous fabricated chip for the TIQ comparator experiment. From the second fabrication, the parametric test result, T1AX-lo-epi shown in Appendix C, was produced. Figure 4.16 shows the die photo of a prototype chip fabricated with 0.18

77 m CMOS technology. Six layers of metal were used for chip design. Like the rst

8-bit 0.50um

8-bit 1.00um

9-bit 1.50um

6-bit 1.0 um

9-bit 1.00um

4 6-bit ADCs

Fig. 4.16. Die photo of a chip fabricated with 0.18 m

fabrication, the details of the chip layout cannot be seen. But, a part of TIQ comparator among the higher metal layers can be identied. All 40 chips work, but the test results are worse than for the chips fabricated with 0.25 m technology. As shown in Table 4.15, only two of the 6-bit ADCs with a gate length of 1.00 m operate with full precision. The precision of the other ADCs is even worse than for the previous ones. The second fabrication with 0.18 m ADCs are smaller in area, lower in power consumption (at least 40%), and shorter in ADC signal delays (at least 100%) than the rst fabrication. The transient signal outputs and signal delay of the 6-bit 1.00 m ADC with a fat tree encoder and the 8-bit 1.00 m ADC

Table 4.15. Summary of 0.18 m chip test results

78

ADCs

Comp. length (m)

Precision (bits) 3 3 6 6 5 6 5 5

Avg. Power (mW ) 77.40 36.01 21.64 26.97 75.64 64.78 111.61 64.81

Signal delay (ns) 3.35 2.97 4.50 2.65 6.65 15.45 29.20 35.50

6-bit

0.18 0.50 1.00 w/ROM 1.00 w/FAT

8-bit

0.50 1.00

9-bit

1.00 1.50

are shown in Figure 4.17. There are no missing codes in the 6-bit 1.00 m ADC with fat tree encoder, and its signal delay is 3.85 ns including the pad delay (1.2 ns). On the other hand, the 8-bit 1.00 m ADC shows that there are missing codes in rst two MSBs. We could be able to obtain a full precision 8-bit TIQ ash ADC if we eliminate the noise problem. The signal delay of this ADC is 16.65 ns, which also includes the pad delay. The measured DNL and INL of the 6-bit fat tree encoder ADC is 0.36 LSB and 1.36 LSB, respectively.

4.2.2.1

Noise eects on the ADCs

The noise problem is more serious in the 0.18 m design. Figure 4.18 shows eects on power supply and input of the ADC. The noise from the probe on the power supply is one of the major factors that makes the input chatter. Figure 4.18(a) shows a large (more than 100 mV ) noise on the power supply when the probe is connected to the chip. However, without the probe connection, we get a small noise (around 10 mV ) on the

79

Pad delay: 1.2 ns

(a) 6-bit 1.00um with fat tree encoder

(b) Signal delay of (a)

Pad delay: 1.2 ns

(c) 8-bit 1.00um ADC

(d) Signal delay of (c)

Fig. 4.17. Oscilloscope outputs of 0.18 m ADCs

80

(a) Noise from the probe

(b) Noise without the probe

(c) Vdd and GND noise in a 6-bit ADC

(d) Vdd and input noise in a 6-bit ADC

(e) Noise reduction with 47K resistor

Fig. 4.18. Noise eects on the ADC

81 power supply as depicted in Figure 4.18(b). The 6-bit ADC is less sensitive to this noise eect, while the higher resolution ADC is very susceptible to this noise. Figure 4.18(c) shows the 6-bit ADC result along with power supply noise. Also this power supply noise makes the input chatter shown in Figure 4.18(d). The noise on the input follows the noise on the power supply. This noise can be reduced by adding a resistor at the end of the outputs. Figure 4.18(e) shows noise reduction on both the input and the power supply after a 47K resistor was added to the chip. Due to these noises, the precision of the ADCs is reduced, especially in higher resolution ADCs. Also, the added resistor degrades the ADCs performance.

4.2.2.2

Fast Fourier Transform (FFT) Test Results

The dynamic performance of the TIQ ash ADC is measured with a FFT test. The measured data FFT result shown in Figure 4.19(a) does not match the FFT test result for the simulated operation (Figure 4.7). The 6-bit data (512 points) was measured for a 80 KHz input frequency at a 10 MHz sampling rate for the 6-bit fat tree encoder ADC. The measured data from the 6-bit ADC shows reduced dynamic parameters due to the noise problems. The small SINAD results in an ENOB of 3.3 bits, while the simulated ENOB is 5.2 bits. On the other hand, the 6-bit data (1024 points) from a pure 1 MHz sine wave input shows ideal dynamic parameters in a 6-bit ADC at 200 MHz sampling rate. Its ENOB is 5.8 bits. From the comparison with the ideal FFT test results, we notice that the TIQ ash ADC should be less sensitive or insensitive to noise for a SoC implementation.

82

0 10 20

Amplitude(dB)

30 40 50 60 70 80 0

sample = 10 MHz, SNR = 23.40 dB SINAD = 21.83 dB THD = -37.42 dB SFDR = 9.13 dB

in = 80 KHz

Frequency(MHz)

(a) FFT test with measured data in 6-bit fat tree encoder
0 10 20

Amplitude(dB)

30 40 50 60 70 80 0

sample = 200 MHz, SNR = 37.78 dB SINAD = 36.56 dB THD = -54.24 dB SFDR = 37.86 dB

in = 1 MHz

20

40

60

80

100

Frequency(MHz)

(b) FFT test with a pure sine wave

Fig. 4.19. FFT spectra of measured and ideal data

83 4.2.3 Test Results of 0.50 m TIQ ash ADC Chips The third fabrication used 0.50 m CMOS technology and produced the SPICE model T26B-lo-epi parametric test result shown in Appendix D. Since only 2 layers of metal have been used in the ADC design, we can see more detail of the prototype chip (Figure 4.20). The systematic increasing/decreasing sizes of the comparator transistors

Fat tree encoder

01 generator

Gain booster

Comparator

Fig. 4.20. Die photo of a chip fabricated with 0.50 m

are shown at the bottom of the photo. Also, the fat tree encoder is shown at the top below the complicated connection lines. For the third fabrication results, we only have the die photo of one of the four received prototype chips. The test results for this chip will be described later.

84

Chapter 5

Low Power Applications with TIQ Comparator

Usually, low power ADC architectures are implemented with pipelined [60, 40, 59, 16, 50], successive approximation [35, 12], and modulator [38]. These are all useful for the medium speed conversion and high resolution applications. On the other hand, the ash architecture is suitable for high speed conversion and low resolution applications due to its parallel architecture. Because many comparators compare the reference voltage with input voltage at the same time, power consumption in the ash architecture is much larger than for the others. Controlling the power consumption in the comparator is the key to reducing the overall power consumption in a ash ADC. This chapter describes two low power modications to the TIQ ash ADC. One is called the power and resolution adaptive ash ADC (PRA-ADC) whose resolution and power can be changed on demand. The other is a power management method in the TIQ ash ADC with a frequency scaling method.

5.1

The Power and Resolution Adaptive Flash ADC (PRA-ADC)


Resolution, speed, and power consumption are the three key parameters for an

ADC. These parameters cannot be changed once an ADC chip has been fabricated. Of course, one can use only 6-bits from an 8-bit ADC chip, while the full 8-bit operation takes place internally. Such an application is non-optimal, resulting in lower speed and

85 extra power consumption due to the full 8-bit internal operation. This proposition applies to the ash ADCs, which are parallel, high-speed, high-power ADCs. A new ash ADC design is proposed in this section: a true variable power and variable resolution ADC. It is named the power and resolution adaptive ADC (PRAADC) [68]. The PRA-ADC can operate at high speeds and will consume less power when it operates at a lower resolution. This feature is highly desirable in many wireless mobile applications. For example, the strength of a radio frequency (RF) signal varies greatly depending on geographic location. Optimally, the ADC resolution can be reduced upon the reception of strong signal, or the resolution can be increased upon the reception of weak signal. The substantial reduction of power consumption at lower resolution will prolong the battery-powered operation.

5.1.1

PRA-ADC Design and Layout The key feature of the TIQ comparator is the fact that the comparator can easily

and quickly switch from active mode to standby mode. Figure 5.1 shows a simple addition to the TIQ comparator input to select either the analog input voltage or the Vstby voltage, selecting the active mode or standby mode, respectively. In the active mode, switch S1 is on and switch S2 is o, connecting the analog input signal to the TIQ comparator input. In the standby mode, S1 is o and S2 is on, connecting Vstby voltage to the TIQ comparator. The analog input signal voltage varies between GND and VDD, but the Vstby voltage is xed either to GND or to VDD. In standby mode, the power consumption of the TIQ comparator is due to only the leakage current of a PMOS or

86
Vstby

S2 analog Vin

TIQ Comparator Vcin

S1

MOD-SEL Circuit

Fig. 5.1. Active mode or standby mode selector circuit

an NMOS transistor. A great deal of power saving is thereby achieved for each TIQ comparator when it enters the standby mode. In the PRA-ADC, the unused TIQ comparators are switched to the standby mode to reduce power consumption. An 8-bit ash ADC requires 28 1 = 255 voltage comparators, and a 7-bit ash ADC requires 27 1 = 127 voltage comparators. The 8-bit PRA-ADC has 255 TIQ comparators. When it is operating at 7-bit precision, every other TIQ comparator is switched to the standby mode, achieving almost an 50% ADC power consumption reduction. When it is operating at 6-bit precision, every three out of four TIQ comparators are switched to the standby mode, achieving almost an 75% ADC power consumption reduction. Similarly a 5-bit precision results in almost 87.5% power reduction. The comparators power consumption is the dominant component of the TIQ ash ADC power consumption, and the overall power consumption is directly proportional to the number of active comparators at any given time. Figure 5.2 shows the block diagram of the PRA-ADC. The input signals R1 and R2 control the ADC precision. The precision control logic unit on the lower left of

87

7 6 5

analog Vin MOD -SEL C255

R2 R1 Gain Booster Encoder

MOD -SEL MOD -SEL MOD -SEL MOD -SEL MOD -SEL MOD -SEL MOD -SEL MOD -SEL Precision Control Logic

C8 C7 C6 C5 C4 C3 C2 C1

Gain Booster 8bit Gain Booster Gain Booster Gain Booster Gain Booster Gain Booster Gain Booster Gain Booster 8 7 8 6 5 5bit 6bit 7bit

4 to 1 MUX (8) R2 R1

Fig. 5.2. The power and resolution adaptive ADC

88 Figure 5.2 generates the mode selection signals to selectively activate the appropriate inverter comparators. Figure 5.3 shows the truth table of the precision control logic.

RA-ADC Precision 8-bit 7-bit 6-bit 5-bit R2 R1

R2 R1 0 0 1 1 0 1 0 1

7 6 5 1 0 0 0 1 1 0 0 1 1 1 0 7 6 5

Precision Control Logic

Fig. 5.3. The precision control logic

The gain booster unit consists of a number of cascaded inverters. If the inverter comparator is in standby mode, the inverters in the gain booster unit are also in standby mode. We use ROM to convert the thermometer code to binary code. Four encoders are connected in parallel, shown on the right side of Figure 5.2. The 8-bit encoder is a 2568 ROM, the 7-bit encoder is a 1287 ROM, the 6-bit encoder is a 646 ROM, and the 5-bit encoder is a 32 5 ROM. The appropriate ROM is selected by the precision control signals R1 and R2 . Unselected ROMs are switched into the standby mode. Figure 5.4 shows the PRA-ADC layout using 0.18 m CMOS technology. The total area is 2.180mm2 (345.72m 630.48m). The layout area overhead required for adding the power and resolution adaptation feature to the xed 8-bit TIQ ash ADC is almost 100%. The xed 8-bit TIQ ash ADC consists of only the TIQ comparator

89

Mode TIQ Gain Selector Comp. Booster 8bit

Encoder 7bit 6bit

5bit

Precision Control Logic

MUX

Fig. 5.4. VLSI layout of the PRA-ADC

90 column, the gain booster column, and the 8-bit encoder ROM column. One can see the extra overhead layout area due to the mode selector column, 7-bit, 6-bit, and 5-bit encoder ROM columns in Figure 5.4.

5.1.2

PRA-ADC Simulation Results Table 5.1 shows a summary of the simulation results. The power dissipation is

reduced by almost 50% for each resolution bit reduction. Figure 5.5 shows the comparison of the theoretical 50% power reduction graph and the simulation results.

Table 5.1. Summary of the PRA-ADC simulation results

Resolution (bits) 8

Power (mW ) 434.63

Speed (GSPS) 1.25

Switching O/H (ps) 484.43 (5bit-to-8bit)

INL (LSB) 0.0347

DNL (LSB) 0.0654

VLSB (mV ) 1.68

223.15

1.61

417.76 (8bit-to-7bit)

0.0162

0.0199

3.36

120.29

2.22

404.56 (7bit-to-6bit)

0.0025

0.0037

6.71

68.63

3.03

237.36 (6bit-to-5bit)

0.0015

0.0012

13.41

The third column of Table 5.1 shows the ADC speed increase as the number of resolution bits is decreased. This is mainly due to the fact that the 128 7 ROM is

91
450 400 350
Measured Power Measured Power Measured Power Measured Power Ideal Power Ideal Power

Ideal Power Ideal Power

Power (mW)

300 250 200 150 100 50 0 5 6 7 8

Resolution (bit)

Fig. 5.5. Power reduction comparison

faster than the 256 8 ROM and the 64 6 ROM is faster than the 128 7 ROM. A smaller ROM is faster than a larger ROM. Also by comparing the 8-bit ADC speed and the 5-bit ADC speed, we can see the fact that the predominant signal delay is due to the encoder ROM circuit. The encoder ROM is the bottleneck of the speed in the TIQ ash ADCs, whereas the voltage comparators are the bottleneck in the non-TIQ ash ADCs. The fourth column of Table 5.1 shows the mode switching overhead time. The power and resolution changes take place in less than 0.5ns, comparable to the PRAADCs high operating speed above 1 giga samples per second (GSPS). The PRA-ADC will suer minimal analog signal loss during the resolution change. Figure 5.6 shows the simulation result of the ADC resolution switching and the switching overhead times. The remaining columns in Table 5.1 show the linearity errors and VLSB change as the ADC resolution changes.

92

Vin d8 d7 d6

1 800m 1.5 0 1.5 0 1.5 0 1.5 7bit-to-6bit O/H 4.0456e-10 0 1.5 8bit-to-7bit O/H 4.1776e-10 0 1.5 0 1.5 0 1.5 0 0 20n 40n 60n 6bit-to-5bit O/H 2.3736e-10 5bit-to-8bit O/H 4.8443e-10

d1

d2

d3

d4

d5

80n 100n 120n 140n 160n 180n 200n Time (lin) (TIME)

Fig. 5.6. Resolution switching and switching overhead time

93 5.1.3 Summary of the PRA-ADC The ash ADCs are parallel, high-speed, high-power ADCs, applicable in RF portable communication devices. In an eort to conserve energy, we proposed a new power and resolution adaptive ash ADC, called PRA-ADC. The PRA-ADC design produces an exponential power reduction with a linear resolution reduction. Unused parallel voltage comparators are switched to standby mode. These voltage comparators dissipate only leakage power during the standby mode. The PRA-ADC layout using a 0.18 m CMOS design rule shows an 100% area overhead. There is no noticeable performance overhead for the PRA-ADC. The voltage comparator switches between the active mode and the standby mode in less than 0.5 ns while the ADC operates at over 1 GSPS speed. The PRA-ADC allows tighter management of power and eciency.

5.2

A Power Management Method in the TIQ Flash ADC


Recently many techniques for building low power ADC circuits have been re-

searched [20, 35, 59, 16]. Among those techniques, voltage scaling is known as the most eective power reduction technique. The power dissipation reduces quadratically as the power supply voltage decreases. However the supply voltage scales down, the signal swings will be decreased, which will degrade the ADC precision and speed. High precision and high gain voltage comparators are dicult to design for operation from a low power supply voltage.

94 Most power reduction techniques utilize the circuit and algorithm approaches. Instead of using large numbers of voltage comparators operating in parallel, one can use only one voltage comparator to sequentially compare the incoming analog voltage and produce the digital output. Such a technique is very eective in power reduction but inevitably slow. Another power reduction technique commonly used in digital circuits is power switching or clock gating. Simply switch o the power supply to the circuit when it is not used, forcing the circuit to be in stand-by mode. With the CMOS digital circuits, this power switching can be easily achieved by stopping the clock transitions to the target circuit. In [10] a new power ecient scheme, called the pruning calibration technique, for a ash ADC was introduced. This technique reduces the power consumption by turning o some comparators during the calibration. Another approach for power control of the comparators is to turn o all the comparators during the idle period, that is, the comparators consume power only during the sampling period, which is small time compared to the idle period. This idea can only be applied to the frequency scaling method. If the sampling interval of a ash ADC can be controlled without changing main clock speed, the power dissipation will be clearly reduced, but the speed of the ADC, not the complete circuit, will be degraded; this is a tradeo between power and speed. Even though there will be speed degradation, the ash ADCs will still be relatively faster than the other ADCs. We apply the last technique to reduce the ash ADC power. More accurately, we designed a ash ADC that is power manageable. The ash ADC can be operated at full

95 speed with the maximum sampling clock speed if desired and it can be operated at slower speed with the sampling clock gated. The power consumption is directly proportional to the sampling clock frequency. This section presents the TIQ ash ADC design with a power management method and detailed simulation results [63].

5.2.1

Power Management Method One of the features of the TIQ based ash ADC is that it can operate without a

clock signal; however, to control the sampling interval, we need to add some additional circuits: a sample-and-hold (S/H) circuit for periodically sampling the input voltage and then holding a constant value and ip-ops for extracting the digital outputs at a xed sampling interval. The function of the S/H circuit is to sample the input voltage when a clock signal is high; otherwise, it holds the input voltage which will be forwarded to the ash ADC core. The other circuits for implementing the proposed power management method are ip-ops. The negative-edge triggered master slave D ip-ops with minimal size transistors are used. These are connected at the end of the TIQ based ash ADC core to clearly get the digital outputs. The power management method with frequency scaling in the TIQ ash ADC uses to advantage one of the major characteristics of the TIQ comparator. The power consumption of an inverter can be shut o by using VDD or GND as an input. With this feature, all comparators in the ADC can be powered o when they are not used, which is called the idle period. Power dissipation in the ADC happens only at the time when the comparators are working, which is called the sampling period. Hence, the idea of

96 this method is to control these sampling intervals by adding an AND gate and a PMOS transistor. Figure 5.7 shows the block diagram for the proposed power management method. CLK represents the system clock signal, while Sample determines the sampling intervals. According to the logic of the AND gate, the input voltage is only sampled when both CLK and Sample are high. In the example shown in Figure 5.7, the input voltage

CLK Sample

Read

VDD

Vin

S/H

TIQ flash ADC

DFFs

Dout

Fig. 5.7. Power management method with TIQ ash ADC

is sampled once every two CLK signals (the Read signal is the output of the AND gate). On the other hand, if the output of the AND gate is 0, the S/H circuit will be disconnected, and the PMOS transistor that is connected to VDD will be activated. Then, the input of the TIQ ash ADC will be at the signal maximum. Therefore, there is no power consumption in the ADC during this idle period. The CLK signal is xed

97 at the highest conversion rate, but the rate of the Sample signal is exible depending on how it is controlled. The highest sampling rate can be achieved when the Sample signal is xed to VDD in this method. Also, the maximum power consumption will occur at this time. By controlling the Sample signal, the ADC consumes less power on the average, but there will be some loss in ADC speed. This power management method is only possible in the TIQ ash ADC. By applying the proposed method to the TIQ ash ADC, there is degradation in ADC speed because of the addition of the clock signal and S/H circuits, but there is a much larger reduction in the ADC power dissipation. In the next section, the simulation results will be explained.

5.2.2

Power Simulation Results A 6-bit and an 8-bit TIQ ash ADC were used for the power management method

simulation. Their conversion rates measured by previous simulation with 1.8V supply voltage were up to 2 GSPS for the 6-bit and 1.25 GSPS for the 8-bit ADC. Figure 5.8 shows the functionality of the 6-bit TIQ based ash ADC when the power management method was applied. This maximum sampling speed can be obtained when the Sample signal is equal to VDD and the CLK speed is 6.2 ns, which is shown in the 2nd row in the Table 5.2. The simulation summary for 6-bit and 8-bit ADCs are shown in Table 5.2. The rst simulation was performed using only the clock signal and the ip-op to measure the highest sampling rates when the clock signal was applied. For this condition, the speed was degraded to 1.7 GSPS for the 6-bit ADC and 278 MSPS for the 8-bit ADC. The

98

1.8 1.6 1.4 Input 1.2 1 800m 600m

100n

200n

300n 400n Time (lin) (TIME)

500n

600n

1.5 d5 0 1.5 d4 0 1.5 d3 0 1.5 d2 0 1.5 d1 0 1.5 0 0 100n 200n 300n 400n Time (lin) (TIME) 500n 600n

d0

Fig. 5.8. 6-bit ADC simulation result with power management method

99 Table 5.2. Power simulation results of the 6-bit and 8-bit ADC

Sampling Rate 6-bit ADC (sps) 1.7 G 161.3 M 32.3 M 6.5 M 1.3 M 258.1 K 51.6 K

Power 6-bit ADC (mW ) 203.7131 69.3894 14.1583 3.3724 0.7833 0.1582 0.0319

Sampling Rate 8-bit ADC (sps) 277.8 M 45.5 M 9.1 M 1.8 M 363.6 K 72.7 K

Power 8-bit ADC (mW ) 307.6429 102.8967 15.9862 3.4259 0.6954 0.1398

second simulation was implemented with all the additional circuits. When the sampling interval was increased by ve times, the power dissipation was proportionally reduced for both the 6-bit and 8-bit ADCs. Figure 5.9 represents that the power dissipation is linearly proportional to the frequency scaling.

5.2.3

Summary of the Power Management Method The frequency scaling technique was applied to the TIQ ash ADC. Because of

its comparator architecture, this frequency scaling reduces the power consumption by turning o whole comparators during the idle period. Also, by controlling the sampling intervals, the power consumption of the ADC can be managed. This power management method enables the TIQ ash ADC to be used at dierent sampling rates, depending on the application. The simulation results show that the 6-bit ADC consumes 204 mW at

100
100 80 Power (mW) 60 40 20 0 0

6bit 8bit

50

100 Frequency (MHz)

150

Fig. 5.9. Power dissipation vs. frequency

1.7 GSPS and 0.0319 mW at 51.6 KSPS; the 8-bit ADC consumes 307.6 mW at 277.8 MSPS and 0.1398 mW at 72.7 KSPS. These results show a ten times smaller power consumption than any low power ADCs [] found in the current literature.

101

Chapter 6

Low Voltage Operation in ADCs

Currently, the minimum channel length of the transistors is 0.13 m. This will be scaled down to 0.065 m in 2007 according to the roadmap of semiconductors [44]. This shortening of the minimum channel length of the transistors results in reduction of the power supply voltage to 0.7 V . Also, the SoC trend forces analog circuits to be integrated with digital circuits. To follow both the scaling down of the minimum channel length of the transistors and the SoC trend, ADCs should be operated at low voltages, especially below 1.0 V for portable devices. However, the minimum supply voltage for the analog circuits predicted in the roadmap [44] does not follow the digital supply voltage reduction. Analog supply voltages between 2.5 V and 1.8 V will still be used by 2007. Therefore, it is a great challenge to design an ADC that operates at a low supply voltage because of the relatively high threshold voltage of short channel length transistors. As a result, an ADC should operate with a small VF SR . Many techniques have been devised to overcome this design challenge of low voltage operation, such as low threshold devices [28], the bootstrap technique [12], switchedopamps [59], and special biasing schemes [35]. In addition to these techniques, several design strategies for low voltage ADCs have been introduced [24, 38, 48, 14]. All of these low voltage techniques have been implemented with additional or modied circuits to

102 all known ADC architectures like the successive approximation, pipeline, ash, and modulator. This chapter describes the simulation results and analysis of the TIQ ash ADCs designed with 0.07 m CMOS technology [64]. A new dierential comparator is proposed for low voltage operation. The new dierential comparator is called the quantum voltage (QV) comparator and uses the TIQ comparator concept for voltage comparison and the SSV technique for choosing the internal reference voltages [65].

6.1

Low Voltage Operation with the TIQ ash ADC


The TIQ ash ADC has been simulated with the HSPICE BSIM level 49 and

0.07 m predictive model from the University of California at Berkeley. Table 6.1 shows the summary of the simulation results. The 6-bit and the 8-bit ADC can respectively

Table 6.1. Summary of the simulation results in 0.07 m technology

resolution CMOS tech. power supply max. speed power consumption VF SR VLSB leakage current DNL INL ADC Area

6-bit 0.07 m 0.7 V 4.76 GSPS 11.32 mW 0.24 V - 0.46 V 3.43 mV 78.5A 0.0075 LSB 0.0062 LSB 0.0170 mm2

8-bit 0.07 m 0.7 V 3.57 GSPS 48.88 mW 0.24 V - 0.46 V 0.81 mV 185.1A 0.1684 LSB 0.1234 LSB 0.0625 mm2

103 operate at the speed of 4.76 GSPS and 3.57 GSPS without any missing codes at a 0.7 V power supply voltage [64]. The SPICE simulation result of the 8-bit ADC is shown in Figure 6.1. Both the DNL and the INL shown in Figure 6.2 are less than 0.01 LSB for the 6-bit and 0.20 LSB for the 8-bit ADC. Table 6.2 compares these results with other ADCs. According to the comparison, the TIQ ash ADC has the highest speed, but a large power dissipation compared to other low voltage ADCs.

Table 6.2. Comparisons with other low-voltage ADCs

ADCs

Architecture

Resolution (bit)

VDD (V ) 0.7 0.7 1.0 1.0 1.0 1.0 0.8 1.1

CMOS (m) 0.07 0.07 0.5 0.18 0.5 1.2 0.13 0.35

Speed (sps) 4.76 G 3.57 G 384 K 200 K 5M 50 K 25 M 16 K

Power (mW ) 11.32 48.88 1.56

TIQ TIQ [28] [12] [59] [35] [24] [38]

ash ash SAR pipelined SAR ash-interpolation

6 8 10 10 9 8 6 14

1.6 0.34 480 W

6.1.1

Power Analysis of the TIQ ash ADC Low power consumption is now one of the main issues in ADC design. The ADCs

in Table 6.2 consume very small amounts of power. The TIQ ash ADC architecture is a pure ash type because all 2n 1 comparators turn on at the same time. Therefore, the TIQ ash ADC dissipates more power than the others. The comparator circuits are

104

* hspice file created from 8b007adc_flat.ext - technology: mmi07

Vin bit7

400m 300m 600m 0 600m

bit6

0 600m

bit5

0 600m

bit4

0 600m

bit3

0 600m

bit2

0 600m

bit1

0 600m 0 0 20n 40n Time (lin) (TIME) 60n

bit0

Fig. 6.1. SPICE simulation result with 0.07 m ADC

105

0.1

0.1

0.05 DNL(LSB)

0.05 INL(LSB)

0.05

0.05

0.1 0

20 40 output code

60

0.1 0

20 40 output code

60

(a) DNL of the 6-bit


0.2

(b) INL of the 6-bit

0.2

0.1 DNL(LSB)
INL(LSB)

0.1

0.1

0.1

0.2 0

50

100 150 output code

200

250

0.2 0

50

100 150 output code

200

250

(c) DNL of the 8-bit

(d) INL of the 8-bit

Fig. 6.2. Linearity errors of the ADC

106 an important consideration in power consumption. The power consumption in the TIQ ash ADC is analyzed for each component. Table 6.3 shows the power analysis of the TIQ ash ADC at the maximum sampling rate.

Table 6.3. Power analysis of the TIQ ash ADC by components

TIQ ash ADC components comparator gain booster 01 generator fat tree encoder total

6-bit (mW ) 10.618 (93.8 %) 0.043 (0.4 %) 0.088 (0.8 %) 0.565 (5.0 %) 11.314 (100 %)

8-bit (mW ) 47.983 (98.1 %) 0.083 (0.2 %) 0.085 (0.2 %) 0.731 (1.5 %) 48.882 (100 %)

Most of the power consumption of the ADC occurs in the comparator as expected. The comparators power dissipation is especially large as its resolution increases. Therefore, the comparator section is the critical component for low power consumption. It is hard to reduce power consumption in the ash architecture when the comparators are operating. But, as we mentioned in Chapter 5, the power management is easy in the TIQ comparator since the TIQ comparator can be easily turned o.

6.1.2

Voltage and Temperature Variations in 0.07 m In the TIQ ash ADC implementation, there are two problems that aect changes

in the oset, gain, and linearity: static variation and dynamic variation. The static variation is the process variation. The dynamic variations are power supply voltage and

107 temperature variation. The internal reference voltages, which are xed by the size of the transistors, are the cause of these variations. To correct them, One can use digital signal processing (DSP) on the ADC output. Unfortunately, there are no representation process parameters available for 0.07 m technology. So, only dynamic variations have been simulated. Table 6.4 shows the variation parameters from the 8-bit ADC simulation results as a result of the power supply voltage and temperature variations. The default condition is a 0.7 V power supply voltage at 25o C. There are changes in both the oset and

Table 6.4. Power supply voltage and temperature variation results from the 0.07 m 8-bit TIQ ash ADC
Variations min. Vm (V ) 0.665 V (-5 %) 0.735 V (+5 %) 40o C 85o C default 0.239831 0.264819 0.276854 0.226461 0.251036 max. Vm (V ) 0.431048 0.491096 0.423492 0.490242 0.456555 DNL (LSB) 0.1874 0.1446 0.2345 0.1745 0.1684 INL (LSB) 0.7083 1.3165 2.1280 2.9707 0.1234

gain with these variations. The temperature variations show an especially large amounts of expansion (at 85o C) or contraction (at 40o C) of the full scale range of the reference voltages. As a result of these changes, all characteristics of the ADC including the sampling rates are degraded, while there was no degradation to performance of the ADC in the 0.25 m technology [67, 69]. However, by using the optimal design method [22], The DNL of the ADC shows less sensitivity over the variations than the INL. A new design

108 method for INL optimization is needed to prevent the degradation of the performance of the ADC as temperature or power supply changes. The TIQ ash ADC has been simulated with 0.07 m CMOS technology to verify functionality at low power supply voltage. Both the 6-bit and the 8-bit ADC worked correctly at a 0.7 V with high speed sampling rates and small values of DNL and INL. On the other hand, the static and dynamic variations are just one of the considerations in the design of the TIQ technique. This simulation shows the TIQ technique can be adapted to the future CMOS technologies.

6.2

Quantum Voltage Comparator


One of the major problems in the TIQ ash ADCs [67, 69], is the noise suscep-

tibility of the TIQ comparator. Because the TIQ comparator, which consists of two cascaded inverters, has a single-ended input, the comparator is very sensitive to power supply noise. Each TIQ comparator has an internal reference voltage set by the sizes of the inverters transistors. The reference voltage is changed when there is noise in the power supply. The changing of the reference voltage causes gain and oset errors. In addition to the power supply voltage variation, temperature variation makes the DNL and the INL larger in the TIQ ash ADC. To overcome these problems, a new comparator has been used. It is a type of dierential voltage comparator. Since this comparator has two inputs for analog signals, the common mode noise rejection is much better. This is the reason why most conventional ash ADCs use a dierential comparators. However, these dierential comparators require a resistor ladder circuit to provide the reference voltages (An additional external

109 circuit is needed). However, the quantum voltage (QV) comparator proposed here does not need a resistor ladder circuit. The new QV comparator has been devised from the simple transconductance amplier [34] with the application of the TIQ comparator concept to generate the internal reference voltages. A 0.7 V 6-bit ash ADC and an 8-bit ash ADC have been designed with 0.07 m CMOS technology to implement this new QV comparator [65].

6.2.1

Simple Transconductance Amplier A simple transconductance amplier (STA) circuit consists of two circuits, a cur-

rent mirror and a dierential pair. Figure 6.3 shows the schematic diagram of the current mirror and the dierential pair. The current mirror is devised to provide a constant cur-

I3 Q1 Q2 V3 Q3 Q4

I4 V4

Ib I1 I2 Vb Qb

(a) current mirror

(b) differential pair

Fig. 6.3. Schematic of the current mirror and the dierential pair [34]

rent at both drains of transistor Q1 and Q2 in Figure 6.3(a). As the gate of Q1 is connected to its drain, the transistor Q1 is always in saturation mode. Therefore, the

110 current I2 is xed at a constant current that is equal to the current I1 . In the dierential pair shown in Figure 6.3(b), the dierence between voltage V3 and V4 determines the current I3 and I4 , where I3 + I4 = Ib . Transistor Qb is a current source, which produces a xed current that depends on the voltage Vb . By combining the current mirror (at the top) and the dierential pair (at the bottom), we can devise the STA circuit. This is commonly used as a transconductance amplier that generates a current output depending on the dierence between two input voltages. This circuit can also be used as a voltage amplier by taking a voltage at the output instead of a current. Many ADCs use this voltage amplier as a comparator to compare a reference voltage with an input voltage. The simple voltage amplier has been used in the proposed QV comparator.

6.2.2

Flash ADC with QV comparator The ADC using the proposed QV comparator is a full ash type. As shown in

Figure 6.4, the ADC consists of four blocks: comparator, gain booster, 01 generator, and a fat tree encoder. An analog input voltage, Vin , is connected to each QV comparator at the same time. The Vin is compared with an internal reference voltage Vref in each comparator. To obtain a larger gain, a gain booster is connected to each comparator output. Since the output of the gain booster stage is a thermometer code, an encoder is needed to change the thermometer code to a binary code. This encoding process has two steps. The rst step is converting the thermometer code to the 1-out-of-n code with simple XOR logic, which is implemented with NAND gates. Next, the fat tree

111

Analog Input Voltage max Vm

Thermometer Code

1-out-of-n Code

Binary Code

MSB

Vin

DIV Comparator

Gain Booster

01 Generator

Fat Tree Encoder LSB

minVm

Fig. 6.4. ADC architecture using the QV comparator

112 encoder [23] is used to change the 1-out-of-n code into a binary code. A ROM type encoder [67, 69] could also be used.

6.2.2.1

The QV Comparator

From the previous experience in fabrication of TIQ ash ADCs, we noticed that the single-ended inverter is very sensitive to noise in both the power supply and input signal. These noises resulted in a reduced precision of the fabricated ADC chips. Consequently, a new comparator that is less sensitive to noises is needed. The advantage of the TIQ comparator is that it is fast and simple. There is no alternative comparator available to replace the TIQ comparator in terms of speed and simplicity. Particularly, it is the main idea of the TIQ comparator that the reference voltage is internally xed by the transistor size of the inverter. Hence, no additional circuits are needed. The underlying idea of the TIQ comparator has been applied to the simple transconductance amplier (STA). To do so, we need to modify the STA implementation of the QV comparator. The schematic diagram of the proposed QV comparator is shown in Figure 6.5(a). One can see there is no dierence from the STA schematic diagram except for changes in the W/L ratios. The VTC of the STA is similar to the VTC of the inverter. Figure 6.5(b) shows the VTC of the QV comparator. The C0 and C2 curves show the voltage output of one QV comparator and the voltage output of two cascading QV comparators, respectively. Both the logic zero values of the C0 and C2 curves are not close to ground because of the lower limitation of the voltage out called the Vmin problem in [34]. One can see dierent low voltage limits in each curve of

113

700m

C0

(Wp / Lp) Q1

Q2 (Wp / Lp)

600m

C1
500m

C2 C3

Vout
Vout

400m 300m Vm1 200m in

Vm3

Vin

Q3 (W / L) Q4

Va

Vb

Qb (Wn / Ln)

100m 200m 300m 400m Vin 500m

(a) QV comparator

(b) VTC of the comparator

Fig. 6.5. Schematic of the QV comparator and its voltage transfer characteristic

Figure 6.5(b). This low voltage limit problem can be solved by adding a gain booster. The gain booster in the ADC architecture makes the comparator output transition sharp and also produces a full rail-to-rail swing. In Figure 6.5(b), there are three dierent curves, C1 , C2 , and C3 , simulated by cascading two QV comparators. These curves illustrate that how dierent reference voltages are internally obtained. In conventional dierential comparators, the transistor sizes are standardized and the input Va is taken from a Vref generated by a resistor ladder circuit. Therefore, all 2n 1 comparators for an n-bit ash ADC are identical, but the externally supplied reference voltages are dierent. On the other hand, the proposed QV comparator has dierent transistor sizes for transistors Q3 and Q4 , while transistor Q1 and Q2 are identical. In addition, the input voltage Va and the bias voltage Vb are xed

114 at a constant voltage between GND and VDD. With this intentional mismatch in the dierential pair, the reference voltages can be internally supplied to the comparators. On account of this mismatch, 2n 1 dierent sizes of QV comparators are needed for the ash ADC implementation. The curve C2 in Figure 6.5(a) has been obtained for the case of equal sizes of the dierential pair. If transistor Q3 is larger than Q4 , the C1 and Vm1 will be obtained as the VTC and the Vref , respectively. Conversely, if transistor Q4 size is larger than Q3 , the C3 and Vm3 will be obtained as the VTC and the Vref , respectively. By systematically increasing the size of transistor Q3 and decreasing the size of transistor Q4 , each of the 2n 1 QV comparators has a dierent reference voltage in descending order as shown in Figure 6.4.

6.2.2.2

ADC Design with QV comparator

The ADC has been designed and simulated with the 0.07 m SPICE model parameter provided by the Berkeley Predictive Technology Model (BPTM) [5]. For the rst design attempt with only one QV comparator, the performance of the ADC was worse than expected since the rising and falling time of the comparator was dierent. Using two cascaded QV comparators can stop this degradation by the unbalanced rise and fall time. There is almost 50% penalty in area of the ADC, but a greater than 50% performance improvement has been achieved. Figure 6.6 shows the 8-bit ash ADC layout using two cascaded QV comparators. This layout has been done with full custom design. One may notice that the dierential pair is systematically increased/decreased in Figure 6.6.

115

gain booster

01 generator

two cascaded QV comparators

fat tree encoder

Fig. 6.6. The 8-bit QVC ash ADC layout used two cascading QV comparators

116 6.2.3 Simulation Results and Comparisons with TIQ Comparator For a 0.7 V power supply voltage, the 6-bit and the 8-bit ADC simulation results are shown in Table 6.5. Also, Figure 6.7 shows the SPICE simulation result of the 8-

Table 6.5. Summary of the QVC ADC simulation results

ADC resolution CMOS technology VDD sampling rate power consumption area VLSB DNL INL

6-bit 0.07 m 0.7 V 2.7 GSPS 4.952 mW 0.029 mm2 3.802 mV 0.0502 LSB 0.0287 LSB

8-bit 0.07 m 0.7 V 2.0 GSPS 19.094 mW 0.109 mm2 0.946 mV 0.2996 LSB 0.1581 LSB

bit ADC. The ADCs with the QV comparators (QVC ash ADC) show lower sampling rates, lower power consumption, and lower noise sensitivity than the ADCs with the TIQ comparators. The TIQ ash ADC with 0.07 m CMOS technology and 0.7 V power supply operates up to 4.76 GSPS and 3.57 GSPS with 6-bit and 8-bit resolution. The performance of QV comparator degrades by 50.4% for 6-bit and to 56.0% for 8-bit ADC in terms of sampling rate. The design area of the ADC, however, has been increased by 70.6% for the 6-bit and by 73.0% for the 8-bit ADC compared to the TIQ ash ADCs.

117

400m 300m 600m

d7

Vin

0 600m

d6

0 600m

d5

0 600m

d4

0 600m

d3

0 600m

d2

0 600m

d1

0 600m 0 0 20n 40n 60n Time 80n 100n 120n

d0

Fig. 6.7. The SPICE simulation result of the 8-bit QVC ash ADC

118 6.2.3.1 Power Consumption Comparison with TIQ Comparator

The power dissipation in the ash ADC can be signicantly reduced by using the proposed QV comparator. Table 6.6 shows the power consumption in each circuit of both TIQ ash ADC and the QVC ash ADC. As expected, the comparator is the most power consuming circuit among the ADC components. In the 6-bit ADC, 93.8% and 89.8% of total power is dissipated in the comparator for TIQ ash ADC and QVC ash ADC, respectively. In case of the 8-bit ADC, the power consumption in the comparator is increased by 98.8% for TIQ ash ADC and 95.2% for QVC ash ADC. The comparator in the QVC ash ADC consumes much less power than the one in the TIQ ash ADC. The QVC ash ADC can save power dissipation by 58.1% in the 6-bit and 62.1% in the

Table 6.6. Power Consumption Comparisons with TIQ Comparator

Components

TIQ 6-bit (mW )

QVC 6-bit (mW ) 4.446 0.125 0.053 0.328 4.952

TIQ 8-bit (mW ) 47.983 0.083 0.085 0.731 48.589

QVC 8-bit (mW ) 18.175 0.417 0.064 0.438 19.094

comparator gain booster 01 generator encoder total

10.618 0.043 0.088 0.565 11.314

8-bit compared to the TIQ ash ADC. The power consumption of the gain booster in the QVC ash ADC is slightly increased.

119 6.2.3.2 Noise Comparisons with TIQ Comparator

The noise problems were the critical degradation of both performance and precision in the TIQ ash ADC. The proposed QV comparator has been designed to reduce these noise problems. To check the noise susceptibility, power supply voltage variation and temperature variation are used. The simulation results of these variations are shown in Table 6.7. In the Table 6.7, default means a 0.7 V power supply and a 25o C temperature. Both the TIQ comparator and the QV comparator were designed with these default parameters. Each percentage shows the dierence from the default value. The power supply voltage variation shows that all internal reference voltages are within 2.3% of the default values in the proposed QV comparator. But, the rejection of power supply voltage variation in the TIQ comparator is not as good as for the QV comparator. The temperature variation also shows almost the same trend as power supply variation results. The linearity errors, DNL and INL, show that the QV comparators linearity is less than 0.5 LSB, however, the linearity of the TIQ comparator is much larger than 0.5 LSB even though its default DNL and INL are much smaller than those of the QV comparator. Therefore, the QV comparator is more useful in low noise application than the TIQ ash comparator.

6.2.4

Summary of the QV Comparator The new QV comparator has been designed and simulated to verify the low voltage

operation. Both the 6-bit QVC ash ADC and the 8-bit QVC ash ADC are correctly operating with high speed and low power consumption. The simulation results with

120

Table 6.7. Power supply voltage and temperature variations results

ADC

Variations

min. Vm (V ) 0.24392951 0.23125632 (-5.2%) 0.25558329 (+4.8%) 0.27159260 (+11.3%) 0.21768998 (-10.8%) 0.23800303 0.23249937 (-2.3%) 0.24348051 (+2.3%) 0.25267587 (+6.2%) 0.21517652 (-9.6%) 0.25103569 0.23787332 (-5.2%) 0.26318532 (+4.8%) 0.27685383 (+10.3%) 0.22646139 (-9.8%) 0.23858866 0.23308409 (-2.3%) 0.24406446 (+2.3%) 0.25889330 (+8.5%) 0.22132918 (-7.2%)

max Vm (V ) 0.45681821 0.42730764 (-6.5%) 0.48730602 (+6.7%) 0.42369262 (-7.2%) 0.49055548 (+7.4%) 0.47371028 0.46734040 (-1.3%) 0.47970900 (+1.3%) 0.44516141 (-6.0%) 0.48549266 (+2.5%) 0.45655458 0.42706004 (-6.5%) 0.48702675 (+6.7%) 0.42349234 (-7.2%) 0.49024182 (+7.4%) 0.47875197 0.47232453 (-1.3%) 0.48479614 (+1.3%) 0.45531032 (-4.9%) 0.49972095 (+4.4%)

VLSB (V ) 0.00343369 0.00316212 (-7.9%) 0.00373746 (+8.8%) 0.00245323 (-28.6%) 0.00440106 (+28.2%) 0.00380173 0.00378776 (-0.4%) 0.00381014 (+0.2%) 0.00310461 (-18.3%) 0.00435994 (+14.7%) 0.00080913 0.00074483 (-7.9%) 0.00088127 (+8.9%) 0.00057732 (-28.6%) 0.00103851 (+28.3%) 0.00094552 0.00094189 (-0.4%) 0.00094776 (+0.2%) 0.00077330 (-18.2%) 0.00109603 (+15.9%)

DNL (LSB) 0.0075 0.0246 0.0298 0.0632 0.0681 0.0502 0.0436 0.0561 0.0390 0.0510 0.1684 0.1901 0.1416 0.2345 0.1745 0.2996 0.2859 0.3066 0.2740 0.3230

INL (LSB) 0.0062 0.1852 0.2587 0.4886 0.6799 0.0287 0.0841 0.0884 0.1701 0.1145 0.1234 0.7986 1.1406 2.1280 2.9707 0.1581 0.3807 0.3502 0.4501 0.4180

TIQ 6-bit

default 0.665 V (-5%) 0.735 V (+5%) 40o C 85o C

QVC 6-bit

default 0.665 V (-5%) 0.735 V (+5%) 40o C 85o C

TIQ 8-bit

default 0.665 V (-5%) 0.735 V (+5%) 40o C 85o C

QVC 8-bit

default 0.665 V (-5%) 0.735 V (+5%) 40o C 85o C

121 a 0.7 V power supply shows that the QV comparator has a great advantage in power consumption and noise rejection. Figure 6.8 shows the summary chart of comparing the QVC ash ADC with the TIQ ash ADC. All 5 factors are normalized to 1, for example, in the case of performance, the sampling speed of the 6-bit TIQ ash ADC and the 8-bit TIQ ash ADC is normalized to 1, respectively.

Fig. 6.8. Summary chart of comparing the QVC ash ADC with the TIQ ash ADC

The proposed QV comparator uses the dierential voltage comparator architecture to minimize the input-oset voltage error. Also, the QV comparator utilizes the TIQ comparator concept to eliminate the resistor ladder circuit. As a result, a dramatic improvement of linearity and a large amount of power saving in an ADC can be achieved. Therefore, the QV comparator is preferable for use in the next generation deep sub-micron low voltage CMOS ash ADC.

122

Chapter 7

Conclusions

A simple and fast ash ADC architecture that uses two cascaded CMOS inverters as a comparator, called Threshold Inverter Quantization (TIQ) technique, has been proposed by Ali Tangel [53]. In this thesis, a new design method (systematic size variation (SSV) technique) and a new type of encoder (fat tree encoder) have been developed for advanced TIQ ash ADCs. Their applications can be wideband RF, wireless local loop, radar/communications, universal computer network adaptor, and so on. The TIQ ash ADC oers higher data conversion rates while maintaining a comparable power consumption level so that it is also highly suitable for the complete SoC integration using the standard digital CMOS process. The SSV design technique [22, 66] improved the linearity of the ADC over the CMOS process, temperature, and power supply voltage variations. In particular, the DNL dependence on the variations was almost eliminated in the simulation and fabrication test results. The fat tree encoder [23] overcame the speed limitation of the ROM type encoder, which is the bottleneck of high speed ADCs. The simulation and fabrication test results showed that the fat tree encoder outperformed the commonly used ROM type encoder in terms of speed, power consumption, and area for the 6-bit TIQ ash ADC. However, an automatic layout generation tool should be developed to ease the diculty of the layout design.

123 In addition to the techniques for improving the performance of the TIQ ash ADCs, two applications of the TIQ technique have been proposed in this thesis: low power consumption and low voltage operation. Because parallel voltage comparison is used in the ash ADC, the power consumption gets much larger as we increase the resolution of the ADC. With the TIQ comparator feature, we have implemented both the power and resolution adaptive ash ADC (PRA-ADC) and the power management method in the TIQ ash ADC. The PRA-ADC can operate at dierent resolutions depending on the amplitude of a reception signal in a wireless application. Substantial reduction of power consumption at lower resolution will prolong the battery-powered operation. The power management method can manage the power consumption by controlling its sampling interval on demand. For the low voltage operation, the TIQ ash ADC has been implemented with 0.07 m CMOS technology to verify the functionality at a low power supply voltage. Without any additional circuits, the TIQ ash ADC worked correctly at high speeds and with small linearity errors. To reduce noise problems in the TIQ ash ADCs, a new dierential comparator, called the quantum voltage (QV) comparator, was proposed and designed with SSV technique. The simulation results shows that the QV comparator is preferable for the next generation deep sub-micron low voltage CMOS ash ADC. Table 7.1 shows a comparison of the TIQ ash ADC with other ADCs. This comparison with other ADCs shows the TIQ ash ADCs to have smaller size, higher speed, and lower power consumption. Therefore, we can conclude the TIQ ash ADC is preferable for SoC implementation. The main advantage of the TIQ ash ADC is its high speed and low power dissipation using the standard CMOS technology because an

124

Table 7.1. Comparison the TIQ ash ADC with other ADCs

ADCs

Architecture

Res. (bits)

Tech. (m) 0.18 0.25 0.25 (1.50) 0.50 0.80 0.13 0.18 0.25 0.25 0.25 0.25 0.25 0.35 0.35 0.35 0.35 0.35 0.4 0.5 0.5 0.6 0.6 0.6

Speed (MSPS) 2000 1000 1000 500 200 22 1600 700 200 400 54 8000 10 100 1000 1100 50 500 100 2000 200 500 150

Power (mW ) 101.98 68.98 200.73 2399 46 0.48 328 187 143 150 295 1100 76 108.9 1155 300 10 400 165 970 380 330 395

Area (mm2 ) 0.037 0.051 1.846 1.722 0.48 0.3 0.12 0.45 0.45 1.2 1.0 0.06 5.01 0.9 0.8 0.3 4.8 2.4 1.68 3.99 2.7 5.25 1.2

TIQ w/ROM TIQ w/ROM TIQ w/FAT TIQ w/FAT TIQ[53] [24] [42] [37] [37] [11] [58] [62] [25] [51] [57] [13] [47] [52] [7] [6] [8] [70] [60]

ash ash ash ash ash ash ash ash ash ash semi-ash ash folding & interpolating subranging ash ash interpolating current-interpolating ash pipeline ash ash ash pipeline

6 6 9 8 6 6 6 6 7 6 12 4 8 8 6 6 6 6 8 6 6 6 8

125 inverter not only is typically fast but also consumes less power at the front-end of the ADC. The other advantages of the TIQ ash ADC are Highly adaptable to future CMOS technology development, going to smaller feature size and lower supply voltage. No need for a resistor ladder circuit as the reference voltage source. No need for switches, clock signals, or coupling capacitors for the voltage comparison. Suitable for the standard CMOS technology - ideal for the complete SoC implementation. In contrast, the following two criteria must be carefully considered to obtain a successful TIQ ash ADC implementation: The ADC input range varies due to process parameter changes from one fabrication to another fabrication. The inverter input is single ended, not dierential, causing the ADC to become more susceptible to noise. The following studies are projected for future works. Reducing the noise eects: The noise problems were the major factor of ADC performance degradation in the chip test results. These noise eects will be especially critical as the CMOS technology goes down to sub-micron dimensions. A combination of a well-designed layout strategy, the deep trench isolation, and a separate analog power supply may signicantly minimize the noise eects.

126 Reducing the linearity errors: The linearity errors are also a concern when the CMOS technology scales down. To improve the DNL, the SSV design technique was used in the TIQ ash ADC. But, we still see the large variations in the INL. As a dynamic solution, we may add a programmable pre-amplier to the signal input of the TIQ ash ADC to adjust the oset and gain. Automatic generation of fat tree encoder: With the fat tree encoder, we could increase the TIQ ash ADC speed, however, it is dicult to design the fat tree encoder because of the connections in the sub-trees. An automatic generation of the fat tree encoder will make the design process faster.

127

References

[1] P. E. Allen and D. R. Holberg. CMOS Analog Circuit Design. Holt, Rinehart and Winston, 1987. [2] B. C. Baker. Fast fourier transforms: A good tool for mixed-signal system analysis. Technical report, Microchip Technology, Inc., 1998. http://www.chipcenter.com/ analog/tn014.htm. [3] R. J. Baker, H. W. Li, and D. E. Boyce. CMOS Circuit Design, Layout, and Simulation. IEEE Press Marketing, 1998. [4] B. Black. Analog-to-Digital Converter Architectures and Choices for System Design. Analog Dialogue, 33-8, 1999. http://www.analog.com/library/analogDialogue/ archive/33-08/adc /index.html. [5] BPTM. 0.07 m SPICE model cards, 2001. http://www-device.eecs.berkeley.

edu/ptm/70um nominal.txt. [6] T. P. E. Broekaert, B. Brar, J. P. A. van der Wagt, A. C. Seabaugh, F. J. Morris, T. S. Moise, E. A. Beam III, and G. A. Frazier. A Monolithic 4-Bit 2-Gsps Resonant Tunneling Analog-to-Digital Converter. IEEE Journal of Solid-State Circuits, 33(9):13421349, September 1998. [7] M. Choe, B. Song, and K. Bacrania. An 8-b 100 MSample/s CMOS Pipelined Folding ADC. IEEE Journal of Solid-State Circuits, 36(2):184194, February 2001.

128 [8] D. Dalton, G. J. Spalding, H. Reyhani, T. Murphy, K. Deevy, M. Walsh, and P. Grin. A 200-MSPS 6-bit Flash ADC in 0.6-m CMOS. IEEE Transactions on Circuits and System II, 45(11):14331444, November 1998. [9] M. J. Demler. High-Speed Analog-to-Digital Conversion. Academic Press, 1991. [10] C. Donovan and M. P. Flynn. A Digital 6-bit ADC in 0.25 m CMOS. In IEEE Custom Integrated Circuits Conference, pages 145148, 2001. [11] C. Donovan and M. P. Flynn. A Digital 6-bit ADC in 0.25 m CMOS. IEEE Journal of Solid-State Circuits, 37(3):432437, March 2002. [12] C. J. B. Fayomi, G. W. Roberts, and M. Sawan. A 1-V 10-bit Rail-to-Rail Successive Approximation Analog-to-Digital Converter in Standard 0.18 m CMOS Technology. In IEEE International Symposium on Circuits and Systems, volume 1, pages 460463, 2001. [13] G. Geelen. A 6b 1.1GSample/s CMOS A/D Converter. In IEEE International Solid-State Circuits Conference, pages 128129, 2001. [14] F. Gerfers and Y. Manoli. A Design Strategy for Low-Voltage Low-Power

Continuous-Time A/D Converters. In Design, Automation and Test in Europe, pages 361368, 2001. [15] J. Goes, J. C. Vital, and J. Franca. Systematic Design for Optimisation of Pipelined ADCs. Kluwer Academic Publishers, 2001.

129 [16] J. B. Hughes, M. Mee, and W. Donaldson. A Low Voltage 8-Bit, 400MS/s Switched Current Pipelined Analog-to-Digital Converter. In IEEE International Symposium on Circuits and Systems, volume 1, pages 572575, 2001. [17] The Institute of Electrical and Electronics Engineers, Inc. (IEEE). IEEE Standard for Teminology and Test Methods for Analog-to-Digital Converters, 2001. IEEE Std 1241-2000. [18] M. Ito, T. Miki, S. Hosotani, T. Kumamoto, Y. Yamashita, M. Kijima, T. Okuda, and K. Okada. A 10bit 20MS/s 3V Supply CMOS A/D Converter. IEEE Journal of Solid-State Circuits, 29(12):15311536, December 1994. [19] R. Kanan, F. Kaess, and M. Declercq. A 640mW High Accuracy 8-bit 1GHz Flash ADC Encoder. In IEEE International Symposium on Circuits and Systems, volume 2, pages 420423, 1999. [20] P. T. F. Kwok and H. C. Luong. Power Optimization for Pipeline Analog-to-Digital Converter. IEEE Transactions on Circuits and System II, 46(5):549553, May 2001. [21] D. Lee. Fat tree encoder for ultra-high speed ash a/d converters. Masters thesis, The Pennsylvania State University, 2002. [22] D. Lee, J. Yoo, and K. Choi. Design Method and Automation of Comparator Generation for Flash A/D Converters. In IEEE International Symposium on Quality Electronic Design, pages 138142, 2002.

130 [23] D. Lee, J. Yoo, K. Choi, and J. Ghaznavi. Fat Tree Encoder Design for Ultra-High Speed Flash A/D Converters, To appear in IEEE Midwest Symposium on Circuits and Systems, 2002. [24] J. Lin and B. Haroun. An Embedded 0.8V/480w 6b/22MHz Flash ADC in 0.13m Digital CMOS Process using Nonlinear Double-Interpolation Technique. In IEEE International Solid-State Circuits Conference, pages 308, 468, 2002. [25] M. Liu and S. Liu. An 8-bit 10 MS/s Folding and Interpolating ADC Using

the Continuous-Time Auto-Zero Technique. IEEE Journal of Solid-State Circuits, 36(1):122128, January 2001. [26] B. Loriferne. Analog-Digital and Digital-Analog Conversion. Heyden, 1982. [27] H. Luong, D. Hebert, and T. Duzer. Fully Parallel Superconducting Analog-toDigital Converter. IEEE Transactions on Applied Superconductivity, 3(1):2633 2636, March 1993. [28] Y. Matsuya and J. Yamada. 1-V Power Supply, Low-Power Consumption A/D Conversion Technique with Swing-Supression Noise Shaping. IEEE Journal of SolidState Circuits, 29(12):15241530, December 1994. [29] Maxim Integrated Products. ADC and DAC Glossary, 2000. http://www.maximic.com/appnotes.cfm/appnote num ber/641.

131 [30] Maxim Integrated Products. INL/DNL Measurements for High-Speed Analoghttp://www.maxim-ic.com/appnotes.cfm/

to-Digital Converters (ADCs), 2000. appnote nu mber/283.

[31] Maxim Integrated Products. Pipeline ADCs Come of Age, 2000. http://www. maxim-ic.com/appnotes.cfm/appnote nu mber/634. [32] Maxim Integrated Products. The ABCs of ADCs: Understanding How ADC Errors Aect System Performance, 2001. http://www.maxim-ic.com/appnotes.cfm/ appnote nu mber/748. [33] Maxim Integrated Products. MAX108 Data Sheet, 2001. http://pdfserv.maximic.com/arpdf/MAX108.pdf. [34] C. Mead. Analog VLSI and Neural Systems. Addison-Wesley, 1989. [35] S. Mortezapour and E. K. F. Lee. A 1-V 8-Bit Successive Approximation ADC in Standard CMOS Process. IEEE Journal of Solid-State Circuits, 35(4):642646, April 2000. [36] A. Moscovici. High Speed A/D Converters: Understanding Data Converters through SPICE. Kluwer Academic Publishers, 2001. [37] K. Nagaraj, D. A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T. Viswanathan. A Dual-Mode 700-Msample/s 6-bit 200-Msample/s 7-bit A/D Converter in a 0.25 m Digital CMOS Process. IEEE Journal of Solid-State Circuits, 35(12):17601768, December 2000.

132 [38] F. Mu oz, A. P. VegaLeal, R. G. Carvajal, A. Torralba, J. Tombs, and J. Ram n irez Angulo. A 1.1V Low-Power Modulator For 14-b 16KHz A/D Conversion. In IEEE International Symposium on Circuits and Systems, volume 1, pages 619622, 2001. [39] S. Padoan, A. Boni, C. Morandi, and F. Venturi. A Novel Coding Schemes for the ROM of parallel ADCs. In IEEE International Symposium on Circuits and Systems, volume 2, pages 271274, 1998. [40] Y. Park, S. Karthikeyan, F. Tsay, and E. Bartolome. A 10b 100MSamples/s CMOS Pipelined ADC with 1.8V Power Supply. In IEEE International Solid-State Circuits Conference, pages 130131, 2001. [41] Jan. M. Rabaey. Digital Integrated Circuits: A Design Perspective. Prentice Hall, 1996. [42] P. C. S. Scholtens and M. Vertregt. A 6-b 1.6-Gsample/s Flash ADC in 0.18m CMOS Using Averaging Termination. IEEE Journal of Solid-State Circuits, 37(12):15991609, December 2002. [43] J. Segura, J. L. Rossello, J. Morra, and H. Sigg. A Variable Threshold Voltage Inverter for CMOS Programmable Logic Circuits. IEEE Journal of Solid-State Circuits, 33(8):12621265, August 1998. [44] Semiconductor Industry Association (SIA). The International Technology Roadmap for Semiconductors, 2001. http://public.itrs.net.

133 [45] N. H. Sheng, R. Yu, C. Chang, K. Cheng, G. Gutierrez, and P. van der Wagt. A 10bit, 500MS/s Analog-to-Digital Converter. In IEEE MTT-S Microwave Symposium Digest, volume 1, pages 197200, 1999. [46] J. Singh. High Speed Multi-Channel Data Aquisition Chip. In IEEE International Conference on Electronics, Circuits and Systems, volume 1, pages 401404, 1998. [47] B. Song, P. Rakers, and S. Gillig. A 1-V 6-b 50-MSample/s Current-Interpolating CMOS ADC. IEEE Journal of Solid-State Circuits, 35(4):647651, April 2000. [48] B. S. Song. Analog Front-End Macro Circuit Design. In International Symposium on VLSI Technology, Systems, and Applications, pages 223226, 1999. [49] S. Song. A high speed ash analog to digital converter using a new type of quantizer. Masters thesis, The Pennsylvania State University, 2000. [50] L. Sumanen and K. Halonen. A Sngle-Amplier 6-Bit CMOS Pipelin A/D Converter for WCDMA Receivers. In IEEE International Symposium on Circuits and Systems, volume 1, pages 584587, 2001. [51] R. Taft and M. Tursi. A 100-MS/s 8-b CMOS Subranging ADC with Sustained Parametric Performance from 3.8V down to 2.2V. IEEE Journal of Solid-State Circuits, 36(3):331338, March 2001. [52] Y. Tamba and K. Yamakido. A CMOS 6b 500 MSample/s ADC for a Hard Disk Drive Read Channel. In IEEE International Solid-State Circuits Conference, pages 324325, 1999.

134 [53] A. Tangel. VLSI Implementation of the Threshold Inverter Quantization (TIQ) Technique for CMOS Flash A/D Converter Applications. PhD thesis, The Pennsylvania State University, 1999. [54] Texas Instruments. Data Acquisition Circuits Data Book: Data Convertsion and DSP Analog Interface, 1995. [55] F. Thomas, F. Debrie, M. Gloanec, M. L. Paih, P. Martin, T. Nguyen, and S. Ruggeri. 1-GHz GaAs ADC Building Blocks. IEEE Journal of Solid-State Circuits, 24(2):223228, April 1989. [56] S. Tsukamoto, W. G. Schoeld, and T. Endo. A CMOS 6-b 400-Msamples/s ADC with Error Correction. IEEE Journal of Solid-State Circuits, 33(12):19391947, December 1998. [57] K. Uyttenhove, A. Marques, and M. Steyaert. A 6-bit 1 GHz Acquisition Speed CMOS Flash ADC with Digital Error Correction. In IEEE Custom Integrated Circuits Conference, pages 249252, 2000. [58] H. van der Ploeg, G. Hoogzaad, H. A. H. Termeer, M. Vertregt, and R. L. J. Roovers. A 2.5-V 12-b 54-Msample/s 0.25-m CMOS ADC in 1-mm2 With Mixed-Signal Chopping and Calibration. IEEE Journal of Solid-State Circuits, 36(12):18591867, December 2001. [59] M. Waltari and K. A. I. Halonen. 1-V 9-Bit Pipelined Switched-Opamp ADC. IEEE Journal of Solid-State Circuits, 36(1):129134, January 2001.

135 [60] Y. Wang and B. Razavi. An 8-Bit 150-MHz CMOS A/D Converter. IEEE Journal of Solid-State Circuits, 35(3):308317, March 2000. [61] P. Xia, K. Jenkins, M. Soyuer, H. Ainspan, J. Burghartz, H. Shin, M. Dolan, and D. Harame. A 4b 8GSample/s A/D Converter in SiGe Bipolar Technology. In IEEE International Solid-State Circuits Conference, pages 124125, 1997. [62] C.-K. K. Yang, V. Stojanovic, S. Modjtahedi, M. A. Horowitz, and W. F. Ellersick. A Serial-Link Transceiver Based on 8-GSamples/s A/D and D/A Converters in 0.25-m CMOS. IEEE Journal of Solid-State Circuits, 36(11):16841692, November 2001. [63] J. Yoo and K. Choi. Design of Low Power Flash A/D Converter and Power Management Method, Submitted to 40th Design Automation Conference, 2003. [64] J. Yoo, K. Choi, and J. Ghaznavi. A 0.07 m CMOS Flash Analog-to-Digital Converter for High Speed and Low Voltage Applications, Submitted to Great Lake Symposium on VLSI, 2003. [65] J. Yoo, K. Choi, and J. Ghaznavi. Quantum Voltage Comparator for 0.07 m CMOS Flash A/D Converters, To appear in IEEE CS Annual Symposium on VLSI, 2003. [66] J. Yoo, K. Choi, and D. Lee. Comparator Genration and Selection for Highly Linear CMOS Flash Analog-to-Dgital Converter, To appear in Journal of Analog Integrated Circuit and Signal Processing, 2003.

136 [67] J. Yoo, K. Choi, and A. Tangel. A 1-GSPS CMOS Flash Analog-to-Digital Converter for System-on-Chip Applications. In IEEE CS Annual Workshop on VLSI, pages 135139, 2001. [68] J. Yoo, D. Lee, K. Choi, and J. Kim. A Power and Resolution Adaptive Flash Analog-to-Digital Converteri. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 233236, 2002. [69] J. Yoo, D. Lee, K. Choi, and A. Tangel. Future-Ready Ultrafast 8bit CMOS ADC for System-on-Chip Applications. In IEEE International ASIC/SOC Conference, pages 455459, 2001. [70] K. Yoon, S. Park, and W. Kim. A 6b 500MSample/s CMOS Flash ADC with a Background Interpolated Auto-Zeroing Technique. In IEEE International SolidState Circuits Conference, pages 326327, 1999.

137

Appendix A

DNL and INL Calculating Program

#include <stdio.h> #include <stdlib.h> #include <math.h> WarnNExit1() { printf( "Memory allocation failed !!\n" ); exit( -1 ); } main( int argc, { double double int char FILE char* argv[] ) *inl, *dnl, *selVm; prevVm, idealLSBVm, temp1, temp2, temp3; i, numOfBit, numOfVm; outFileName1[40], outFileName2[40]; *fp_in, *fp_out_dnl, *fp_out_inl;

if( argc != 2 ) { printf( "Usage: iderr xBit_VmFile\n" ); exit( -1 ); } printf( "Which bit ADC is it ? " ); scanf( "%d", &numOfBit ); numOfVm = (int)pow(2.0, (double)numOfBit)-1; inl = (double *)malloc( numOfVm*sizeof(double) ); if( inl == NULL ) WarnNExit1(); dnl = (double *)malloc( numOfVm*sizeof(double) ); if( dnl == NULL ) WarnNExit1(); selVm = (double *)malloc( numOfVm*sizeof(double) ); if( selVm == NULL ) WarnNExit1(); fp_in = fopen( argv[1], "r" ); for( i=0; i<numOfVm; i++ ) { fscanf( fp_in, "%lf", &selVm[i] ); } fclose( fp_in );

138
idealLSBVm = (selVm[numOfVm-1]-selVm[0]) / (numOfVm-1); prevVm = selVm[0]-idealLSBVm; for( i=0; i<numOfVm; i++ ) { dnl[i] = ((selVm[i]-prevVm)/idealLSBVm) - 1.0; inl[i] = ((selVm[i]-selVm[0])/idealLSBVm) - (double)i; prevVm = selVm[i]; } strcpy( strcat( strcpy( strcat( outFileName1, outFileName1, outFileName2, outFileName2, argv[1] ); "_dnl.m" ); argv[1] ); "_inl.m" );

fp_out_dnl = fopen( outFileName1, "w" ); fp_out_inl = fopen( outFileName2, "w" ); fprintf( fp_out_dnl, "x = [\n" ); fprintf( fp_out_inl, "x = [\n" ); for( i=0; i<numOfVm; i++) { fprintf( fp_out_dnl, "%d; \n", i ); fprintf( fp_out_inl, "%d; \n", i ); } fprintf( fp_out_dnl, "]\n\n" ); fprintf( fp_out_inl, "]\n\n" ); fprintf( fp_out_dnl, "y = [\n" ); fprintf( fp_out_inl, "y = [\n" ); for( i=0; i<numOfVm; i++ ) { fprintf( fp_out_dnl, "%13.10f; \n", dnl[i] ); fprintf( fp_out_inl, "%13.10f; \n", inl[i] ); } fprintf( fp_out_dnl, "]\n" ); fprintf( fp_out_inl, "]\n" ); fclose( fp_out_dnl ); fclose( fp_out_inl ); free( inl ); free( dnl ); free( selVm ); }

139

Appendix B

MOSIS Parametric Test Results for TSMC 0.25 m CMOS Run

MOSIS PARAMETRIC TEST RESULTS RUN: T14Y (LO_EPI) TECHNOLOGY: SCN025 VENDOR: TSMC FEATURE SIZE: 0.25 microns

INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on a selected wafer are also attached. COMMENTS: TSMC 0251P5M

TRANSISTOR PARAMETERS MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K (Uo*Cox/2) Low-field Mobility

W/L 0.36/0.24

N-CHANNEL P-CHANNEL

UNITS

0.51 20.0/0.24 548 0.53 7.6 20.0/0.24 6.9 50/50 0.44 5.9 <50.0 0.44 120.1 403.46

-0.50

volts

-249 -0.54 -7.2

uA/um volts volts

< 2.5

pA/um

-0.58 -7.0 <50.0 0.63 -23.9 80.29

volts volts pA V^0.5 uA/V^2 cm^2/V*s

COMMENTS: Poly bias varies with design technology. To account for mask and etch bias use the appropriate value for the parameters XL and XW in your SPICE model card. Design Technology XL XW ----------------------- ------

140
SCN5M_DEEP (lambda=0.12) thick oxide, thick oxide, TSMC25 thick oxide, thick oxide, SCN5M_SUBM (lambda=0.15) thick oxide, thick oxide, 0.03 0.02 -0.03 0.03 0.03 0.03 -0.03 0.02 -0.03 -0.04 -0.04 -0.04 0.00 0.00 0.00 0.00 0.00 0.00

NMOS PMOS NMOS PMOS NMOS PMOS

FOX TRANSISTORS Vth

GATE Poly

N+ACTIVE >6.6

P+ACTIVE <-6.6

UNITS volts

PROCESS PARAMETERS Sheet Resistance Contact Resistance Gate Oxide Thickness PROCESS PARAMETERS Sheet Resistance Contact Resistance

N+ACTV 4.4 5.8 58

P+ACTV 3.4 5.0

POLY 4.0 5.0

N+BLK 58.9

MTL1 0.07

MTL2 0.07 3.26

MTL3 0.07 6.08

UNITS ohms/sq ohms angstrom

PLY+BLK 184.5

MTL4 0.07 9.40

MTL5 0.03 12.14

N_WELL 1076

UNITS ohms/sq ohms

COMMENTS: BLK is silicide block.

CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY Area (substrate) 1770 1921 101 Area (N+active) 5968 Area (P+active) 5726 Area (poly) Area (metal1) Area (metal2) Area (metal3) Area (metal4) Fringe (substrate) 425 357 Fringe (poly) Fringe (metal1) Fringe (metal2) Fringe (metal3) Fringe (metal4) Overlap (N+active) 614 Overlap (P+active) 674

M1 M2 39 19 52 21 63 18 39

M3 13 14 11 16 41

M4 9 12 8 10 16 44 43 25 30 37 54

M5 8 10 6 7 10 16 45 25 22 25 31 42 63

N_WELL 65

21 61 71 42 56

56 31 37 58

UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um aF/um aF/um

CIRCUIT PARAMETERS Inverters Vinv K 1.0 1.02

UNITS

volts

141
Vinv Vinv Gain Ring Oscillator Freq. DIV1024_T (31-stg,3.3V) DIV1024 (31-stg,2.5V) Ring Oscillator Power DIV1024_T (31-stg,3.3V) DIV1024 (31-stg,2.5V) COMMENTS: DEEP_SUBMICRON 1.5 2.0 2.0 1.07 1.12 -16.65 199.80 260.20 0.13 0.06 MHz MHz uW/MHz/gate uW/MHz/gate volts volts

T14Y SPICE BSIM3 VERSION 3.1 PARAMETERS SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8 * DATE: May 21/01 * LOT: T14Y WAF: * Temperature_parameters=Default .MODEL CMOSN NMOS ( +VERSION = 3.1 TNOM +XJ = 1E-7 NCH +K1 = 0.4503218 K2 +K3B = 2.7511903 W0 +DVT0W = 0 DVT1W +DVT0 = 0.4948826 DVT1 +U0 = 300.237024 UA +UC = 2.411595E-11 VSAT +AGS = 0.2493074 B0 +KETA = 9.120027E-4 A1 +RDSW = 117.272191 PRWG +WR = 1 WINT +XL = 3E-8 XW +DWB = 5.476111E-9 VOFF +CIT = 0 CDSC +CDSCB = 0 ETA0 +DSUB = 0.0311455 PCLM +PDIBLC2 = 4.688174E-3 PDIBLCB +PSCBE1 = 7.991332E10 PSCBE2 +DELTA = 0.01 RSH +PRT = 0 UTE +KT1L = 0 KT2 +UB1 = -7.61E-18 UC1 +WL = 0 WLN +WWN = 1 WWL +LLN = 1 LW +LWL = 0 CAPMOD +CGDO = 6.14E-10 CGSO +CJ = 1.753617E-3 PB +CJSW = 4.328986E-10 PBSW

101 LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 49 5.8E-9 0.3877332 1E-3 2.684962E-7 0 -0.5 2.358208E-18 1.4820567 3.568634E-6 0.4500971 -0.2 4.377598E-9 -2.290208E-8 1.9975727 0 8.333134E-4 0.9990847 0.8506408 0.0099971 1 -0.11 4.31E-9 3.3E4 0 0 1 0.5 1E-12 0.4591946 0.3552107

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

27 2.3549E17 7.498548E-3 1E-7 0 0.5924031 -1.207596E-9 1.423302E5 -2.000837E-7 3.802033E-5 0.5 0 -4E-8 -0.0948739 2.4E-4 4.108112E-3 1.8275359 -0.0999829 5.16406E-10 4.4 -1.5 0.022 -5.6E-11 1 0 0 2 6.14E-10 0.99 0.99

142
+CJSWG = 3.29E-10 +CF = 0 +PK2 = 2.428891E-3 * .MODEL CMOSP PMOS ( +VERSION = 3.1 +XJ = 1E-7 +K1 = 0.6126803 +K3B = 14.442188 +DVT0W = 0 +DVT0 = 2.3705962 +U0 = 121.9538647 +UC = -1E-10 +AGS = 0.1657709 +KETA = 0.01749 +RDSW = 1.050595E3 +WR = 1 +XL = 3E-8 +DWB = 3.248109E-8 +CIT = 0 +CDSCB = 0 +DSUB = 0.9345426 +PDIBLC2 = 0.0213771 +PSCBE1 = 2.607383E10 +DELTA = 0.01 +PRT = 0 +KT1L = 0 +UB1 = -7.61E-18 +WL = 0 +WWN = 1 +LLN = 1 +LWL = 0 +CGDO = 6.74E-10 +CJ = 1.913294E-3 +CJSW = 3.825105E-10 +CJSWG = 2.5E-10 +CF = 0 +PK2 = 3.434527E-3 * PBSWG PVTH0 WKETA = 0.99 = -0.01 = 0.0103867 MJSWG PRDSW LKETA LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA = 0.3552107 = -10 = -7.732829E-3 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 49 5.8E-9 -0.5887506 0 1E-9 0 -0.1278685 1E-21 0.9432943 5E-6 0.3 -0.3344162 3.148114E-8 -4.599354E-8 1.2000247 0 -0.1020914 8.653573E-4 0.4304851 6.011881E-3 1 -0.11 4.31E-9 3.3E4 0 0 1 0.5 1E-12 0.4712889 0.296387 0.296387 -12.3017562 -0.0136271

TNOM NCH K2 W0 DVT1W DVT1 UA VSAT B0 A1 PRWG WINT XW VOFF CDSC ETA0 PCLM PDIBLCB PSCBE2 RSH UTE KT2 UC1 WLN WWL LW CAPMOD CGSO PB PBSW PBSWG PVTH0 WKETA

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

27 4.1589E17 7.885899E-3 1E-6 0 0.7414674 1.62789E-9 2E5 1.621073E-6 6.582776E-4 0.1217968 0 -4E-8 -0.1241961 2.4E-4 0.4473028 0.7700996 -1E-3 6.650832E-9 3.4 -1.5 0.022 -5.6E-11 1 0 0 2 6.74E-10 0.9893175 0.6116479 0.6116479 6.429985E-3 0.0244275

143

Appendix C

MOSIS Parametric Test Results for TSMC 0.18 m CMOS Run

MOSIS PARAMETRIC TEST RESULTS RUN: T1AX (LO_EPI) TECHNOLOGY: SCN018 VENDOR: TSMC FEATURE SIZE: 0.18 microns

INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on a selected wafer are also attached. COMMENTS: DSCN6M018_TSMC

TRANSISTOR PARAMETERS MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K (Uo*Cox/2) Low-field Mobility

W/L 0.27/0.18

N-CHANNEL P-CHANNEL

UNITS

0.54 20.0/0.18 537 0.54 4.8 20.0/0.18 10.5 50/50 0.45 3.8 <50.0 0.55 163.1 396.76

-0.56

volts

-255 -0.55 -5.4

uA/um volts volts

-4.3

pA/um

-0.44 -5.1 <50.0 0.64 -35.3 85.87

volts volts pA V^0.5 uA/V^2 cm^2/V*s

COMMENTS: Poly bias varies with design technology. To account for mask and etch bias use the appropriate value for the parameters XL and XW in your SPICE model card. Design Technology XL XW ----------------------- ------

144
SCN6M_DEEP (lambda=0.09) thick oxide TSMC18 thick oxide SCN6M_SUBM (lambda=0.10) thick oxide -0.02 -0.03 -0.02 -0.02 -0.04 -0.07 -0.01 -0.01 0.00 0.00 0.00 0.00

FOX TRANSISTORS Vth COMMENTS:

GATE Poly

N+ACTIVE >6.6

P+ACTIVE <-6.6

UNITS volts

PROCESS PARAMETERS N+ACTV P+ACTV POLY Sheet Resistance 6.8 7.6 7.9 Contact Resistance 11.2 11.5 10.1 Gate Oxide Thickness 42

N+BLK 59.8

PLY+BLK 332.0

MTL1 0.08

MTL2 0.08 5.17

UNITS ohms/sq ohms angstrom

PROCESS PARAMETERS Sheet Resistance Contact Resistance

MTL3 0.08 9.99

MTL4 0.07 15.10

MTL5 0.07 19.91

MTL6 0.03 23.55

N_WELL 971

UNITS ohms/sq ohms

COMMENTS: BLK is silicide block.

CAPACITANCE PARAMETERS Area (substrate) Area (N+active) Area (P+active) Area (poly) Area (metal1) Area (metal2) Area (metal3) Area (metal4) Area (metal5) Area (no well) Fringe (substrate) Fringe (poly) Fringe (metal1) Fringe (metal2) Fringe (metal3) Fringe (metal4) Fringe (metal5) Overlap (P+active) COMMENTS:

N+ACTV P+ACTV 972 1127

POLY M1 M2 M3 M4 M5 99 37 18 13 8 8 8160 49 19 13 10 9 7944 60 16 10 7 5 36 14 9 6 37 14 9 36 15 41

M6 3 8 4 5 6 9 14 33 -17 19 22 27 35 52

N_WELL 70

145 263

222

15 58 53 41 23 63 38 29 23 20 54 34 22 51 35 27 55 35 57 650

UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um aF/um aF/um

CIRCUIT PARAMETERS Inverters Vinv Vinv Vol (100 uA)

UNITS K 1.0 1.5 2.0 0.76 0.80 0.08 volts volts volts

145
Voh (100 uA) Vinv Gain Ring Oscillator Freq. D1024_THK (31-stg,3.3V) DIV1024 (31-stg,1.8V) Ring Oscillator Power D1024_THK (31-stg,3.3V) DIV1024 (31-stg,1.8V) COMMENTS: DEEP_SUBMICRON 2.0 2.0 2.0 1.62 0.83 -24.58 322.43 372.40 0.07 0.02 volts volts

MHz MHz uW/MHz/gate uW/MHz/gate

T1AX SPICE BSIM3 VERSION 3.1 PARAMETERS SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8 * DATE: Dec 4/01 * LOT: T1AX WAF: * Temperature_parameters=Default .MODEL CMOSN NMOS ( +VERSION = 3.1 TNOM +XJ = 1E-7 NCH +K1 = 0.5981832 K2 +K3B = 2.629076 W0 +DVT0W = 0 DVT1W +DVT0 = 1.4116057 DVT1 +U0 = 297.4590133 UA +UC = -4.61214E-12 VSAT +AGS = 0.3492206 B0 +KETA = 5.39682E-3 A1 +RDSW = 124.5038577 PRWG +WR = 1 WINT +XL = -2E-8 XW +DWB = -3.105321E-9 VOFF +CIT = 0 CDSC +CDSCB = 0 ETA0 +DSUB = 1 PCLM +PDIBLC2 = 0.01 PDIBLCB +PSCBE1 = 1.032223E9 PSCBE2 +DELTA = 0.01 RSH +PRT = 0 UTE +KT1L = 0 KT2 +UB1 = -7.61E-18 UC1 +WL = 0 WLN +WWN = 1 WWL +LLN = 1 LW +LWL = 0 CAPMOD +CGDO = 7.75E-10 CGSO +CJ = 9.673165E-4 PB +CJSW = 2.597686E-10 PBSW +CJSWG = 3.3E-10 PBSWG +CF = 0 PVTH0

4001 LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 49 4.2E-9 0.3805625 1E-3 2.149234E-7 0 0.0697787 1.33445E-18 1.8184754 -1E-7 1 -0.2 5.802111E-9 -1.17481E-8 2.5 0 -0.0366657 0.178682 0.653609 0.220923 1 -0.11 4.31E-9 3.3E4 0 0 1 0.5 1E-12 0.3622159 0.1233505 0.1233505 -4.9618035

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

27 2.3549E17 2.175458E-3 1E-7 0 0.3365752 -6.78356E-10 9.309996E4 -1.585191E-8 0 0.5 0 -1E-8 -0.0836352 2.4E-4 0 1.0387434 -0.0826371 5.396023E-10 6.8 -1.5 0.022 -5.6E-11 1 0 0 2 7.75E-10 0.7293021 0.6680142 0.6680142 2.743569E-4

146
+PK2 = 6.870311E-4 +PU0 = 37.3850131 +PVSAT = 1.98836E3 * .MODEL CMOSP PMOS ( +VERSION = 3.1 +XJ = 1E-7 +K1 = 0.599858 +K3B = 11.7223493 +DVT0W = 0 +DVT0 = 0.4283261 +U0 = 118.6156817 +UC = -1E-10 +AGS = 0.3889784 +KETA = 0.0182318 +RDSW = 255.0721045 +WR = 1 +XL = -2E-8 +DWB = 6.976785E-9 +CIT = 0 +CDSCB = 0 +DSUB = 0.7200259 +PDIBLC2 = 0.0125103 +PSCBE1 = 2.048769E9 +DELTA = 0.01 +PRT = 0 +KT1L = 0 +UB1 = -7.61E-18 +WL = 0 +WWN = 1 +LLN = 1 +LWL = 0 +CGDO = 6.5E-10 +CJ = 1.116942E-3 +CJSW = 2.000101E-10 +CJSWG = 4.22E-10 +CF = 0 +PK2 = 2.552749E-3 +PU0 = -1.7513087 +PVSAT = -50 * WKETA PUA PETA0 = 7.774837E-3 = 1.660666E-10 = -1E-4 LKETA PUB PKETA LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA PUB PKETA = -9.045823E-3 = 9.47369E-25 = -4.207608E-3 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 49 4.2E-9 -0.4244996 0 9.709252E-8 0 0.1 1E-21 1.6970275 5E-6 0.3 -0.4238984 1.942069E-8 -3.974819E-8 2 0 -0.1822938 1.832458E-3 0 13.5059723 1 -0.11 4.31E-9 3.3E4 0 0 1 0.5 1E-12 0.4292283 0.2893301 0.2893301 11.8314491 0.0154256 1E-21 1.743747E-3

TNOM NCH K2 W0 DVT1W DVT1 UA VSAT B0 A1 PRWG WINT XW VOFF CDSC ETA0 PCLM PDIBLCB PSCBE2 RSH UTE KT2 UC1 WLN WWL LW CAPMOD CGSO PB PBSW PBSWG PVTH0 WKETA PUA PETA0

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

27 4.1589E17 0.0279437 1E-6 0 0.2481671 1.583381E-9 2E5 1.561212E-6 0.3633365 0.5 0 -1E-8 -0.0985219 2.4E-4 0.0426564 2.1991692 -1E-3 5.917325E-10 7.6 -1.5 0.022 -5.6E-11 1 0 0 2 6.5E-10 0.8657518 0.6339172 0.6339172 1.786781E-3 2.467859E-3 -7.55425E-11 1E-4

147

Appendix D

MOSIS Parametric Test Results for AMI C5 (0.50 m) Run

MOSIS PARAMETRIC TEST RESULTS RUN: T26B TECHNOLOGY: SCN05 VENDOR: AMI FEATURE SIZE: 0.5 microns

INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on a selected wafer are also attached. COMMENTS: American Microsystems, Inc. C5N

TRANSISTOR PARAMETERS MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K (Uo*Cox/2) Low-field Mobility

W/L 3.0/0.6

N-CHANNEL P-CHANNEL

UNITS

0.80 20.0/0.6 443 0.70 10.0 20.0/0.6 < 2.5 50/50 0.72 11.6 <50.0 0.49 58.6 478.57

-0.93

volts

-243 -0.91 -10.0

uA/um volts volts

< 2.5

pA/um

-0.95 -11.8 <50.0 0.59 -18.8 153.53

volts volts pA V^0.5 uA/V^2 cm^2/V*s

COMMENTS: Poly bias varies with design technology. To account for mask and etch bias use the appropriate value for the parameter XL in your SPICE model card. Design Technology XL -----------------------

148
SCN_SUBM (lambda=0.30) AMI_C5 SCN (lambda=0.35) 0.00 0.00 -0.10

FOX TRANSISTORS Vth

GATE Poly

N+ACTIVE >15.0

P+ACTIVE <-15.0

UNITS volts

PROCESS PARAMETERS Sheet Resistance Contact Resistance Gate Oxide Thickness PROCESS PARAMETERS Sheet Resistance Contact Resistance

N+ACTV 84.5 58.4 141 N\PLY 829

P+ACTV 104.6 138.5

POLY 22.1 15.2

POLY2 39.0 24.7

MTL1 0.09

MTL2 0.10 0.77

MTL3 0.04 0.70

UNITS ohms/sq ohms angstrom

N_WELL 825

UNITS ohms/sq ohms

COMMENTS: N\POLY is N-well under polysilicon.

CAPACITANCE PARAMETERS N+ACTV P+ACTV Area (substrate) 424 727 Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Area (metal2) Fringe (substrate) 315 262 Fringe (poly) Fringe (metal1) Fringe (metal2) Overlap (N+active) Overlap (P+active)

POLY 87 2441 2359

POLY2

M1 33 37 64 58

M2 17 17 17 37

M3 11 12 10 14 39 40 30 37 59

N_WELL 41

883

76 58

59 41 55

207 264

UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um

CIRCUIT PARAMETERS Inverters Vinv Vinv Vol (100 uA) Voh (100 uA) Vinv Gain Ring Oscillator Freq. DIV256 (31-stg,5.0V) D256_WIDE (31-stg,5.0V) Ring Oscillator Power DIV256 (31-stg,5.0V) D256_WIDE (31-stg,5.0V)

UNITS K 1.0 1.5 2.0 2.0 2.0 2.0 2.04 2.29 0.13 4.85 2.47 -20.10 94.92 148.91 0.47 0.99 volts volts volts volts volts

MHz MHz uW/MHz/gate uW/MHz/gate

149
COMMENTS: SUBMICRON

T26B SPICE BSIM3 VERSION 3.1 PARAMETERS SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8 * DATE: Aug 13/02 * LOT: T26B WAF: * Temperature_parameters=Default .MODEL CMOSN NMOS ( +VERSION = 3.1 TNOM +XJ = 1.5E-7 NCH +K1 = 0.8816805 K2 +K3B = -7.2365541 W0 +DVT0W = 0 DVT1W +DVT0 = 3.4115308 DVT1 +U0 = 459.4056043 UA +UC = 1.752656E-11 VSAT +AGS = 0.1336177 B0 +KETA = -1.278225E-3 A1 +RDSW = 1.495435E3 PRWG +WR = 1 WINT +XL = 0 XW +DWB = 5.441284E-8 VOFF +CIT = 0 CDSC +CDSCB = 0 ETA0 +DSUB = 0.3061953 PCLM +PDIBLC2 = 3.41146E-3 PDIBLCB +PSCBE1 = 5.782445E8 PSCBE2 +DELTA = 0.01 RSH +PRT = 0 UTE +KT1L = 0 KT2 +UB1 = -7.61E-18 UC1 +WL = 0 WLN +WWN = 1 WWL +LLN = 1 LW +LWL = 0 CAPMOD +CGDO = 2.07E-10 CGSO +CJ = 4.202552E-4 PB +CJSW = 3.292519E-10 PBSW +CJSWG = 1.64E-10 PBSWG +CF = 0 PVTH0 +PK2 = -0.0299731 WKETA * .MODEL CMOSP PMOS ( +VERSION = 3.1 TNOM +XJ = 1.5E-7 NCH +K1 = 0.5559776 K2 +K3B = -0.591565 W0 +DVT0W = 0 DVT1W +DVT0 = 2.1960105 DVT1 +U0 = 220.7789332 UA

3203 LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 49 1.41E-8 0.6831202 20.4100577 1E-9 0 -0.1015774 1.53315E-18 0.6040461 5E-6 0.3328298 0.0354674 3.032999E-8 -2.186171E-8 1.047271 0 -2.498627E-3 -0.0801838 0.4643998 0 1 -0.11 4.31E-9 3.3E4 0 0 1 0.5 1E-9 0.4429826 0.1129753 0.1129753 211.9317467 1.965474E-3 49 1.41E-8 -0.9195653 5.9729105 4.077083E-8 0 -0.1202092 1E-21

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

27 1.7E17 -0.0937802 1E-8 0 0.4312588 1E-13 1.742215E5 2.906546E-6 4.683373E-5 0.0317989 2.770012E-7 0 -8.357693E-4 2.4E-4 0.0132197 2.6357241 0.0459471 6.530591E-5 84.5 -1.5 0.022 -5.6E-11 1 0 0 2 2.07E-10 0.9853234 0.1 0.1 0.0333334 -0.0240476

= = = = = = =

27 1.7E17 8.698444E-3 1E-8 0 0.5261473 3.151288E-9

150
+UC +AGS +KETA +RDSW +WR +XL +DWB +CIT +CDSCB +DSUB +PDIBLC2 +PSCBE1 +DELTA +PRT +KT1L +UB1 +WL +WWN +LLN +LWL +CGDO +CJ +CJSW +CJSWG +CF +PK2 * = = = = = = = = = = = = = = = = = = = = = = = = = = -5.13969E-11 0.1501171 -2.596552E-3 3E3 1 0 2.090226E-8 0 0 1 3.628304E-3 5.115908E9 0.01 0 0 -7.61E-18 0 1 1 0 2.64E-10 7.225681E-4 2.836454E-10 6.4E-11 0 3.73981E-3 VSAT B0 A1 PRWG WINT XW VOFF CDSC ETA0 PCLM PDIBLCB PSCBE2 RSH UTE KT2 UC1 WLN WWL LW CAPMOD CGSO PB PBSW PBSWG PVTH0 WKETA = = = = = = = = = = = = = = = = = = = = = = = = = = 1.741524E5 9.729034E-7 0 -0.0382094 3.026679E-7 0 -0.0705362 2.4E-4 0.3028635 2.2191478 -0.060075 5.003749E-10 104.5 -1.5 0.022 -5.6E-11 1 0 0 2 2.64E-10 0.9574686 0.99 0.99 5.98016E-3 4.213663E-3 A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA = = = = = = = = = = = = = = = = = = = = = = = = = = 0.8761413 5E-6 0.3 -4.289989E-3 4.990553E-8 -2.441288E-8 0.8513831 0 -0.0641126 0.0483969 0.2330696 0.0149972 1 -0.11 4.31E-9 3.3E4 0 0 1 0.5 1E-9 0.4979615 0.2895449 0.2895449 14.8598424 -5.008006E-3

Vita

Jincheol Yoo was born in Seoul, Korea on June 24, 1967. He received a Bachelor of Science degree in Computer Science from the Korea Military Academy (KMA), Seoul, Korea in 1989. At the same time, he was commissioned as a second lieutenant. He then served at the Korean Army as a platoon leader. In 1991, he was sent to the Department of Statistics at the Iowa State University for his MS degree by the Korean Army and the KMA. After getting his MS degree, he joined the Department of Mathematics at the KMA as an instructor. In 1995, he was transferred to the Department of Computer Science at the KMA as a full-time instructor. With full support from the Korean Army and the KMA, he enrolled in the Ph.D. program in Computer Science and Engineering at the Pennsylvania State University in August, 1998. His research interests include high speed and low power ADC design for system-on-chip and design automation of mixed-signal circuits. Jincheol Yoo is a student member of IEEE Circuits and Systems Society, and IEEE Solid-State Circuits Society.