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May 13-15, 2008 Kuala Lumpur, Malaysia
Performance of CMOS Schmitt Trigger
R. Sapawi, R.L.S Chee, S.K Sahari, N. Julai Department of Electronics, Faculty of Engineering, Universiti Malaysia Sarawak, 94300 Kota Samarahan, Sarawak. Tel: 082-583289 Email: firstname.lastname@example.org Abstract
This paper presents the effect of load capacitance and source voltage on performance of proposed Schmitt trigger circuit. The proposed circuit was designed based on Conventional Schmitt Trigger by manipulating the arrangement of transistors and the width-length ratio. All simulation results have been carried out based on Microwind software on three different designs in term of propagation delay, Energy-delay Product and hystheresis. From the result, the proposed full swing CMOS Schmitt Trigger was able to operate as low voltage (0.8V-1.5V). I. INTRODUCTION The Schmitt trigger circuit is widely used in analog and digital circuit as wave shaping circuit to solve the noise problem. Beside that this circuit is widely design in various styles in order to drive the load with fast switching, low power dissipation and low-supply voltage, especially for the high capacitive load problem . Conventional Schmitt Trigger is shown in Figure 1 and the detail design is presented in  where the switching thresholds are dependent on the ratio of NMOS and PMOS. However, this circuit will exhibit racing phenomena after the transition starts. Therefore in this paper, we proposed CMOS Schmitt Trigger circuit which is capable to operate in low voltages (0.8V1.5V) at high capacitance, less propagation delay and stable hysteresis width. II. CIRCUIT DESCRIPTION
Figure 2. The Proposed Schmitt Trigger
Figure 1. The Conventional Schmitt Trigger
The proposed Schmitt Trigger  is shown in Figure 2 and is categorized into two parts which is Part 1 and Part 2. Similarly to Conventional Schmitt Trigger, the proposed circuit is formed by a combination of two subcircuits, P sub-circuit (which consist of P1, P2 and P3) and N sub-circuit (which consist of N1, N2 and N3). There is no direct connection between the source voltage and ground as P sub-circuit is connected to the path between the source voltage and output while the N sub-
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N1 and N2 is turned on while N3 is off.circuit is connected between the path of output and ground. Thus.80/0. The respective transistor dimensions for the three designs are shown in Table 1.30 0.90/0.80/0.90/0. ⎛ W ⎜ ⎜ L eff ⎝ ⎞ ⎛ W ⎟ = r⎜ ⎟ ⎜ L eff ⎠ PMOS ⎝ ⎞ ⎟ ⎟ ⎠ NMOS represent the Conventional Schmitt Trigger with the ratio of transistor are set similarly with the 3rd Design which is the proposed Schmitt Trigger.30 0. 2nd Design A. Typically. By increasing the width of PMOS. Each of the transistors is sized accordingly to their arrangement. they are scaled by factor of 2 each while transistors in parallel are scaled by a factor of 1 each. This parasitic capacitance will be added into load capacitance and together will degrades the performance of the two designs.30 0. (P3) and a NMOS.69 RC L = PHL PLJH (1) 2 It is preferably to reduce PMOS delay because delay is more concentrated to PMOS due to high mobility of PMOS compare to NMOS. at higher supply voltage and larger load capacitance. Therefore.30/0.2V) and lower load capacitance (< 0. During this condition.60/0.30/0. the 3rd Design has the highest hysteresis width followed by 2nd and 1st Design. Propagation delay The delay times of these circuits are measured as the average of the response time of the gate for positive and negative output transition for a square input waveform at 1GHz. THE TRANSISTORS DIMENSION W Leff 1st Design 2. Therefore.30/0. The 1st Design represent the Conventional Schmitt Trigger with the ratio of transistor is set according to . Leff = 0. the 2nd Design has the widest hysteresis width and followed by 3rd and 1st Design. When the input is low. the output voltage is pull down to GND.30 2nd Design 1.30 μm (for 0. Therefore.30 0. III. Part 1 of the proposed circuit forms a NAND gate is designed according to De Morgan’s Theorem. The PMOS and NMOS ratio is set according to equation 2 with the effective length.30 P1 P2 P3 N1 N2 N3 (2) It is recommended to widen the PMOS transistor to allow the resistance matches the pull down NMOS device. the ratio is set to be three to maximize the noise margin and to create a circuit with symmetrical voltage-transfer characteristic (VTC).30 2. (N3) where both the MOSFET is directly connected through the gate terminal of each. The sizings of the transistor are set by locating the minimum component path of each sub-circuit. it moves the switching threshold voltage towards VDD. At lower source voltage (< 1.015pF). However. the three designs are said to be stable at variation of load capacitance.30 0. SIMULATION RESULTS Three designs (1st. the 1st Design gives better performances. the propagation delay can be reduced as shown in equation (1).30 3.5 .30 3rd Design 0.00/0. the output voltage is pull to VDD. both P1 and P2 are on. When the input increases to VDD. 2nd and 3rd Design) are simulated with 0. For transistors that are in series.30 0. While at VDD > 0. Thus. but P3 is off (because V SG < Vtp as P3’s source voltage and gate voltage is equal). there is no static power consumption due to no direct path between source voltage and ground.40/0. Thus.60/0.35 technology using Microwind software.90/0. Part 2 of the Proposed Schmitt Trigger consists of a PMOS.60/0. which makes the hysteresis width more rectangles which are desirable in a Schmitt Trigger design. the propagation delay will reduce when the source voltage is increased. energy delay product and hysteresis width.60/0.8V. the resistance of the P sub-circuit will be reduced by halves.30 2. B.30 3. The increasing of PMOS widths in 2nd and 3rd Design will improves tPLH but will degrades tPHL at the same time due to the increase of parasitic capacitance. the 3rd Design has higher performance compared to the other two design. Two PMOS (P1and P2) are formed by a parallel connection while two NMOS (N1 and N2) are formed by a series connection. Hysteresis width Figure 4 show that the increasing of load capacitance will increase the hysteresis width (in small amount) for all three designs.00/0.30 0.40/0.30 0.30 1.30 0. r = 3 → 3.35 technology). t +t t P = 0.40/0. The comparison are made in term of propagation delay. As shown in Figure 3. Δ H = V TH − V T :L (4) At VDD = 0. By designing the PMOS in parallel. The P3 act as a pull up while the N3 act as a pull down for the output at each case.30 0. The decreased of hysteresis width for 1st and 3rd Design shows that the gap 1318 . TABLE I.90/0. only the P sub-circuit will be considered and causes the output to be high (equal to VDD).8V.
A high-speed direct bootstrapped CMOS Schmitt trigger circuit . the 1st Design gives the less EDP. Kuo S.015pF). Rabaey J. Semiconductor Electronics. Melaka.010pF Figure 5 shows that as load capacitance increases.2 1..K Sahari. Besides that.Delay (ps) between the high. Energy-delay product The Energy-Delay Product (EDP) is measured using equation (3) and theoretically EDP is directly proportional to Power-Delay Product (PDP) and propagation delay. IEEE International Conference. M. A. ICSE 2004.00pF 100 50 0 0. Wang C. 0. IEEE Transactions Circuits System. ⎛1 2 EDP = ⎜ C L V DD ⎝2 ⎞ ⎟ t p = PDP × t p ⎠ Propagation De lay at C L = 0. The Proposed circuit give less EDP as low voltages (<1. Borivoje Nikolic. P. R.0 1. Page 46-49. 7-9 December 2004. T.8 1. CMOS Schmitt Trigger Design...5 VDD (V) Propagation Delay at CL = 0.. Y.-Circuits Devices System. No.144. Suhaili.015pF) due to less delay as discussed in section A.8V. 4-6 December 2007. 2nd Edition. Rerkmaneewan.0 1.1.5 VDD (V) Propagation Delay at CL = 0.and low. (2003). Sapawi. (1994). S. Baltes. S.2V) and low load capacitance (<0.2 1. it gives the highest EDP and thus is not preferably in a Schmitt Trigger. 5. Soonyeekan. Page 303-308. The hysteresis width is clear and less sensitive to the variation of load capacitance and source voltages.8 1. CONCLUSION A new proposed CMOS Schmitt Trigger is presented which is capable to function under low voltages as much as 0. I. As for the 2nd Design.5 VDD (V) (3) 150 Delay (ps) 100 50 0 Propagation Delay at CL = 0.. New Jersey: Pearson Education. Yuan S.2 1. REFERENCES  Dejhan.. Simulation of CMOS Schmitt Trigger. Tooprakai.0 1.S Chee.005pF 100 Delay (ps) 50 0 0. M.015pF 200 150 100 50 0 0. the EDP also increases. 2004. Vol.8 1. R. K.. Asia-Pacific Conference on Applied Electronicmagnetics. All the designs give a few mV hysteresis width. IV. Vol.0 1.5 VDD (V)     Figure 3: Propagation Delay versus Load Capacitance 1319 Delay (ps) . Y.0V) and high load capacitance (>0. Digital Integrated Circuits: A Design Perspective. Full Swing BiCMOS Schmitt Trigger. S. While at higher voltages (>1. Filanovsky.L. C.8 1.2 1. C.010pF). (1997). Chandrakasan. 41. IEEE Proc. No.2V) and low capacitance (<0.. thus it is neither too wide nor too small for a Schmitt Trigger. the proposed circuit gives less delay and Energy-Delay Product at low source voltage (< 1..threshold voltage is reduced as the source voltage increases. H.
005 0.000 0.00 0.015 0.10 0.010 0.000 0.20 0.20 0.Hysteresis Width at VDD = 0.10 0.05 0.10 0.0V Hysteresis Width (V) 0.020 Figure 4: Hysteresis Width versus Load Capacitance Figure 5: Energy-Delay Product versus Source Voltages 1320 .000 0.00 0.2V Hysteresis Width (V) 0.05 0.10 0.020 C L (pF) Hyste re sis W idth at VDD = 1.010 C L (pF) 0.010 CL (pF) 0.015 0.020 Hyste re sis W idth at VDD = 1.020 0.25 Hysteresis Width at VDD = 1.20 0.000 0.15 0.05 0.05 0.015 0.5V Hysteresis Width (V) 0.8V Hysteresis Width (V) 0.00 0.005 0.00 0.20 0.005 0.005 0.015 0.010 CL (pF) 0.15 0.15 0.15 0.
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