Enhanced A/D Flash Type MCU 8-Bit MCU with EEPROM

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60

Revision: 1.30

Date: October 4, 2010

Contents

Table of Contents
Technical Document ...........................................................................1 Features ...............................................................................................1
CPU Features ........................................................................................................1 Peripheral Features ................................................................................................1

General Description ............................................................................1 Selection Table ....................................................................................2 Block Diagram .....................................................................................2 Pin Assignment ...................................................................................3 Pin Description ....................................................................................7
HT66F20 ................................................................................................................7 HT66F30 ................................................................................................................8 HT66F40 ................................................................................................................9 HT66F50 ..............................................................................................................11 HT66F60 ..............................................................................................................12

Absolute Maximum Ratings .............................................................14 D.C. Characteristics ..........................................................................14 A.C. Characteristics ..........................................................................16 A/D Converter Characteristics .........................................................17 Comparator Electrical Characteristics ............................................18 Power-on Reset Characteristics ......................................................18 System Architecture .........................................................................19
Clocking and Pipelining ........................................................................................19 Program Counter..................................................................................................20 Stack ....................................................................................................................20 Arithmetic and Logic Unit - ALU............................................................................20

Flash Program Memory ....................................................................21
Structure...............................................................................................................21 Special Vectors.....................................................................................................21 Look-up Table.......................................................................................................21 Table Program Example .......................................................................................21 In Circuit Programming.........................................................................................22

RAM Data Memory.............................................................................23
Structure...............................................................................................................23

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Contents

Special Function Register Description ...........................................26 Indirect Addressing Registers - IAR0, IAR1....................................26
Memory Pointers - MP0, MP1...............................................................................26 Bank Pointer - BP.................................................................................................27 Accumulator - ACC...............................................................................................28 Program Counter Low Register - PCL ..................................................................28 Look-up Table Registers - TBLP, TBHP, TBLH......................................................28 Status Register - STATUS ....................................................................................28

EEPROM Data Memory .....................................................................30
EEPROM Data Memory Structure ........................................................................30 EEPROM Registers..............................................................................................30 Reading Data from the EEPROM .........................................................................32 Writing Data to the EEPROM ...............................................................................32 Write Protection ....................................................................................................33 EEPROM Interrupt ...............................................................................................33 Programming Considerations ...............................................................................33

Oscillator............................................................................................34
Oscillator Overview...............................................................................................34 System Clock Configurations................................................................................34 External Crystal/ Ceramic Oscillator - HXT ...........................................................35 External RC Oscillator - ERC................................................................................35 Internal RC Oscillator - HIRC................................................................................35 External 32.768kHz Crystal Oscillator - LXT .........................................................35 LXT Oscillator Low Power Function ......................................................................36 Internal 32kHz Oscillator - LIRC ...........................................................................36 Supplementary Oscillators....................................................................................36

Operating Modes and System Clocks .............................................37
System Clocks......................................................................................................37 System Operation Modes .....................................................................................38 Control Register ...................................................................................................39 Fast Wake-up .......................................................................................................40 Operating Mode Switching and Wake-up..............................................................41 NORMAL Mode to SLOW Mode Switching...........................................................41 SLOW Mode to NORMAL Mode Switching...........................................................42 Entering the SLEEP0 Mode..................................................................................42 Entering the SLEEP1 Mode..................................................................................43 Entering the IDLE0 Mode .....................................................................................43 Entering the IDLE1 Mode .....................................................................................43 Standby Current Considerations...........................................................................43 Wake-up...............................................................................................................44 Programming Considerations ...............................................................................44

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Contents

Watchdog Timer ................................................................................45
Watchdog Timer Clock Source .............................................................................45 Watchdog Timer Control Register.........................................................................45 Watchdog Timer Operation...................................................................................46

Reset and Initialisation .....................................................................47
Reset Functions ...................................................................................................47 Reset Initial Conditions .........................................................................................48

Input/Output Ports.............................................................................61
Pull-high Resistors................................................................................................64 Port A Wake-up ....................................................................................................66 I/O Port Control Registers.....................................................................................66 Pin-remapping Functions......................................................................................69 Pin-remapping Registers ......................................................................................69 I/O Pin Structures .................................................................................................74 Programming Considerations ...............................................................................74

Timer Modules - TM...........................................................................76
Introduction ..........................................................................................................76 TM Operation .......................................................................................................77 TM Clock Source..................................................................................................77 TM Interrupts ........................................................................................................77 TM External Pins ..................................................................................................77 TM Input/Output Pin Control Registers .................................................................78 Programming Considerations ...............................................................................86

Compact Type TM..............................................................................87
Compact TM Operation ........................................................................................87 Compact Type TM Register Description ...............................................................88 Compact Type TM Operating Modes ....................................................................91 Compare Match Output Mode ..............................................................................91 Timer/Counter Mode.............................................................................................91 PWM Output Mode...............................................................................................94

Standard Type TM - STM...................................................................96
Standard TM Operation ........................................................................................96 Standard Type TM Register Description ...............................................................96 Standard Type TM Operating Modes..................................................................104 Compare Output Mode .......................................................................................104 Timer/Counter Mode...........................................................................................107 PWM Output Mode.............................................................................................107 Single Pulse Mode..............................................................................................110 Capture Input Mode ............................................................................................111

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Contents

Enhanced Type TM - ETM ...............................................................112
Enhanced TM Operation.....................................................................................112 Enhanced Type TM Register Description............................................................113 Enhanced Type TM Operating Modes.................................................................118 Compare Output Mode .......................................................................................118 Timer/Counter Mode...........................................................................................123 PWM Output Mode.............................................................................................123 Single Pulse Output Mode ..................................................................................128 Capture Input Mode............................................................................................130

Analog to Digital Converter............................................................132
A/D Overview .....................................................................................................132 A/D Converter Register Description ....................................................................132 A/D Converter Data Registers - ADRL, ADRH....................................................133 A/D Converter Control Registers - ADCR0, ADCR1, ACERL, ACERH ...............133 A/D Operation.....................................................................................................138 A/D Input Pins ....................................................................................................138 Summary of A/D Conversion Steps ....................................................................139 Programming Considerations .............................................................................140 A/D Transfer Function.........................................................................................140 A/D Programming Example ................................................................................140

Comparators ....................................................................................142
Comparator Operation........................................................................................142 Comparator Registers ........................................................................................142 Comparator Interrupt ..........................................................................................142 Programming Considerations .............................................................................142

Serial Interface Module - SIM .........................................................145
SPI Interface.......................................................................................................145 SPI Registers .....................................................................................................146 SPI Communication............................................................................................149 I2C Interface .......................................................................................................151 I2C Bus Communication......................................................................................155 I2C Bus Start Signal ............................................................................................155 Slave Address ....................................................................................................155 I2C Bus Read/Write Signal..................................................................................155 I2C Bus Slave Address Acknowledge Signal.......................................................155 I2C Bus Data and Acknowledge Signal ...............................................................156

Peripheral Clock Output .................................................................158
Peripheral Clock Operation.................................................................................158

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..................................................................................................................................................................................................................179 Entering the IDLE or SLEEP Mode.........................................................175 A/D Converter Interrupt.................................................................................................................................................................................................................................................................187 UART Module Pin Description ...............................................................................................................................178 Power Down Mode and Wake-up ..................................................................177 EEPROM Interrupt ..........................................................175 Multi-function Interrupt ........................................................................................................C........ Characteristics......................................................186 UART Module Features ............................................................................177 LVD Interrupt ................181 LCD Bias Control..................................................................................186 Pin Assignment .......................................................................................................................179 Wake-up............186 UART Module Overview..............................................................................180 LVD Register ............................................................................................181 LCD Operation ......................................................................................Contents Interrupts..............................159 Interrupt Operation ..........................................................................191 v ...........................180 LVD Operation.......175 Time Base Interrupts .......184 Application Circuits ............................181 SCOM Function for LCD .....159 Interrupt Registers ....179 Standby Current Considerations...................... Characteristics.......................190 UART Module Functional Description...........................................181 Configuration Options ..........C...............................................................................................................................................................................................................................LVD............171 External Interrupt .................................................................................178 Programming Considerations ...............................................................................189 UART Module A....175 Serial Interface Module Interrupt............189 UART Module D....191 UART Module Internal Signal ................................177 TM Interrupts .......................................................................................................................................................185 UART Module Serial Interface ...........................................................................................186 UART Module Block Diagram.................................................................................................................................................177 External Peripheral Interrupt ..........................175 Comparator Interrupt .................................................................179 Low Voltage Detector .......................................................................................................178 Interrupt Wake-up Function .............................................................................................................

..........................................................................................210 Package Information ...198 UART Module Setup and Control............................................................228 24-pin SKDIP (300mil) Outline Dimensions ........................................................................192 UART Commands .......233 28-pin SKDIP (300mil) Outline Dimensions .............................................................................................220 16-pin NSOP (150mil) Outline Dimensions ...................................................................................................................................................................................208 Other Operations.............................................................207 Moving and Transferring Data ....................................................240 vi .....................................................................................................................................................207 Introduction.....................................................225 20-pin SOP (300mil) Outline Dimensions...........205 Application Circuit with UART Module................................................223 16-pin SSOP (150mil) Outline Dimensions .191 SPI Timing................................................................................................203 UART Module Power-down and Wake-up .......................204 Using the UART Function......238 44-pin QFP (10mm´10mm) Outline Dimensions ............................220 16-pin DIP (300mil) Outline Dimensions ...............................................................................234 28-pin SOP (300mil) Outline Dimensions...........206 Instruction Set .............................................................203 UART Module Interrupt Structure .......................................................................................207 Branches and Control Transfer......................................235 28-pin SSOP (150mil) Outline Dimensions .....................................................................................237 SAW Type 40-pin (6mm´6mm for 0........191 UART Module External Pin Interfacing...........................224 20-pin DIP (300mil) Outline Dimensions ...........................207 Arithmetic Operations ........................................193 UART Status and Control Registers ......................236 SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions...............................................................232 24-pin SSOP (150mil) Outline Dimensions ........207 Logical and Rotate Operations ...................................................................................................................................................200 Managing Receiver Errors ................229 24-pin SOP (300mil) Outline Dimensions........................................................................207 Bit Operations.................................................................................................................................................................Contents UART Module SPI Interface ...........................................75mm) QFN Outline Dimensions.............................................................................................................................................................207 Instruction Timing ....................................................................................................................................................................................................................................................................208 Instruction Set Summary ..............................................................193 Baud Rate Generator .......................................................................................................................................................208 Table Read Operations....................227 20-pin SSOP (150mil) Outline Dimensions ....208 Instruction Definition .....................................................................239 48-pin SSOP (300mil) Outline Dimensions .................................................................192 UART Data Transfer Scheme ......

....................241 52-pin QFP (14mm´14mm) Outline Dimensions ...................................246 vii .................243 Product Tape and Reel Specifications ......................242 44-pin LQFP (10mm´10mm) (FP3..........................................244 Reel Dimensions ................................................................................................................244 Carrier Tape Dimensions ......................................................2mm) Outline Dimensions..........................Contents SAW Type 48-pin (7mm´7mm) QFN Outline Dimensions.......

input · · · · · · capture. low-cost data links between PCs and peripheral devices.30 . 1. Protective features such as an internal Watchdog Timer.UART module for fully duplex · Wide range of available package types General Description The HT66FXX series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontrollers. these devices also include a wide range of functions and features. The UART module is contained in the HT66FUx0 series of devices. motor driving in addition to many others. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. handheld instruments. LXT.768kHz Crystal -.LIRC Multi-mode operation: NORMAL. 8MHz and 12MHz oscillator requires no external components All instructions executed in one or two instruction cycles Table read instructions 63 powerful instructions Up to 12-level subroutine nesting Bit manipulation instruction 1/2 bias · Multiple pin-shared external interrupts · Multiple Timer Module for time measure.HIRC Internal 32kHz RC -. The inclusion of flexible I/O programming features. HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. A full choice of HXT. 2010 Rev. electronically controlled tools.5V fSYS= 12MHz: 2. portable and battery operated device communication. Time-Base functions along with many other features ensure that the devices will find excellent use in applications such as electronic metering. Offering users the convenience of Flash Memory multi-programming features.5V Up to 0. Analog features include a multi-channel 12-bit A/D converter and dual comparator functions. calibration data etc. PWM output or single pulse output function Serial Interfaces Module -. SLOW.5V~5. etc.HXT External 32.7V~5. Communication with the outside world is catered for by including fully integrated SPI or I2C interface functions.2ms instruction cycle with 20MHz system clock at VDD=5V Power down and wake-up functions to reduce power consumption Five oscillators: External Crystal -. Multiple and extremely flexible Timer Modules provide timing. compare match output. ERC.HA0075E MCU Reset and Oscillator Circuits Application Note Features CPU Features · Operating Voltage: Peripheral Features · Flash Program Memory: 1K´14 ~ 12K´16 · RAM Data Memory: 64´8 ~ 576´8 · EEPROM Memory: 32´8~256´8 · Watchdog Timer function · Up to 50 bidirectional I/O lines · Software controlled 4-SCOM lines LCD driver with · · · · · · · · · · fSYS= 8MHz: 2. environmental monitoring. pulse generation and PWM generation functions. household appliances. IDLE and SLEEP Fully integrated internal 4MHz. 1 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type MCU 8-Bit MCU with EEPROM Technical Document · Application Note . Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers. It can support the applications such as data communication networks between microcontrollers.ERC Internal RC -. two popular interfaces which provide designers with a means of easy communication with external peripheral hardware.5V fSYS= 20MHz: 4.LXT External RC -.SIM for SPI or I2C Dual Comparator functions Dual Time-Base functions for generation of fixed time interrupt signals Multi-channel 12-bit resolution A/D converter Low voltage reset function Low voltage detect function asynchronous communication · Optional peripheral -.2V~5.

40QFN. 10-bit ETM´1.5V 22 2K´14 96´8 64´8 14 2 12-bit´8 10-bit CTM´1.5V 10-bit CTMx2. stack capacity and package types. 44LQFP 48SSOP/LQFP/QFN 12 Ö 52QFP. 16-bit STM´1 Ö ¾ 8 Ö ¾ HT66FU50 HT66F60 HT66FU60 2.2V~ 5.5V 42 8K´16 384´8 256´8 34 50 12K´16 576´8 256´8 42 4 2 12-bit´8 10-bit CTM´2. 16-bit STMx1 Ö Note: As devices exist in more than one package format. I/O count. 40QFN. All information related to the UART Module will be described in the following UART Module section. the table reflects the situation for the package with the most pins. 2010 . The following table summarises the main features of each device. TM features. 10-bit ETM´1 Ö ¾ 4 Ö ¾ HT66FU30 HT66F40 2.5V Program Memory 1K´14 Data Memory 64´8 Data EEPROM 32´8 I/O Ext.30 2 October 4. Block Diagram L o w V o lta g e D e te c t L o w V o lta g e R e s e t W a tc h d o g T im e r R e s e t C ir c u it 8 . 48QFN 52QFP. 1. 44LQFP 48LQFP/QFN HT66F20 18 12-bit´8 Ö 4 HT66F30 2.B it A /D C o n v e rte r C o m p a ra to rs L IR C /L X T O s c illa to r I/O U A R T S IM T M 0 T M 1 T M n Rev. There is an additional peripheral known as the UART module in HT66FU30. 12-bit´12 10-bit ETMx1. VDD 2.b it R IS C M C U C o re In te rru p t C o n tr o lle r F la s h /E E P R O M P r o g r a m m in g C ir c u itr y ( IS P ) S ta c k E R C /H X T O s c illa to r F la s h P ro g ra m M e m o ry E E P R O M D a ta M e m o ry T B 0 /T B 1 R A M D a ta M e m o ry H IR C O s c illa to r 1 2 . 40QFN 48SSOP/QFN 44LQFP. 2 A/D Timer Module 10-bit CTM´1. 48SSOP/QFN 40QFN.2V~ 5. HT66FU50 and HT66FU60 devices. 10-bit STM´1 Interface (SPI/I2C) Ö UART Stack Package 16DIP/NSOP/SSOP 20DIP/SOP/SSOP 16DIP/NSOP/SSOP 20DIP/SOP/SSOP 24SKDIP/SOP/SSOP 24SKDIP/SOP 24/28SKDIP/SOP/SSOP 44LQFP 32/40QFN. 10-bit ETM´1. Int. 44LQFP. 48SSOP/QFN 28SKDIP/SOP/SSOP 44LQFP.5V 42 4K´15 192´8 128´8 34 2 12-bit´8 10-bit CTM´1.2V~ 5. HT66FU40.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Selection Table Most features are common to all devices.2V~ 5. 16-bit STM´1 Ö Ö 8 HT66FU40 HT66F50 2.2V~ 5. Part No. the main feature distinguishing them are Memory capacity.

Rev. VDD&AVDD means the VDD and AVDD are the double bonding. Bracketed pin names indicate non-default pinout remapping locations. If the pin-shared pin functions have multiple outputs simultaneously.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pin Assignment P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 2 3 4 5 6 7 8 9 1 0 V S S & A V S S P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 2 3 4 5 6 7 8 V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 P A 1 /T P 1 _ 0 /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S P C 1 /S C O M 1 P C 0 /T P 1 _ 1 /S C O M 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 P A 1 /T P 1 _ 0 /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P C 2 /P C K /C 1 + /S C O M 2 P C 3 /P IN T /C 1 -/S C O M 3 H T 6 6 F 2 0 1 6 D IP -A /N S O P -A /S S O P -A H T 6 6 F 2 0 2 0 D IP -A /S O P -A /S S O P -A P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 2 3 4 5 6 7 8 9 V S S & A V S S P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 2 3 4 5 6 7 8 V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S P C 1 /T P 1 B _ 1 /[S D O ]/S C O M 1 P C 0 /T P 1 B _ 0 /[S D I/S D A ]/S C O M 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 0 1 1 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P C 2 /P C K /C 1 + P C 3 /P IN T /C 1 - H T 6 6 F 3 0 1 6 D IP -A /N S O P -A /S S O P -A H T 6 6 F 3 0 2 0 D IP -A /S O P -A /S S O P -A P A 0 /C 0 X /T P 0 _ 0 /A N 0 V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S P C 1 /T P 1 B _ 1 /[S D O ]/S C O M 1 P C 0 /T P 1 B _ 0 /[S D I/S D A ]/S C O M 0 P C 7 /[S C K /S C L ]/S C O M 3 P C 6 /[S C S ]/S C O M 2 9 8 7 6 5 4 3 2 1 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 0 1 1 1 2 1 5 1 4 1 3 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P C 2 /P C K /C 1 + P C 3 /P IN T /C 1 P C 4 /[P IN T ] P C 5 /T P 0 _ 1 /[P C K ] H T 6 6 F 3 0 2 4 S K D IP -A /S O P -A /S S O P -A P A 0 /C 0 X /T P 0 _ 0 /A N 0 V S S & A V S S P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S P C 1 /T P 1 B _ 1 /S C O M 1 P C 0 /T P 1 B _ 0 /S C O M 0 P C 7 /[T P 1 A ]/S C O M 3 P C 6 /[T P 0 _ 0 ]/S C O M 2 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P C 2 /T C K 2 /P C K /C 1 + P C 3 /P IN T /T P 2 _ 0 /C 1 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S P C 1 /T P 1 B _ 1 /S C O M 1 P C 0 /T P 1 B _ 0 /S C O M 0 P C 7 /[T P 1 A ]/S C O M 3 P C 6 /[T P 0 _ 0 ]/S C O M 2 P D 3 /[T C K 1 ]/[S D O ] P D 2 /[T C K 0 ]/[S D I/S D A ] 9 1 0 1 1 1 2 1 3 1 4 8 7 6 5 4 3 2 1 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P C 2 /T C K 2 /P C K /C 1 + P C 3 /P IN T /T P 2 _ 0 /C 1 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P D 0 /[T C K 2 ]/[S C S ] P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] H T 6 6 F 4 0 2 4 S K D IP -A /S O P -A /S S O P -A H T 6 6 F 4 0 2 8 S K D IP -A /S O P -A /S S O P -A Note: 1. 2. its pin names at the right side of the ²/² sign can be used for higher priority. 2010 . 3.30 3 October 4. 1.

3. Rev. 2.30 4 October 4. VDD&AVDD means the VDD and AVDD are the double bonding. If the pin-shared pin functions have multiple outputs simultaneously. 1. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C P D 0 /[T C K 2 ]/[S C P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C P C 4 /[IN T 0 ]/[P IN T ]/T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C P C 4 /[IN T 0 ]/[P IN T ]/T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A K ] _ 1 1 1 + E F N 7 N 6 N 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 L ] S ] K ] _ 1 1 1 + S ] L ] A ] O ] 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C P F 0 /[C P E 7 /[IN N 3 N 2 N 1 N 0 1 X ] 0 X ] T 1 ] N 4 H T 6 6 F 4 0 3 2 Q F N -A 2 1 2 0 1 9 1 8 1 7 P D 0 P D 1 P D 2 P D 3 P C 6 P C 7 P C 0 P C 1 /[T /[T /[T /[T /[T /[T /T /T C K 2 ]/[S C P 2 _ 0 ]/[S D C K 0 ]/[S D C K 1 ]/[S D P 0 _ 0 ]/S C P 1 A ]/S C O P 1 B _ 0 /S C P 1 B _ 1 /S C S ] O ]/[S C K /S C L ] I/S D A ] O ] O M 2 M 3 O M 0 O M 1 P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C N 7 N 6 N 5 N 4 N 3 N 2 N 1 N 0 1 X ] E F H T 6 6 F 4 0 4 0 Q F N -A 2 6 2 5 2 4 2 3 2 2 2 1 P D 2 P D 3 P D 4 P D 5 P C 6 P C 7 P C 0 P C 1 P E 4 P E 5 /[T /[T /[T /[T /[T /[T /T /T /[T C K 0 ]/[S C K 1 ]/[S P 2 _ 1 ] P 0 _ 1 ] P 0 _ 0 ]/S P 1 A ]/S C P 1 B _ 0 /S P 1 B _ 1 /S P 1 B _ 2 ] D I/S D A ] D O ] C O O M C O C O M 2 3 M 0 M 1 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 /R E & A /O S /O S /X T /X T & A /[IN S V D D C 1 C 2 1 2 V S S T 0 ] P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 P F 1 /[C 1 X ] P F 0 /[C 0 X ] P E 7 /[IN T 1 ] P E 6 /[IN T 0 ] V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S P E 5 P E 4 /[T P 1 B _ 2 ] P C 1 /T P 1 B _ 1 /S C O M 1 P C 0 /T P 1 B _ 0 /S C O M 0 N C P C 7 /[T P 1 A ]/S C O M 3 P C 6 /[T P 0 _ 0 ]/S C O M 2 P E 3 P E 2 P E 1 P E 0 P D 5 /[T P 0 _ 1 ] 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P B 6 /[S D O ] P B 7 /[S D I/S D A ] P D 6 /[S C K /S C L ] P D 7 /[S C S ] P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 N C N C N C P C 2 /T C K 2 /P C K /C 1 + P C 3 /P IN T /T P 2 _ 0 /C 1 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P D 0 /[T C K 2 ]/[S C S ] P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P D 2 /[T C K 0 ]/[S D I/S D A ] P D 3 /[T C K 1 ]/[S D O ] P D 4 /[T P 2 _ 1 ] P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C P F 0 /[C N 7 N 6 E F 1 2 3 4 5 6 7 8 1 0 1 1 9 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /R E S & A V /O S C /O S C /X T 1 /X T 2 & A V /[IN T /[IN T /[C 0 X S S 0 ] 1 ] ] D D 3 3 3 2 3 1 3 0 2 1 P D 2 /[T C K 0 ]/[S D I/S D P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C P D 0 /[T C K 2 ]/[S C P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C P C 4 /[IN T 0 ]/[P IN T ]/T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D A ] L ] S ] K ] _ 1 1 1 + S ] L ] A ] O ] N 5 N 4 N 3 N 2 N 1 N 0 1 X ] 0 X ] H T 6 6 F 4 0 4 4 L Q F P -A 2 9 2 8 2 7 2 6 2 5 2 4 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 P D 3 P D 4 P D 5 P E 0 P E 1 P E 2 P E 3 P C 6 P C 7 P C 0 P C 1 /[T C K 1 ]/[S D O ] /[T P 2 _ 1 ] /[T P 0 _ 1 ] /[T /[T /T /T P 0 _ P 1 A P 1 B P 1 B 0 ]/S ]/S C _ 0 /S _ 1 /S C O O M C O C O M 2 3 M 0 M 1 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 /R E & A /O S /O S /X T /X T & A /[IN /[IN S V D D C 1 C 2 1 2 V S S T 0 ] T 1 ] P C 5 /[IN T 1 ]/T P 0 P C 4 /[IN P C 3 P C /[T P 1 B _ 2 ] P D 2 /[T C K 0 ]/[S D I/S D P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C P D 0 /[T C K 2 ]/[S C H T 6 6 F 4 0 4 8 S S O P -A _ 1 /T P 1 B _ 2 /[P C T 0 ]/[P IN T ]/T P 2 /P IN T /T P 2 _ 0 /C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D P B 5 /S C S /V P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 N R E /A N /A N /A N /A N /A N /A N /A N /A N N P F 1 /[C 1 C F 1 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 2 3 N A ] L ] S ] C K ] _ 1 1 1 + S ] L ] A ] O ] 3 6 3 5 4 3 4 5 3 3 6 3 2 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 9 6 4 1 7 5 2 0 3 H T 6 6 F 4 0 4 8 Q F N -A 3 1 3 0 2 9 2 8 2 7 2 6 2 5 C X ] P D 3 P D 4 P D 5 P E 0 P E 1 P E 2 P E 3 P C 6 P C 7 N C P C 0 P C 1 /[T C K 1 ]/[S D O ] /[T P 2 _ 1 ] /[T P 0 _ 1 ] /[T P 0 _ 0 ]/S C O M 2 /[T P 1 A ]/S C O M 3 /T P 1 B _ 0 /S C O M 0 /T P 1 B _ 1 /S C O M 1 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /R E S & A V /O S C /O S C /X T 1 /X T 2 & A V /[IN T /[IN T /[C 0 X S S 0 ] 1 ] ] D D 1 2 /[T P 1 B _ 2 ] Note: 1. Bracketed pin names indicate non-default pinout remapping locations. its pin names at the right side of the ²/² sign can be used for higher priority.

2010 Rev. If the pin-shared pin functions have multiple outputs simultaneously. 2.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 P D 1 /[T P P C 5 /[IN T P C 4 /[IN 1 D P T 2 _ 0 ]/[S D O ]/[S C K /S C 0 /[T C K 2 ]/T P 3 _ 1 /[S C ]/T P 0 _ 1 /T P 1 B _ 2 /[P C 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D P A 0 /C 0 X /T P 0 _ 0 /A N 0 V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D P B 0 /R E S P C 1 /T P 1 B _ 1 /S C O M 1 P C 0 /T P 1 B _ 0 /S C O M 0 P C 7 /[T P 1 A ]/S C O M 3 P C 6 /[T P 0 _ 0 ]/S C O M 2 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ] P D 2 /[T C K 0 ]/[S D I/S D A ] 9 8 7 6 5 4 3 2 1 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 0 1 1 1 2 1 3 1 4 1 9 1 8 1 7 1 6 1 5 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P C 2 /T C K 2 /P C K /C 1 + P C 3 /P IN T /T P 2 _ 0 /C 1 P C 4 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 _ 1 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C S ] P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C N 7 N 6 N 5 N 4 N 3 N 2 N 1 N 0 1 X ] E F 1 2 3 4 5 6 7 8 9 1 0 L ] S ] K ] _ 1 1 1 + S ] L ] A ] O ] 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 H T 6 6 F 5 0 4 0 Q F N -A 2 6 2 5 2 4 2 3 2 2 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 P D 2 P D 3 P D 4 P D 5 P C 6 P C 7 P C 0 P C 1 P E 4 P E 5 /[T /[T /[T /[T /[T /[T /T /T /[T /[T C K 0 ]/[S C K 1 ]/T P P 2 _ 1 ] P 0 _ 1 ] P 0 _ 0 ]/S P 1 A ]/S C P 1 B _ 0 /S P 1 B _ 1 /S P 1 B _ 2 ] P 3 _ 0 ] D I/S D A ] 3 _ 0 /[S D O ] C O O M C O C O M 2 3 M 0 M 1 H T 6 6 F 5 0 2 8 S K D IP -A /S O P -A /S S O P -A P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /R E S & A V /O S C /O S C /X T 1 /X T 2 & A V /[IN T /[IN T /[C 0 X S S 0 ] 1 ] ] D D 2 1 P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 2 3 4 5 6 7 8 9 P F 1 /[C 1 X ] P F 0 /[C 0 X ] P E 7 /[IN T 1 ] P E 6 /[IN T 0 ] V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S P E 5 /[T P 3 _ 0 ] P E 4 /[T P 1 B _ 2 ] P C 1 /T P 1 B _ 1 /S C O M 1 P C 0 /T P 1 B _ 0 /S C O M 0 N C P C 7 /[T P 1 A ]/S C O M 3 P C 6 /[T P 0 _ 0 ]/S C O M 2 P E 3 /[T P 3 _ 1 ] P E 2 P E 1 P E 0 P D 5 /[T P 0 _ 1 ] 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P B 6 /[S D O ] P B 7 /[S D I/S D A ] P D 6 /[S C K /S C L ] P D 7 /[S C S ] P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 N C N C N C P C 2 /T C K 2 /P C K /C 1 + P C 3 /P IN T /T P 2 _ 0 /C 1 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P D 0 /[T C K 2 ]/[S C S ] P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P D 2 /[T C K 0 ]/[S D I/S D A ] P D 3 /[T C K 1 ]/[S D O ] P D 4 /[T P 2 _ 1 ] P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C P F 0 /[C N 7 N 6 N 5 N 4 N 3 N 2 N 1 N 0 1 X ] 0 X ] E F 1 2 3 4 5 6 7 8 1 0 1 1 9 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 H T 6 6 F 5 0 4 4 L Q F P -A 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 P D 1 /[T P P C 5 /[IN T P C 4 /[IN 1 D P T P D 2 /[T C K 0 ]/[S D I/S D 2 _ 0 ]/[S D O ]/[S C K /S C 0 /[T C K 2 ]/T P 3 _ 1 /[S C ]/T P 0 _ 1 /T P 1 B _ 2 /[P C 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D A ] L ] S ] K ] _ 1 1 1 + S ] L ] A ] O ] 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 P D 3 P D 4 P D 5 P E 0 P E 1 P E 2 P E 3 P C 6 P C 7 P C 0 P C 1 /[T C K 1 ]/T P 3 _ 0 /[S D O ] /[T P 2 _ 1 ] /[T P 0 _ 1 ] /[T /[T /[T /T /T P 3 _ P 0 _ P 1 A P 1 B P 1 B 1 ] 0 ]/S ]/S C _ 0 /S _ 1 /S C O O M C O C O M 2 3 M 0 M 1 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 /[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S & A V D D /O S C 1 /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ] /[IN T 1 ] H T 6 6 F 5 0 4 8 S S O P -A P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C P C 4 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D N C E F N 7 N 6 N 5 N 4 N 3 N 2 N 1 N 0 N C P F 1 /[C 1 X ] R /A /A /A /A /A /A /A /A 1 2 3 4 5 6 7 8 1 0 1 1 1 2 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 P D 2 /[T C K 0 ]/[S D I/S D P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C 3 6 3 5 3 4 3 3 3 2 N A ] L ] S ] C K ] _ 1 1 1 + S ] L ] A ] O ] P D 3 P D 4 P D 5 P E 0 P E 1 P E 2 P E 3 P C 6 P C 7 N C P C 0 P C 1 /[T C K 1 ]/T P 3 _ 0 /[S D O ] /[T P 2 _ 1 ] /[T P 0 _ 1 ] P B 5 /S C S /V P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 H T 6 6 F 5 0 4 8 Q F N -A 3 1 3 0 2 9 2 8 2 7 2 6 /[T P 3 _ 1 ] /[T P 0 _ 0 ]/S C O M 2 /[T P 1 A ]/S C O M 3 /T P 1 B _ 0 /S C O M 0 /T P 1 B _ 1 /S C O M 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S & A V D D /O S C 1 /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ] /[IN T 1 ] /[C 0 X ] Note: 1. Bracketed pin names indicate non-default pinout remapping locations.30 . its pin names at the right side of the ²/² sign can be used for higher priority. 3. 5 October 4. VDD&AVDD means the VDD and AVDD are the double bonding. 1.

6 October 4.30 . 3. If the pin-shared pin functions have multiple outputs simultaneously. VDD&AVDD means the VDD and AVDD are the double bonding. its pin names at the right side of the ²/² sign can be used for higher priority. 2. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 P D 1 /[T P P C 5 /IN T 3 /[IN T P C 4 /IN T 2 /[IN P D 1 /[T P P C 5 /IN T 3 /[IN T P C 4 /IN T 2 /[IN 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 1 D P T 1 D P D 2 /[T C K 0 ]/[S D I/S D 2 _ 0 ]/[S D O ]/[S C K /S C 0 /[T C K 2 ]/T P 3 _ 1 /[S C ]/T P 0 _ 1 /T P 1 B _ 2 /[P C 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D P T 2 _ 0 ]/[S D O ]/[S C K /S C 0 /[T C K 2 ]/T P 3 _ 1 /[S C ]/T P 0 _ 1 /T P 1 B _ 2 /[P C 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D L ] S ] K ] _ 1 1 1 + S ] L ] A ] O ] 3 0 2 9 2 8 2 7 A ] L ] S ] K ] _ 1 1 1 + S ] L ] A ] O ] 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 2 3 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 9 P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C 1 X ]/A N N 5 N 4 N 3 N 2 N 1 N 0 1 1 E F N 7 N 6 H T 6 6 F 6 0 4 0 Q F N -A 2 6 2 5 2 4 2 3 2 2 2 1 P D 2 P D 3 P D 4 P D 5 P C 6 P C 7 P C 0 P C 1 P E 4 P E 5 /[T /[T /[T /[T /[T /[T /T /T /[T /[T C K 0 ]/[S C K 1 ]/T P P 2 _ 1 ] P 0 _ 1 ] P 0 _ 0 ]/S P 1 A ]/S C P 1 B _ 0 /S P 1 B _ 1 /S P 1 B _ 2 ] P 3 _ 0 ] D I/S D A ] 3 _ 0 /[S D O ]/[S C K /S C L ] C O O M C O C O M 2 3 M 0 M 1 P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C 1 X ]/A N P F 0 /[C 0 X ]/A N N 5 N 4 N 3 N 2 N 1 N 0 1 1 1 0 N 7 N 6 E F 3 3 3 2 3 1 3 0 H T 6 6 F 6 0 4 4 L Q F P -A 2 9 2 8 2 7 2 6 2 5 2 4 2 3 P D 3 P D 4 P D 5 P E 0 P E 1 P E 2 P E 3 P C 6 P C 7 P C 0 P C 1 /[T C /[T P /[T P /[IN /[IN /[IN /[T P /[T P /[T P /T P /T P K 1 ]/T P 2 _ 1 ] 0 _ 1 ] T 0 ] T 1 ] T 2 ] 3 _ 1 ] 0 _ 0 ]/S 1 A ]/S C 1 B _ 0 /S 1 B _ 1 /S 3 _ 0 /[S D O ]/[S C K /S C L ] C O O M C O C O M 2 3 M 0 M 1 N C 1 2 3 4 5 6 7 8 9 N C P D 7 /[S C S ] P D 6 /[S C K /S C L ] P B 7 /[S D I/S D A ] P B 6 /[S D O ] P F 2 P B 5 /S C S /V R E F P A 7 /S C K /S C L /A N 7 P A 6 /S D I/S D A /A N 6 P A 5 /C 1 X /S D O /A N 5 P A 4 /IN T 1 /T C K 1 /A N 4 P A 3 /IN T 0 /C 0 -/A N 3 P A 2 /T C K 0 /C 0 + /A N 2 P A 1 /T P 1 A /A N 1 P A 0 /C 0 X /T P 0 _ 0 /A N 0 P F 1 /[C 1 X ]/A N 1 1 P F 0 /[C 0 X ]/A N 1 0 P E 7 /[IN T 1 ]/A N 9 P E 6 /[IN T 0 ]/A N 8 V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /R E S & A V /O S C /O S C /X T 1 /X T 2 & A V /[IN T /[IN T /[C 0 X S S 0 ]/A N 8 1 ]/A N 9 ]/A N 1 0 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 H T 6 6 F 6 0 4 8 S S O P -A D D 1 2 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 P C 2 /T C K 2 /P C K /C 1 + P C 3 /P IN T /T P 2 _ 0 /C 1 P C 4 /IN T 2 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 _ 1 P C 5 /IN T 3 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C S ] P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P D 2 /[T C K 0 ]/[S D I/S D A ] P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P D 4 /[T P 2 _ 1 ] P D 5 /[T P 0 _ 1 ] P E 0 /[IN T 0 ] P E 1 /[IN T 1 ] P E 2 /[IN T 2 ] P E 3 /[T P 3 _ 1 ] P G 1 /[C 1 X ] P C 6 /[T P 0 _ 0 ]/S C O M 2 P C 7 /[T P 1 A ]/S C O M 3 P C 0 /T P 1 B _ 0 /S C O M 0 P C 1 /T P 1 B _ 1 /S C O M 1 P E 4 /[T P 1 B _ 2 ] P E 5 /[T P 3 _ 0 ] P B 0 /R E S V D D & A V D D P B 1 /O S C 1 P B 5 /S C S /V P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 N C E F N 7 N 6 N 5 N 4 N 3 N 2 N 1 N 0 N C P F 1 /[C 1 X ]/A N 1 1 R /A /A /A /A /A /A /A /A 1 2 3 4 5 6 7 8 1 0 1 1 1 2 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 P F 3 P F 2 P B 5 /S C S /V R E F P A 7 /S C K /S C L /A N 7 P A 6 /S D I/S D A /A N 6 P A 5 /C 1 X /S D O /A N 5 P A 4 /IN T 1 /T C K 1 /A N 4 P A 3 /IN T 0 /C 0 -/A N 3 P A 2 /T C K 0 /C 0 + /A N 2 P A 1 /T P 1 A /A N 1 P A 0 /C 0 X /T P 0 _ 0 /A N 0 P F 1 /[C 1 X ]/A N 1 1 P F 0 /[C 0 X ]/A N 1 0 1 2 3 4 5 6 7 9 1 0 1 1 1 2 1 3 8 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 /[T P 1 B _ 2 ] P D 1 /[T /[T P 3 _ 0 ] P /R E S & A V D D P C 5 /IN T 3 /[IN T /O S C 1 P C 4 /IN T 2 /[IN /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ]/A N 8 /[IN T 1 ]/A N 9 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C T 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D T P D 2 /[T C K 0 ]/[S D I/S D 2 _ 0 ]/[S D O ]/[S C K /S C 0 /[T C K 2 ]/T P 3 _ 1 /[S C ]/T P 0 _ 1 /T P 1 B _ 2 /[P C 0 ]/[P IN T ]/T C K 3 /T P 2 P C 3 /P IN T /T P 2 _ 0 /C P C 2 /T C K 2 /P C K /C P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D P B 6 /[S D P P F 4 A ] L ] S ] K ] _ 1 1 1 + S ] L ] A ] O ] F 5 3 9 3 8 3 7 3 6 3 5 H T 6 6 F 6 0 5 2 Q F P -A 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 P D 3 P D 4 P D 5 P E 0 P E 1 P E 2 P E 3 P F 6 P F 7 P G 0 P G 1 P C 6 P C 7 /[T /[T /[T /[IN /[IN /[IN /[T /[C /[C /[T /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P 2 _ 1 ] P 0 _ 1 ] T 0 ] T 1 ] T 2 ] P 3 _ 1 ] 0 X 1 X P 0 P 1 ] ] _ 0 ]/S C O M 2 A ]/S C O M 3 /S C O M 0 /S C O M 1 ] N 8 P C P C P E P E P B V D P B P B P B P B V S P E P E 0 /T P 1 B _ 0 1 /T P 1 B _ 1 4 /[T P 1 B _ 2 5 /[T P 3 _ 0 ] 0 /R E S D & A V D D 1 /O S C 1 2 /O S C 2 3 /X T 1 4 /X T 2 S & A V S S 6 /[IN T 0 ]/A 7 /[IN T 1 ]/A N 9 H T 6 6 F 6 0 4 8 L Q F P -A /Q F N -A P D 2 /[T C K 0 ]/[S D I/S D P 2 _ 0 ]/[S D O ]/[S C K /S C D 0 /[T C K 2 ]/T P 3 _ 1 /[S C 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 N A ] L ] S ] C K ] _ 1 1 1 + S ] L ] A ] O ] P D 3 P D 4 P D 5 P E 0 P E 1 P E 2 P E 3 P C 6 P C 7 N C P C 0 P C 1 /[T /[T /[T /[IN /[IN /[IN /[T /[T /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P 2 _ 1 ] P 0 _ 1 ] T 0 ] T 1 ] T 2 ] P 3 _ 1 ] P 0 _ 0 ]/S C O M 2 P 1 A ]/S C O M 3 /T P 1 B _ 0 /S C O M 0 /T P 1 B _ 1 /S C O M 1 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /[T P 1 B _ 2 ] P D 1 /[T /[T P 3 _ 0 ] P /R E S P C 5 /IN T 3 /[IN T & A V D D P C 4 /IN T 2 /[IN /O S C 1 /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ]/A N 8 /[IN T 1 ]/A N 9 /[C 0 X ]/A N 1 0 1 D P Note: 1. Bracketed pin names indicate non-default pinout remapping locations. 2010 Rev.

PC2. The function of each pin is listed in the following table. PC3 PA2. PA4 PA0 PA1. 1. 1 input Comparator 0. TM1 input TM0 I/O TM1 I/O Ext. 2010 . PA5 PA2. C1X TCK0. The following tables only include the pins which are directly related to the MCU. PC1. PA4 PC3 PC2 PA6 PA5 PB5 PA7 PA7 PA6 PC0. The pin descriptions of the additional peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional description.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pin Description With the exception of the power pins. however the details behind how each pin is configured is contained in other sections of the datasheet. e. Interrupt 0. INT1 PINT PCK SDI SDO SCS SCK SCL SDA SCOM0~SCOM3 OSC1 OSC2 XT1 XT2 RES VDD AVDD VSS AVSS Port A Port B Port C ADC input ADC reference input Comparator 0.0.30 7 October 4. TP1_1 INT0. 1 input Comparator 0. C1+ C0X.1 etc. PC0 PA3. PC2 PA0. C1C0+. all pins on these devices can be referenced by their Port name. Serial Port pins etc. PA.g. PA. 1 output TM0. PC3 PB1 PB2 PB3 PB4 PB0 ¾ ¾ ¾ ¾ Rev. TCK1 TP0_0 TP1_0. However these Port pins are also shared with other function such as the Analog to Digital Converter. which refer to the digital I/O function of the pins. 1 Peripheral Interrupt Peripheral Clock output SPI Data input SPI Data output SPI Slave Select SPI Serial Clock I C Clock I C Data SCOM0~SCOM3 HXT/ERC pin HXT pin LXT pin LXT pin Reset input Power supply * ADC power supply * Ground ** ADC ground ** 2 2 Function OP PAWU PAPU PBPU PCPU ACERL ADCR1 CP0C CP1C ¾ TMPC0 TMPC0 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SCOMC CO CO CO CO CO ¾ ¾ ¾ ¾ I/T ST ST ST AN AN AN AN ¾ ST ST ST ST ST ¾ ST ¾ ST ST ST ST ¾ HXT ¾ LXT ¾ ST PWR PWR PWR PWR O/T CMOS CMOS CMOS ¾ ¾ ¾ ¾ CMOS ¾ CMOS CMOS ¾ ¾ CMOS ¾ CMOS CMOS CMOS NMOS NMOS SCOM ¾ HXT ¾ LXT ¾ ¾ ¾ ¾ ¾ Pin-Shared Mapping ¾ ¾ ¾ PA0~PA7 PB5 PA3. HT66F20 Pin Name PA0~PA7 PB0~PB5 PC0~PC3 AN0~AN7 VREF C0-.

The AVSS pin is bonded together internally with VSS. As the Pin Description Summary table applies to the package type with the most pins. 1. The AVDD pin is bonded together internally with VDD. 2010 . PA4 PC3 or PC4 PC2 or PC5 PA6 or PC0 PA5 or PC1 PB5 or PC6 PA7 or PC7 PA7 or PC7 PA6 or PC0 PC0. PC1. PC1 PA3. PA4 PA0. ST: Schmitt Trigger input CMOS: CMOS output. HT66F30 Pin Name PA0~PA7 PB0~PB5 PC0~PC7 AN0~AN7 VREF C0-.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Note: I/T: Input type. CO: Configuration option. TCK1 TP0_0. not all of the above listed pins may be present on package types with smaller numbers of pins. C1+ C0X. **: VSS is the device ground pin while AVSS is the ADC ground pin. PC7 PB1 PB2 PB3 PB4 Rev. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. PC6. TP1B_1 INT0. INT1 PINT PCK SDI SDO SCS SCK SCL SDA SCOM0~SCOM3 OSC1 OSC2 XT1 XT2 Port A Port B Port C ADC input ADC reference input Comparator 0. TP0_1 TP1A TP1B_0. NMOS: NMOS output SCOM: Software controlled LCD COM. C1C0+. PC2 PA0. 1 Peripheral Interrupt Peripheral Clock output SPI Data input SPI Data output SPI Slave Select SPI Serial Clock I C Clock I C Data SCOM0~SCOM3 HXT/ERC pin HXT pin LXT pin LXT pin 2 2 Function OP PAWU PAPU PBPU PCPU ACERL ADCR1 CP0C CP1C ¾ TMPC0 TMPC0 TMPC0 ¾ PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 SCOMC CO CO CO CO I/T ST ST ST AN AN AN AN ¾ ST ST ST ST ST ST ¾ ST ¾ ST ST ST ST ¾ HXT ¾ LXT ¾ O/T CMOS CMOS CMOS ¾ ¾ ¾ ¾ CMOS ¾ CMOS CMOS CMOS ¾ ¾ CMOS ¾ CMOS CMOS CMOS NMOS NMOS SCOM ¾ HXT ¾ LXT Pin-Shared Mapping ¾ ¾ ¾ PA0~PA7 PB5 PA3. PC3 PA2. PA5 PA2. TM1 input TM0 I/O TM1 I/O TM1 I/O Ext. 1 input Comparator 0. PC5 PA1 PC0.30 8 October 4. Interrupt 0. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. 1 output TM0. C1X TCK0. 1 input Comparator 0.

PC3 PA2. PC1. CO: Configuration option.30 9 October 4. 2010 . NMOS: NMOS output SCOM: Software controlled LCD COM. 1 output ¾ CMOS PA0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pin Name RES VDD AVDD VSS AVSS Note: Function Reset input Power supply * ADC power supply * Ground ** ADC ground ** I/T: Input type. HT66F40 Pin Name PA0~PA7 PB0~PB7 PC0~PC7 PD0~PD7 PE0~PE7 PF0~PF1 AN0~AN7 VREF C0-. The AVSS pin is bonded together internally with VSS. 1 input Function OP PAWU PAPU PBPU PCPU PDPU PEPU PFPU ACERL ADCR1 CP0C CP1C CP0C CP1C CP0C CP1C PRM0 PRM1 TMPC0 PRM2 TMPC0 PRM2 TMPC0 PRM2 I/T ST ST ST ST ST ST AN AN AN AN O/T CMOS CMOS CMOS CMOS CMOS CMOS ¾ ¾ ¾ ¾ Pin-Shared Mapping ¾ ¾ ¾ ¾ ¾ ¾ PA0~PA7 PB5 PA3. PC5 or -. PC2 OP CO ¾ ¾ ¾ ¾ I/T ST PWR PWR PWR PWR O/T ¾ ¾ ¾ ¾ ¾ Pin-Shared Mapping PB0 ¾ ¾ ¾ ¾ C0X. C1X Comparator 0. ST: Schmitt Trigger input CMOS: CMOS output. C1C0+. PD3. not all of the above listed pins may be present on package types with smaller numbers of pins. The AVDD pin is bonded together internally with VDD. PD5 PA1 or PC7 PC0. PD0 PA0. PA5 or PF0. PC2 or PD2. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. **: VSS is the device ground pin while AVSS is the ADC ground pin. 1. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. -. PC5 or PC6. PF1 PA2. C1+ Port A Port B Port C Port D Port E Port F ADC input ADC reference input Comparator 0. 1 input Comparator 0. TP0_1 TP1A TP1B_0~TP1B_2 TM0~TM2 input TM0 I/O TM1 I/O TM1 I/O ST ST ST ST ¾ CMOS CMOS CMOS Rev. PE4 TCK0~TCK2 TP0_0. PA4. As the Pin Description Summary table applies to the package type with the most pins.

PC7 PB1 PB2 PB3 PB4 PB0 ¾ ¾ ¾ ¾ Rev. The AVDD pin is bonded together internally with VDD. PD4 PA3. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. PC6.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pin Name TP2_0. 2 2 Function OP TMPC1 PRM2 PRM1 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 SCOMC CO CO CO CO CO ¾ ¾ ¾ ¾ I/T ST ST ST ¾ ST ¾ ST ST ST ST ¾ HXT ¾ LXT ¾ ST PWR PWR PWR PWR O/T CMOS ¾ ¾ CMOS ¾ CMOS CMOS CMOS NMOS NMOS SCOM ¾ HXT ¾ LXT ¾ ¾ ¾ ¾ ¾ Pin-Shared Mapping PC3. 1. NMOS: NMOS output SCOM: Software controlled LCD COM. TP2_1 INT0. CO: Configuration option. PC4 or PD1. INT1 PINT PCK SDI SDO SCS SCK SCL SDA SCOM0~SCOM3 OSC1 OSC2 XT1 XT2 RES VDD AVDD VSS AVSS Note: TM2 I/O Ext. PA4 or PC4. 2010 . 1 Peripheral Interrupt Peripheral Clock output SPI Data input SPI Data output SPI Slave Select SPI Serial Clock I C Clock I C Data SCOM0~SCOM3 HXT/ERC pin HXT pin LXT pin LXT pin Reset input Power supply * ADC power supply * Ground ** ADC ground ** I/T: Input type. PC5 or PE6. PE7 PC3 or PC4 PC2 or PC5 PA6 or PD2 or PB7 PA5 or PD3 or PB6 PB5 or PD0 or PD7 PA7 or PD1 or PD6 PA7 or PD1 or PD6 PA6 or PD2 or PB7 PC0. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. **: VSS is the device ground pin while AVSS is the ADC ground pin. As the Pin Description Summary table applies to the package type with the most pins. The AVSS pin is bonded together internally with VSS. not all of the above listed pins may be present on package types with smaller numbers of pins. Interrupt 0.30 10 October 4. PC1. ST: Schmitt Trigger input CMOS: CMOS output.

PE7 PC3 or PC4 PC2 or PC5 PA6 or PD2 or PB7 PA5 or PD3 or PB6 PB5 or PD0 or PD7 PA7 or PD1 or PD6 PA7 or PD1 or PD6 PA6 or PD2 or PB7 PC0. 1 output ¾ CMOS PA0. 1 input Comparator 0. PA5 or PF0. PC1. PC2. 1 Peripheral Interrupt Peripheral Clock output SPI Data input SPI Data output SPI Slave Select SPI Serial Clock I C Clock I2C Data SCOM0~SCOM3 HXT/ERC pin HXT pin LXT pin 2 ST ST ST ST ST ST ST ST ¾ ST ¾ ST ST ST ST ¾ HXT ¾ LXT ¾ CMOS CMOS CMOS CMOS CMOS ¾ ¾ CMOS ¾ CMOS CMOS CMOS NMOS NMOS SCOM ¾ HXT ¾ Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 HT66F50 Pin Name PA0~PA7 PB0~PB7 PC0~PC7 PD0~PD7 PE0~PE7 PF0~PF1 AN0~AN7 VREF C0-.30 11 October 4. PE4 PC3. PC5 or -. TP3_1 INT0. PC5 or PC6. C1C0+. PF1 PA2. PA0. PD0. PC7 PB1 PB2 PB3 TCK0~TCK3 TP0_0. PC6. PC5 or PE6. PE3 PA3. PC2 C0X. INT1 PINT PCK SDI SDO SCS SCK SCL SDA SCOM0~SCOM3 OSC1 OSC2 XT1 TM0~TM3 input TM0 I/O TM1 I/O TM1 I/O TM2 I/O TM3 I/O Ext. PA4 or PC4. PD4 PD3. TP2_1 TP3_0. 1. TP0_1 TP1A TP1B_0~TP1B_2 TP2_0. 1 input Function OP PAWU PAPU PBPU PCPU PDPU PEPU PFPU ACERL ADCR1 CP0C CP1C CP0C CP1C CP0C CP1C PRM0 PRM1 TMPC0 PRM2 TMPC0 PRM2 TMPC0 PRM2 TMPC1 PRM2 TMPC1 PRM2 PRM1 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 SCOMC CO CO CO I/T ST ST ST ST ST ST AN AN AN AN O/T CMOS CMOS CMOS CMOS CMOS CMOS ¾ ¾ ¾ ¾ Pin-Shared Mapping ¾ ¾ ¾ ¾ ¾ ¾ PA0~PA7 PB5 PA3. PA4. C1X Comparator 0. PD5 PA1 or PC7 PC0. PC4 or PD1. PD3. PC4 or PD2. C1+ Port A Port B Port C Port D Port E Port F ADC input ADC reference input Comparator 0. PD0 or PE5. PC1. PC3 PA2. -. 2010 . Interrupt 0.

PD3.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pin Name XT2 RES VDD AVDD VSS AVSS Note: LXT pin Reset input Power supply * ADC power supply * Ground ** ADC ground ** I/T: Input type. PC5 or PC6. As the Pin Description Summary table applies to the package type with the most pins. 2010 . PA5 or PF0.30 12 October 4. **: VSS is the device ground pin while AVSS is the ADC ground pin. PC2 PA0. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. 1 input Function OP PAWU PAPU PBPU PCPU PDPU PEPU PFPU PGPU ACERH ADCR1 CP0C CP1C CP0C CP1C CP0C CP1C PRM0 PRM1 TMPC0 PRM2 I/T ST ST ST ST ST ST ST AN AN AN AN O/T CMOS CMOS CMOS CMOS CMOS CMOS CMOS ¾ ¾ ¾ ¾ Pin-Shared Mapping ¾ ¾ ¾ ¾ ¾ ¾ ¾ PA0~PA7. C1X Comparator 0. PF1 PB5 PA3. PE7. ST: Schmitt Trigger input CMOS: CMOS output. PC2. The AVSS pin is bonded together internally with VSS. PD5 Function OP CO CO ¾ ¾ ¾ ¾ I/T ¾ ST PWR PWR PWR PWR O/T LXT ¾ ¾ ¾ ¾ ¾ Pin-Shared Mapping PB4 PB0 ¾ ¾ ¾ ¾ C0X. CO: Configuration option. C1+ Port A Port B Port C Port D Port E Port F Port G ADC input ADC reference input Comparator 0. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. The AVDD pin is bonded together internally with VDD. 1 input Comparator 0. 1 output ¾ CMOS TCK0~TCK3 TP0_0. PD0. PC4 or PD2. PE6. PC3 PA2. 1. PF0. C1C0+. PA4. HT66F60 Pin Name PA0~PA7 PB0~PB7 PC0~PC7 PD0~PD7 PE0~PE7 PF0~PF7 PG0~PG1 AN0~AN11 VREF C0-. NMOS: NMOS output SCOM: Software controlled LCD COM. PF1 or PG0. TP0_1 TM0~TM3 input TM0 I/O ST ST ¾ CMOS Rev. PA0. PG1 PA2. not all of the above listed pins may be present on package types with smaller numbers of pins.

PE4 PC3. or PE0. NMOS: NMOS output SCOM: Software controlled LCD COM. PC5. Interrupt 0~3 PRM1 ST ¾ PINT PCK SDI SDO SCS SCK SCL SDA SCOM0~SCOM3 OSC1 OSC2 XT1 XT2 RES VDD AVDD VSS AVSS Note: Peripheral Interrupt Peripheral Clock output SPI Data input SPI Data output SPI Slave Select SPI Serial Clock I2C Clock I2C Data SCOM0~SCOM3 HXT/ERC pin HXT pin LXT pin LXT pin Reset input Power supply * ADC power supply * Ground ** ADC ground ** PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 SCOMC CO CO CO CO CO ¾ ¾ ¾ ¾ ST ¾ ST ¾ ST ST ST ST ¾ HXT ¾ LXT ¾ ST PWR PWR PWR PWR ¾ CMOS ¾ CMOS CMOS CMOS NMOS NMOS SCOM ¾ HXT ¾ LXT ¾ ¾ ¾ ¾ ¾ I/T: Input type. 2010 . PC4 or PD1. TP3_1 TM1 I/O TM1 I/O TM2 I/O TM3 I/O Function OP TMPC0 PRM2 TMPC0 PRM2 TMPC1 PRM2 TMPC1 PRM2 I/T ST ST ST ST O/T CMOS CMOS CMOS CMOS Pin-Shared Mapping PA1 or PC7 PC0. PD0 or PE5.or PE6. As the Pin Description Summary table applies to the package type with the most pins. PE1. -. . PC1. PC1. CO: Configuration option.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pin Name TP1A TP1B_0~TP1B_2 TP2_0. -. PC4. PC7 PB1 PB2 PB3 PB4 PB0 ¾ ¾ ¾ ¾ INT0~INT3 Ext. PC5 or PC4. PE3 PA3. not all of the above listed pins may be present on package types with smaller numbers of pins. AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. ST: Schmitt Trigger input CMOS: CMOS output. The AVDD pin is bonded together internally with VDD.30 13 October 4. -. 1. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. TP2_1 TP3_0. PD4 PD3. -. PC6. PE7. O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power. PC5 or -. PE2. Rev. PA4. PC3 or PC4 PC2 or PC5 PA6 or PD2 or PB7 PA5 or PD3 or PB6 or PD1 PB5 or PD0 or PD7 PA7 or PD1 or PD6 or PD3 PA7 or PD1 or PD6 or PD3 PA6 or PD2 or PB7 PC0.

..9VDD ¾ ¾ ¾ 0.. Normal Mode... Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device........ D.....80mA Total Power Dissipation ..... Typ. fSYS=fL (LXT...00 1 2 3..... ADC off. Normal Mode............83 2.... Ta=25°C Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V IDD3 IIDLE0 IIDLE1 ISLEEP0 ISLEEP1 VIL1 VIH1 VIL2 VIH2 Rev. ERC... fSYS=fH=8MHz... HIRC) ¾ Conditions fSYS=8MHz fSYS=12MHz fSYS=20MHz 3V 5V IDD1 Operating Current..0 10 30 1....5 5.........7VDD 0 0..0 5........2 2..7 4...... ERC. ADC off... ADC off.....0 6..-50°C to 125°C Operating Temperature....3VDD VDD 0............3 7... fSYS=fH (HXT) Operating Current.500mW Storage Temperature . WDT enable No load... ADC off.....55 1...2 5.VSS-0. fSYS=12MHz on No load. 2010 ..-40°C to 85°C IOH Total.. WDT enable No load. WDT enable No load.. WDT enable ¾ ¾ ¾ ¾ 2......HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Absolute Maximum Ratings Supply Voltage ..... fSYS=fH=12MHz. Characteristics Test Conditions Symbol VDD Parameter VDD Operating Voltage (HXT.... ADC off.-80mA Note: These are stress ratings only........5 3......5 ¾ ¾ ¾ ¾ 5..... HIRC) SLEEP0 Mode Standby Current (LXT and LIRC off) SLEEP1 Mode Standby Current (LXT or LIRC on) Input Low Voltage for I/O Ports or Input Pins except RES pin Input High Voltage for I/O Ports or Input Pins except RES pin Input Low Voltage (RES) Input High Voltage (RES) 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V ¾ ¾ ¾ ¾ No load.. fSYS=fH=20MHz..7 1..... ADC off..0 20 50 3.........0 3... ADC off.. fSYS=fH=4MHz. WDT enable No load..3V IOL Total ....5 5....3 2......... fSYS=fH (HXT..... HIRC) 3V 5V 3V 5V IDD2 Operating Current..0 0.....5 1.6 3. WDT enable No load...8 1..... WDT disable No load.0V Input Voltage.......1 2.3V to VDD+0. WDT enable No load......C..4VDD VDD Min..0 6. ADC off.....................7 2........3V to VSS+6...0 0.... LIRC) IDLE0 Mode Standby Current (LXT or LIRC on) IDLE1 Mode Standby Current (HXT.... 1. Slow Mode........30 ¾ ¾ 1.5 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 0 0....4 5........VSS-0.5 2...... fSYS=fL.....30 14 October 4.0 0..5 9.. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. WDT enable.......... ADC off... ERC.. Max.

475 -3% ¾ 100 200 0. Unit I125 200 300 mA Rev.30 15 October 4. 3. 2010 .40 2.4V VLVD LVD Voltage Level ¾ LVDEN=1.55V option LVR Enable.40 60 75 90 ¾ ¾ ¾ ¾ 60 30 25.00 3.2V LVDEN=1. ISEL[1:0]=10 SCOMC.0 50 +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% 90 115 135 0.6V LVDEN=1.3 0.2mA IOH=-7.5 35 2.25V Reference with Buffer is used 5V ¾ ¾ No load ¾ ¾ 70 140 0. VLVD=2.15 4.55 3.0V LVDEN=1.3V LVDEN=1. LVDEN=1 LVR enable.4mA ¾ SCOMC. 2.7 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Ta=25°C Test Conditions Symbol Parameter VDD Conditions LVR Enable.5 20 10 17.60 4.4V LVR Enable. VLVD=2.5 65 V V V V V V V V V V V V mA mA mA V V V V kW kW mA mA mA mA VDD V Min. VLVD=2.20 2. 4.0V LVDEN=1.500 1.25V Reference with Buffer Voltage Additional Power Consumption if 1.30 3. Max. ISEL[1:0]=11 VSCOM V125 VDD/2 Voltage for LCD COM 1.70 3. LVDEN=1 VOL 3V Output Low Voltage I/O Port 5V VOH 3V Output High Voltage I/O Port 5V RPH Pull-high Resistance for I/O Ports 3V 5V IOL=20mA IOH=-3. 2.5 ¾ ¾ 100 50 32.7V LVDEN=1. 1. Typ.15V option LVR Enable. VLVD=3. VLVD=2.00 2. LVDEN=0 ILV Additional Power Consumption if LVR and LVD is Used ¾ LVR disable. VLVD=4.10 2. VLVD=3.20V option LVDEN=1.10V option VLVR LVR Voltage Level ¾ LVR Enable. ISEL[1:0]=00 ISCOM SCOMC.525 +3% IOL=9mA -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% ¾ ¾ ¾ ¾ ¾ 2.25 130 260 0.20 2. ISEL[1:0]=01 SCOM Operating Current 5V SCOMC. VLVD=3.

0V~ Ta= -40°C~85°C 5.5V R=120kW * 2.5V~5.4 0.5V 3V/5V Ta=25°C 3V/5V Ta=25°C 5V Ta=25°C DC DC DC 0.2V~5.5V 5V 5V 5V fERC System Clock (ERC) Ta=25°C.2V~ Ta=0~70°C 3. R=120kW * Ta=0~70°C.5V 2.30 16 October 4. Unit Ta=25°C 3V/5V Ta=0~70°C 3V/5V Ta=0~70°C 5V Ta=0~70°C 2.0V~ Ta= -40°C~85°C. 5.5V 2.2V~ Ta= -40°C~85°C 3.6V 3.5V 4. Characteristics Test Conditions Symbol fCPU Parameter VDD Operating Clock ¾ Conditions 2. 2010 .5V R=120kW * fLXT System Clock (LXT) ¾ ¾ Rev. R=120kW * fHIRC System Clock (HIRC) 3.6V 3.5V 3.0V~ Ta=0~70°C 5.5V~5. Max.C.7V~5.4 -2% -2% -2% -5% -4% -5% -7% -5% -6% -4% -6% -12% -10% -15% -8% -12% -2% -5% -7% -9% -15% ¾ ¾ ¾ ¾ ¾ ¾ ¾ 4 8 12 4 8 12 4 4 8 8 12 4 4 8 8 12 8 8 8 8 8 32. Typ.5V 2.5V 3.2V~ Ta= -40°C~85°C.2V~ Ta= -40°C~85°C 3.768 8 12 20 8 12 20 +2% +2% +2% +5% +4% +3% +7% +9% +4% +9% +7% +8% +9% +4% +9% +7% +2% +6% +9% +10% +10% ¾ MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz Min.0V~ Ta= -40°C~85°C 5.7V~5. R=120kW * Ta= -40°C~85°C. 5.5V fSYS System Clock (HXT) ¾ 2.5V 4.2V~ Ta=0~70°C 3.2V~5. 1.5V 2.0V~ Ta= -40°C~85°C 5.0V~ Ta=0~70°C 5.6V 3.4 0.6V 3.5V 2.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A.0V~ Ta=0~70°C 5.

30 17 October 4.90 1. Ta=25°C Unit V V V LSB LSB mA mA ms tADCK tADCK ms Rev.5ms No load.0ms tADCK= 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Ta=25°C Test Conditions Symbol fLIRC fTIMER tRES tINT tLVR tLVD tLVDS tBGS tEERD tEEWR Parameter VDD System Clock (LIRC) Timer Input Pin Frequency External Reset Low Pulse Width Interrupt Pulse Width Low Voltage Width to Reset Low Voltage Width to Interrupt LVDO stable time VBG Turn on Stable Time EEPROM Read Time EEPROM Write Time System Start-up Timer Period (Wake-up from HALT) 5V ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Conditions Ta=25°C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ fSYS=HXT or LXT tSST ¾ fSYS=ERC or HIRC fSYS=LIRC OSC Note: 1. as the resistor tolerance will influence the frequency a precision resistor is recommended. Max.1mF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. tADCK= 0. 2010 . 1.5ms ¾ 12-bit A/D Converter ¾ ¾ 2. * For fERC. -10% ¾ 1 1 120 20 15 200 ¾ ¾ ¾ ¾ ¾ 32 ¾ ¾ ¾ 240 45 ¾ ¾ 45 2 1024 15~16 1~2 +10% 1 ¾ ¾ 480 90 ¾ ¾ 90 4 ¾ ¾ ¾ tSYS kHz fSYS ms tSYS ms ms ms ms ms ms Min.5 ¾ ¾ 2 ¾ ¾ ¾ ±1 ±2 0. To maintain the accuracy of the internal HIRC oscillator frequency.20 ¾ 16 4 ¾ 5.0ms No load.7 0 2 ¾ ¾ ¾ ¾ 0. tADCK= 0. Typ.80 10 ¾ ¾ ¾ Min.5 VREF AVDD ±2 ±4 1. Typ. Max.35 1. 3. a 0. tSYS=1/fSYS 2. Unit A/D Converter Characteristics Test Conditions Symbol AVDD VADI VREF DNL INL IADC tADCK tADC tADS tON2ST Parameter VDD A/D Converter Operating Voltage A/D Converter Input Voltage A/D Converter Reference Voltage Differential Non-linearity Integral Non-linearity Additional Power Consumption if A/D Converter is Used A/D Converter Clock Period A/D Conversion Time (Include Sample and Hold Time) A/D Converter Sampling Time A/D Converter On-to-Start Time ¾ ¾ ¾ 5V 5V 3V 5V ¾ ¾ ¾ ¾ Conditions ¾ ¾ ¾ tADCK= 1.

4V ¾ 560 V mA mA mV mV V dB ns Min. Ta=25°C Test Conditions Min.30 18 October 4.5 56 200 10 60 VDD-1. 1. Typ. 2010 . Max.4)/2 while the other pin input transition from VSS to (VCM +100mV) or from VDD to (VCM -100mV). Max. Unit Ta=25°C Measured with comparator one input pin at VCM = (VDD-1. Unit Power-on Reset Characteristics Symbol VPOR RRVDD tPOR Parameter VDD Start Voltage to Ensure Power-on Reset VDD Raising Rate to Ensure Power-on Reset Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset V D D tP O R R R V D D V P O R T im e Rev.035 1 ¾ ¾ ¾ 100 ¾ ¾ mV V/ms ms ¾ ¾ ¾ Typ.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Comparator Electrical Characteristics Test Conditions Symbol VCMP ICMP VCMPOS VHYS VCM AOL tPD Note: Parameter VDD Comparator Operating Voltage Comparator Operating Current 5V Comparator Input Offset Voltage Hysteresis Width Comparator Common Mode Voltage Range Comparator Open Loop Gain Comparator Response Time ¾ ¾ ¾ ¾ ¾ ¾ 3V Conditions ¾ ¾ ¾ ¾ ¾ ¾ ¾ With 100mV overdrive (Note) 2.2 ¾ ¾ -10 20 VSS 60 ¾ ¾ 37 130 ¾ 40 ¾ 80 370 5. VDD Conditions ¾ ¾ ¾ ¾ 0.

For instructions involving branches. two machine cycles are required to complete instruction execution. In this way. 2010 . (P C ) F e tc h In s t. HIRC. branch decisions. etc. 1 E x e c u te In s t. in which case the instruction will take one more instruction cycle to execute. (P C ) E x e c u te In s t. (P C + 1 ) E x e c u te In s t. This makes the device suitable for low-cost. T1~T4. 6 E x e c u te In s t. (S y s te m fS Y S C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r P C P C + 1 P C + 2 P ip e lin in g F e tc h In s t. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. (P C -1 ) F e tc h In s t. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions.30 19 October 4. An 8-bit wide ALU is used in practically all instruction set operations. (P C + 2 ) E x e c u te In s t. rotation. 7 N O P Instruction Fetching Rev. The exception to this are instructions where the contents of the Program Counter are changed. 3 F lu s h P ip e lin e F e tc h In s t. LXT. the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles. Clocking and Pipelining The main system clock. increment. 6 F e tc h In s t. 2 E x e c u te In s t. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped. such as jump or call instructions. hence instructions are effectively executed in one cycle. The internal data path is simplified by moving data through the Accumulator and the ALU. decrement. with the exception of branch or call instructions. which carries out arithmetic operations. high-volume production for controller applications. 1 F e tc h In s t. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. such as subroutine calls or jumps. LIRC or ERC oscillator is subdivided into four internally generated non-overlapping clocks. 1. (P C + 1 ) System Clocking and Pipelining 1 2 3 4 5 6 D E L A Y : : : M O V A . derived from either a HXT. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. one T1~T4 clock cycle forms one instruction cycle. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. logic operations. 2 F e tc h In s t.[1 2 H ] C A L L D E L A Y C P L [1 2 H ] F e tc h In s t.

a subroutine call. SDZ. are directly addressable by the application program. SBCM. as only this low byte is available for manipulation. RLC · Increment and Decrement INCA. signaled by a return instruction.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Program Counter During program execution. such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program Memory address. DAA · Logic operations: AND. The activated level is indexed by the Stack Pointer. At a subroutine call or interrupt acknowledge signal. SUBM.30 20 Arithmetic and Logic Unit . When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction. Rev. SBC. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. If the stack is overflow. RR. Program Counter Device HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 Program Counter High Byte PC9. It is automatically incremented by one each time an instruction is executed except for instructions. At the end of a subroutine or an interrupt routine. The ALU supports the following functions: · Arithmetic operations: ADD. the interrupt request flag will be recorded but the acknowledge signal will be inhibited. OR. when the stack is full. and is neither readable nor writeable. XOR. ADC. As these ALU calculation or operations may result in carry. the next instruction. This feature prevents stack overflow allowing the programmer to use the structure more easily. If the stack is full and an enabled interrupt takes place. the jumps are limited to the present page of memory. SIZ. is available for program control and is a readable and writeable register. 1. etc. Manipulating the PCL register may cause program branching. which has already been fetched during the present instruction execution. SZA. RET. DECA. 2010 . borrow or other status changes. the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. that is 256 locations. however. RL. the first Program Counter save in the stack will be lost. ADCM. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space. a short program jump can be executed directly. known as the Program Counter Low Register. the interrupt will be serviced. RET or RETI.ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. the Program Counter is restored to its previous value from the stack. and is neither readable nor writeable. the Program Counter is used to keep track of the address of the next instruction to be executed. so an extra cycle is needed to pre-fetch. SZ. SDZA. the status register will be correspondingly updated to reflect these changes. XORM. is discarded and a dummy cycle takes its place while the correct instruction is obtained. DEC · Branch decision. RLCA. CALL. JMP. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. PC8 PC10~PC8 PC11~PC8 PC12~PC8 PC13~PC8 Program Counter The lower byte of the Program Counter. by RET or RETI.. RRC. For conditional skip instructions. SIZA. CPL. Connected to the main microcontroller data bus. SNZ. a CALL subroutine instruction can still be executed which will result in a stack overflow. ORM. By transferring data directly into this register. interrupt or reset. RETI October 4. P ro g ra m C o u n te r T o p o f S ta c k S ta c k P o in te r S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry PCL Register B o tto m o f S ta c k S ta c k L e v e l N Device PCL7~PCL0 HT66F20/HT66F30 HT66F40/HT66F50 HT66F60 Stack Levels 4 8 12 SUB. ADDM. once the condition has been met. RRCA. Only the lower 8 bits. ANDM. However. RLA. After a device reset. the microcontroller manages program control by loading the required address into the Program Counter. When the Stack Pointer is decremented. the contents of the Program Counter are pushed onto the stack. known as the Program Counter Low register or PCL. the Stack Pointer will point to the top of the stack. INC. CPLA · Rotation RRA.

The Program Memory is addressed by the Program Counter and also contains data. the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register. respectively. After a device reset is initiated. To use the look-up table. Structure The Program Memory has a capacity of 1K´14 bits to 12K´16 bits. is addressed by a separate table pointer register. For this device series the Program Memory is Flash type. certain locations are reserved for the reset and interrupts. which can be setup in any location within the Program Memory. This example uses raw table data located in the Program Memory which is stored there usH T 6 6 F 5 0 R e s e t In te rru p t V e c to r 0 0 3 C H H T 6 6 F 6 0 R e s e t In te rru p t V e c to r B a n k 0 1 F F F H 2 0 0 0 H 2 F F F H 1 6 b its B a n k 1 Program Memory Structure Rev. The required Bank is selected using Bit 5 of the BP Register. By using the appropriate programming tools. TBLP and TBHP. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. table information and interrupt entries. the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. the program will jump to this location and begin execution. Any unused bits in this transferred higher order byte will be read as ²0². The location 000H is reserved for use by the device reset for program initialisation. After setting up the table pointer. which means it can be programmed and re-programmed a large number of times. allowing the user the convenience of code modification on the same device. When the instruction is executed. Bank 0 and Bank 1. P ro g ra m A d d re s s M e m o ry D a ta 1 4 ~ 1 6 b its The HT66F60 has its Program Memory divided into two Banks. The accompanying diagram illustrates the addressing data flow of the look-up table. H T 6 6 F 2 0 0 0 0 0 H 0 0 0 4 H 0 0 2 C H 0 3 F F H R e s e t In te rru p t V e c to r 1 4 b its 0 7 F F H 1 4 b its 0 F F F H 1 5 b its 1 F F F H 1 6 b its H T 6 6 F 3 0 R e s e t In te rru p t V e c to r H T 6 6 F 4 0 R e s e t In te rru p t V e c to r R e g is te r T B L H H ig h B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. Device HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 Capacity 1K´14 2K´14 4K´15 8K´16 12K´16 Banks 0 0 0 0 0. 1.30 21 October 4. 1 U s e r S e le c te d R e g is te r L o w B y te L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Flash Program Memory The Program Memory is the location where the user code or program is stored. Table data. the table data can be retrieved from the Program Memory using the ²TABRD[m]² or ²TABRDL[m]² instructions. Special Vectors Within the Program Memory. these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. 2010 . These registers define the total address of the look-up table.

temporary register #1 tempreg2 db ? . and then programming or upgrading the program at a later stage. During the programming process the RES pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. 01Bh : : Rev. The table pointer is setup here to have an initial value of ²06H².a . 00Bh. the interrupts should be disabled prior to the execution of any main routine table-read instructions. temporary register #2 : : mov a. 00Ch.30 22 October 4. If using the table read instructions.note that this address mov tblp. · Table Read Program Example tempreg1 db ? . The user must there take care to ensure that no other outputs are connected to these two pins. However. Because the TBLH register is a read-only register and cannot be restored. Note that the value for the table pointer is referenced to the first address of the present page if the ²TABRD [m]² instruction is being used. The value at this ORG statement is ²700H² which refers to the start address of the last page within the 2K Program Memory of the HT66F30. .a : : tabrd tempreg1 . . transfers value in table referenced by table pointer data at program . 1. reduce value of table pointer by one . Note that all table related instructions require two instruction cycles to complete their operation. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the ²TABRD [m]² instruction is executed.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ing the ORG statement. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller. 00Eh. is referenced mov a. 2010 . 00Fh.07h . This will ensure that the first data read from the data table will be at the Program Memory address ²706H² or 6 locations after the start of the last page. the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. memory address ²706H² transferred to tempreg1 and TBLH dec tblp tabrd tempreg2 . initialise low table pointer . care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. Two additional lines are required for the power supply and one line for the reset. Holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. transfers value in table referenced by table pointer data at program memory address ²705H² transferred to tempreg2 and TBLH in this example the data ²1AH² is transferred to tempreg1 and data ²0FH² to register tempreg2 : : org 700h .06h . 00Dh. MCU Programming Pins PA0 PA2 RES VDD VSS Function Serial Data Input/Output Serial Clock Device Reset Power Supply Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 5-wire interface. initialise high table pointer tbhp. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. As an additional convenience. sets initial address of program memory dc 00Ah. 01Ah. in situations where simultaneous use cannot be avoided. In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. .

30 23 October 4. Here are located registers which are necessary for correct operation of the device. some remain protected from user manipulation. known as the Special Function Data Memory. Structure Divided into two sections. Many of these registers can be read from and written to directly under program control. the first of these is an area of RAM. 1. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 W r ite r C o n n e c to r S ig n a ls W r ite r _ V D D M C U V D D P r o g r a m m in g P in s Device HT66F20 Capacity 64´8 Banks 0: 60H~7FH 1: 60H~7FH 0: 60H~7FH 1: 60H~7FH 2: 60H~7FH 0: 80H~FFH 1: 80H~BFH 0: 80H~FFH 1: 80H~FFH 2: 80H~FFH 0: 80H~ 1: 80H~FFH 2: 80H~FFH 3: 80H~FFH 4: 80H~BFH R E S D A T A R E S D A T A HT66F30 96´8 HT66F40 C L K C L K 192´8 HT66F50 W r ite r _ V S S * * * V S S 384´8 HT66F60 576´8 T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1kW or the capacitance of * must be less than 1nF. 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H B a n IA M IA M k 0 . Programmer Pin RES DATA Pins PB0 PA0 PA2 Programmer and MCU Pins RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. however. 1 R 0 P 0 R 1 P 1 B P A C C P C L T B L P T B L H T B H P S T A T U S S M O D L V D C IN T E G W D T C T B C IN T C 0 IN T C 1 IN T C 2 U n u s e d M F I0 M F I1 M F I2 U n u s e d P A W U P A P U P A P A C P B P U P B P B C P C P U P C P C C U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d A D R L A D R H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H 3 A H 3 B H 3 C H 3 D H 3 E H 3 F H 4 0 H 4 1 H 4 2 H 4 3 H 4 4 H 4 5 H 4 6 H 4 7 H 4 8 H 4 9 H 4 A H 4 B H 4 C H 4 D H 4 E H 4 F H 5 0 H 5 1 H 5 2 H 5 3 H 5 4 H 5 5 H 5 6 H 5 7 H 5 8 H 5 9 H 5 A H 5 B H 5 C H 5 D H 5 E H 5 F H B a n k 0 A A A U B a n k 1 D C R 0 D C R 1 C E R L n u s e d C P 0 C C P 1 C S IM C 0 S IM C 1 S IM D S IM A /S IM C 2 T M 0 C 0 T M 0 C 1 T M 0 D L T M 0 D H T M 0 A L T M 0 A H U n u s e d E E C E E A E E D T M P C 0 U n u s e d U n u s e d U n u s e d U n u s e d T M 1 C 0 T M 1 C 1 U n u s e d T M 1 D L T M 1 D H T M 1 A L T M 1 A H U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d S C O M C U n u s e d HT66F20 Special Purpose Data Memory Rev.

2010 . 1.30 24 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 B a n k IA M IA M 0 . 1 R 0 P 0 R 1 P 1 B P A C C P C L T B L P T B L H T B H P S T A T U S S M O D L V D C IN T E G W D T C T B C IN T C 0 IN T C 1 IN T C 2 U n u s e d M F I0 M F I1 M F I2 U n u s e d P A W U P A P U P A P A C P B P U P B P B C P C P U P C P C C P D P U P D P D C P E P U P E P E C P F P U P F P F C U n u s e d U n u s e d U n u s e d A D R L A D R H A D C R 0 A D C R 1 A C E R L U n u s e d C P 0 C C P 1 C S IM C 0 S IM C 1 S IM D S IM A /S IM C 2 T M 0 C 0 T M 0 C 1 T M 0 D L T M 0 D H T M 0 A L T M 0 A H B a n IA M IA M B a n k 0 U n u s e d B a n k 1 E E C 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H 3 A H 3 B H 3 C H 3 D H 3 E H 3 F H 4 0 H 4 1 H 4 2 H 4 3 H 4 4 H 4 5 H 4 6 H 4 7 H 4 8 H 4 9 H 4 A H 4 B H 4 C H 4 D H 4 E H 4 F H 5 0 H 5 1 H 5 2 H 5 3 H 5 4 H 5 5 H 5 6 H 5 7 H 5 8 H 5 9 H 5 A H 5 B H 5 C H 5 D H 5 E H 5 F H HT66F30 Special Purpose Data Memory 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H 3 A H 3 B H 3 C H 3 D H 3 E H 3 F H 4 0 H 4 1 H 4 2 H 4 3 H 4 4 H 4 5 H 4 6 H 4 7 H 4 8 H 4 9 H 4 A H 4 B H 4 C H 4 D H 4 E H 4 F H 5 0 H 5 1 H 5 2 H 5 3 H 5 4 H 5 5 H 5 6 H 5 7 H 5 8 H 5 9 H 5 A H 5 B H 5 C H 5 D H 5 E H 5 F H 6 0 H 6 1 H 6 2 H 6 3 H 6 4 H 6 5 H 6 6 H 6 7 H 6 8 H 6 9 H 6 A H 6 B H 6 C H 6 D H 6 E H 6 F H 7 0 H 7 1 H 7 2 H 7 3 H 7 4 H 7 5 H 7 6 H 7 7 H 7 8 H 7 9 H 7 A H 7 B H 7 C H 7 D H 7 E H 7 F H E E A E E D T M P C 0 T M P C 1 P R M 0 P R M 1 P R M 2 T M 1 C 0 T M 1 C 1 T M 1 C 2 T M 1 D L T M 1 D H T M 1 A L T M 1 A H T M 1 B L T M 1 B H T M 2 C 0 T M 2 C 1 T M 2 D L T M 2 D H T M 2 A L T M 2 A H T M 2 R P U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d S C O M C U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d HT66F40 Special Purpose Data Memory Rev. A A A U 2 B a n k 1 D C R 0 D C R 1 C E R L n u s e d C P 0 C C P 1 C S IM C 0 S IM C 1 S IM D S IM A /S IM C 2 T M 0 C 0 T M 0 C 1 T M 0 D L T M 0 D H T M 0 A L T M 0 A H U n u s e d E E C E E A E E D T M P C 0 U n u s e d P R M 0 U n u s e d U n u s e d T M 1 C 0 T M 1 C 1 T M 1 C 2 T M 1 D L T M 1 D H T M 1 A L T M 1 A H T M 1 B L T M 1 B H U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d S C O M C U n u s e d k 0 . 2 R 0 P 0 R 1 P 1 B P A C C P C L T B L P T B L H T B H P S T A T U S S M O D L V D C IN T E G W D T C T B C IN T C 0 IN T C 1 IN T C 2 U n u s e d M F I0 M F I1 M F I2 U n u s e d P A W U P A P U P A P A C P B P U P B P B C P C P U P C P C C U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d A D R L A D R H B a n k 0 . 1 .

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
0 , 1 , 2 R 0 P 0 R 1 P 1 B P A C C P C L T B L P T B L H T B H P S T A T U S S M O D L V D C IN T E G W D T C T B C IN T C 0 IN T C 1 IN T C 2 U n u s e d M F I0 M F I1 M F I2 M F I3 P A W U P A P U P A P A C P B P U P B P B C P C P U P C P C C P D P U P D P D C P E P U P E P E C P F P U P F P F C U n u s e d U n u s e d U n u s e d A D R L A D R H A D C R 0 A D C R 1 A C E R L U n u s e d C P 0 C C P 1 C S IM C 0 S IM C 1 S IM D S IM A /S IM C 2 T M 0 C 0 T M 0 C 1 T M 0 D L T M 0 D H T M 0 A L T M 0 A H B a n k IA M IA M B a n k 0 , 2 B a n k 1 U n u s e d E E C E E A E E D T M P C 0 T M P C 1 P R M 0 P R M 1 P R M 2 T M 1 C 0 T M 1 C 1 T M 1 C 2 T M 1 D L T M 1 D H T M 1 A L T M 1 A H T M 1 B L T M 1 B H T M 2 C 0 T M 2 C 1 T M 2 D L T M 2 D H T M 2 A L T M 2 A H T M 2 R P T M 3 C 0 T M 3 C 1 T M 3 D L T M 3 D H T M 3 A L T M 3 A H S C O M C U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d B a n k 0 , 1 , 2 , 3 , 4 IA R 0 M P 0 IA R 1 M P 1 B P A C C P C L T B L P T B L H T B H P S T A T U S S M O D L V D C IN T E G W D T C T B C IN T C 0 IN T C 1 IN T C 2 IN T C 3 M F I0 M F I1 M F I2 M F I3 P A W U P A P U P A P A C P B P U P B P B C P C P U P C P C C P D P U P D P D C P E P U P E P E C P F P U P F P F C P G P U P G P G C A D R L A D R H A D C R 0 A D C R 1 A C E R L A C E R H C P 0 C C P 1 C S IM C 0 S IM C 1 S IM D S IM A /S IM C 2 T M 0 C 0 T M 0 C 1 T M 0 D L T M 0 D H T M 0 A L T M 0 A H B a n k 0 , 2 , 3 , 4 B a n k 1 U n u s e d E E C E E A E E D T M P C 0 T M P C 1 P R M 0 P R M 1 P R M 2 T M 1 C 0 T M 1 C 1 T M 1 C 2 T M 1 D L T M 1 D H T M 1 A L T M 1 A H T M 1 B L T M 1 B H T M 2 C 0 T M 2 C 1 T M 2 D L T M 2 D H T M 2 A L T M 2 A H T M 2 R P T M 3 C 0 T M 3 C 1 T M 3 D L T M 3 D H T M 3 A L T M 3 A H S C O M C U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d U n u s e d

0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H 3 A H 3 B H 3 C H 3 D H 3 E H 3 F H

4 0 H 4 1 H 4 2 H 4 3 H 4 4 H 4 5 H 4 6 H 4 7 H 4 8 H 4 9 H 4 A H 4 B H 4 C H 4 D H 4 E H 4 F H 5 0 H 5 1 H 5 2 H 5 3 H 5 4 H 5 5 H 5 6 H 5 7 H 5 8 H 5 9 H 5 A H 5 B H 5 C H 5 D H 5 E H 5 F H 6 0 H 6 1 H 6 2 H 6 3 H 6 4 H 6 5 H 6 6 H 6 7 H 6 8 H 6 9 H 6 A H 6 B H 6 C H 6 D H 6 E H 6 F H 7 0 H 7 1 H 7 2 H 7 3 H 7 4 H 7 5 H 7 6 H 7 7 H 7 8 H 7 9 H 7 A H 7 B H 7 C H 7 D H 7 E H 7 F H

0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H 3 A H 3 B H 3 C H 3 D H 3 E H 3 F H

4 0 H 4 1 H 4 2 H 4 3 H 4 4 H 4 5 H 4 6 H 4 7 H 4 8 H 4 9 H 4 A H 4 B H 4 C H 4 D H 4 E H 4 F H 5 0 H 5 1 H 5 2 H 5 3 H 5 4 H 5 5 H 5 6 H 5 7 H 5 8 H 5 9 H 5 A H 5 B H 5 C H 5 D H 5 E H 5 F H 6 0 H 6 1 H 6 2 H 6 3 H 6 4 H 6 5 H 6 6 H 6 7 H 6 8 H 6 9 H 6 A H 6 B H 6 C H 6 D H 6 E H 6 F H 7 0 H 7 1 H 7 2 H 7 3 H 7 4 H 7 5 H 7 6 H 7 7 H 7 8 H 7 9 H 7 A H 7 B H 7 C H 7 D H 7 E H 7 F H

HT66F50 Special Purpose Data Memory

HT66F60 Special Purpose Data Memory

Rev. 1.30

25

October 4, 2010

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into several banks, the structure of which depends upon the device chosen. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation. Memory Pointers - MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. Note that for the HT66F20 and HT66F30 devices, bit 7 of the Memory Pointers is not required to address the full memory space. When bit 7 of the Memory Pointers for HT66F20 and HT66F30 devices is read, a value of ²1² will be returned. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4.

Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a

· Indirect Addressing Program Example

data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ¢code¢ org 00h start: mov a,04h mov block,a mov a,offset adres1 mov mp0,a loop: clr inc sdz jmp IAR0 mp0 block loop ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared

continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.

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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
Bank Pointer - BP Depending upon which device is used, the Program and Data Memory are divided into several banks. Selecting the required Program and Data Memory area is achieved using the Bank Pointer. Bit 5 of the Bank Pointer is used to select Program Memory Bank 0 or 1, while bits 0~2 are used to select Data Memory Banks 0~4. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming.

Device HT66F20 HT66F40 HT66F30 HT66F50 HT66F60

Bit 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ PMBP0 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ DMBP2 1 ¾ DMBP1 DMBP1 0 DMBP0 DMBP0 DMBP0

BP Registers List
· BP Register
¨

HT66F20/HT66F40 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 ¾ ¾ ¾ 0 DMBP0 R/W 0

Bit 7 ~ 1 Bit 0

Unimplemented, read as ²0² DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1

¨

HT66F30/HT66F50 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 DMBP1 R/W 0 0 DMBP0 R/W 0

Bit 7 ~ 2 Bit 1 ~ 0

Unimplemented, read as ²0² DMBP1, DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Undefined

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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨

HT66F60 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 PMBP0 R/W 0 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 DMBP2 R/W 0 1 DMBP1 R/W 0 0 DMBP0 R/W 0

Bit 7 ~ 6 Bit 5

Unimplemented, read as ²0² PMBP0: Select Program Memory Banks 0: Bank 0, Program Memory Address is from 0000H ~ 1FFFH 1: Bank 1, Program Memory Address is from 2000H ~ 2FFFH Unimplemented, read as ²0² DMBP2 ~ DMBP0: Select Data Memory Banks 000: Bank 0 001: Bank 1 010: Bank 2 011: Bank 3 100: Bank 4 101~111: Undefined

Bit 4 ~ 3 Bit 2 ~ 0

Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, Rev. 1.30 28

for example using the ²INC² or ²DEC² instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
· C is set if an operation results in a carry during an ad-

dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the

low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

October 4, 2010

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
· Z is set if the result of an arithmetic or logical operation

is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-

est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the

In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.
· TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.

· STATUS Register

Bit Name R/W POR Bit 7, 6 Bit 5

7 ¾ ¾ ¾

6 ¾ ¾ ¾

5 TO R 0

4 PDF R 0

3 OV R/W x

2 Z R/W x

1 AC R/W x

0 C R/W x
²x² unknown

Bit 4

Bit 3

Bit 2

Bit 1

Unimplemented, read as ²0² TO: Watchdog Time-Out flag 0: After power up or executing the ²CLR WDT² or ²HALT² instruction 1: A watchdog time-out occurred. PDF: Power down flag 0: After power up or executing the ²CLR WDT² instruction 1: By executing the ²HALT² instruction OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction.

Bit 0

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according to the device selected. As both the EEA and EED registers are located in Bank 0. EED and a single control register.30 30 October 4. The EEC register however. specific user data. with data retention even when its power supply is removed. By incorporating this kind of data memory. the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register. EEPROM Data Memory Structure The EEPROM Data Memory capacity varies from 32x8 to 256´8 bits. 01H. is by its nature a non-volatile form of re-programmable memory. system setup data or other product information to be stored directly within the product microcontroller. IAR1. EEPROM. calibration values. BP. the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 EEPROM Data Memory The device contains an area of internal EEPROM Data Memory. being located in Bank1. the data register. EEA. before any operations on the EEC register are executed. 1. cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register. which stands for Electrically Erasable Programmable Read Only Memory. a whole new host of application possibilities are made available to the designer. · EEPROM Register List ¨ Device HT66F20 HT66F30 HT66F40 HT66F50/HT66F60 EEPROM Registers Capacity 32´8 64´8 128´8 256´8 Address 00H ~ 1FH 00H ~ 3FH 00H ~ 7FH 00H ~ FFH Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register. set to the value. they can be directly accessed in the same was as any other Special Function Register. Because the EEC control register is located at address 40H in Bank 1. HT66F20 Name EEA EED EEC Bit 7 ¾ D7 ¾ 6 ¾ D6 ¾ 5 ¾ D5 ¾ 4 D4 D4 ¾ 3 D3 D3 WREN 2 D2 D2 WR 1 D1 D1 RDEN 0 D0 D0 RD ¨ HT66F30 Name EEA EED EEC Bit 7 ¾ D7 ¾ 6 ¾ D6 ¾ 5 D5 D5 ¾ 4 D4 D4 ¾ 3 D3 D3 WREN 2 D2 D2 WR 1 D1 D1 RDEN 0 D0 D0 RD ¨ HT66F40 Name EEA EED EEC Bit 7 ¾ D7 ¾ 6 D6 D6 ¾ 5 D5 D5 ¾ 4 D4 D4 ¾ 3 D3 D3 WREN 2 D2 D2 WR 1 D1 D1 RDEN 0 D0 D0 RD Rev. The availability of EEPROM storage allows information such as product identification numbers. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. Unlike the Program Memory and RAM Data Memory. EEC. 2010 .

read as ²0² Data EEPROM address Data EEPROM address bit 6 ~ bit 0 ¨ HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W x 6 D6 R/W x 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Bit 7 ~ 0 Data EEPROM address Data EEPROM address bit 7 ~ bit 0 Rev.30 31 October 4. 2010 . read as ²0² Data EEPROM address Data EEPROM address bit 5 ~ bit 0 ¨ HT66F40 Bit Name R/W POR 7 ¾ ¾ ¾ 6 D6 R/W x 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Bit 7 Bit 6 ~ 0 Unimplemented. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F50/HT66F60 Name EEA EED EEC Bit 7 D7 D7 ¾ 6 D6 D6 ¾ 5 D5 D5 ¾ 4 D4 D4 ¾ 3 D3 D3 WREN 2 D2 D2 WR 1 D1 D1 RDEN 0 D0 D0 RD · EEA Register ¨ HT66F20 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Bit 7 ~ 5 Bit 4 ~ 0 Unimplemented. read as ²0² Data EEPROM address Data EEPROM address bit 4 ~ bit 0 ¨ HT66F30 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Bit 7 ~ 6 Bit 5 ~ 0 Unimplemented.

2010 . after which the data can be read from the EED register. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. Writing Data to the EEPROM To write data to the EEPROM. read as ²0² WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Setting this bit high will have no effect if the WREN has not first been set high. If the WR bit in the EEC register is now set high. Clearing this bit to zero will inhibit Data EEPROM read operations. When the write cycle terminates. the WR bit will be automatically cleared to zero by the microcontroller. Bit 0 RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. a read cycle will be initiated. The EEPROM address of the data to be read must then be placed in the EEA register. When the read cycle terminates. Note: The WREN. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · EEC Register Bit Name R/W POR Bit 7 ~ 4 Bit 3 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 WREN R/W 0 2 WR R/W 0 1 RDEN R/W 0 0 RD R/W 0 Unimplemented. The EEPROM address of the data to be written must then be placed in the EEA regis- ter and the data placed in the EED register. a certain time will elapse before the data will have been written into the EEPROM. If the RD bit in the EEC register is now set high. the read enable bit. The data will remain in the EED register until another read or write operation is executed. Rev. Setting this bit high will have no effect if the RDEN has not first been set high. The WR and RD can not be set to ²1² at the same time. WR. 1. informing the user that the data has been written to the EEPROM. the write enable bit. Clearing this bit to zero will inhibit Data EEPROM write operations. RDEN. The application program can therefore poll the WR bit to determine when the write cycle has ended. This bit will be automatically reset to zero by the hardware after the read cycle has finished. The application program can poll the RD bit to determine when the data is valid for reading. in the EEC register must first be set high to enable the write function. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. in the EEC register must first be set high to enable the read function. an internal write cycle will then be initiated. Bit 2 WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. Reading Data from the EEPROM To read data from the EEPROM. As the EEPROM write cycle is controlled using an internal t i m e r w h o se o p e r a t i o n i s a syn ch r o n o u s t o microcontroller system clock. the RD bit will be automatically cleared to zero. RDEN and RD can not be set to ²1² at the same time in one instruction. WREN.30 32 October 4. This bit will be automatically reset to zero by the hardware after the write cycle has finished.

If the global. · Programming Examples ¨ Reading data from the EEPROM . A SET IAR1. A . A SET IAR1.0 BACK: SZ IAR1. check for read cycle end . this adds a further measure of protection against spurious write operations. A MOV A. 040H MOV MP1. More details can be obtained in the Interrupt section. enable write operations SET IAR1. start Write Cycle . Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. A MOV A.polling method MOV A. setup memory pointer MP1 MOV MP1. EEPROM Interrupt The EEPROM write or read interrupt is generated when an EEPROM write or read cycle has ended. a jump to the associated Multi-function Interrupt vector will take place. setup Bank Pointer MOV BP.30 33 October 4.1 SET IAR1. Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. check for write cycle end JMP BACK CLR IAR1 . 1. setup Bank Pointer . After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. 01H . A .0 JMP BACK CLR IAR1 CLR BP MOV A. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. 2010 . setup memory pointer MP1 .set WR bit BACK: SZ IAR1. disable EEPROM read/write . EEPROM_DATA . When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset. EEPROM_ADRES . EEDATA MOV READ_DATA.2 . which means that Data Memory Bank 0 will be selected. user defined data MOV EED. MP1 points to EEC register MOV A. the DEF request flag and its associated multi-function interrupt request flag will both be set. ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. Although certainly not necessary. user defined address MOV EEA. A MOV A. the associated multi-function interrupt enable bit must also be set. EEPROM and Multi-function interrupts are enabled and the stack is not full. the EEPROM interrupt flag must be manually reset by the application program. When an EEPROM write cycle ends. During normal program operation. set WREN bit. user defined address . consideration might be given in the application program to the checking of the validity of new write data by a simple read back process.polling method MOV A. 01H MOV BP. will be reset to zero. disable EEPROM read/write CLR BP Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Write Protection Protection against inadvertent write operation is provided in several ways. A MOV A.2 . EEPROM_ADRES MOV EEA.3 . Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. 040H . enable read operations . Also at power-on the Bank Pointer. set RDEN bit. However as the EEPROM is contained within a Multi-function Interrupt. start Read Cycle . move read data to register ¨ Writing Data to the EEPROM . BP. As the EEPROM control register is located in Bank 1. MP1 points to EEC register .set RD bit .

The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements.30 34 October 4. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. CKS2~CKS0 bits fSY S fS UB Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only) System Clock Configurations Rev. external RC network oscillator and the internal 4MHz. External oscillators requiring some external components as well as fully integrated internal oscillators. are provided to form a wide range of both fast and slow system oscillators. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected. High Speed Oscillation HXT ERC HIRC High Speed Oscillation Configuration Option Low Speed Oscillation LIRC fH 6-stage Prescaler f H/2 fH /4 fH/8 fH/16 f H/32 fH/64 fL LXT Low Speed Oscillation Configuration Option HLCLK. the device has the flexibility to optimize the performance/power ratio. 2010 . All oscillator options are selected through the configuration options. while the opposite is of course true for the lower frequency oscillators. 8MHz or 12MHz RC oscillator. 8 or 12MHz 32. a feature especially important in power sensitive portable applications. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. 400kHz~ 20MHz 8MHz 4. The two low speed oscillators are the internal 32kHz RC oscillator and the external 32. Type External Crystal External RC Internal High Speed RC External Low Speed Crystal Internal Low Speed RC Name HXT ERC HIRC LXT LIRC Freq. requiring no external components. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts.768kHz 32kHz Pins OSC1/ OSC2 OSC1 ¾ XT1/ XT2 ¾ Oscillator Types System Clock Configurations There are five methods of generating the system clock. three high speed oscillators and two low speed oscillators. The high speed oscillators are the external crystal/ ceramic oscillator. Oscillator selections and operation are selected through a combination of configuration options and registers.768kHz crystal oscillator. With the capability of dynamically switching between fast and slow system clock.

768kHz Crystal Oscillator . As a resistance/frequency reference point. 8MHz or 12MHz will have a tolerance within 2%. C 1 a n d C 2 a r e r e q u ir e d . Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. which is selected via configuration option.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 The actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. 2010 Crystal/Resonator Oscillator . For most crystal oscillator configurations. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register. with a value between 56kW and 2. Internal RC Oscillator . which is shared with I/O pin PB1. the external capacitor has no influence over the frequency and is connected for stability purposes only. leaving pin PB2 free for use as a normal I/O pin. The internal RC oscillator has three fixed frequencies of either 4MHz. 8MHz or 12MHz. External 32. R p is n o r m a lly n o t r e q u ir e d . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F . to ensure oscillation. which is selected via configuration option. Using a ceramic resonator will usually require two small value capacitors. for some crystal types and frequencies. 2 . It is only the external resistor that de- Rev. as it requires no external pins for its operation.768kHz crystal are necessary to provide oscillation. As a result. these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. without requiring external capacitors. and a capacitor is connected between OSC1 and ground.ERC Using the ERC oscillator only requires that a resistor. Note that if this internal system clock option is selected.HXT The External Crystal/ Ceramic System Oscillator is one of the high frequency oscillator choices.768kHz crystal to be connected between pins XT1 and XT2.30 .4MW. C 1 R p O S C 1 R f In te r n a l O s c illa to r C ir c u it termines the oscillation frequency. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. the oscillator will have a frequency of 8MHz within a tolerance of 2%. I/O pins PB1 and PB2 are free for use as normal I/O pins.HXT Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz 8MHz 4MHz 1MHz Note: C1 0pF 0pF 0pF 100pF C2 0pF 0pF 0pF 100pF C1 and C2 values are for guidance only. 35 October 4. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer¢s specification. Here only the OSC1 pin is used. Crystal Recommended Capacitor Values External RC Oscillator . C1 and C2. is connected between OSC1 and VDD. However. This clock source has a fixed frequency of 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices. it can be noted that with an external 120kW resistor connected and with a 5V voltage power supply and temperature of 25°C degrees. 1. For applications where precise frequencies are essential. C1 and C2.HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. it may be necessary to add two small value capacitors. the fixed oscillation frequency of 4MHz. the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation. to be connected as shown for oscillation to occur.768kHz and requires a 32. temperature and process variations on the oscillation frequency are minimised. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage. External RC Oscillator .LXT The External 32. External Crystal/ Ceramic Oscillator . at a power supply of either 3V or V D D R O S C 2 T o in te r n a l c ir c u its O S C O S C 1 4 7 0 p F C 2 N o te : 1 . temperature and process variations on the oscillation frequency are minimised.ERC 5V and at a temperature of 25°C degrees. providing a low cost oscillator configuration. The external resistor and capacitor components connected to the 32.

In power sensitive applications. in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. C 1 a n d C 2 a r e r e q u ir e d . N o te : 1 . C1 and C2. 2 . 1.7 6 8 k H z X T 2 C 2 X T 1 In te r n a l O s c illa to r C ir c u it In te rn a l R C O s c illa to r T o in te r n a l c ir c u its After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. the only difference is that it will take more time to start up if in the Low-power mode. after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. the LXT oscillator will always function normally.768kHz Note: C1 10pF C2 10pF 1. 2010 . It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V. for some crystals.LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices. where power consumption must be kept to a minimum. C1 and C2 values are for guidance only. the Quick Start Mode and the Low Power Mode. requiring no external components for its implementation. no matter what condition the LXTLP bit is set to. independent of the system clock. Supplementary Oscillators The low speed oscillators. to ensure oscillation and accurate frequency generation. the system clock is switched off to stop microcontroller activity and to conserve power.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 When the microcontroller enters the SLEEP or IDLE Mode. The mode selection is executed using the LXTLP bit in the TBC register. · If the LXT oscillator is used for any clock source. 32. The external parallel feedback resistor. · If the LXT oscillator is not used for any clock source. the 32. is required. it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. at a power supply of 5V and at a temperature of 25°C degrees. To do this. as the higher current consumption is only required during the LXT oscillator start-up. which is selected via configuration option. It should be noted that. However. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage. The oscillator will continue to run but with reduced current consumption. Internal 32kHz Oscillator . However. However. in addition to providing a system clock source are also used to provide a clock source to two other device functions. another clock. it is necessary to add two small value external capacitors. LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes.30 36 October 4. 2. LXTLP Bit 0 1 LXT Mode Quick Start Low-power the XT1/XT2 pins can be used as normal I/O pins.768kHz Crystal Recommended Capacitor Values Rev. C 1 R p 3 2 . the fixed oscillation frequency of 32kHz will have a tolerance within 10%. temperature and process variations on the oscillation frequency are minimised. RP=5M~10MW is recommended. These are the Watchdog Timer and the Time Base Interrupts. As a result.768kHz crystal should be connected to the XT1/XT2 pins. Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. must be provided. A lth o u g h n o t s h o w n p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F . such as battery applications. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer¢s specification. R p . Rp. External LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency 32.

ERC or HIRC oscillator. or low frequency. can come from either a high frequency. The low speed system clock source can be sourced from internal clock fL. CKS2~CKS0 bits fS YS fSUB Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only) fTB C fTB fSYS /4 TBCK Time Base fS UB fS fSYS/ 4 Configuration Option WDT System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH. 1. selected via a configuration option. fL. the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. conflicting requirements that are especially true in battery powered portable applications. source. 37 October 4. and the Time Base clock. By providing the user with a wide range of clock options using configuration options and register programming. fTBC. High Speed Oscillation HXT ERC HIRC High Speed Oscillation Configuration Option Low Speed Oscillation LIRC The main system clock. The other choice. There are two additional internal clocks for the peripheral circuits.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Operating Modes and System Clocks P re s e n t d a y appl i c a t i ons r equi r e t ha t t h e i r microcontrollers have high performance but often still demand that they consume as little power as possible. The high speed system clock can be sourced from either an HXT. and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. selected via a configuration option. The fSUB clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. If fL is selected then it can be sourced by either the LXT or LIRC oscillators. fH. selected via configuration options. a clock system can be configured to obtain maximum application performance. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa. lower speed clocks reduce current consumption. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. the high speed oscillation will stop to conserve the power. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically. Thus there is no fH~fH/64 for peripheral circuit to use.30 . the substitute clock. fH 6-stage Prescaler fH /2 fH /4 fH/8 fH/16 f H/32 fH /64 fL LXT Low Speed Oscillation Configuration Option HLCLK. 2010 Rev. which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Each of these internal clocks are sourced by either the LXT or LIRC oscillators. fSUB.

and this system oscillator may be high speed or low speed system oscillator. and the fSUB and fS clocks will be stopped too. Although a high speed oscillator is used. In the IDLE0 Mode the Watchdog Timer clock. The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. The fTBC clock is used as a source for the Time Base interrupt functions and for the TMs. either the HXT. TMs and SIM. the system oscillator will be stopped.30 38 October 4. it won¢t enter the SLEEP0 Mode. If the source is fSYS/4 then the fS clock will be on. Description Operation Mode CPU NORMAL Mode SLOW Mode IDLE0 Mode IDLE1 Mode SLEEP0 Mode SLEEP1 Mode On On Off Off Off Off fSYS fH~ fH/64 fL Off On Off Off fSUB On On On On Off On fS On On On/Off On Off On fTBC On On On On Off Off · NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. However the fSUB and fS clocks will continue Rev. IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. In the SLOW Mode. · IDLE0 Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. · SLEEP0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is low. If the LVDEN is set to ²1². This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer. the LVDEN is must set to ²0². fS. TMs and SIM. Running the microcontroller in this mode allows it to run with much lower operating currents. the actual ratio being selected by the CKS2~LCKS0 and HLCLK bits in the SMOD register. The remaining four modes. will be on. In the IDLE1 Mode. 2010 . If the source is fSYS/4 then the fS clock will be off. the SLEEP0. · SLEEP1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is high. In the SLEEP1 mode the CPU will be stopped. 1. fS. In the IDLE0 Mode. In this mode. the fH is off. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer. running the microcontroller at a divided clock ratio reduces the operating current. System Operation Modes There are six different modes of operation for the microcontroller.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Together with fSYS/4 it is also used as one of the clock sources for the Watchdog timer. will either be on or off depending upon the fS clock source. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64. and if the source comes from fSUB then fS will be on. · SLOW Mode to operate if the LVDEN is ²1² or the Watchdog Timer function is enabled and if its clock source is chosen via configuration option to come from the fSUB. the system oscillator will continue to run. and the Watchdog Timer function is disabled. In the IDLE1 Mode the Watchdog Timer clock. and if the source comes from fSUB then fS will be on. The clock source used will be from one of the low speed oscillators. either the LXT or the LIRC. SLEEP1. the NORMAL Mode and SLOW Mode. There are two modes allowing normal operation of the microcontroller. each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. In the SLEEP0 mode the CPU will be stopped. ERC or HIRC oscillators. · IDLE1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low.

The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Control Register A single register. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. · SMOD Register Bit Name R/W POR Bit 7~5 7 CKS2 R/W 0 6 CKS1 R/W 0 5 CKS0 R/W 0 4 FSTEN R/W 0 3 LTO R 0 2 HTO R 0 1 IDLEN R/W 1 0 HLCLK R/W 1 CKS2~CKS0: The system clock selection when HLCLK is ²0² 000: fL (fLXT or fLIRC) 001: fL (fLXT or fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used after the device wakes up. the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator is used. which can be either the LXT or LIRC.30 . If FSYSON bit is low. LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. If this bit is high. if FSYSON bit is high. SMOD. a divided version of the high speed system oscillator can also be chosen as the system clock source. IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. Therefore this flag will always be read as ²1² by the application program after device power-on. 39 October 4. when a HALT instruction is executed the device will enter the IDLE Mode. When the bit is high. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will be selected. In addition to the system clock source. is used for overall control of the internal clocks within the device. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational. the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. This flag is cleared to ²0² by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. the CPU and the system clock will all stop in IDLE0 mode. 2010 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. HLCLK: system clock selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock. the flag will change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred.

The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. stabilise and allow normal operation to resume. to act as a temporary clock to first drive the system until the original system oscillator has stabilised. If the HXT oscillator is selected as the NORMAL Mode system clock. System Oscillator FSTEN Bit 0 Wake-up Time (SLEEP0 Mode) 1024 HXT cycles 1024 HXT cycles 15~16 ERC cycles 15~16 HIRC cycles 1~2 LIRC cycles 1024 LTX cycles Wake-up Time (SLEEP1 Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) 1~2 HXT cycles 1~2 HXT cycles 1~2 ERC cycles 1~2 HIRC cycles 1~2 LIRC cycles 1~2 LXT cycles 1024 HXT cycles 1~2 fSUB cycles (System runs with fSUB first for 1024 HXT cycles and then switches over to run with the HXT clock) 15~16 ERC cycles 15~16 HIRC cycles 1~2 LIRC cycles 1024 LXT cycles Wake-Up Times HXT 1 X X X X ERC HIRC LIRC LXT Note that if the Watchdog Timer is disabled. it can take a considerable time for the original system oscillator to restart. FSTEN will have no effect in these cases. and if the Fast Wake-up function is enabled. which allows fSUB. When the device is woken up from the SLEEP0 mode. If the ERC or HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the ERC or HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode.30 40 October 4. then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for the system to wake-up. The system will then initially run under the fSUB clock source until 1024 HXT clock cycles have elapsed. then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode. As the clock source for the Fast Wake-up function is fSUB. the Fast Wake-up function has no effect because the fSUB clock is stopped. where the system clock source to the device will be stopped. The Fast Wake-up bit. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode. 2010 . To ensure the device is up and running as fast as possible a Fast Wake-up function is provided. namely either the LXT or LIRC oscillator. fS N O R M A L Y S = f H ~ f H / 6 4 fH o n C P U ru n fS Y S o n fT B C o n fS U B o n ID L E 1 H A L T in s tr u c tio n is e x e c u te d C P U s to p ID L E N = 1 F S Y S O N = 1 fS Y S o n fT B C o n fS U B o n S L E E P 0 H A L T in s tr u c tio n is e x e c u te d fS Y S o ff C P U s to p ID L E N = 0 fT B C o ff fS U B o ff W D T & L V D o ff ID L E 0 H A L T in s tr u c tio n is e x e c u te d C P U s to p ID L E N = 1 F S Y S O N = 0 fS Y S o ff fT B C o n fS U B o n S L E E P 1 H A L T in s tr u c tio n is e x e c u te d fS Y S o ff C P U s to p ID L E N = 0 fT B C o ff fS U B o n W D T o r L V D o n S L O W fS Y S = fL fL o n C P U ru n fS Y S o n fT B C o n fS U B o n fH o ff Rev. However when the device is woken up again. the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. which means that the LXT and LIRC are all both off. at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator.

which implies that clock source is switched from the high speed clock source. fH/2~fH/64 or fL. 2010 . Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. This is monitored using the LTO bit in the SMOD register. which uses the high speed system oscillator. the high speed clock source will stop running to conserve power. 1. to the clock source. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d ID E L 0 M o d e ID L E N = 1 . F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e Rev. When a HALT instruction is executed. N O R M A L M o d e C K S 2 ~ C K S 0 = 0 0 x B & H L C L K = 0 S L O W M o d e W D T a n d L V D a r e a ll o ff ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d S L E E P 0 M o d e W D T o r L V D is o n ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d S L E E P 1 M o d e ID L E N = 1 . and therefore consumes more power. If the clock is from the fL. fH. whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register.30 41 October 4. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. In simple terms. the system clock can switch to run in the SLOW Mode by set the HLCLK bit to ²0² and set the CKS2~CKS0 bits to ²000² or ²001² in the SMOD register. This will then use the low speed system oscillator which will consume less power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Operating Mode Switching and Wake-up The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. The accompanying flowchart shows what happens when the device moves between the various operating modes. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. When the HLCLK bit switches to a low level. NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode. which may affect the operation of other internal functions such as the TMs and the SIM.

WDT clock and Time Base clock will be stopped and the application program will stop at the ²HALT² instruction. Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in SMOD register equal to ²0² and the WDT and LVD both off. To switch back to the NORMAL Mode. but CKS2~CKS0 is set to ²010². where the high speed system oscillator is used. ²011². ²100². the following will occur: · The system clock. F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. the status of the HTO bit is checked. ²101². As a certain amount of time will be required for the high frequency clock to stabilise. When this instruction is executed under the conditions described above. Rev. 1. 0 0 1 B a s H L C L K = 0 o r H L C L K = 1 N O R M A L M o d e W D T a n d L V D a r e a ll o ff ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d S L E E P 0 M o d e W D T o r L V D is o n ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d S L E E P 1 M o d e ID L E N = 1 . will be cleared. · In the status register. will be set and the Watchdog time-out flag. the Power Down flag. 2010 . ²110² or ²111².30 42 October 4. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. · The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB clock or from the system clock.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 S L O W M o d e C K S 2 ~ C K S 0 ¹ 0 0 0 B . · The Data Memory contents and registers will maintain their present condition. · The I/O ports will maintain their present conditions. PDF. F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d ID L E 0 M o d e ID L E N = 1 . the HLCLK bit should be set to ²1² or HLCLK bit is ²0². TO.

the Power Down flag.30 43 October 4. When this instruction is executed under the with conditions described above. will be set and the Watchdog time-out flag. such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LXT or LIRC oscillator. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible. 2010 . 1. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current. · The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock as the WDT is enabled. Rev. · The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock and the WDT is enabled. will WDT is enabled regardless of the WDT clock source which originates from the fSUB clock or from the system clock. PDF. PDF. · The Data Memory contents and registers will maintain will be on and the application program will stop at the ²HALT² instruction. will be cleared. · The I/O ports will maintain their present conditions. the following will occur: · The system clock will be stopped and the application be set and the Watchdog time-out flag. TO. · In the status register. as there may be unbonbed pins. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in SMOD register equal to ²1² and the FSYSON bit in WDTC register equal to ²0². which are setup as outputs.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in SMOD register equal to ²0² and the WDT or LVD on. will be cleared. perhaps only in the order of several micro-amps except in the IDLE1 Mode. · In the status register. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. · The Data Memory contents and registers will maintain their present condition. the additional standby current will also be perhaps in the order of several hundred micro-amps program will stop at the ²HALT² instruction. In the IDLE1 Mode the system oscillator is on. This also applies to devices which have different package types. PDF. · In the status register. which are connected to I/O pins. Special attention must be made to the I/O pins on the device. the following will occur: · The system clock and Time Base clock will be Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in SMOD register equal to ²1² and the FSYSON bit in WDTC register equal to ²1². TO. there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. the following will occur: · The system clock and Time Base clock and fSUB clock stopped and the application program will stop at the ²HALT² instruction. but the WDT or LVD will remain with the clock source coming from the fSUB clock. When this instruction is executed under the conditions described above. · The I/O ports will maintain their present conditions. · The WDT will be cleared and resume counting if the their present condition. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. the Power Down flag. TO. Care must also be taken with the loads. the Power Down flag. The WDT will stop if its clock source originates from the system clock. · The I/O ports will maintain their present conditions. will be cleared. · The Data Memory contents and registers will maintain their present condition. When this instruction is executed under the conditions described above. will be set and the Watchdog time-out flag. but the Time Base clock and fSUB clock will be on. if the system oscillator is from the high speed system oscillator.

The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the ²HALT² instruction. a Watchdog Timer reset will be initiated. the system clock can be switched to the LXT or LIRC oscillator after wake up. 2010 . If the system clock source is switched from fH to fL. such as WDT. At this time. if the device is woken up by a WDT overflow. When a Port A pin wake-up occurs.30 44 October 4. The same situation occurs in the power-on state. In this situation. the NORMAL Mode. then two possible situations may occur. if the system is woken up from the SLEEP0 Mode and both the HXT and LXT oscillators need to start-up from an off state. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full. in which case the regular interrupt response takes place. in which case the program will resume execution at the instruction following the ²HALT² instruction. it can be woken up from one of various sources listed as follows: · An external reset · An external falling edge on Port A · A system interrupt · A WDT overflow Programming Considerations The HXT and LXT oscillators both use the same SST counter. · If the device is woken up from the SLEEP1 Mode to NORMAL Mode. the wake-up function of the related interrupt will be disabled. The LXT oscillator uses the SST counter after HXT oscillator has finished its SST period. and the system clock source is from HXT oscillator and FSTEN is ²1². · There are peripheral functions. · The on/off condition of fSUB and fS depends upon whether the WDT is enabled or disabled as the WDT clock source is selected from fSUB. 1. If the system is woken up by an interrupt. for which the fSYS is used. but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the interrupt which woke-up the device will not be immediately serviced. Rev. the device will experience a full system reset. The LXT oscillator is not ready yet when the first instruction is executed. The TO flag is set if a WDT time-out occurs. the actual source of the wake-up can be determined by examining the TO and PDF flags.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Wake-up After the system enters the SLEEP or IDLE Mode. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. the LXT oscillator may not be stability if fSUB is from LXT oscillator. the high speed system oscillator needs an SST period. Although both of these wake-up methods will initiate a reset operation. · If the device is woken up from the SLEEP0 Mode to If the system is woken up by an external reset. the other flags remain in their original status. however. and causes a wake-up that only resets the Program Counter and Stack Pointer. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode. The device will execute first instruction after HTO is ²1². the program will resume execution at the instruction following the ²HALT² instruction. the clock source to the peripheral functions mentioned above will change accordingly. TMs and SIM. For example. The other situation is where the related interrupt is enabled and the stack is not full.

WS0 : WDT time-out period selection 000: 256/fS 001: 512/fS 010: 1024/fS 011: 2048/fS 100: 4096/fS 101: 8192/fS 110: 16384/fS 111: 32768/fS These three bits determine the division ratio of the Watchdog Timer source clock. However. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts. due to certain uncontrollable external events such as electrical noise. controls the required timeout period as well as the enable/disable operation. WDTEN1. WDTC. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock. fS. · WDTC Register Bit Name R/W POR Bit 7 7 FSYSON R/W 0 6 WS2 R/W 1 5 WS1 R/W 1 4 WS0 R/W 1 3 WDTEN3 R/W 1 2 WDTEN2 R/W 0 1 WDTEN1 R/W 1 0 WDTEN0 R/W 0 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable WS2. WDTEN2. The other Watchdog Timer clock source option is the fSYS/4 clock. WS1. 1. The fSUB clock can be sourced from either the LXT or LIRC oscillators. which in turn determines the timeout period. The Watchdog Timer clock source can originate from its own internal LIRC oscillator. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V.768kHz crystal. 2010 . again chosen via a configuration option. the LXT oscillator or fSYS/4. temperature and process variations. It is divided by a value of 28 to 215.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations. This register together with several configuration options control the overall operation of the Watchdog Timer. the actual value being chosen using the WS2~WS0 bits in the WDTC register. using the WS2~WS0 bits in the WDTC register to obtain the required Watchdog Timer time-out period. Bit 6 ~ 4 Bit 3 ~ 0 WDTEN3.30 45 October 4. The LXT oscillator is supplied by an external 32. which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. it should be noted that this specified internal clock period can vary with VDD. Watchdog Timer Control Register A single register. WDTEN0 : WDT Software Control 1010: Disable Other: Enable Rev.

768kHz LXT oscillator as its source clock. these clear instructions will not be executed in the correct manner. which means a low level on the RES pin. the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. then the instruction clock is stopped and the Watchdog Timer may lose its protecting purposes. then any instruction relating to its operation will result in no operation. If the fSYS/4 clock is used as the Watchdog Timer clock source. when a Watchdog Timer time-out occurs. Watchdog Timer Enable/Disable Control Under normal program operation. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. 1. such as enable/disable. using the fSUB clock source is strongly recommended. a Watchdog Timer time-out will initialise a device reset and set the status C L R C L R W D T 1 F la g W D T 2 F la g C le a r W D T T y p e C o n fig u r a tio n O p tio n C L R 8 1 o r 2 In s tr u c tio n s fS L X T M U X L IR C Y S /4 M fS U B U X fS 8 . in which case the Watchdog Timer will overflow and reset the device. If the program malfunctions for whatever reason. Note that if the Watchdog Timer has been disabled. jumps to an unkown location. this will give a maximum watchdog period of around 1 second for the 215 division ratio. the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. as well as the configuration option being set to disable. it should be noted that when the system enters the SLEEP or IDLE0 Mode. Some of the Watchdog Timer options. For systems that operate in noisy environments. in the WDTC register to offer an additional enable/disable control of the Watchdog Timer. with a 32. As an example. To disable the Watchdog Timer. if the system is in the SLEEP or IDLE Mode. For the first option. or enters an endless loop. a simple execution of ²CLR WDT² will clear the WDT while for the second option. irrespective of the configuration enable/disable setting.30 46 October 4. WDTEN3~WDTEN0. The first is an external hardware reset. This is done using the clear watchdog instructions. Three methods can be adopted to clear the contents of the Watchdog Timer. the WDTEN3~WDTEN0 bits must also be set to a specific value of ²1010². In addition to a configuration option to enable/disable the Watchdog Timer. Similarly after the ²CLR WDT2² instruction has been executed. clock source selection and clear instruction type are selected using configuration options. The first option is to use the single ²CLR WDT² instruction while the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². only a successive ²CLR WDT1² instruction can clear the Watchdog Timer.o u t (2 8 /fS ~ 2 15/fS ) Watchdog Timer Rev. Note that for this second option. Any other values for these bits will keep the Watchdog Timer enabled. However.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. only the execution of a ²CLR WDT2² instruction will clear the Watchdog Timer. successive executions of this instruction will have no effect. both ²CLR WDT1² and ²CLR WDT2² must both be executed alternately to successfully clear the Watchdog Timer. If the Watchdog Timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity.8ms for the 28 division ration. After power on these bits will have the value of 1010. 2010 . there are also four bits. if ²CLR WDT1² is used to clear the Watchdog Timer.s ta g e D iv id e r fS /2 W D T P r e s c a le r C o n fig u r a tio n O p tio n C o n fig u r a tio n O p tio n 8 -to -1 M U X W S 2 ~ W S 0 (fS /2 8 ~ fS /2 15) W D T T im e . WDT Configuration Option WDT Enable WDT Disable WDT Disable WDTEN3~ WDTEN0 Bits xxxx Except 1010 1010 WDT Enable Enable Disable bit TO. one of which must be chosen by configuration option. The maximum time out period is when the 215 division ratio is selected. There are two methods of using software instructions to clear the Watchdog Timer. and a minimum timeout of 7.

One example of this is where after power has been applied and the microcontroller is already running. the reset function must be selected using a configuration option. After this power-on reset. the internal reset function may be incapable of providing proper reset operation. the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation.0 1 m F * * 1 N 4 1 4 8 * D D V D D 1 0 k W ~ 1 0 0 k W P B 0 /R E S 3 0 0 W * 0 . which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In such a case. In addition to the power-on reset.1 ~ 1 m F V S S Note: The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. through events occurring both internally and externally: · Power-on Reset · RES Pin As the reset pin is shared with PB. t RR SS TT DD ++ t SS SS TT Note: tRSTD is power-on delay. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. the RES line is forcefully pulled low.9 V D D ²*² It is recommended that this component is added for added ESD protection ²**² It is recommended that this component is added in environments where power line noise is significant External RES Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. 2010 . some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. after a short delay. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. For this reason it is recommended that an external RC network is connected to the RES pin. where a full reset. will be in a well defined state and ready to execute the first program instruction. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.0. Reset Functions There are five ways in which a microcontroller reset can occur. Although the microcontroller has an internal RC reset function. normal operation of the microcontroller will be inhibited. if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on. As well as ensuring that the Program Memory begins execution from the first memory address.30 47 October 4. In this case. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. known as a normal operation reset. During this time delay. One of these registers is the Program Counter. V D D R E S In te rn a l R e s e t 0 . typical time=100ms Power-On Reset Timing Chart Rev. whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. All types of reset operations result in different register conditions being setup. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. After the RES line reaches a certain voltage value. The most important reset condition is after power is first applied to the microcontroller. The abbreviation SST in the figures stands for System Start-up Timer. 1. internal circuitry will ensure that the microcontroller. V 0 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. certain important internal registers will be set to defined states before the program commences. a power-on reset also ensures that certain other registers are preset to known conditions. situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. LVR. Another reset exists in the form of a Low Voltage Reset.

the LVR will automatically reset the device internally. Stack Pointer Stack Pointer will point to the top of the stack Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the W D T T im e . These flags. The LVR includes the following specifications: For a valid LVR signal. Refer to the A.o u t tS In te rn a l R e s e t S T WDT Time-out Reset during SLEEP or IDLE Timing Chart Rev. which is selected via a configuration option. L V R Note: ²u² stands for unchanged tR S T D + tS S T In te rn a l R e s e t Note: tRSTD is power-on delay.. a voltage in the range between 0.4 V 0 . the LVR will ignore it and will not perform a reset function. 2010 .9V~VLVR must exist for greater than the value tLVR specified in the A.C. tR In te rn a l R e s e t S T D + tS S T Reset Initial Conditions RES Reset Timing Chart The different types of reset described affect the reset flags in different ways. typical time=100ms WDT Time-out Reset during Normal Operation Timing Chart · Watchdog Time-out Reset during SLEEP or IDLE I/O ports will be setup as inputs. WDT begins counting Timer Counter will be turned off The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to ²1².HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pulling the RES Pin low using external hardware will also execute a device reset. If the low voltage state does not exceed tLVR. the Program Counter will reset to zero and program execution initiated from this point. One of a range of specified voltage values for VLVR can be selected using configuration options. a low voltage. such as the SLEEP or IDLE Mode function or Watchdog Timer. 1. The reset flags are shown in the table: TO PDF 0 u 1 1 0 u u 1 RESET Conditions Power-on reset RES or LVR reset during NORMAL or SLOW Mode operation WDT time-out reset during NORMAL or SLOW Mode operation WDT time-out reset during IDLE or SLEEP Mode operation Note: tRSTD is power-on delay. The tSST is 1024 clock for HXT or LXT. Note: The tSST is 15~16 clock cycles if the system clock source is provided by ERC or HIRC.LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. i. R E S 0 . as in the case of other resets. characteristics.C. Item Program Counter Interrupts WDT Timer/Event Counter Condition After RESET Reset to zero All interrupts will be disabled Clear after reset.o u t tR In te rn a l R e s e t S T D + tS S T Note: tRSTD is power-on delay.e.30 48 October 4. The tSST is 1~2 clock for LIRC. Characteristics for tSST details. known as PDF and TO are located in the status register and are controlled by various microcontroller operations. If the supply voltage of the device drops to within a range of 0.9 V D D D D Program Counter and the Stack Pointer will be cleared to ²0² and the TO flag will be set to ²1². typical time=100ms Low Voltage Reset Timing Chart · Watchdog Time-out Reset during Normal Operation The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. W D T T im e .9V~VLVR such as might occur when changing the battery. Input/Output Ports and AN0~AN11 in as A/D input pin. In this case. typical time=100ms · Low Voltage Reset .

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs.0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 --00 --00 --00 --00 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 ---.--uu --11 uuuu uuuu uuuu --uu -uuu ---.1111 xxxx ---xxxx xxxx xxxx xxxx RES or LVR Reset -xxx xxxx -xxx xxxx ---.uuuu ---.---0 uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---.0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 --00 --00 --00 --00 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 ---.uuuu uuuu ---uuuu uuuu uuuu uuuu Rev.---0 xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx ---.1111 ---.0000 ---.0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 --00 --00 --00 --00 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 ---. Note that where more than one package type exists the table will reflect the situation for the larger package type. The following table describes how each type of reset affects each of the microcontroller internal registers.0000 ---.---u uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---.30 49 October 4.1111 xxxx ---xxxx xxxx xxxx xxxx WDT Time-out (IDLE) -uuu uuuu -uuu uuuu ---. · HT66F20 Register Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG WDTC TBC INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC ADRL (ADREF=0) ADRL (ADREF=1) ADRH (ADREF=0) Reset (Power-on) -xxx xxxx -xxx xxxx ---.uuuu ---. it is important to know what condition the microcontroller is in after a particular reset occurs. 2010 .1111 ---.1111 xxxx ---xxxx xxxx xxxx xxxx WDT Time-out (Normal Operation) -xxx xxxx -xxx xxxx ---.1111 ---.0000 ---.---0 uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---.--xx --00 xxxx 0000 0011 --00 -000 ---.--uu --uu uuuu 0000 0011 --00 -000 ---.uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu --uu --uu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu --uu uuuu ---. 1.--uu --1u uuuu 0000 0011 --00 -000 ---.

--00 0000 0000 ---.--00 0000 0000 RES or LVR Reset ---.0000 --01 ---1 0000 0000 0000 0000 0000 0000 ---.xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.--uu uuuu uuuu ---. 1.--00 ---x xxxx xxxx xxxx ---.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Register ADRH (ADREF=1) ADCR0 ADCR1 ACERL CP0C CP1C SIMC0 SIMC1 SIMD SIMA/SIMC2 TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH EEA EED EEC TMPC0 TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH SCOMC Note: Reset (Power-on) ---.--00 0000 0000 WDT Time-out (IDLE) ---.--uu ---0 0000 uuuu uuuu ---.--uu uuuu uuuu ---.--00 0000 0000 ---.--00 ---x xxxx xxxx xxxx ---.xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.--00 0000 0000 ---.0000 --01 ---1 0000 0000 0000 0000 0000 0000 ---.0000 --01 ---1 0000 0000 0000 0000 0000 0000 ---. 2010 .--00 0000 0000 ---.--00 ---x xxxx xxxx xxxx ---.uuuu uuu.--00 0000 0000 ---.uuuu --uu ---u uuuu uuuu uuuu uuuu uuuu uuuu ---.xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.30 50 October 4.--00 0000 0000 WDT Time-out (Normal Operation) ---.uuuu uu-u -uuu uuuu uuuu uuuu u--u uuuu u--u uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---.--00 0000 0000 ---.--uu uuuu uuuu ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev.

uuuu uuuu -uuu uu-u -uuu uuuu uuuu uuuu u--u Rev.0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 --00 --00 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 0000 0000 1111 1111 1111 1111 xxxx ---xxxx xxxx xxxx xxxx ---.30 51 October 4.--00 uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---. 1.-uuu --1u uuuu 0000 0011 --00 -000 ---.uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu --uu --uu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu ---.xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 WDT Time-out (Normal Operation) -xxx xxxx -xxx xxxx ---.--00 xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx ---.-uuu --uu uuuu 0000 0011 --00 -000 ---.xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 WDT Time-out (IDLE) -uuu uuuu -uuu uuuu ---.--00 uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---.-xxx --00 xxxx 0000 0011 --00 -000 ---.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · HT66F30 Register Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG WDTC TBC INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC ADRL (ADREF=0) ADRL (ADREF=1) ADRH (ADREF=0) ADRH (ADREF=1) ADCR0 ADCR1 ACERL CP0C Reset (Power-on) -xxx xxxx -xxx xxxx ---.0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 --00 --00 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 0000 0000 1111 1111 1111 1111 xxxx ---xxxx xxxx xxxx xxxx ---. 2010 .0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 --00 --00 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 0000 0000 1111 1111 1111 1111 xxxx ---xxxx xxxx xxxx xxxx ---.-uuu --11 uuuu uuuu uuuu --uu -uuu ---.--uu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---.xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 RES or LVR Reset -xxx xxxx -xxx xxxx ---.

uuuu u-uu --uu ---.--uu uuuu uuuu ---.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Register CP1C SIMC0 SIMC1 SIMD SIMA/SIMC2 TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH EEA EED EEC TMPC0 PRM0 TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL TM1AH TM1BL TM1BH SCOMC Note: Reset (Power-on) 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.-000 0000 0000 0000 0000 0000 0000 0000 0000 ---.--00 0000 0000 WDT Time-out (Normal Operation) 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.--00 0000 0000 ---.--00 0000 0000 ---.--00 --xx xxxx xxxx xxxx ---.--00 0000 0000 ---.--00 0000 0000 ---.0000 1-01 --01 ---.--00 0000 0000 ---.--00 --xx xxxx xxxx xxxx ---.--uu --uu uuuu uuuu uuuu ---.--00 0000 0000 WDT Time-out (IDLE) uuuu u--u uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---.-000 0000 0000 0000 0000 0000 0000 0000 0000 ---.--00 --xx xxxx xxxx xxxx ---.--00 0000 0000 ---.--00 0000 0000 RES or LVR Reset 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.--uu uuuu uuuu ---.-uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---.--uu uuuu uuuu ---.--00 0000 0000 ---.--00 0000 0000 ---.0000 1-01 --01 ---. 2010 .--uu uuuu uuuu ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev. 1.0000 1-01 --01 ---.--00 0000 0000 ---.30 52 October 4.-000 0000 0000 0000 0000 0000 0000 0000 0000 ---.

xxxx RES or LVR Reset xxxx xxxx xxxx xxxx ---.uuuu October 4.xxxx WDT Time-out (IDLE) uuuu uuuu uuuu uuuu ---.--00 ---.uuuu --uu uuuu 0000 0011 --00 -000 ---.xxxx 53 WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx ---.0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---.---0 xxxx xxxx 0000 0000 xxxx xxxx -xxx xxxx ---.--uu ---.xxxx --00 xxxx 0000 0011 --00 -000 ---.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · HT66F40 Register Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG WDTC TBC INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC PFPU PF PFC ADRL (ADREF=0) ADRL (ADREF=1) ADRH (ADREF=0) ADRH (ADREF=1) Reset (Power-on) xxxx xxxx xxxx xxxx ---.---u uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---.---0 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---.30 . 2010 Rev.--11 ---.---0 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---.--11 xxxx ---xxxx xxxx xxxx xxxx ---.--uu uuuu ---uuuu uuuu uuuu uuuu ---.--00 ---.uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---.uuuu --11 uuuu uuuu uuuu --uu -uuu ---.--11 xxxx ---xxxx xxxx xxxx xxxx ---.--11 ---. 1.0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---.--11 xxxx ---xxxx xxxx xxxx xxxx ---.uuuu --1u uuuu 0000 0011 --00 -000 ---.--uu ---.0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---.--11 ---.--00 ---.

--uu uuuu uuuu ---.--uu -uuu uuuu uuuu uuuu ---.0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---.--uu uuuu uuuu ---.--uu uuuu u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev. 2010 .--00 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT Time-out (IDLE) uuuu -uuu uu-u -uuu uuuu uuuu uuuu u--u uuuu u--u uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---.--00 0000 0000 ---.--00 0000 0000 ---.--00 0000 0000 ---.--00 0000 0000 ---.--00 0000 0000 ---.30 54 October 4.--00 -xxx xxxx xxxx xxxx ---.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Register ADCR0 ADCR1 ACERL CP0C CP1C SIMC0 SIMC1 SIMD SIMA/SIMC2 TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH EEA EED EEC TMPC0 TMPC1 PRM0 PRM1 PRM2 TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL TM1AH TM1BL TM1BH TM2C0 TM2C1 TM2DL TM2DH TM2AL TM2AH TM2RP SCOMC Note: Reset (Power-on) 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---.--00 0000 0000 ---.--00 -xxx xxxx xxxx xxxx ---.uuuu uuuu --uu ---.--uu -u-u uuuu uuu.0000 1001 --01 ---.--01 -0-0 0000 000.0000 1001 --01 ---. 1.--00 0000 0000 ---.--00 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT Time-out (Normal Operation) 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.--00 0000 0000 ---.--01 -0-0 0000 000.--01 -0-0 0000 000.--00 -xxx xxxx xxxx xxxx ---.--uu uuuu uuuu ---.--00 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RES or LVR Reset 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---.--00 0000 0000 ---.0000 1001 --01 ---.0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---.0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
· HT66F50 Register

Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG WDTC TBC INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 MFI3 PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC PFPU

Reset (Power-on) xxxx xxxx xxxx xxxx ---- --00 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx ---x xxxx --00 xxxx 0000 0011 --00 -000 ---- 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00

RES or LVR Reset xxxx xxxx xxxx xxxx ---- --00 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---u uuuu --uu uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00

WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx ---- --00 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---u uuuu --1u uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00

WDT Time-out (IDLE) uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---u uuuu --11 uuuu uuuu uuuu --uu -uuu ---- uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu -uuu uuuu uuuu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu

Rev. 1.30

55

October 4, 2010

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
Register PF PFC ADRL (ADREF=0) ADRL (ADREF=1) ADRH (ADREF=0) ADRH (ADREF=1) ADCR0 ADCR1 ACERL CP0C CP1C SIMC0 SIMC1 SIMD SIMA/SIMC2 TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH EEA EED EEC TMPC0 TMPC1 PRM0 PRM1 PRM2 TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL TM1AH TM1BL TM1BH Reset (Power-on) ---- --11 ---- --11 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 xxxx xxxx xxxx xxxx ---- 0000 1001 --01 --01 --01 -0-0 0000 000- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 RES or LVR Reset ---- --11 ---- --11 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 xxxx xxxx xxxx xxxx ---- 0000 1001 --01 --01 --01 -0-0 0000 000- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 WDT Time-out (Normal Operation) ---- --11 ---- --11 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 -000 00-0 -000 1111 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 xxxx xxxx xxxx xxxx ---- 0000 1001 --01 --01 --01 -0-0 0000 000- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 WDT Time-out (IDLE) ---- --uu ---- --uu uuuu ---uuuu uuuu uuuu uuuu ---- uuuu uuuu -uuu uu-u -uuu uuuu uuuu uuuu u--u uuuu u--u uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- uuuu uuuu --uu --uu --uu -u-u uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu ---- --uu

Rev. 1.30

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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
Register TM2C0 TM2C1 TM2DL TM2DH TM2AL TM2AH TM2RP TM3C0 TM3C1 TM3DL TM3DH TM3AL TM3AH SCOMC Note: Reset (Power-on) 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 RES or LVR Reset 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 WDT Time-out (Normal Operation) 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 WDT Time-out (IDLE) uuuu u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu

²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented

Rev. 1.30

57

October 4, 2010

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
· HT66F60 Register

Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG WDTC TBC INTC0 INTC1 INTC2 INTC3 MFI0 MFI1 MFI2 MFI3 PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC PFPU

Reset (Power-on) xxxx xxxx xxxx xxxx - - 0- - 0 0 0 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --xx xxxx --00 xxxx 0000 0011 --00 -000 0000 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000

RES or LVR Reset xxxx xxxx xxxx xxxx - - 0- - 0 0 0 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu 0000 0011 --00 -000 0000 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000

WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx - - 0- - 0 0 0 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --uu uuuu --1u uuuu 0000 0011 --00 -000 0000 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000

WDT Time-out (IDLE) uuuu uuuu uuuu uuuu --u- -uuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu uuuu uuuu --uu -uuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu -uuu uuuu uuuu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

Rev. 1.30

58

October 4, 2010

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
Register PF PFC PGPU PG PGC ADRL (ADREF=0) ADRL (ADREF=1) ADRH (ADREF=0) ADRH (ADREF=1) ADCR0 ADCR1 ACERL ACERH CP0C CP1C SIMC0 SIMC1 SIMD SIMA/SIMC2 TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH EEA EED EEC TMPC0 TMPC1 PRM0 PRM1 PRM2 TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL Reset (Power-on) 1111 1111 1111 1111 ---- --00 ---- --11 ---- --11 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 0000 00-0 -000 1111 1111 ---- 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 xxxx xxxx xxxx xxxx ---- 0000 1001 --01 --01 --01 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 RES or LVR Reset 1111 1111 1111 1111 0000 0000 ---- --11 ---- --11 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 0000 00-0 -000 1111 1111 ---- 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 xxxx xxxx xxxx xxxx ---- 0000 1001 --01 --01 --01 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 WDT Time-out (Normal Operation) 1111 1111 1111 1111 0000 0000 ---- --11 ---- --11 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 0000 00-0 -000 1111 1111 ---- 1111 1000 0--1 1000 0--1 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 xxxx xxxx xxxx xxxx ---- 0000 1001 --01 --01 --01 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 WDT Time-out (IDLE) uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu ---- --uu uuuu ---uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu uu-u -uuu uuuu uuuu ---- uuuu uuuu u--u uuuu u--u uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- uuuu uuuu --uu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu

Rev. 1.30

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October 4, 2010

--00 0000 0000 ---.--00 0000 0000 WDT Time-out (Normal Operation) ---.--00 0000 0000 WDT Time-out (IDLE) ---. 1.--uu uuuu uuuu ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev.--00 0000 0000 ---.--00 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---.--00 0000 0000 RES or LVR Reset ---.--uu uuuu uuuu ---.--00 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---. 2010 .--uu uuuu uuuu ---.--00 0000 0000 ---.--00 0000 0000 ---.--00 0000 0000 ---.30 60 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Register TM1AH TM1BL TM1BH TM2C0 TM2C1 TM2DL TM2DH TM2AL TM2AH TM2RP TM3C0 TM3C1 TM3DL TM3DH TM3AL TM3AH SCOMC Note: Reset (Power-on) ---.--00 0000 0000 ---.--uu uuuu u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---.--00 0000 0--0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---.

the user is provided with an I/O structure to meet the needs of a wide range of application possibilities.30 61 October 4. · I/O Register List ¨ HT66F20 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC Bit 7 D7 D7 D7 D7 ¾ ¾ ¾ ¾ ¾ ¾ 6 D6 D6 D6 D6 ¾ ¾ ¾ ¾ ¾ ¾ 5 D5 D5 D5 D5 D5 D5 D5 ¾ ¾ ¾ 4 D4 D4 D4 D4 D4 D4 D4 ¾ ¾ ¾ 3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 ¨ HT66F30 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC Bit 7 D7 D7 D7 D7 ¾ ¾ ¾ D7 D7 D7 6 D6 D6 D6 D6 ¾ ¾ ¾ D6 D6 D6 5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 Rev. these ports are non-latching.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. For output operation. The device provides bidirectional input/output lines labeled with port names PA~PG. 1. where m denotes the port address. 2010 .[m]². For input operation. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. which means the inputs must be ready at the T2 rising edge of instruction ²MOV A. All of these I/O ports can be used for input and output operations. pull-high selections for all ports and wake-up selections on certain pins. With the input or output designation of every pin fully under user program control. all the data is latched and remains unchanged until the output latch is rewritten.

30 62 October 4. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F40/HT66F50 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC PFPU PF PFC Bit 7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 ¾ ¾ ¾ 6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 ¾ ¾ ¾ 5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 ¾ ¾ ¾ 4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 ¾ ¾ ¾ 3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 ¾ ¾ ¾ 2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 ¾ ¾ ¾ 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 Rev. 2010 .

2010 .30 63 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F60 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC PFPU PF PFC PGPU PG PGC Bit 7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 ¾ ¾ ¾ 6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 ¾ ¾ ¾ 5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 ¾ ¾ ¾ 4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 ¾ ¾ ¾ 3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 ¾ ¾ ¾ 2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 ¾ ¾ ¾ 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 Rev. 1.

These pull-high resistors are selected using registers PAPU~PGPU.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. and are implemented using weak PMOS transistors. 1. 2010 .30 64 October 4. all I/O pins. when configured as an input have the capability of being connected to an internal pull-high resistor. To eliminate the need for these external resistors. · PAPU Register Bit Name R/W POR · PBPU Register ¨ 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 · PCPU Register ¨ HT66F30/HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 · PDPU Register ¨ HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 · PEPU Register ¨ HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Rev.

30 65 October 4. read as ²0² PCPU: Port C bit 3 ~ bit 0 Pull-High Control 0: Disable 1: Enable · PFPU Register ¨ HT66F40/HT66F50 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D1 R/W 0 0 D0 R/W 0 Bit 7~2 Bit 1~0 ²¾² Unimplemented. 1. 2010 . read as ²0² PBPU: Port B bit 5 ~ bit 0 Pull-High Control 0: Disable 1: Enable · PCPU Register ¨ HT66F20 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit 7~4 Bit 3~0 ²¾² Unimplemented. read as ²0² PFPU: Port F bit 1 ~ bit 0 Pull-High Control 0: Disable 1: Enable Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · PFPU Register ¨ HT66F60 Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit 7~0 I/O Port bit 7 ~ bit 0 Pull-High Control 0: Disable 1: Enable · PBPU Register ¨ HT66F20/HT66F30 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit 7~6 Bit 5~0 ²¾² Unimplemented.

a feature that is important for battery and other low-power applications.30 66 October 4. the corresponding bit of the control register must be written as a ²1². each CMOS output or input can be reconfigured dynamically under software control. With this control register. If the pin is currently setup as an output. When the corresponding bit of the control register is written as a ²0². 2010 . instructions can still be used to read the output register. This will then allow the logic state of the input pin to be directly read by instructions. it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. one of which is to change the logic condition on one of the Port A pins from high to low. read as ²0² PGPU: Port G bit 1 ~ bit 0 Pull-High Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power. This function is especially suitable for applications that can be woken up via external switches. 1. · PAC Register Bit Name R/W POR · PBC Register ¨ 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1 HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1 Rev. to control the input/output configuration.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · PGPU Register ¨ HT66F60 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D1 R/W 0 0 D0 R/W 0 Bit 7~2 Bit 1~0 ²¾² Unimplemented. · PAWU Register Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 PAWU: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PGC. Various methods exist to wake-up the microcontroller. For the I/O pin to function as an input. the I/O pin will be setup as a CMOS output. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. However.

2010 . 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · PCC Register ¨ HT66F30/HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1 · PDC Register ¨ HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1 · PEC Register ¨ HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1 · PFC Register ¨ HT66F60 Bit Name R/W POR 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1 Bit 7~0 I/O Port bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input · PBC Register ¨ HT66F20/HT66F30 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit 7~6 Bit 5~0 ²¾² Unimplemented. read as ²0² PBC: Port B bit 5 ~ bit 0 Input/Output Control 0: Output 1: Input Rev.30 67 October 4.

30 68 October 4. read as ²0² PFC: Port F bit 1 ~ bit 0 Input/Output Control 0: Output 1: Input · PGC Register ¨ HT66F60 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D1 R/W 0 0 D0 R/W 0 Bit 7~2 Bit 1~0 ²¾² Unimplemented. 1. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · PCC Register ¨ HT66F20 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit 7~4 Bit 3~0 ²¾² Unimplemented. read as ²0² PGC: Port G bit 1 ~ bit 0 Input/Output Control 0: Output 1: Input Rev. read as ²0² PCC: Port C bit 3 ~ bit 0 Input/Output Control 0: Output 1: Input · PFC Register ¨ HT66F40/HT66F50 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D1 R/W 0 0 D0 R/W 0 Bit 7~2 Bit 1~0 ²¾² Unimplemented.

Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions. many of these difficulties can be overcome. Additionally there are a series of PRM0. 1. Pin-remapping Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pin-remapping Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. PRM1 and PRM2 registers to establish certain pin functions.30 69 October 4. PRM1 or PRM2 registers which can select the functions of certain pins. a wide range of different functions can be incorporated into even relatively small package sizes. However by allowing the same pins to share several different functions and providing a means of function selection. · Pin-remapping Register List ¨ HT66F30 Register Name PRM0 Bit 7 ¾ 6 ¾ 5 ¾ 4 ¾ 3 ¾ 2 PCPRM 1 SIMPS0 0 PCKPS ¨ HT66F40 Register Name PRM0 PRM1 PRM2 Bit 7 ¾ TCK2PS ¾ 6 C1XPS0 TCK1PS ¾ 5 ¾ TCK0PS TP21PS 4 C0XPS0 ¾ TP20PS 3 PDPRM INT1PS1 TP1B2PS 2 SIMPS1 INT1PS0 TP1APS 1 SIMPS0 INT0PS1 TP01PS 0 PCKPS INT0PS0 TP00PS ¨ HT66F50 Register Name PRM0 PRM1 PRM2 Bit 7 ¾ TCK2PS TP31PS 6 C1XPS0 TCK1PS TP30PS 5 ¾ TCK0PS TP21PS 4 C0XPS0 ¾ TP20PS 3 PDPRM INT1PS1 TP1B2PS 2 SIMPS1 INT1PS0 TP1APS 1 SIMPS0 INT0PS1 TP01PS 0 PCKPS INT0PS0 TP00PS ¨ HT66F60 Register Name PRM0 PRM1 PRM2 Bit 7 C1XPS1 TCK2PS TP31PS 6 C1XPS0 TCK1PS TP30PS 5 C0XPS1 TCK0PS TP21PS 4 C0XPS0 INT2PS1 TP20PS 3 PDPRM INT1PS1 TP1B2PS 2 SIMPS1 INT1PS0 TP1APS 1 SIMPS0 INT0PS1 TP01PS 0 PCKPS INT0PS0 TP00PS Rev. Some devices include PRM0. 2010 .

SCK/SCL on PA7. 2010 . PINT on PC4 Bit 5 Bit 4 Bit 3 Bit 2~1 Bit 0 Rev. read as ²0² C1XPS0: C1X Pin Remapping Control 0: C1X on PA5 1: C1X on PF1 ²¾² Unimplemented. PINT on PC3 1: PCK on PC5. SCS on PC6 PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2. SDI/SDA on PC0. TP1B_1 on PC1 change to PA7 if SIMPS0=1 SIMPS0: SIM Pin Remapping Control 0: SDO on PA5. SIMPS0: SIM Pin Remapping Control 00: SDO on PA5. SCS on PD7 11: Undefined PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2. SCS on PD0 10: SDO on PB6. SCK/SCL on PD1. 1. TCK0 on PD2 change to PD6. SCK/SCL on PD6.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · PRM0 Register ¨ HT66F30 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 PCPRM R/W 0 1 SIMPS0 R/W 0 0 PCKPS R/W 0 Bit 7~3 Bit 2 ²¾² Unimplemented. TCK1 on PD3 change to PD7 if SIMPS1. SCS on PB5 01: SDO on PD3. TP2_0 on PD1 change to PB7. SDI/SDA on PD2. PINT on PC4 Bit 1 Bit 0 · PRM0 Register ¨ HT66F40/HT66F50 Bit Name R/W POR 7 ¾ ¾ ¾ 6 C1XPS0 R/W 0 5 ¾ ¾ ¾ 4 C0XPS0 R/W 0 3 PDPRM R/W 0 2 SIMPS1 R/W 0 1 SIMPS0 R/W 0 0 PCKPS R/W 0 Bit 7 Bit 6 ²¾² Unimplemented. SIMPS0=01 SIMPS1. SDI/SDA on PA6. SCK/SCL on PC7. SDI/SDA on PB7. read as ²0² PCPRM: PC1~PC0 pin-shared function Pin Remapping Control 0: No change 1: TP1B_0 on PC0 change to PA6. SCK/SCL on PA7. PINT on PC3 1: PCK on PC5. SDI/SDA on PA6. read as ²0² C0XPS0: C0X Pin Remapping Control 0: C0X on PA0 1: C0X on PF0 PDPRM: PD3~PD0 pin-shared function Pin Remapping Control 0: No change 1: TCK2 on PD0 change to PB6. SCS on PB5 1: SDO on PC1.30 70 October 4.

SDI/SDA on PD2. SCK/SCL on PA7. SIMPS0: SIM Pin Remapping Control 00: SDO on PA5. C0XPS0: C0X Pin Remapping Control 00: C0X on PA0 01: C0X on PF0 10: C0X on PG0 11: Undefined PDPRM: PD3~PD0 pin-shared function Pin Remapping Control 0: No change 1: TCK2 on PD0 change to PB6. C1XPS0: C1X Pin Remapping Control 00: C1X on PA5 01: C1X on PF1 10: C1X on PG1 11: Undefined C0XPS1. SCS on PD7 11: SDO on PD1. read as ²0² INT1PS1. SCS on PD0 PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2.30 71 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · PRM0 Register ¨ HT66F60 Bit Name R/W POR 7 C1XPS1 R/W 0 6 C1XPS0 R/W 0 5 C0XPS1 R/W 0 4 C0XPS0 R/W 0 3 PDPRM R/W 0 2 SIMPS1 R/W 0 1 SIMPS0 R/W 0 0 PCKPS R/W 0 Bit 7~6 C1XPS1. PINT on PC3 1: PCK on PC5. SCS on PB5 01: SDO on PD3. INT1PS0: INT1 Pin Remapping Control 00: INT1 on PA4 01: INT1 on PC5 10: Undefined 11: INT1 on PE7 INT0PS1. TCK1 on PD3 change to PD7 if SIMPS1. SIMPS0=01 or 11 SIMPS1. TCK0 on PD2 change to PD6. 1. SCS on PD0 10: SDO on PB6. SDI/SDA on PD2. SCK/SCL on PD3. SCK/SCL on PD6. SCK/SCL on PD1. INT0PS0: INT0 Pin Remapping Control 00: INT0 on PA3 01: INT0 on PC4 10: Undefined 11: INT0 on PE6 Bit 6 Bit 5 Bit 4 Bit 3~2 Bit 1~0 Rev. PINT on PC4 Bit 5~4 Bit 3 Bit 2~1 Bit 0 · PRM1 Register ¨ HT66F40/HT66F50 Bit Name R/W POR 7 TCK2PS R/W 0 6 TCK1PS R/W 0 5 TCK0PS R/W 0 4 ¾ ¾ ¾ 3 INT1PS1 R/W 0 2 INT1PS0 R/W 0 1 INT0PS1 R/W 0 0 INT0PS0 R/W 0 Bit 7 TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PD0 TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PD3 TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PD2 ²¾² Unimplemented. SDI/SDA on PB7. TP2_0 on PD1 change to PB7. SDI/SDA on PA6. 2010 .

INT0PS0: INT0 Pin Remapping Control 00: INT0 on PA3 01: INT0 on PC4 10: INT0 on PE0 11: INT0 on PE6 Bit 6 Bit 5 Bit 4 Bit 3~2 Bit 1~0 · PRM2 Register ¨ HT66F40 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 TP21PS R/W 0 4 TP20PS R/W 0 3 TP1B2PS R/W 0 2 TP1APS R/W 0 1 TP01PS R/W 0 0 TP00PS R/W 0 Bit 7~6 Bit 5 ²¾² Unimplemented. read as ²0² TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD4 TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD1 TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PE4 TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PC7 TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PC5 1: TP0_1 on PD5 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PC6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. INT1PS0: INT1 Pin Remapping Control 00: INT1 on PA4 01: INT1 on PC5 10: INT1 on PE1 11: INT1 on PE7 INT0PS1.30 72 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · PRM1 Register ¨ HT66F60 Bit Name R/W POR 7 TCK2PS R/W 0 6 TCK1PS R/W 0 5 TCK0PS R/W 0 4 INT2PS R/W 0 3 INT1PS1 R/W 0 2 INT1PS0 R/W 0 1 INT0PS1 R/W 0 0 INT0PS0 R/W 0 Bit 7 TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PD0 TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PD3 TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PD2 INT2PS: INT2 Pin Remapping Control 0: INT2 on PC4 1: INT2 on PE2 INT1PS1. 1. 2010 .

2010 .30 73 October 4. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · PRM2 Register ¨ HT66F50/HT66F60 Bit Name R/W POR 7 TP31PS R/W 0 6 TP30PS R/W 0 5 TP21PS R/W 0 4 TP20PS R/W 0 3 TP1B2PS R/W 0 2 TP1APS R/W 0 1 TP01PS R/W 0 0 TP00PS R/W 0 Bit 7 TP31PS: TP3_1 Pin Remapping Control 0: TP3_1 on PD0 1: TP3_1 on PE3 TP30PS: TP3_0 Pin Remapping Control 0: TP3_0 on PD3 1: TP3_0 on PE5 TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD4 TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD1 TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PE4 TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PC7 TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PC5 1: TP0_1 on PD5 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PC6 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types.i² and ²CLR [m].30 74 October 4. As the exact logical construction of the I/O pin will differ from these drawings.u p W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r I/O D a ta B it Q D C K Q S M U X P A o n ly p in W r ite D a ta R e g is te r R e a d D a ta R e g is te r S y s te m W a k e -u p W a k e . One of these is a high to low transition of any of the Port A pins. one of the first things to consider is port initialisation. Port A has the additional capability of providing wake-up functions. PA~PG. they are supplied as a guide only to assist with the functional understanding of the I/O pins.H ig h R e g is te r S e le c t V D D W e a k P u ll. After a reset. are first programmed. these output pins will have an initial high output value unless the associated port data registers. the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. 1. This means that all I/O pins will default to an input state. a read-modify-write operation takes place. If the port control registers. Note that when using these bit control instructions.u p S e le c t Generic Input/Output Structure Rev. PAC~PGC.i² instructions. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the ²SET [m]. are then programmed to setup some pins as outputs. 2010 . Programming Considerations Within the user program. all of the I/O data and port control registers will be set high. When the device is in the SLEEP or IDLE Mode. Single or multiple pins on Port A can be setup to have this function. The wide range of pin-shared structures does not permit all types to be shown. C o n tr o l B it D a ta B u s D Q C K S Q P u ll. modify it to the required new bit values and then rewrite this data back to the output ports. various methods are available to wake the device up. The microcontroller must first read in the data on the entire port.

H ig h R e g is te r S e le c t D D D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r W e a k P u ll.u p A /D D a ta B it Q D C K S Q M U X In p u t P o rt W r ite D a ta R e g is te r R e a d D a ta R e g is te r A n a lo g In p u t S e le c to r T o A /D C o n v e rte r A C S 3 ~ A C S 0 A/D Input/Output Structure Rev. 2010 .30 75 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 V C o n tr o l B it Q D C K S Q P u ll. 1.

The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. TM1. The common features of the different TM types are described here with more detailed information provided in the individual Compact. Standard Type TM or Enhanced Type TM. Standard Type and Enhanced Type TM units which are shown in the table together with their individual reference name. TM0~TM3. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter. Function Timer/Counter I/P Capture Compare Match Output PWM Channels Single Pulse Output PWM Alignment PWM Adjustment Period & Duty CTM Ö ¾ Ö 1 ¾ Edge Duty or Period TM Function Summary STM Ö Ö Ö 1 1 Edge Duty or Period ETM Ö Ö Ö 2 2 Edge & Centre Duty or Period Each device in the series contains a specific number of either Compact Type. the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table.30 76 October 4. 2010 .TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. Each individual TM can be categorised as a certain type. Standard and Enhanced TMs will be described in this section. Input Capture. The common features to all of the Compact. Each of the TMs has either two or three individual interrupts. Standard and Enhanced TM sections. the different TM types vary in their feature complexity. namely Compact Type TM. 1. TM2 and TM3. To implement time related functions each device includes several Timer Modules. abbreviated to the name TM. Device HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 TM0 10-bit CTM 10-bit CTM 10-bit CTM 10-bit CTM 10-bit CTM TM1 10-bit STM 10-bit ETM 10-bit ETM 10-bit ETM 10-bit ETM TM Name/Type Reference TM2 ¾ ¾ 16-bit STM 16-bit STM 16-bit STM TM3 ¾ ¾ ¾ 10-bit CTM 10-bit CTM Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Timer Modules . Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Introduction The devices contain from two to four TMs depending upon which device is selected with each TM having a reference name of TM0. Although similar in nature.

TP0_1 TP3_0. The internal TM counter is driven by a user selectable clock source. TP0_1 TP3_0. Pin names that include a ²_1² or ²_2² suffix indicate that they are from a TM with multiple output pins. TP1B_2 TP1A. When the free ru n n in g c ount er h a s t he s a m e v al u e a s t h e pre-programmed comparator. TP1B_1. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. TP3_1 STM TP1_0. The external TPn output pin is also the pin where the TM generates the PWM output waveform. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. known as a compare match situation. TP0_1 TP0_0. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. Device HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 CTM TP0_0 TP0_0. As the Enhanced type TM has three internal comparators and comparator A or comparator B or comparator P compare match functions.30 77 October 4. TP1B_0. 2010 . these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. This allows the TM to generate a complimentary output pair. TP1B_2 TP1A. TP1B_1. a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. As the TM output pins are pin-shared with other function. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TMPC1 TMPC0. irrespective of what type. it consequently has three internal interrupts. TM Interrupts The Compact and Standard type TMs each have two internal interrupts. TP1_1 ¾ TP2_0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 TM Operation The three different types of TM offer a diverse range of functions. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH. TP2_1 TM Output Pins ETM ¾ TP1A. from simple timing operations to PWM signal generation. TP2_1 TP2_0. The key to understanding how the TM operates is to see it in terms of a free running counter whose v a lu e is t h e n c o m p a r ed w i t h t h e v a l u e o f pre-programmed internal comparators. TP1B_0. in effect disconnecting the TM clock source. The TM input pin. with the label TCKn. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. TMPC1 Rev. This external TM input pin allows an external clock source to drive the internal TM. TP2_1 TP2_0. The TM input pin can be chosen to have either a rising or falling active edge. TM External Pins Each of the TMs. TP0_1 TP0_0. one for each of the internal comparator A or comparator P. 1. TP1B_2 Registers TMPC0 TMPC0 TMPC0. When the TM is in the Compare Match Output Mode. TMPC1 TMPC0. which can be an internal clock or an external pin. Note that setting these bits to the value 101 will select a reserved clock input. the fTBC clock source or the external TCKn pin. All TM output pin names have an ²_n² suffix. is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. the TM output function must first be setup using registers. TP1B_1. The TMs each have one or more output pins with the label TPn. TP1B_0. which generate a TM interrupt when a compare match condition occurs. selected using the I/O register data bits. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. has one TM input pin. the details are provided in the accompanying table. TP1B_0. TP1B_1 TP1A. The number of output pins for each TM type and device is different. TP3_1 TP0_0.

Registers TMPC0 TMPC0 TMPC0 TMPC1 TMPC1 Device HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66F40 HT66F50 HT66F60 Bit 7 ¾ T1ACP0 T1ACP0 ¾ ¾ 6 ¾ ¾ T1BCP2 ¾ ¾ 5 T1CP1 T1BCP1 T1BCP1 ¾ T3CP1 4 T1CP0 T1BCP0 T1BCP0 ¾ T3CP0 3 ¾ ¾ ¾ ¾ ¾ 2 ¾ ¾ ¾ ¾ ¾ 1 ¾ T0CP1 T0CP1 T2CP1 T2CP1 0 T0CP0 T0CP0 T0CP0 T2CP0 T2CP0 TM Input/Output Pin Control Registers List P A 0 O u tp u t F u n c tio n 1 O u tp u t T M 0 (C T M ) T C K In p u t 0 P A 0 /T P 0 _ 0 T 0 C P 0 P A 2 /T C K 0 P A 1 O u tp u t F u n c tio n 0 1 0 1 P A 1 P C 0 O u tp u t F u n c tio n 0 1 0 1 P C 0 1 0 T 1 C P 1 1 0 T 1 C P 0 T C K In p u t C a p tu re In p u t T M 1 (S T M ) O u tp u t P A 1 /T P 1 _ 0 T 1 C P 0 P C 0 /T P 1 _ 1 T 1 C P 1 P A 4 /T C K 1 HT66F20 TM Function Pin Control Block Diagram Note: 1.30 78 October 4. is implemented using one or two registers. the TM pin control register must never enable more than one TM input. 2. Setting the bit high will setup the corresponding pin as a TM input/output. Rev. 2010 . with a single bit in each register corresponding to a TM input/output pin. 1. if reset to zero the pin will retain its original other function. The I/O register data bits shown are used for TM output inversion control. In the Capture Input Mode.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function.

Rev. The I/O register data bits shown are used for TM output inversion control. In the Capture Input Mode.30 79 October 4. the TM pin control register must never enable more than one TM input. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 P A 0 O u tp u t F u n c tio n 0 1 P A 0 P C 5 O u tp u t F u n c tio n O u tp u t 0 1 P C 5 P A 2 /T C K 0 T M 0 (C T M ) T C K In p u t 1 T 0 C P 1 0 P C 5 /T P 0 _ 1 1 T 0 C P 0 0 P A 0 /T P 0 _ 0 P A 1 O u tp u t F u n c tio n C C R A O u tp u t 1 0 P A 1 /T P 1 A T 1 A C P 0 C C R A C a p tu re In p u t 0 T 1 A C P 0 1 P C 0 O u tp u t F u n c tio n 0 1 0 1 P C 0 T M 1 (E T M ) C C R B O u tp u t 0 1 P C 1 1 0 C C R B C a p tu re In p u t P C 1 O u tp u t F u n c tio n 0 1 P C 0 /T P 1 B _ 0 T 1 B C P 0 P C 1 /T P 1 B _ 1 T 1 B C P 1 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT66F30 TM Function Pin Control Block Diagram Note: 1. 1. 2.

1. Rev. 2010 .30 80 October 4. In the Capture Input Mode.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 P A 0 O u tp u t F u n c tio n 0 1 P A 0 P C 5 O u tp u t F u n c tio n O u tp u t 0 1 P C 5 P A 2 /T C K 0 T M 0 (C T M ) T C K In p u t 1 T 0 C P 1 0 P C 5 /T P 0 _ 1 1 T 0 C P 0 0 P A 0 /T P 0 _ 0 P C 3 O u tp u t F u n c tio n 0 1 0 1 P C 3 P C 4 O u tp u t F u n c tio n 0 1 0 1 P C 4 1 0 T 2 C P 1 1 0 T 2 C P 0 T C K In p u t C a p tu re In p u t T M 2 (S T M ) O u tp u t P C 3 /T P 2 _ 0 T 2 C P 0 P C 4 /T P 2 _ 1 T 2 C P 1 P C 2 /T C K 2 HT66F40 TM0 & TM2 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. the TM pin control register must never enable more than one TM input.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
P A 1 O u tp u t F u n c tio n C C R A O u tp u t 1 T 1 A C P 0 C C R A C a p tu re In p u t 0 T 1 A C P 0 1 0

P A 1 /T P 1 A

P C 0 O u tp u t F u n c tio n 0 1 0 1 P C 0 P C 1 O u tp u t F u n c tio n 0 1 0 1 T M 1 (E T M ) P C 1 P C 5 O u tp u t F u n c tio n 0 1 0 1 P C 5 1 0 C C R B C a p tu re In p u t C C R B O u tp u t

P C 0 /T P 1 B _ 0

T 1 B C P 0

P C 1 /T P 1 B _ 1

T 1 B C P 1

P C 5 /T P 1 B _ 2

T 1 B C P 2

T 1 B C P 2 1 0 T 1 B C P 1 1 0 T 1 B C P 0 P A 4 /T C K 1

T C K In p u t

HT66F40 TM1 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.

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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
P A 0 O u tp u t F u n c tio n 0 1 P A 0 P C 5 O u tp u t F u n c tio n O u tp u t 0 1 P C 5 P A 2 /T C K 0 T M 0 (C T M ) T C K In p u t 1 T 0 C P 1 0 P C 5 /T P 0 _ 1 1 T 0 C P 0 0 P A 0 /T P 0 _ 0

P C 3 O u tp u t F u n c tio n 0 1 0 1 P C 3 P C 4 O u tp u t F u n c tio n 0 1 0 1 P C 4 1 0 T 2 C P 1 1 0 T 2 C P 0 T C K In p u t C a p tu re In p u t T M 2 (S T M ) O u tp u t

P C 3 /T P 2 _ 0

T 2 C P 0

P C 4 /T P 2 _ 1

T 2 C P 1

P C 2 /T C K 2

P D 3 O u tp u t F u n c tio n 0 1 P D 3 P D 0 O u tp u t F u n c tio n O u tp u t 0 1 P D 0 T M 3 (C T M ) T C K In p u t 1 0 1

0 P D 3 /T P 3 _ 0

T 3 C P 0

P D 0 /T P 3 _ 1

T 3 C P 1

P C 4 /T C K 3

HT66F50 and HT66F60 TM0, TM2, TM3 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. 82 October 4, 2010

Rev. 1.30

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
P A 1 O u tp u t F u n c tio n C C R A O u tp u t 1 T 1 A C P 0 C C R A C a p tu re In p u t 0 T 1 A C P 0 1 0

P A 1 /T P 1 A

P C 0 O u tp u t F u n c tio n 0 1 0 1 P C 0 P C 1 O u tp u t F u n c tio n 0 1 0 1 T M 1 (E T M ) P C 1 P C 5 O u tp u t F u n c tio n 0 1 0 1 P C 5 1 0 C C R B C a p tu re In p u t C C R B O u tp u t

P C 0 /T P 1 B _ 0

T 1 B C P 0

P C 1 /T P 1 B _ 1

T 1 B C P 1

P C 5 /T P 1 B _ 2

T 1 B C P 2

T 1 B C P 2 1 0 T 1 B C P 1 1 0 T 1 B C P 0 P A 4 /T C K 1

T C K In p u t

HT66F50 and HT66F60 TM1 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.

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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
· TMPC0 Register
¨

HT66F20 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 T1CP1 R/W 0 4 T1CP0 R/W 1 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 ¾ ¾ ¾ 0 T0CP0 R/W 1

Bit 7, 6 Bit 5

Bit 4

Unimplemented, read as ²0² T1CP1: TP1_1 pin Control 0: disable 1: enable T1CP0: TP1_0 pin Control 0: disable 1: enable Unimplemented, read as ²0² T0CP0: TP0_0 pin Control 0: disable 1: enable

Bit 3~1 Bit 0

¨

HT66F30 Bit Name R/W POR 7 T1ACP0 R/W 1 6 ¾ ¾ ¾ 5 T1BCP1 R/W 0 4 T1BCP0 R/W 1 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T0CP1 R/W 0 0 T0CP0 R/W 1

Bit 7

T1ACP0: TP1A pin Control 0: disable 1: enable Unimplemented, read as ²0² T1BCP1: TP1B_1 pin Control 0: disable 1: enable T1BCP0: TP1B_0 pin Control 0: disable 1: enable Unimplemented, read as ²0² T0CP1: TP0_1 pin Control 0: disable 1: enable T0CP0: TP0_0 pin Control 0: disable 1: enable

Bit 6 Bit 5

Bit 4

Bit 3~2 Bit 1

Bit 0

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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨

HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 T1ACP0 R/W 1 6 T1BCP2 R/W 0 5 T1BCP1 R/W 0 4 T1BCP0 R/W 1 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T0CP1 R/W 0 0 T0CP0 R/W 1

Bit 7

Bit 6

Bit 5

Bit 4

T1ACP0: TP1A pin Control 0: disable 1: enable T1BCP2: TP1B_2 pin Control 0: disable 1: enable T1BCP1: TP1B_1 pin Control 0: disable 1: enable T1BCP0: TP1B_0 pin Control 0: disable 1: enable Unimplemented, read as ²0² T0CP1: TP0_1 pin Control 0: disable 1: enable T0CP0: TP0_0 pin Control 0: disable 1: enable

Bit 3~2 Bit 1

Bit 0

· TMPC1 Register
¨

HT66F40 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T2CP1 R/W 0 0 T2CP0 R/W 1

Bit 7~2 Bit 1

Unimplemented, read as ²0² T2CP1: TP2_1 pin Control 0: disable 1: enable T2CP0: TP2_0 pin Control 0: disable 1: enable

Bit 0

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October 4, 2010

note that here data is only written to the 8-bit buffer. using the following access procedures. Step 2. all have a low and high byte structure. ¨ Rev. named TMxAL and TMxBL. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. reading or writing to these register pairs must be carried out in a specific way.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F50/HT66F60 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 T3CP1 R/W 0 4 T3CP0 R/W 1 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T2CP1 R/W 0 0 T2CP0 R/W 1 Bit 7~6 Bit 5 Unimplemented. read as ²0² T3CP1: TP3_1 pin Control 0: disable 1: enable T3CP0: TP3_0 pin Control 0: disable 1: enable Unimplemented. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values. Write data to Low Byte TMxAL or TMxBL . The high bytes can be directly accessed. TM Counter Register (Read only) TMxDL 8-bit Buffer TMxDH TMxAL TMxAH TM CCRA Register (Read/Write) TMxBL TMxBH Data Bus TM CCRB Register (Read/Write) As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above. The following steps show the read and write procedures: · Writing Data to CCRB or CCRA ¨ Step 1. being either 10-bit or 16-bit.here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. 1. Write data to High Byte TMxAH or TMxBH . it is recommended to use the ²MOV² instruction to access the CCRA and CCRB low byte registers. 2010 . read as ²0² T2CP1: TP2_1 pin Control 0: disable 1: enable T2CP0: TP2_0 pin Control 0: disable 1: enable Bit 4 Bit 3~2 Bit 1 Bit 0 Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRB registers. but as the low bytes can only be accessed via an internal 8-bit buffer.30 86 October 4.

is to clear the counter by changing the TnON bit from low to high. TCK3 TM Output Pin TP0_0 TP0_0. which are Compare Match Output. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. TP3_0. These two external output pins can be the same signal or the inverse signal. TP0_1 TP0_0. 1.30 87 October 4. These comparators will compare the value in the counter with CCRP and CCRA registers. All operating setup conditions are selected using relevant internal registers. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins. C C R P 3 . TMxAL or TMxBL . can be driven by different clock sources including an input pin and can also control an output pin. TMxAH or TMxBH . The Compact Type TM can operate in a number of different operational modes. There are also two internal comparators with the names.b it C o u n t. 2010 .here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. Timer/Event Counter and PWM Output modes. Read data from the High Byte TMxDH.u p C o u n te r C o u n te r C le a r 0 1 O u tp u t C o n tro l P o la r ity C o n tro l T P n P in O u tp u t T C K n b 0 ~ b 9 T n C C L R T n M 1 . Read data from the Low Byte TMxDL. 0 0 0 0. ¨ Compact Type TM Although the simplest form of the three TM types. The only way of changing the value of the 10-bit counter using the application program. 3 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · Reading Data from the Counter Registers and CCRB or CCRA ¨ Step 1. CTM HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 Name 10-bit CTM 10-bit CTM 10-bit CTM 10-bit CTM 10-bit CTM TM No. T n IO 0 T n P O L 1 0 . TP3_1 TP0_0. TP3_0.this step reads data from the 8-bit buffer. Comparator A and Comparator P.b it C o m p a r a to r P C o m p a ra to r P M a tc h T n P F In te rru p t Y S /4 fS Y S fH /1 6 fH /6 4 fT B C R e s e rv e d fS 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 T n O N T n P A U b 7 ~ b 9 T n O C T P n _ 0 T P n _ 1 1 0 . TCK3 TCK0. the Compact TM type still contains three operating modes. Step 2. When these conditions occur. TP0_1 TP0_0. TP3_1 Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. a TM interrupt signal will also usually be generated. TP0_1.b it C o m p a r a to r A T n C K 2 ~ T n C K 0 C C R A C o m p a ra to r A M a tc h T n A F In te rru p t Compact Type TM Block Diagram Rev. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. 3 TM Input Pin TCK0 TCK0 TCK0 TCK0. TP0_1. T n M 0 T n IO 1 .

30 88 October 4. 1. read as ²0² TMnDH: TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 · TMnAL Register Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 TMnAL: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 · TMnAH Register Bit Name R/W POR Bit 7~2 Bit 1~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R/W 0 0 D8 R/W 0 Unimplemented. 2010 . The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. read as ²0² TMn 10-bit CCRA bit 9 ~ bit 8 Rev. A read only register pair exists to store the internal counter 10-bit value.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. Name TMnC0 TMnC1 TMnDL TMnDH TMnAL TMnAH Bit7 TnPAU TnM1 D7 ¾ D7 ¾ Bit6 TnCK2 TnM0 D6 ¾ D6 ¾ Bit5 TnCK1 TnIO1 D5 ¾ D5 ¾ Bit4 TnCK0 TnIO0 D4 ¾ D4 ¾ Bit3 TnON TnOC D3 ¾ D3 ¾ Bit2 TnRP2 TnPOL D2 ¾ D2 ¾ Bit1 TnRP1 TnDPX D1 D9 D1 D9 Bit0 TnRP0 TnCCLR D0 D8 D0 D8 Compact TM Register List (n=0 or 3) · TMnDL Register Bit Name R/W POR Bit 7~0 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0 TMnDL: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 · TMnDH Register Bit Name R/W POR Bit 7~2 Bit 1~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R 0 0 D8 R 0 Unimplemented. while a read/write register pair exists to store the internal 10-bit CCRA value.

The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.30 89 October 4. The external pin clock source can be chosen to be active on the rising or falling edge. 1. the internal counter will retain its residual value. TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. the details of which can be found in the oscillator section. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. As the CCRP bits are only compared with the highest three counter bits. Bit 6~4 Bit 3 Bit 2~0 Rev. Selecting the Reserved clock input will effectively disable the internal counter. TnRP2~TnRP0: TMn CCRP 3-bit register. when the TnON bit changes from low to high. TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: undefined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. the compare values exist in 128 clock cycle multiples. while fH and fTBC are other internal clocks. 2010 . If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition. When the bit changes state from low to high the internal counter value will be reset to zero. compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. The clock source fSYS is the system clock. Setting the bit high enables the counter to run. as specified by the TnOC bit.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · TMnC0 Register Bit Name R/W POR Bit 7 7 TnPAU R/W 0 6 TnCK2 R/W 0 5 TnCK1 R/W 0 4 TnCK0 R/W 0 3 TnON R/W 0 2 TnRP2 R/W 0 1 TnRP1 R/W 0 0 TnRP0 R/W 0 TnPAU: TMn Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. clearing the bit disables the TM. which are then compared with the internal counter's highest three bits. however when the bit changes from high to low. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter.

In the PWM Mode. switch low or to toggle its present state when a compare match occurs from the Comparator A. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. In the Compare Match Output Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. The function that these bits select depends upon in which mode the TM is running. the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin.30 90 October 4. In the Timer/Counter Mode. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. In the PWM Mode it determines if the PWM signal is active high or active low. 2010 . TnIO1~TnIO0: Select TPn_0. The PWM output function is modified by changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. then no change will take place on the output. TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/counter Mode unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running TnOC: TPn_0. It has no effect if the TM is in the Timer/Counter Mode.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · TMnC1 Register Bit Name R/W POR Bit 7~6 7 TnM1 R/W 0 6 TnM0 R/W 0 5 TnIO1 R/W 0 4 TnIO0 R/W 0 3 TnOC R/W 0 2 TnPOL R/W 0 1 TnDPX R/W 0 0 TnCCLR R/W 0 TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. Bit 5~4 Bit 3 Rev. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. When the bits are both zero. The TM output pin can be setup to switch high. the TM output pin control must be disabled. 1. the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A.

It has no effect if the TM is in the Timer/Counter Mode. PWM Mode or Timer/Counter Mode. Timer/Counter Mode To select this mode. bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. The TnCCLR bit is not used in the PWM Mode. the counter will overflow when its reaches its maximum 10-bit. TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. CCRA . The TnPF interrupt request flag.period. will have no effect on the TM output pin. Bit 1 Bit 0 Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high. either of which can be selected to clear the internal counter. the pin can be used as a normal I/O pin or other pin-shared function. 3FF Hex. Remember that the Compact TM contains two comparators. With the TnCCLR bit set high. Compare Match Output Mode. to go low or to toggle from its present condition when a compare match occurs from Comparator A.duty. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. CCRA . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. after a comparison is made. When the bit is low. generated from a compare match occurs from Comparator P. Rev. will both be generated. The initial condition of the TM output pin. When the TnCCLR bit is low. the counter will be cleared when a compare match occurs from the Comparator A. there are two ways in which the counter can be cleared. Compare Match Output Mode To select this mode. 2010 . In this mode once the counter is enabled and running it can be cleared by three methods. As the TM output pin is not used in this mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. One is when a compare match occurs from Comparator P. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. bits TnM1 and TnM0 in the TMnC1 register. the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. The exception is that in the Timer/Counter Mode the TM output pin is not used. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. However. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. If the CCRA bits are all zero. here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. 1. is setup using the TnOC bit. a compare match from Comparator A and a compare match from Comparator P. As the name of the mode suggests. These are a counter overflow. Comparator A and Comparator P. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function.period This bit. the TM output pin will change state.duty 1: CCRP . The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Bit 2 TnPOL: TPn_0.30 91 October 4. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively. TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. should be set to ²00² respectively. determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. value. however here the TnAF interrupt request flag will not be generated. which is setup after the TnON bit changes from low to high. the other is when the CCRP bits are all zero which allows the counter to overflow. TnDPX: TMn PWM period/duty Control 0: CCRP .

a Comparator P match will clear the counter 2.TnCCLR = 0 Note: 1. Flag TnAF TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. With TnCCLR=0. TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value Resume Counter Restart CCRP > 0 CCRA Time TnON TnPAU TnPOL CCRP Int. The TM output pin is controlled only by the TnAF flag 3. 2010 . Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode -. The output pin is reset to its initial state by a TnON bit rising edge Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value 0x3FF CCRP Pause Stop Counter overflow CCRP=0 TnCCLR = 0.30 92 October 4. 1. Flag TnPF CCRA Int.

Flag TnAF CCRP Int. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode -. 1. The TM output pin is controlled only by the TnAF flag 3. The TnPF flag is not generated when TnCCLR=1 Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value 0x3FF Resume TnCCLR = 1. TnM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0 Stop Counter Restart CCRA = 0 Counter overflow CCRA CCRP Pause Time TnON TnPAU TnPOL CCRA Int. The output pin is reset to its initial state by a TnON bit rising edge 4. a Comparator A match will clear the counter 2. Flag TnPF TnPF not generated Output does not change Output not affected by TnAF flag.TnCCLR = 1 Note: 1.30 93 October 4. 2010 . With TnCCLR=1.

30 94 October 4. Here TnDPX=0 -. one register is used to clear the internal counter and thus control the PWM waveform frequency. The PWM function within the TM is useful for applications which require functions such as motor control. TnM [1:0] = 10 Counter Reset when TnON returns high Counter Stop if TnON bit low CCRP CCRA Time TnON TnPAU TnPOL CCRA Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode -. a square wave AC waveform can be generated with varying equivalent DC RMS values.TnDPX = 0 Note: 1. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 PWM Output Mode To select this mode. 1. the TnCCLR bit has no effect on the PWM operation. Flag TnAF CCRP Int. The TnCCLR bit has no influence on PWM operation Rev. An interrupt flag. As both the period and duty cycle of the PWM waveform can be controlled. A counter clear sets the PWM Period 3. heating control.Counter cleared by CCRP 2. The TnPOL bit is used to reverse the polarity of the PWM output waveform. the choice of generated waveform is extremely flexible. illumination control etc. Counter Value Counter cleared by CCRP Pause Resume TnDPX = 0. one for each of the CCRA and CCRP. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. 2010 . By providing a signal of fixed frequency but of varying duty cycle on the TM output pin. Both of the CCRA and CCRP registers are used to generate the PWM waveform. In the PWM mode. will be generated when a compare match occurs from either Comparator A or Comparator P. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register.

Edge-aligned Mode. The TnCCLR bit has no influence on PWM operation Rev.8125 kHz. If the Duty value defined by the CCRA register is equal to or greater than the Period value. TM clock source is fSYS/4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · CTM. 1. PWM Mode. T0DPX=1 CCRP Period Duty 001b 010b 011b 100b CCRA 101b 110b 111b 000b 128 256 384 512 640 768 896 1024 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value.TnDPX = 1 Note: 1. · CTM. Edge-aligned Mode. Counter Value Counter cleared by CCRA Pause Resume TnDPX = 1. The CTM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7. duty = 128/512 = 25%. PWM Mode. 2010 . T0DPX=0 CCRP Period Duty 001b 128 010b 256 011b 384 100b 512 CCRA 101b 640 110b 768 111b 896 000b 1024 If fSYS = 16MHz. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4.30 95 October 4. Here TnDPX = 1 -.Counter cleared by CCRA 2. then the PWM output duty is 100%. Flag TnPF CCRA Int. A counter clear sets the PWM Period 3. TnM [1:0] = 10 Counter Reset when TnON returns high Counter Stop if TnON bit low CCRA CCRP Time TnON TnPAU TnPOL CCRP Int. CCRP = 100b and CCRA =128. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode -.

which are Compare Match Output. Comparator A and Comparator P. TP1_1 ¾ TP2_0. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins.STM The Standard Type TM contains five operating modes.u p C o u n te r C o u n te r C le a r 1 T n C C L R 0 O u tp u t C o n tro l P o la r ity C o n tro l T P n P in In p u t/O u tp u t b 0 ~ b 9 o r b 0 ~ b 1 5 1 0 o r 1 6 . The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. Timer/Event Counter.b it C o u n t. Capture Input. Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. T n IO 0 T n A F In te rru p t T n C K 2 ~ T n C K 0 C C R A E d g e D e te c to r Standard Type TM Block Diagram Rev. Single Pulse Output and PWM Output modes. T n IO 0 T n P O L C o m p a ra to r A M a tc h T n IO 1 . is to clear the counter by changing the TnON bit from low to high.30 96 October 4. a TM interrupt signal will also usually be generated.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Standard Type TM . These comparators will compare the value in the counter with CCRP and CCRA registers. can be driven by different clock sources including an input pin and can also control an output pin. TP2_1 Standard TM Operation There are two sizes of Standard TMs. The CCRP comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the CCRA is the ten or sixteen bits and therefore compares all counter bits. while a read/write register pair exists to store the internal 10 or 16-bit CCRA value.b it C o m p a r a to r P C o m p a ra to r P M a tc h T n P F In te rru p t fS Y S /4 Y S fS fH /1 6 fH /6 4 fT B C R e s e rv e d T C K n 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 T n O N T n P A U b 7 ~ b 9 o r b 8 ~ b 1 5 T n O C T P n _ 0 T P n _ 1 1 0 o r 1 6 .b it C o m p a ra to r A T n M 1 . A read only register pair exists to store the internal counter 10 or 16-bit value. 2010 . TP2_1 TP2_0. At the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. 1. When these conditions occur. The Standard Type TM can operate in a number of different operational modes. CTM HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 Name 10-bit STM ¾ 16-bit STM 16-bit STM 16-bit STM TM No. 1 ¾ 2 2 2 TM Input Pin TCK1 ¾ TCK2 TCK2 TCK2 TM Output Pin TP1_0. T n M 0 T n IO 1 . There are also two internal comparators with the names. C C R P 3 o r 8 . All operating setup conditions are selected using relevant internal registers. The only way of changing the value of the 10 or 16-bit counter using the application program. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits. TP2_1 TP2_0. one is 10-bits wide and the other is 16-bits wide.

HT66F20 ¨ TM1C0 Register . 2010 . The clock source fSYS is the system clock. When in a Pause condition the TM will remain powered up and continue to consume power. 1. The external pin clock source can be chosen to be active on the rising or falling edge. T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.10-bit STM Bit Name R/W POR 7 T1PAU R/W 0 6 T1CK2 R/W 0 5 T1CK1 R/W 0 4 T1CK0 R/W 0 3 T1ON R/W 0 2 T1RP2 R/W 0 1 T1RP1 R/W 0 0 T1RP0 R/W 0 Bit 7 T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. the details of which can be found in the oscillator section. Selecting the Reserved clock input will effectively disable the internal counter. Clearing the bit to zero restores normal counter operation. Bit 6~4 Rev. while fH and fTBC are other internal clocks.30 97 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Name TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH Bit7 T1PAU T1M1 D7 ¾ D7 ¾ Bit6 T1CK2 T1M0 D6 ¾ D6 ¾ Bit5 T1CK1 T1IO1 D5 ¾ D5 ¾ Bit4 T1CK0 T1IO0 D4 ¾ D4 ¾ Bit3 T1ON T1OC D3 ¾ D3 ¾ Bit2 T1RP2 T1POL D2 ¾ D2 ¾ Bit1 T1RP1 T1DPX D1 D9 D1 D9 Bit0 T1RP0 T1CCLR D0 D8 D0 D8 10-bit Standard TM Register List (for HT66F20) Name TM2C0 TM2C1 TM2DL TM2DH TM2AL TM2AH TM2RP Bit7 T2PAU T2M1 D7 D15 D7 D15 D7 Bit6 T2CK2 T2M0 D6 D14 D6 D14 D6 Bit5 T2CK1 T2IO1 D5 D13 D5 D13 D5 Bit4 T2CK0 T2IO0 D4 D12 D4 D12 D4 Bit3 T2ON T2OC D3 D11 D3 D11 D3 Bit2 ¾ T2POL D2 D10 D2 D10 D2 Bit1 ¾ T2DPX D1 D9 D1 D9 D1 Bit0 ¾ T2CCLR D0 D8 D0 D8 D0 16-bit Standard TM Register List (for HT66F40/HT66F50/HT66F60) · 10-bit Standard TM Register List .

As the CCRP bits are only compared with the highest three counter bits. In the Timer/Counter Mode.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Bit 3 T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. T1IO1~T1IO0: Select TP1_0. When the bit changes state from low to high the internal counter value will be reset to zero. however when the bit changes from high to low. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TP1_1 11: Input capture disabled Timer/counter Mode: Unused Bit 5~4 Rev. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register. when the T1ON bit changes from low to high. Setting the bit high enables the counter to run. as specified by the T1OC bit. the internal counter will retain its residual value until the bit returns high again. TP1_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1_0. TP1_1 01: Input capture at falling edge of TP1_0. 1. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register. clearing the bit disables the TM.10-bit STM Bit Name R/W POR 7 T1M1 R/W 0 6 T1M0 R/W 0 5 T1IO1 R/W 0 4 T1IO0 R/W 0 3 T1OC R/W 0 2 T1POL R/W 0 1 T1DPX R/W 0 0 T1CCLR R/W 0 Bit 7~6 T1M1~T1M0: Select TM1 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition. the compare values exist in 128 clock cycle multiples. the TM output pin control must be disabled. 2010 . The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. ¨ TM1C1 Register . TP1_1 10: Input capture at falling/rising edge of TP1_0.30 98 October 4. which are then compared with the internal counter's highest three bits.

T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparatror P match 1: TM1 Comparatror A match This bit is used to select the method which clears the counter. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1 register. TP1_1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the TP1_0 or TP1_1 output pin. Single Pulse or Input Capture Mode. The T1CCLR bit is not used in the PWM. The PWM output function is modified by changing these two bits. In the PWM Mode. The TM output pin can be setup to switch high. CCRA . Remember that the Standard TM contains two comparators. It has no effect if the TM is in the Timer/Counter Mode. the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. TP1_1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. switch low or to toggle its present state when a compare match occurs from the Comparator A. It has no effect if the TM is in the Timer/Counter Mode. CCRA . then no change will take place on the output.30 99 October 4. the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin when a compare match occurs.duty 1: CCRP . In the Compare Match Output Mode. When the bit is low. The function that these bits select depends upon in which mode the TM is running. With the T1CCLR bit set high. Unpredictable PWM outputs will occur if the T1IO1 and T1IO0 bits are changed when the TM is running Bit 3 T1OC: TP1_0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 These two bits are used to determine how the TM output pin changes state when a certain condition is reached. the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. It is necessary to change the values of the T1IO1 and T1IO0 bits only after the TM has been switched off. Comparator A and Comparator P.duty. 2010 . T1DPX: TM1 PWM period/duty Control 0: CCRP . In the PWM Mode it determines if the PWM signal is active high or active low. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. either of which can be selected to clear the internal counter.period. Bit 1 Bit 0 Rev. Bit 2 T1POL: TP1_0. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform.period This bit. 1. When the bits are both zero. the counter will be cleared when a compare match occurs from the Comparator A.

1.30 100 October 4. read as ²0² TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 ¨ TM1AL Register .10-bit STM Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R/W 0 0 D8 R/W 0 Bit 7~2 Bit 1~0 Unimplemented.10-bit STM Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R 0 0 D8 R 0 Bit 7~2 Bit 1~0 Unimplemented.10-bit STM Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit 7~0 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 ¨ TM1AH Register .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ TM1DL Register .10-bit STM Bit Name R/W POR 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0 Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 ¨ TM1DH Register . read as ²0² TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 Rev. 2010 .

clearing the bit disables the TM. as specified by the T2OC bit. however when the bit changes from high to low. T2CK2. 2010 . The external pin clock source can be chosen to be active on the rising or falling edge. when the T2ON bit changes from low to high. When in a Pause condition the TM will remain powered up and continue to consume power. When the bit changes state from low to high the internal counter value will be reset to zero. the internal counter will retain its residual value until the bit returns high again. The clock source fSYS is the system clock.30 101 October 4. while fH and fTBC are other internal clocks.HT66F40/HT66F50/HT66F60 ¨ TM2C0 Register . Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. 1. Unimplemented. T2CK1. the details of which can be found in the oscillator section. Setting the bit high enables the counter to run. T2CK0: Select TM2 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: undefined 110: TCK2 rising edge clock 111: TCK2 falling edge clock These three bits are used to select the clock source for the TM. read as ²0² Bit 6~4 Bit 3 Bit 2~0 Rev.16-bit STM Bit Name R/W POR 7 T2PAU R/W 0 6 T2CK2 R/W 0 5 T2CK1 R/W 0 4 T2CK0 R/W 0 3 T2ON R/W 0 2 ¾ ¾ ¾ 1 ¾ ¾ ¾ 0 ¾ ¾ ¾ Bit 7 T2PAU: TM2 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. T2ON: TM2 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Selecting the Reserved clock input will effectively disable the internal counter.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · 16-bit Standard TM Register List . Clearing the bit to zero restores normal counter operation.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60
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TM2C1 Register - 16-bit STM Bit Name R/W POR 7 T2M1 R/W 0 6 T2M0 R/W 0 5 T2IO1 R/W 0 4 T2IO0 R/W 0 3 T2OC R/W 0 2 T2POL R/W 0 1 T2DPX R/W 0 0 T2CCLR R/W 0

Bit 7~6

T2M1~T2M0: Select TM2 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T2M1 and T2M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T2IO1~T2IO0: Select TP2_0, TP2_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/ Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP2_0, TP2_1 01: Input capture at falling edge of TP2_0, TP2_1 10: Input capture at falling/rising edge of TP2_0, TP2_1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T2OC bit in the TM2C1 register. Note that the output level requested by the T2IO1 and T2IO0 bits must be different from the initial value setup using the T2OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T2ON bit from low to high. In the PWM Mode, the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T2IO1 and T2IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T2IO1 and T2IO0 bits are changed when the TM is running

Bit 5~4

Bit 3

T2OC: TP2_0, TP2_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high

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This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T2POL: TP2_0, TP2_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP2_0 or TP2_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 T2DPX: TM2 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 T2CCLR: Select TM2 Counter clear condition 0: TM2 Comparator P match 1: TM2 Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T2CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
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TM2DL Register - 16-bit STM Bit Name R/W POR 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0

Bit 7~0

TM2DL: TM2 Counter Low Byte Register bit 7~bit 0 TM2 16-bit Counter bit 7~bit 0

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TM2DH Register - 16-bit STM Bit Name R/W POR 7 D15 R 0 6 D14 R 0 5 D13 R 0 4 D12 R 0 3 D11 R 0 2 D10 R 0 1 D9 R 0 0 D8 R 0

Bit 7~0

TM2DH: TM2 Counter High Byte Register bit 7~bit 0 TM2 16-bit Counter bit 15~bit 8

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TM2AL Register - 16-bit STM Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0

Bit 7~0

TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0 TM2 16-bit CCRA bit 7~bit 0

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TM2AH Register - 16-bit STM Bit Name R/W POR 7 D15 R/W 0 6 D14 R/W 0 5 D13 R/W 0 4 D12 R/W 0 3 D11 R/W 0 2 D10 R/W 0 1 D9 R/W 0 0 D8 R/W 0

Bit 7~0

TM2AH: TM2 CCRA High Byte Register bit 7~bit 0 TM2 16-bit CCRA bit 15~bit 8

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TM2RP Register - 16-bit STM Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0

Bit 7~0

TM2RP: TM2 CCRP Register bit 7 ~ bit 0 TM2 CCRP 8-bit register, compared with the TM2 Counter bit 15 ~ bit 8. Comparator P Match Period 0: 65536 TM2 clocks 1~255: 256 x (1~255) TM2 clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter's highest eight bits. The result of this comparison can be selected to clear the internal counter if the T2CCLR bit is set to zero. Setting the T2CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value.

Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs

from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to ²0². As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place.

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Counter Value 0x3FF CCRP
Pause Stop

Counter overflow

CCRP=0

TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value
Resume Counter Restart

CCRP > 0

CCRA

Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF

TM O/P Pin
Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function

Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to itsinitial state by a TnON bit rising edge

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Counter Value 0x3FF
Resume

TnCCLR = 1; TnM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0
Stop Counter Restart

CCRA = 0 Counter overflow

CCRA CCRP

Pause

Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF
TnPF not generated Output does not change Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow

TM O/P Pin
Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function

Compare Match Output Mode -- TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. A TnPF flag is not generated when TnCCLR=1

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2010 . duty = 128/512 = 25%. while the other one is used to control the duty cycle. the TnCCLR bit has no effect as the PWM period. one for each of the CCRA and CCRP. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin. the pin can be used as a normal I/O pin or other pin-shared function. An interrupt flag. The exception is that in the Timer/Counter Mode the TM output pin is not used. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level.8125 kHz. T0DPX=0 CCRP Period Duty 001b 128 010b 256 011b 384 100b 512 CCRA 101b 640 110b 768 111b 896 000b 1024 If fSYS = 16MHz. Edge-aligned Mode. 1. heating control. CCRP = 100b and CCRA =128. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. T0DPX=1 CCRP Period Duty 001b 010b 011b 100b CCRA 101b 110b 111b 000b 128 256 384 512 640 768 896 1024 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively.30 107 October 4. a square wave AC waveform can be generated with varying equivalent DC RMS values. one register is used to clear the internal counter and thus control the PWM waveform frequency. will be generated when a compare match occurs from either Comparator A or Comparator P. TM clock source is fSYS/4. Both of the CCRA and CCRP registers are used to generate the PWM waveform. The PWM function within the TM is useful for applications which require functions such as motor control. PWM Mode. Edge-aligned Mode. In the PWM mode. If the Duty value defined by the CCRA register is equal to or greater than the Period value. PWM Output Mode To select this mode. The STM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7. the choice of generated waveform is extremely flexible. · 10-bit STM. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Timer/Counter Mode To select this mode. bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. Rev. As both the period and duty cycle of the PWM waveform can be controlled. The TnPOL bit is used to reverse the polarity of the PWM output waveform. As the TM output pin is not used in this mode. · 10-bit STM. PWM Mode. illumination control etc. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. then the PWM output duty is 100%.

TnM [1:0] = 10 Counter Reset when TnON returns high Counter Stop if TnON bit low CCRP CCRA Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. CCRP = 2 and CCRA =128. Edge-aligned Mode.30 108 October 4.8125 kHz. · 16-bit STM. T0DPX=1 CCRP Period Duty 001b CCRA CCRP ´ 256 010b 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the (CCRP x 256) except when the CCRP value is equal to 000b. T0DPX=1 CCRP Period Duty 1~255 CCRP ´ 256 CCRA 000b 65536 If fSYS = 16MHz. PWM Mode. If the Duty value defined by the CCRA register is equal to or greater than the Period value. Here TnDPX=0 ¡V Counter cleared by CCRP 2. PWM Mode. Edge-aligned Mode.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · 10-bit STM. 1. The internal PWM function continues running even when TnIO [1:0] = 00 or 01 4. A counter clear sets the PWM Period 3. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Period set by CCRP PWM Mode -. Counter Value Counter cleared by CCRP Pause Resume TnDPX = 0. TM clock source is fSYS/4. 2010 . duty = 128 / (2´512) = 25%. The TnCCLR bit has no influence on PWM operation Rev. The STM PWM output frequency = (fSYS/4) / (2´256) = fSYS/2048 = 7. then the PWM output duty is 100%.TnDPX = 0 Note: 1.

Counter cleared by CCRA 2. Here TnDPX=1 -. 1. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. TnM [1:0] = 10 Counter Reset when TnON returns high Counter Stop if TnON bit low CCRA CCRP Time TnON TnPAU TnPOL CCRP Int. 2010 . Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM Mode -.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value Counter cleared by CCRA Pause Resume TnDPX = 1.TnDPX = 1 Note: 1.30 109 October 4. Flag TnPF CCRA Int. A counter clear sets the PWM Period 3. The TnCCLR bit has no influence on PWM operation Rev.

Flag TnPF CCRA Int. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. The Single Pulse Output Mode. which will in turn initiate the Single Pulse output. will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit. T r a ilin g E d g e T n O N b it 1 ® 0 S /W C o m m a n d C L R "T n O N " o r C C R A M a tc h C o m p a re T M n O u tp u t P in P u ls e W id th = C C R A V a lu e Single Pulse Generation Counter Value TnM [1:0] = 10 . However in the Single Pulse Mode. TnIO [1:0] must be set to ²11² and can not be changed. the counter will start running and the pulse leading edge will be generated. Counter stopped by CCRA 2. which can be implemented using the application program. set by TCKn pin Software Trigger Software Trigger Software Clear Software Trigger TCKn pin TnPAU TnPOL CCRP Int.30 . the TnON bit can also be made to C o m m a n d S E T "T n O N " o r T C K n P in T r a n s itio n S /W L e a d in g E d g e T n O N b it 0 ® 1 automatically change from low to high using the external TCKn pin. CCRP is not used 3. A TCKn pin active edge will automatically set the TnON bit high 5. TnIO [1:0] = 11 Counter Reset when TnON returns high Pause Resume Counter Stops by software Counter stopped by CCRA CCRA CCRP Time TnON Software Trigger Cleared by CCRA match Auto. as the name suggests. In the Single Pulse Mode. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Single Pulse Mode To select this mode. 2010 Rev. bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. which can be implemented using the application program or when a compare match occurs from Comparator A. 110 October 4. The TnON bit should remain high when the pulse is in its active state. When the TnON bit transitions to a high level. Flag TnAF No CCRP Interrupts generated TCKn pin Trigger TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) Pulse Width set by CCRA Output Inverts when TnPOL = 1 Single Pulse Mode Note: 1. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero.

The TnCCLR and TnDPX bits are not used in this Mode. Flag TnPF CCRA Value TnIO [1:0] Value 00 Rising edge Active edge Active edge XX YY XX YY 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note: 1. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. In the Single Pulse Mode CCRP is not used. The counter is started when the TnON bit changes from low to high which is initiated using the application program. Counter cleared by CCRP TnM [1:0] = 01 Counter Counter Stop Reset CCRP YY XX Time TnON TnPAU Active edge Resume Pause TM capture pin TPn_x CCRA Int. The TnCCLR and TnDPX bits are not used in this Mode. 1. 2010 Rev. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits 2. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge. A compare match from Comparator A will also generate a TM interrupt. whose active edge can be either a rising edge. If the TnIO1 and TnIO0 bits are both set high. A TM Capture input pin active edge transfers the counter value to CCRA 3. then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin. care must be taken if the TM is in the Input Capture Mode. As the TPn_0 or TPn_1 pin is pin shared with other functions. 111 October 4. a falling edge or both rising and falling edges. No output function -. When a CCRP compare match occurs the counter will reset back to zero. When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the counter will Counter Value be latched into the CCRA registers and a TM interrupt generated. a TM interrupt will also be generated. TnCCLR bit not used 4. The external signal is supplied on the TPn_0 or TPn_1 pin. then any transitions on this pin may cause an input capture operation to be executed. When a CCRP compare match occurs from Comparator P. In this way the CCRA value can be used to control the pulse width. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. falling edge or both edge types.TnOC and TnPOL bits are not used 5. however it must be noted that the counter will continue to run.. Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. Flag TnAF CCRP Int. in this way the CCRP value can be used to control the maximum counter value.30 . CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. This is because if the pin is setup as an output. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge.

b it U p /D o w n C o u n te r C o u n te r C le a r 0 1 T n C C L R O u tp u t C o n tro l P o la r ity C o n tro l T P n A P in In p u t/O u tp u t T P n A T n O N T n P A U b 0 ~ b 9 T n A M 1 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced Type TM . The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins. TP1B_2 TP1A. TP1B_2 Enhanced TM Operation At its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. TP1B_0. ¾ 1 1 1 1 TM Input Pin ¾ TCK1 TCK1 TCK1 TCK1 TM Output Pin ¾ TP1A.ETM The Enhanced Type TM contains five operating modes.30 112 October 4. Comparator B and Comparator P. T n B M 0 T n B IO 1 . T n IO 0 Enhanced Type TM Block Diagram Rev. can be driven by different clock sources including an input pin and can also control output pins. T n B IO 0 T n B P O L T n IO 1 . All operating setup conditions are selected using relevant internal registers.b it C o m p a ra to r A C o m p a ra to r A M a tc h T n A F In te rru p t T n A IO 1 . T n A IO 0 T n A P O L T n C K 2 ~ T n C K 0 1 0 . The CCRP comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while CCRA and CCRB are 10-bits wide and therefore compared with all counter bits. When these conditions occur. TP1B_0.b it C o m p a ra to r B C o m p a ra to r B M a tc h T n B F In te rru p t E d g e D e te c to r O u tp u t C o n tro l P o la r ity C o n tro l T P n B P in In p u t/O u tp u t C C R B T n B M 1 . a TM interrupt signal will also usually be generated. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. TP1B_0. T n A IO 0 C C R A E d g e D e te c to r T n B O C T P n B -0 T P n B -1 T P n B -2 1 0 . Capture Input. is to clear the counter by changing the TnON bit from low to high. TP1B_0. 2010 . TP1B_1. T n A M 0 T n A IO 1 . The Enhanced Type TM can operate in a number of different operational modes. CCRB and CCRP registers. Timer/Event Counter. These comparators will compare the value in the counter with the CCRA. There are three internal comparators with the names. 1.b it C o m p a r a to r P T n P F In te rru p t fS Y S /4 Y S fS fH /1 6 fH /6 4 fT B C R e s e rv e d T C K n 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 b 7 ~ b 9 T n A O C 1 0 . CTM HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 Name ¾ 10-bit ETM 10-bit ETM 10-bit ETM 10-bit ETM TM No. TP1B_1 TP1A. Single Pulse Output and PWM Output modes. Comparator A. which are Compare Match Output. C C R P C o m p a ra to r P M a tc h 3 . TP1B_2 TP1A. The only way of changing the value of the 10-bit counter using the application program. TP1B_1. TP1B_1.

the internal counter will retain its residual value until the bit returns high again.10-bit ETM Bit Name R/W POR 7 T1PAU R/W 0 6 T1CK2 R/W 0 5 T1CK1 R/W 0 4 T1CK0 R/W 0 3 T1ON R/W 0 2 T1RP2 R/W 0 1 T1RP1 R/W 0 0 T1RP0 R/W 0 Bit 7 T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. A read only register pair exists to store the internal counter 10-bit value.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced Type TM Register Description Overall operation of the Enhanced TM is controlled using a series of registers. clearing the bit disables the TM. The clock source fSYS is the system clock. When in a Pause condition the TM will remain powered up and continue to consume power. while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value.30 113 October 4. while fH and fTBC are other internal clocks. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. The external pin clock source can be chosen to be active on the rising or falling edge. Rev. Setting the bit high enables the counter to run. Name TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL TM1AH TM1BL TM1BH Bit7 T1PAU T1AM1 T1BM1 D7 ¾ D7 ¾ D7 ¾ Bit6 T1CK2 T1AM0 T1BM0 D6 ¾ D6 ¾ D6 ¾ Bit5 T1CK1 T1AIO1 T1BIO1 D5 ¾ D5 ¾ D5 ¾ Bit4 T1CK0 T1AIO0 T1BIO0 D4 ¾ D4 ¾ D4 ¾ Bit3 T1ON T1AOC T1BOC D3 ¾ D3 ¾ D3 ¾ Bit2 T1RP2 T1APOL T1BPOL D2 ¾ D2 ¾ D2 ¾ Bit1 T1RP1 T1CDN T1PWM1 D1 D9 D1 D9 D1 D9 Bit0 T1RP0 T1CCLR T1PWM0 D0 D8 D0 D8 D0 D8 10-bit Enhanced TM Register List (if ETM is TM1) · 10-bit Enhanced TM Register List . Clearing the bit to zero restores normal counter operation. however when the bit changes from high to low. the details of which can be found in the oscillator section. When the bit changes state from low to high the internal counter value will be reset to zero. 1.HT66F30/HT66F40/HT66F50/HT66F60 ¨ TM1C0 Register . 2010 . The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Selecting the Reserved clock input will effectively disable the internal counter. Bit 3 T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Bit 6~4 T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM.

when the T1ON bit changes from low to high. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register. as specified by the T1OC bit.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition. the TM output pin control must be disabled. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. As the CCRP bits are only compared with the highest three counter bits. The function that these bits select depends upon in which mode the TM is running. which are then compared with the internal counter¢s highest three bits. 2010 . compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register.10-bit ETM Bit Name R/W POR 7 T1AM1 R/W 0 6 T1AM0 R/W 0 5 T1AIO1 R/W 0 4 T1AIO0 R/W 0 3 T1AOC R/W 0 2 T1APOL R/W 0 1 T1CDN R 0 0 T1CCLR R/W 0 Bit 7~6 T1AM1~T1AM0: Select TM1 CCRA Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. Bit 5~4 T1AIO1~T1AIO0: Select TP1A output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/ Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1A 01: Input capture at falling edge of TP1A 10: Input capture at falling/rising edge of TP1A 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. ¨ TM1C1 Register . In the Timer/Counter Mode. Rev. To ensure reliable operation the TM should be switched off before any changes are made to the T1AM1 and T1AM0 bits.30 114 October 4. 1. the compare values exist in 128 clock cycle multiples. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter.

switch low or to toggle its present state when a compare match occurs from the Comparator A. the counter will be cleared when a compare match occurs from the Comparator A. 2010 . Unpredictable PWM outputs will occur if the T1AIO1 and T1AIO0 bits are changed when the TM is running Bit 3 T1AOC: TP1A Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. The PWM output function is modified by changing these two bits. When the bits are both zero. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. The initial value of the TM output pin should be setup using the T1AOC bit in the TM1C1 register. Bit 2 T1APOL: TP1A Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1A output pin. Remember that the Enhanced TM contains three comparators. the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. but only Comparator A or Comparator Pan be selected to clear the internal counter. The TM output pin can be setup to switch high. It has no effect if the TM is in the Timer/Counter Mode. the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. When the bit is low. Comparator A. It is necessary to change the values of the T1AIO1 and T1AIO0 bits only after the TM has been switched off.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 In the Compare Match Output Mode. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. With the T1CCLR bit set high. The T1CCLR bit is not used in the PWM. Bit 1 T1CDN: TM1 Counter count up or down flag 0: Count up 1: Count down T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparator P match 1: TM1 Comparator A match This bit is used to select the method which clears the counter. Bit 0 Rev. Comparator B and Comparator P. the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow.30 115 October 4. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Single Pulse or Input Capture Mode. In the PWM Mode. then no change will take place on the output. Note that the output level requested by the T1AIO1 and T1AIO0 bits must be different from the initial value setup using the T1AOC bit otherwise no change will occur on the TM output pin when a compare match occurs. 1.

In the Compare Match Output Mode. When the bits are both zero. then no change will take place on the output. the TM output pin control must be disabled. TP1B_2 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. It is necessary to change the values of the T1BIO1 and T1BIO0 bits only after the TM has been switched off.10-bit ETM Bit Name R/W POR 7 T1BM1 R/W 0 6 T1BM0 R/W 0 5 T1BIO1 R/W 0 4 T1BIO0 R/W 0 3 T1BOC R/W 0 2 T1BPOL R/W 0 1 T1PWM1 R 0 0 T1PWM0 R/W 0 Bit 7~6 T1BM1~T1BM0: Select TM1 CCRB Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter mode These bits setup the required operating mode for the TM.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ TM1C2 Register . TP1B_1. To ensure reliable operation the TM should be switched off before any changes are made to the T1BM1 and T1BM0 bits. TP1B_1. In the PWM Mode. the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. TP1B_2 01: Input capture at falling edge of TP1B_0. switch low or to toggle its present state when a compare match occurs from the Comparator A. TP1B_2 10: Input capture at falling/rising edge of TP1B_0.30 116 October 4. 2010 . Unpredictable PWM outputs will occur if the T1BIO1 and T1BIO0 bits are changed when the TM is running Bit 3 T1BOC: TP1B_0. TP1B_1. In the Timer/Counter Mode. 1. The PWM output function is modified by changing these two bits. TP1B_2 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high Rev. The function that these bits select depends upon in which mode the TM is running. TP1B_1. The TM output pin can be setup to switch high. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. TP1B_1. Note that the output level requested by the T1BIO1 and T1BIO0 bits must be different from the initial value setup using the T1BOC bit otherwise no change will occur on the TM output pin when a compare match occurs. the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. Bit 5~4 T1BIO1~T1BIO0: Select TP1B_0. The initial value of the TM output pin should be setup using the T1BOC bit in the TM1C2 register. TP1B_2 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1B_0.

10-bit ETM Bit Name R/W POR 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0 Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 ¨ TM1DH Register .30 117 October 4. compare match on count up 10: Centre aligned. It has no effect if the TM is in the Timer/Counter Mode. compare match on count up or down ¨ TM1DL Register .10-bit ETM Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit 7~0 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 ¨ TM1AH Register . In the PWM Mode it determines if the PWM signal is active high or active low. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. TP1B_2 output pin. compare match on count down 11: Centre aligned. 1. Bit 1~0 T1PWM1~T1PWM0: Select PWM Mode 00: Edge aligned 01: Centre aligned. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero.10-bit ETM Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R 0 0 D8 R 0 Bit 7~2 Bit 1~0 Unimplemented. read as ²0² TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 Rev. TP1B_1. read as ²0² TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 ¨ TM1AL Register .10-bit ETM Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R/W 0 0 D8 R/W 0 Bit 7~2 Bit 1~0 Unimplemented.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 This is the output control bit for the TM output pin. Bit 2 T1BPOL: TP1B_0. 2010 . TB1B_2 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1B_0. TP1B_1.

One is when a compare match occurs from Comparator P. PWM Output Mode. bits TnAM1. TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. 2010 . However. will both be generated. Compare Match Output Mode.30 118 October 4. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1. These are a counter overflow.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ TM1BL Register . here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. ²¾² : not permitted Compare Output Mode To select this mode.10-bit ETM Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R/W 0 0 D8 R/W 0 Bit 7~2 Bit 1~0 Unimplemented. ETM Operating Mode CCRB Compare Match Output Mode CCRB Timer/Counter Mode CCRB PWM Output Mode CCRB Single Pulse Output Mode CCRB Input Capture Mode CCRA ComCCRA CCRA Single CCRA Input CCRA PWM pare Match Timer/CounPulse Output Capture Output Mode Output Mode ter Mode Mode Mode Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ²Ö²: permitted.10-bit ETM Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit 7 ~ 0 TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0 TM1 10-bit CCRB bit 7~bit 0 ¨ TM1BH Register . Here both the TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively. TnAM0 and TnBM1. and the TnBM1 and TnBM0 bits in the TMnC2 register. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. Capture Input Mode or Timer/Counter Mode. a compare match from Comparator A and a compare match from Comparator P. 1. Rev. there are two ways in which the counter can be cleared. read as ²0² TM1BH: TM1 CCRB High Byte Register bit 1~bit 0 TM1 10-bit CCRB bit 9 ~ bit 8 Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes. In this mode once the counter is enabled and running it can be cleared by three methods. Single Pulse Output Mode. the other is when the CCRP bits are all zero which allows the counter to overflow. When the TnCCLR bit is low.

TnAIO0 and TnBIO1. 2010 . The TM output pin can be selected using the TnAIO1. 1. will have no effect on the TM output pin. will change state. TnBIO0 bits (for the TPnB_0. The TM output pin condition however only changes state when an TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator A or Comparator B. The TPnA output pin is controlled only by the TnAF flag 3. With TnCCLR=0 a Comparator P match will clear the counter 2. the TM output pin. TPnB_2 output pins. Flag TnPF CCRA Int. The TnPF interrupt request flag. TPnB_1 or TPnB_2 pins) to go high. TnAIO0 bits (for the TPnA pin) and TnBIO1. The output pin is reset to its initial state by a TnON bit rising edge Rev.30 119 October 4. Counter Value 0x3FF CCRP Counter overflow CCRP=0 TnCCLR = 0. to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 As the name of the mode suggests. is setup using the TnAOC or TnBOC bit for TPnA or TPnB_0. Flag TnAF TPnA O/P Pin Output pin set to initial Level Low if TnAOC=0 Output Toggle with TnAF flag Here TnAIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. Note that if the TnAIO1. generated from a compare match from Comparator P. which is setup after the TnON bit changes from low to high. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA.TnCCLR = 0 Note: 1. TPnB_1. TnBIO0 bits are zero then no pin change will take place. The initial condition of the TM output pin. TnAM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value Resume Pause Stop Counter Restart CCRP > 0 CCRA Time TnON TnPAU TnAPOL CCRP Int. after a comparison is made. Remains High until reset by TnON bit Note TnAIO [1:0] = 10 Active High Output select Output Inverts when TnAPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function ETM CCRA Compare Match Output Mode -. and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB.

Flag TnBF TPnB O/P Pin Output pin set to initial Level Low if TnBOC=0 Output Toggle with TnBF flag Here TnBIO [1:0] = 11 Toggle Output select Output not affected by TnBF flag.TnCCLR = 0 Note: 1. The output pin is reset to its initial state by a TnON bit rising edge Rev. With TnCCLR=0 a Comparator P match will clear the counter 2. 1. The TPnB output pin is controlled only by the TnBF flag 3. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value 0x3FF CCRP Pause Stop Counter overflow CCRP=0 TnCCLR = 0. TnBM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value Resume Counter Restart CCRP > 0 CCRB Time TnON TnPAU TnBPOL CCRP Int. Remains High until reset by TnON bit Note TnBIO [1:0] = 10 Active High Output select Output Inverts when TnBPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function ETM CCRB Compare Match Output Mode -.30 120 October 4. Flag TnPF CCRB Int.

Remains High until reset by TnON bit Note TnAIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow TPnA O/P Pin Output pin set to initial Level Low if TnAOC=0 Output Toggle with TnAF flag Here TnAIO [1:0] = 11 Toggle Output select Output Inverts when TnAPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function ETM CCRA Compare Match Output Mode -. The TPnA output pin is controlled only by the TnAF flag 3.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value 0x3FF Resume TnCCLR = 1. TnAM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0 Stop Counter Restart CCRA = 0 Counter overflow CCRA CCRP Pause Time TnON TnPAU TnAPOL CCRA Int. The TPnA output pin is reset to its initial state by a TnON bit rising edge 4. Flag TnPF TnPF not generated Output does not change Output not affected by TnAF flag. The TnPF flag is not generated when TnCCLR=1 Rev. 2010 .TnCCLR = 1 Note: 1.30 121 October 4. Flag TnAF CCRP Int. With TnCCLR=1 a Comparator A match will clear the counter 2. 1.

With TnCCLR=1 a Comparator A match will clear the counter 2. 2010 . Flag TnBF No TnAF flag generated on CCRA overflow TPnB O/P Pin Output pin set to initial Level Low if TnBOC=0 Output Toggle with TnBF flag Output not affected by TnBF flag. TnBM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0 Stop Counter Restart CCRA = 0 Counter overflow CCRA CCRB Pause Time TnON TnPAU TnBPOL CCRA Int. Remains High until reset by TnON bit Note TnBIO [1:0] = 10 Active High Output select Output Inverts when TnBPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Here TnBIO [1:0] = 11 Toggle Output select ETM CCRB Compare Match Output Mode -. 1. The TPnB output pin is reset to its initial state by a TnON bit rising edge 4. The TPnB output pin is controlled only by the TnBF flag 3.TnCCLR = 1 Note: 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value 0x3FF Resume TnCCLR = 1.30 122 October 4. Flag TnAF CCRB Int. The TnPF flag is not generated when TnCCLR=1 Rev.

bits TnAM1.8125kHz. a square wave AC waveform can be generated with varying equivalent DC RMS values. TnBM0 should be set to 10 respectively and also the TnAIO1. The PWM output can only be generated on the TPnB output pins. CCRA = 128 and CCRB = 256. 2010 . TnAM0 and TnBM1. With the TnCCLR bit set high. As the TM output pin is not used in this mode. the TnCCLR bit is used to determine in which way the PWM period is controlled. Edge-aligned Mode. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. TnAIO0 and TnBIO1. In edge alignment. TnAM1. heating control. The exception is that in the Timer/Counter Mode the TM output pin is not used. which can be either edge or centre type. CCRP Period A Duty B Duty 001b 128 010b 256 011b 384 100b 512 CCRA CCRB 101b 640 110b 768 111b 896 000b 1024 If fSYS = 16MHz.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Timer/Counter Mode To select this mode. Interrupt flags. In centre alignment the centre of the PWM active signals will occur sequentially. PWM Output Mode To select this mode. then the PWM output duty is 100%. TnCCLR=0 can be finely controlled using the CCRA registers. · ETM. TnBIO0 bits pairs are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPWM1 and TnPWM0 bits determine the PWM alignment type. duty = 256/512 = 50%. CCRB and CCRP. the required bit pairs. the pin can be used as a normal I/O pin or other pin-shared function. PWM Mode. The TnAOC and TnBOC bits in the TMnC1 and TMnC2 register are used to select the required polarity of the PWM waveform while the two TnAIO1. TnCCLR=1 CCRA Period B Duty 1 1 2 2 3 3 511 511 CCRB 512 512 1021 1021 1022 1022 1023 1023 · ETM.8125kHz. one for each of the CCRA. If the Duty value defined by CCRA or CCRB register is equal to or greater than the Period value. With the TnCCLR bit cleared to zero. TnBIO0 bits should be set to 10 respectively. In the PWM mode.30 123 October 4. The PWM function within the TM is useful for applications which require functions such as motor control. duty = 128/512 = 25%. TnAM0 and TnBM1. this may give rise to problems in higher power applications. Comparator B or Comparator P. The TP1B_n PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7. Edge-aligned Mode. TnCCLR=0 CCRP Period A Duty B Duty 001b 256 010b 512 011b 768 100b 1024 101b 1280 110b 1536 111b 1792 000b 2046 (CCRA´2)-1 (CCRB´2)-1 Rev. The TP1A PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin. The TnAPOL and TnBPOL bit are used to reverse the polarity of the PWM output waveform. in multiples of 128. In this case the CCRB registers are used to set the PWM duty value (for TPnB output pins). Now both CCRA and CCRB registers can be used to setup different duty cycle values to provide dual PWM outputs on their relative TPnA and TPnB pins. 1. the PWM period is set using one of the eight values of the three CCRP bits. TnAIO0 and TnBIO1. PWM Mode. will be generated when a compare match occurs from either the Comparator A. the leading edge of the PWM signals will all be generated concurrently when the counter is reset to zero. TnBM0 in the TMnC1 and TMnC2 register should all be set high. CCRP = 100b. the choice of generated waveform is extremely flexible. PWM Mode. TM clock source select fSYS/4. illumination control etc. With all power currents switching on at the same time. thus reducing the level of simultaneous power switching currents. Center-aligned Mode. The CCRP bits are not used and TPnA output pin is not used. the PWM period · ETM. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. As both the period and duty cycle of the PWM waveform can be controlled.

TnAM [1:0] = 10. Flag TnBF CCRP Int. TnCCLR=1 CCRA Period B Duty 1 2 2 4 3 6 511 1022 512 1024 1021 2042 1022 2044 1023 2046 (CCRB´2)-1 Counter Value Counter Cleared by CCRP CCRP CCRA TnCCLR = 0. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01 3. Here TnCCLR=0 therefore CCRP clears counter and determines the PWM period 2. PWM Mode. 1. Flag TnPF TPnA Pin (TnAOC=1) Duty Cycle set by CCRA Duty Cycle set by CCRA Duty Cycle set by CCRA Output Inverts when TnAPOL is high TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) Duty Cycle set by CCRB Output controlled by other pin-shared function Output Pin Reset to Initial value PWM Period set by CCRP ETM PWM Mode -.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · ETM. TnBM [1:0] = 10. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty Rev. 2010 .Edge Aligned Note: 1.30 124 October 4. Flag TnAF CCRB Int. TnPWM [1:0] = 00 Pause Resume Stop Counter Restart CCRB Time TnON TnPAU TnAPOL CCRA Int. Center-aligned Mode.

1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value Counter Cleared by CCRA CCRA Resume Counter Restart TnCCLR = 1. Rev. TnPWM [1:0] = 00 Pause Stop CCRB Time TnON TnPAU TnBPOL CCRP Int. Here the TM pin control register should not enable the TPnA pin as a TM output pin. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 3. The CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 4. Flag TnPF CCRB Int.30 125 October 4. TnBM [1:0] = 10.Edge Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. 2010 . Flag TnBF TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) Duty Cycle set by CCRB Output controlled by other pin-shared function Output Pin Reset to Initial value Output Inverts when TnBPOL is high PWM Period set by CCRA ETM PWM Mode -.

Flag TnAF CCRB Int.Centre Aligned Note: 1. TnAM [1:0] = 10. TnPWM [1:0] =11 therefore the PWM is centre aligned 3. 2010 . CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty 5. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period 2. TnBM [1:0] = 10. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01 4. Flag TnPF TPnA Pin (TnAOC=1) Duty Cycle set by CCRA TPnB Pin (TnBOC=1) Output Inverts when TnAPOL is high TPnB Pin (TnBOC=0) Duty Cycle set by CCRB PWM Period set by CCRP Output controlled by Other pin-shared function Output Pin Reset to Initial value ETM PWM Mode -. 1. TnPWM [1:0] = 11 Stop Counter Restart CCRP CCRA CCRB Resume Pause Time TnON TnPAU TnAPOL CCRA Int. CCRP will generate an interrupt request when the counter decrements to its zero value Rev. Flag TnBF CCRP Int.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value TnCCLR = 0.30 126 October 4.

TnPWM [1:0] =11 therefore the PWM is centre aligned 3.30 127 October 4.Centre Aligned Note: 1. 1. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 4. Flag TnBF CCRP Int. TnPWM [1:0] = 11 Stop Counter Restart CCRP CCRA CCRB Resume Pause Time TnON TnPAU TnAPOL CCRA Int.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value TnCCLR = 0. 2010 . TnAM [1:0] = 10. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 5. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. Flag TnAF CCRB Int. TnBM [1:0] = 10. CCRP will generate an interrupt request when the counter decrements to its zero value Rev. Flag TnPF TPnA Pin (TnAOC=1) Duty Cycle set by CCRA TPnB Pin (TnBOC=1) Output Inverts when TnAPOL is high TPnB Pin (TnBOC=0) Duty Cycle set by CCRB PWM Period set by CCRP Output controlled by Other pin-shared function Output Pin Reset to Initial value ETM PWM Mode -.

The TnON bit should remain high when the pulse is in its active state. However in the Single Pulse Mode. the counter will start running and the pulse leading edge of TPnA will be generated. In this way the CCRA value can be used to control the pulse width of TPnA. In the Single Pulse Mode CCRP is not used. the required bit pairs. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit.30 128 October 4. will generate a single shot pulse on the TM output pin. which can be implemented using the application program. as the name suggests. 1. Single Pulse Generation Rev. which will in turn initiate the Single Pulse output of TPnA. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB. The CCRA-CCRB value can be used to control the pulse width of TPnB. 2010 . TnAM0 and TnBM1. TnBIO0 bits should be set to 11 respectively. TnBM0 should be set to 10 respectively and also the corresponding TnAIO1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Single Pulse Output Mode To select this mode. TnAIO0 and TnBIO1. The trigger for the pulse TPnB output leading edge is a compare match from Comparator B. TnAM1. The Single Pulse Output Mode. When the TnON bit transitions to a high level. The generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to zero. which can be implemented using the application program. The TnCCLR bit is also not used. the TnON bit can also be made to automatically change from low to high using the external TCKn pin. which can be implemented using the application program or when a compare match occurs from Comparator A. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. A compare match from Comparator A and Comparator B will also generate TM interrupts.

TnBIO [1:0] = 11 Counter Reset when TnON returns high Counter stopped by CCRA CCRA Pause Resume Counter Stops by software CCRB Time TnON Software Trigger Cleared by CCRA match Auto. CCRP is not used 3. 1. Rev. A TCKn pin active edge will automatically set the TnON bit high 5. TnAIO [1:0] and TnBIO [1:0] must be set to ²11² and can not be changed. Counter stopped by CCRA 2.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Counter Value TnAM [1:0] = 10. Flag TnAF TPnA Pin (TnAOC=1) TCKn pin Trigger TPnA Pin (TnAOC=0) Pulse Width set by CCRA Output Inverts when TnAPOL=1 TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) Pulse Width set by (CCRA-CCRB) Output Inverts when TnBPOL=1 ETM -. In the Single Pulse Mode.30 129 October 4. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. Flag TnBF CCRA Int. TnAIO [1:0] = 11.Single Pulse Mode Note: 1. 2010 . TnBM [1:0] = 10. set by TCKn pin Software Trigger Software Trigger Software Clear Software Trigger TCKn pin TnPAU TnAPOL TnBPOL CCRB Int.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Capture Input Mode To select this mode bits TnAM1. TnBOC. When a CCRP compare match occurs from Comparator P. No output function -. TnAOC. then any transitions on this pin may cause an input capture operation to be executed. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. Flag TnAF CCRP Int. TPnB_2 pins. Flag TnPF CCRA Value TnAIO [1:0] Value XX Active edge Active edge YY XX YY 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture ETM CCRA Capture Input Mode Note: 1. As the TPnA and TPnB_0. TPnB_1. TPnB_1. TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low. TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. TnAM [1:0] = 01 and active edge set by the TnAIO [1:0] bits 2. The external signal is supplied on the TPnA and TPnB_0. TPnB_1. Irrespective of what events occur on the TPnA and TPnB_0. 1. TPnB_2 pins to be a rising edge. falling edge or both edge types. The TM Capture input pin active edge transfers he counter value to CCRA 3. TnBIO0 bits in the TMnC1 and TMnC2 registers. The TnCCLR. TPnB_1. TnAIO0 and TnBIO1. Counter Value Counter cleared by CCRP TnAM [1:0] = 01 Counter Counter Stop Reset CCRP YY XX Time TnON TnPAU Active edge Resume Pause TM capture pin TPnA CCRA Int. 2010 . TnBIO0 bits are both set high. in this way the CCRP value can be used to control the maximum counter value. TnAM0 and TnBM1. TPnB_1. the active edge transition type is selected using the TnAIO1. The counter is started when the TnON bit changes from low to high which is initiated using the application program. TPnB_2 pins the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. TnCCLR bit not used 4. a TM interrupt will also be generated. care must be taken if the TM is in the Capture Input Mode.30 130 October 4. TPnB_2 pins. If the TnAIO1. then no capture operation will take place irrespective of what happens on the TPnA and TPnB_0. TnAPOL and TnBPOL bits are not used in this mode. TPnB_1. The TnAIO1. however it must be noted that the counter will continue to run. TnBIO0 bits can select the active trigger edge on the TPnA and TPnB_0. a falling edge or both rising and falling edges.TnAOC and TnAPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. When a CCRP compare match occurs the counter will reset back to zero. When the required edge transition appears on the TPnA and TPnB_0. TnAIO0 and TnBIO1. whose active edge can be either a rising edge. TPnB_2 pins are pin shared with other functions. Rev. This is because if the pin is setup as an output. TnAIO0 and TnBIO1.

TnBM [1:0] = 01 and active edge set by the TnBIO [1:0] bits 2.Both edges 11 . The TM Capture input pin active edge transfers the counter value to CCRB 3.Rising edge 01 . CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. TnBIO0 Value XX YY XX YY 00 . Flag TnBF CCRP Int. No output function -. Flag TnPF CCRB Value TnBIO1.30 131 October 4. Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 TnBM1.Falling edge 10 .Disable Capture ETM CCRB Capture Input Mode Note: 1. 2010 . 1. TnCCLR bit not used 4.TnBOC and TnBPOL bits not used 5. TnBM0 = 01 Counter Value CCRP YY XX Pause Resume Counter overflow Stop Counter Reset Time TnON bit TnPAU bit Active edge Active edge Active edges TM Capture Pin CCRB Int.

the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. ACS2~ACS0 ACS4. A read only register pair exists to store the ADC data 12-bit value. By integrating the A/D conversion electronic circuitry into the microcontroller. 1. ACS3~ACS0 Input Pins Part No. The remaining three or four registers are control registers which setup the operating and control function of the A/D converter.30 132 October 4. Input Channels A/D Channel Select Bits ACS4. HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 8 AN0~AN7 12 AN0~AN11 The accompanying block diagram shows the overall internal structure of the A/D converter. A/D Converter Register Description Overall operation of the A/D converter is controlled using six registers. to properly process these signals by a microcontroller. However. 2010 . such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. A/D Overview The devices contains a multi-channel analog to digital converter which can directly interface to external analog signals. together with its associated registers. they must first be converted into digital signals by A/D converters. Register Name ADRL(ADRFS=0) ADRL(ADRFS=1) ADRH(ADRFS=0) ADRH(ADRFS=1) ADCR0 ADCR1 ACERL Bit 7 D3 D7 D11 ¾ START ACS4 ACE7 6 D2 D6 D10 ¾ EOCB V125EN ACE6 5 D1 D5 D9 ¾ ADOFF ¾ ACE5 4 D0 D4 D8 ¾ ADRFS VREFS ACE4 3 ¾ D3 D7 D11 ¾ ¾ ACE3 2 ¾ D2 D6 D10 ACS2 ADCK2 ACE2 1 ¾ D1 D5 D9 ACS1 ADCK1 ACE1 0 ¾ D0 D4 D8 ACS0 ADCK0 ACE0 HT66F20/HT66F30/HT66F40/HT66F50 A/D Converter Register List Bit 7 D3 D7 D11 ¾ START ACS4 ACE7 ¾ 6 D2 D6 D10 ¾ EOCB V125EN ACE6 ¾ 5 D1 D5 D9 ¾ ADOFF ¾ ACE5 ¾ 4 D0 D4 D8 ¾ ADRFS VREFS ACE4 ¾ 3 ¾ D3 D7 D11 ACS3 ¾ ACE3 ACE11 2 ¾ D2 D6 D10 ACS2 ADCK2 ACE2 ACE10 1 ¾ D1 D5 D9 ACS1 ADCK1 ACE1 ACE9 0 ¾ D0 D4 D8 ACS0 ADCK0 ACE0 ACE8 Register Name ADRL(ADRFS=0) ADRL(ADRFS=1) ADRH(ADRFS=0) ADRH(ADRFS=1) ADCR0 ADCR1 ACERL ACERH HT66F60 A/D Converter Register List Rev.

Any unused bits will be read as zero. As the device contains only one actual analog to digital converter hardware circuit. ADCR1.ADRL. ADRFS 0 1 ADRH 7 D11 0 6 D10 0 5 D9 0 4 D8 0 3 D7 D11 2 D6 D10 1 D5 D9 0 D4 D8 7 D3 D7 6 D2 D6 5 D1 D5 ADRL 4 D0 D4 3 0 D3 2 0 D2 1 0 D1 0 0 D0 A/D Data Registers A/D Converter Control Registers ADCR0. known as ADRL.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 fS A D C K 2 ~ A D C K 0 A C E 1 1 ~ A C E 0 A /D ¸ 2 Y S V D D N (N = 0 ~ 6 ) P B 5 /V R E F A D O F F B it A /D V R E F S B it R e fe r e n c e V o lta g e A D R L A D R H V S S C lo c k P A 0 /A N P E P E P F P F 0 ~ P 6 /A 7 /A 0 /A N 1 /A N A 7 /A N 7 N 8 N 9 1 0 1 1 1 . its original function whether it is an I/O or other pin-shared function will be removed. When the pin is selected to be an A/D input.30 133 October 4.2 5 V V 1 2 5 E N A C S 4 ~ A C S 0 S T A R T A /D C o n v e rte r A /D D a ta R e g is te r s A D R F S b it E O C B A D O F F A/D Converter Structure A/D Converter Data Registers . ACERL and ACERH are provided. the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. these registers can be directly read by the microcontroller to obtain the digitised conversion value. These are a high byte register. In addition. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter. and a low byte register. The ACERH and ACERL control registers contain the ACER11~ACER0 bits which determine which pins on Port A.25V is actually connected to the internal A/D converter. each of the individual 8 or 12 analog inputs must be routed to the converter. It is the function of the ACS4~ACS0 bits to determine which analog channel input pins or internal 1. clearing the bit to zero will select either the I/O or other pin-shared function. ACERL. three or four control registers known as ADCR0. The ACS3~ACS0 bits in the ADCR0 register and ACS4 bit is the ADCR1 register define the ADC input channel number. After the conversion process takes place. known as ADRH. Rev. PE6. ADCR1. Setting the corresponding bit high will select the A/D input function. any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. ADRH As the devices contain an internal 12-bit A/D converter. As only 12 bits of the 16-bit register space is utilised. the digitised data format. PF0 and PF1 are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. ACERH To control the function and operation of the A/D converter. they require two data registers to store the converted value. 1. 2010 . PE7. the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits.

Bit 3 Bit 2~0 unimplemented. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the bit is set high the A/D converter will be reset. The bit is normally low but if set high and then cleared low again.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · ADCR0 Register ¨ HT66F20/HT66F30/HT66F40/HT66F50 Bit Name R/W POR 7 START R/W 0 6 EOCB R 1 5 ADOFF R/W 1 4 ADRFS R/W 0 3 ¾ ¾ ¾ 2 ACS2 R/W 0 1 ACS1 R/W 0 0 ACS0 R/W 0 Bit 7 START: Start the A/D conversion 0®1®0 : start 0®1 : reset the A/D converter and set EOCB to ²1² This bit is used to initiate an A/D conversion process. Note: 1. this may be an important consideration in power sensitive battery powered applications. 2010 . If bit ACS4 in the ADCR1 register is set high then the internal 1. Bit 5 ADOFF : ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. read as ²0² ACS2.30 134 October 4. the A/D converter will initiate a conversion process. ADOFF=1 will power down the ADC module. Details are provided in the A/D data register section. As the A/D converter will consume a limited amount of power. even when not executing a conversion.25V will be routed to the A/D Converter. This bit should be cleared to zero to enable the A/D converter. LSB is ADRL bit 4 1: ADC Data MSB is ADRH bit 3. When the conversion process is running the bit will be high. 1. LSB is ADRL bit 0 This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. As there is only one internal hardware A/D converter each of the eight A/D inputs must be routed to the internal converter using these bits. ACS1. Rev. ACS0: Select A/D channel (when ACS4 is ²0²) 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 These are the A/D channel select control bits. Bit 4 ADRFS: ADC Data Format Control 0: ADC Data MSB is ADRH bit 7. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. If the bit is set high then the A/D converter will be switched off reducing the device power consumption.

it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. ACS1. 1. ADOFF=1 will power down the ADC module. Bit 5 ADOFF : ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. As there is only one internal hardware A/D converter each of the eight A/D inputs must be routed to the internal converter using these bits. even when not executing a conversion. the A/D converter will initiate a conversion process. The bit is normally low but if set high and then cleared low again. This bit should be cleared to zero to enable the A/D converter. LSB is ADRL bit 4 1: ADC Data MSB is ADRH bit 3.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · ADCR0 Register ¨ HT66F60 Bit Name R/W POR 7 START R/W 0 6 EOCB R 1 5 ADOFF R/W 1 4 ADRFS R/W 0 3 ACS3 R/W 0 2 ACS2 R/W 0 1 ACS1 R/W 0 0 ACS0 R/W 0 Bit 7 START: Start the A/D conversion 0®1®0 : start 0®1 : reset the A/D converter and set EOCB to ²1² This bit is used to initiate an A/D conversion process. If bit ACS4 in the ADCR1 register is set high then the internal 1.25V will be routed to the A/D Converter. Bit 3~0 ACS3. ACS2. As the A/D converter will consume a limited amount of power. LSB is ADRL bit 0 This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. can¢t be used These are the A/D channel select control bits. this may be an important consideration in power sensitive battery powered applications. Note: 1. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. Rev. ACS0: Select A/D channel (when ACS4 is ²0²) 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000: AN8 1001: AN9 1010: AN10 1011: AN11 1100~1111: undefined.30 135 October 4. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. 2010 . 2. When the bit is set high the A/D converter will be reset. Bit 4 ADRFS: ADC Data Format Control 0: ADC Data MSB is ADRH bit 7. When the conversion process is running the bit will be high.

25V voltage will be routed to the A/D converter and the other A/D input channels disconnected. Bit 5 Bit 4 unimplemented.25V can be used by the A/D converter. 1. read as ²0² ADCK2. the bandgap 1. If 1.25V as ADC input Control 0: Disable 1: Enable This bit enables 1. If the pin is low. The V125EN bit must first have been set to enable the bandgap circuit 1.25V to be connected to the A/D converter. When the ACS4 bit is set high. ADCK1. Rev. If the bit is high.25V Control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. then the internal reference is used which is taken from the power supply pin VDD. a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion.30 136 October 4. then the A/D converter reference voltage is supplied on the external VREF pin.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · ADCR1 Register Bit Name R/W POR Bit 7 7 ACS4 R/W 0 6 V125EN R/W 0 5 ¾ ¾ ¾ 4 VREFS R/W 0 3 ¾ ¾ ¾ 2 ADCK2 R/W 0 1 ADCK1 R/W 0 0 ADCK0 R/W 0 ACS4: Selecte Internal 1.25V is switched on for use by the A/D converter. When the bit is set high the bandgap voltage 1. ADCK0: Select ADC clock source 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These three bits are used to select the clock source for the A/D converter.25V voltage to be used by the A/D converter. Bit 6 V125EN: Internal 1.25V is not used by the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. read as ²0² VREFS: Selecte ADC reference voltage 0: Internal ADC power 1: VREF pin This bit is used to select the reference voltage for the A/D converter. Bit 3 Bit 2~0 unimplemented. 2010 . When 1.

AN4 ACE3: Define PA3 is A/D input or not 0: Not A/D input 1: A/D input. AN1 ACE0: Define PA0 is A/D input or not 0: Not A/D input 1: A/D input. AN0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 · ACERH Register ¨ HT66F60 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ACE11 R/W 1 2 ACE10 R/W 1 1 ACE9 R/W 1 0 ACE8 R/W 1 Bit 7~4 Bit 3 unimplemented.30 137 October 4. AN2 ACE1: Define PA1 is A/D input or not 0: Not A/D input 1: A/D input. read as ²0² ACE11: Define PF1 is A/D input or not 0: Not A/D input 1: A/D input. AN7 ACE6: Define PA6 is A/D input or not 0: Not A/D input 1: A/D input.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · ACERL Register Bit Name R/W POR Bit 7 7 ACE7 R/W 1 6 ACE6 R/W 1 5 ACE5 R/W 1 4 ACE4 R/W 1 3 ACE3 R/W 1 2 ACE2 R/W 1 1 ACE1 R/W 1 0 ACE0 R/W 1 ACE7: Define PA7 is A/D input or not 0: Not A/D input 1: A/D input. AN10 ACE9: Define PE7 is A/D input or not 0: Not A/D input 1: A/D input. 1. AN5 ACE4: Define PA4 is A/D input or not 0: Not A/D input 1: A/D input. AN9 ACE8: Define PE6 is A/D input or not 0: Not A/D input 1: A/D input. AN8 Bit 2 Bit 1 Bit 0 Rev. AN11 ACE10: Define PF0 is A/D input or not 0: Not A/D input 1: A/D input. 2010 . AN6 ACE5: Define PA5 is A/D input or not 0: Not A/D input 1: A/D input. AN3 ACE2: Define PA2 is A/D input or not 0: Not A/D input 1: A/D input.

depending upon the device. ADCK1. ADCK0 = 011 (fSYS/8) 8ms 4ms 2ms 1ms 667ns ADCK2. As the VREF pin is pin-shared with other Rev. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. is 0. The desired selection is made using the VREFS bit. which are setup through register programming. an analog to digital conversion cycle will be initiated. The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin. which originates from the system clock fSYS.5ms. the VREF pin function will be selected and the other pin functions will be disabled automatically.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. ADCK0 = 010 (fSYS/4) 4ms 2ms 1ms 500ns 333ns* ADCK2. The ACE11~ ACE0 bits in the ACERH and ACERL registers. there are some limitations on the maximum A/D clock source speed that can be selected. or from an external reference sources supplied on pin VREF. ADCK1. When the microcontroller sets this bit from low to high and then low again. 2010 . as the values may be less than the specified minimum A/D Clock Period. must be allowed before an A/D conversion is initiated. The clock source for the A/D converter. where values marked with an asterisk * show where. When the START bit is brought from low to high but not low again.33ms ADCK2. For example. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. PF7. ADCK1. 1. PE6. the ADCK2~ADCK0 bits should not be set to ²000². In this way. ADCK1. an appropriate internal interrupt signal will be generated. Although the A/D clock source is determined by the system clock fSYS. If the A/D internal interrupt is disabled. If the ACE11~ ACE0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. ADCK0 = 001 (fSYS/2) 2ms 1ms 500ns 250ns* 167ns* ADCK2. ADCK0 = 000 (fSYS) 1ms 500ns 250ns* 125ns* 83ns* ADCK2. can be chosen to be either fSYS or a subdivided version of fSYS. ADCK0 = 100 (fSYS/16) 16ms 8ms 4ms 2ms 1. will be automatically disconnected if the pins are setup as A/D inputs. All pull-high resistors. Note that it is not necessary to first setup the A/D October 4. In addition. As the minimum value of permissible A/D clock period. The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions.67ms ADCK2. the corresponding A/D interrupt request flag will be set in the interrupt control register. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay. the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. This bit must be zero to power on the A/D converter. ADCK1. as indicated in the timing diagram. and if the interrupts are enabled. pins can be changed under program control to change their function between A/D inputs and other functions.30 138 functions. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A. tADCK. A/D Clock Period (tADCK) fSYS ADCK2. PF0 or PF1 as well as other functions. if the system clock operates at a frequency of 4MHz. the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. ADCK0 = 111 Undefined Undefined Undefined Undefined Undefined 1MHz 2MHz 4MHz 8MHz 12MHz A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. VDD. when the VREFS bit is set high. Refer to the following table for examples. if the ADOFF bit is zero then some power will still be consumed. This bit will be automatically set to ²0² by the microcontroller after a conversion cycle has ended. care must be taken for system clock frequencies equal to or greater than 4MHz. ADCK0 = 110 (fSYS/64) 64ms 32ms 16ms 8ms 5. special care must be taken. ADCK1. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. Even if no pins are selected for use as A/D inputs by clearing the ACE11~ACE0 bits in the ACERH and ACERL registers.33ms ADCK2. ADCK0 = 101 (fSYS/32) 32ms 16ms 8ms 4ms 2. and by bits ADCK2~ADCK0. ADCK1. ADCK1.

the status of the port control register will be overridden. the EOCB bit in the ADCR0 register can be polled. 1. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. · Step 7 A/D Input Structure Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. The analog input values must not be allowed to exceed the value of VREF. The conversion process is complete when this bit goes low. · Step 2 To check when the analog to digital conversion process is complete. and the A/D converter interrupt bit. EMI. A D O F F tO A D C M o d u le O N o ff o n N 2 S T A /D tA D S s a m p lin g tim e A /D tA D S s a m p lin g tim e o ff o n S T A R T E O C B A C S 4 ~ A C S 0 0 0 0 1 1 B P o w e r-o n R e s e t R e s e t A /D c o n v e rte r 1 : D e fin e p o r t c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D 0 0 0 1 0 B S ta rt o f A /D c o n v e r s io n 0 0 0 0 0 B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 0 0 0 0 1 B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e A /D tA D C c o n v e r s io n tim e A/D Conversion Timing Rev. · Step 4 Select which pins are to be used as A/D inputs and configure them by correctly programming the ACE11~ACE0 bits in the ACERH and ACERL registers.b it A D C V R E F S V D D B a n d g a p R e fe re n c e V o lta g e V R E F P B 5 /V R E F The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from low to high and then low again. · Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero. if the method of polling the EOCB bit in the ADCR0 register is used. P A 0 /A N 0 A C S 4 ~ A C S 0 In p u t V o lta g e B u ffe r V 1 2 5 E N P F 1 /A N 1 1 1 . · Step 5 If the interrupts are to be used. the interrupt enable step above can be omitted. a choice which is made through the VREFS bit in the ADCR1 register. the program can wait for an A/D interrupt to occur. however the reference voltage can also be supplied from the power supply pin. · Step 6 1 2 . The A/D converter has its own reference voltage pin.30 139 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 pin as an input in the PAC. Note: When checking for the end of the conversion process. the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. As an alternative method.2 5 V · Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4~ACS0 bits which are also contained in the ADCR1 and ADCR0 register. PEC or PFC port control register to enable the A/D input as when the ACE11~ ACE0 bits enable an A/D input. 2010 . EADI. if the interrupts are enabled and the stack is not full. VREF. The master interrupt control bit. must both be set high to do this. Note that this bit should have been originally cleared to zero.

the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete. After an A/D conversion process has been initiated by the application program. its full-scale converted digitised value is equal to FFFH. during which time the program can continue with other functions. When this happens. then this may lead to some increase in power consumption.30 140 October 4. then care must be taken as if the input voltage is not at a valid logic level.5 LSB below the VDD or VREF level.5 L S B o r V 4 0 9 6 R E F ) A n a lo g In p u t V o lta g e Ideal A/D Transfer Function Rev. the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. this gives a single bit analog input value of VDD or VREF divided by 4096.5 L S B F F F H F F E H F F D H A /D C o n v e r s io n R e s u lt 0 3 H 0 2 H 0 1 H 0 1 2 3 4 0 9 3 4 0 9 4 4 0 9 5 4 0 9 6 ( V D D 0 . the subsequent digitised values will change at a point 0. 1. whereas in the second example. Since the full-scale analog input value is equal to the VDD or VREF voltage. 1 . A/D Transfer Function As the devices contain a 12-bit A/D converter. the A/D interrupt is used to determine when the conversion is complete. In the first example. Except for the digitised zero value. A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. 1 LSB= (VDD or VREF) ¸ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value ´ (VDD or VREF) ¸ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. the A/D internal circuitry can be switched off to reduce power consumption. the microcontroller internal hardware will begin to carry out the conversion. and the last full scale digitised value will change at a point 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. by setting bit ADOFF high in the ADCR0 register. The time taken for the A/D conversion is 16tADCK where tADCK is equal to the A/D clock period. If the A/D converter input lines are used as normal I/Os. 2010 . Programming Considerations During microcontroller operations where the A/D converter is not being used.5 LSB below where they would change without the offset.

reset A/D clr START . reset A/D clr START .a . enable and connect AN0 channel to A/D converter : start_conversion: clr START .00h mov ADCR0. continue polling mov a. clear ADC interrupt request flag set EADI . save result to user defined register : : EXIT_INT_ISR: mov a.a . start A/D polling_EOC: sz EOCB . select fSYS/8 as A/D clock and switch off 1.25V clr ADOFF mov a. select fSYS/8 as A/D clock and switch off 1. read high byte conversion result value mov ADRH_buffer.a . 1.a mov a.a .a . save result to user defined register mov a. enable and connect AN0 channel to A/D converter Start_conversion: clr START .00h .ADRH . save ACC to user defined memory mov a.a . setup ACERL and ACERH to configure pins AN0~AN3 mov ACERL. setup ACERL and ACERH to configure pins AN0~AN3 mov ACERL.a . of A/D conversion jmp polling_EOC . ACERH is only for HT66F60 mov a.00h mov ADCR0.03H mov ADCR1. read low byte conversion result value mov adrl_buffer.03H mov ADCR1. start next a/d conversion Example: using the interrupt method to detect the end of conversion clr EADI . 2010 .ADRH . save result to user defined register : : jmp start_conversion . save STATUS to user defined memory : : mov a.STATUS mov status_stack.25V Clr ADOFF mov a. enable global interrupt : : . high pulse on START bit to initiate conversion set START . ACERH is only for HT66F60 mov a. high pulse on start bit to initiate conversion set START .0Fh .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Example: using an EOCB polling method to detect the end of conversion clr EADI . start A/D clr ADF . poll the ADCR0 register EOCB bit to detect end .ADRL .acc_stack . restore STATUS from user defined memory mov a.00h mov ACERH. read high byte conversion result value mov adrh_buffer. save result to user defined register mov a. read low byte conversion result value mov ADRL_buffer.a mov a.0Fh .00h mov ACERH.a .a .30 141 October 4.status_stack mov STATUS.ADRL .a . restore ACC from user defined memory reti Rev. disable ADC interrupt mov a. disable ADC interrupt mov a.a . ADC interrupt service routine ADC_ISR: mov acc_stack. enable ADC interrupt set EMI .00h .

it will remain active when the microcontroller enters the SLEEP or IDLE Mode. C n P O L C n + C n C n S E L C n O U T C n X Comparator Comparator Operation The device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. but can also be transferred out onto a shared I/O pin. Full control over the two internal comparators is provided via two control registers. As comparator pins are shared with normal I/O pins the I/O registers for these pins will be read as zero (port control register is ²1²) or read as port data register value (port control register is ²0²) if the comparator function is enabled. also increases the switching offset value. then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. polarity select. Additional comparator functions include. 1. Any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. CP0C and CP1C. Register Name CP0C CP1C Bit 7 C0SEL C1SEL 6 C0EN C1EN 5 C0POL C1POL 4 C0OUT C1OUT 3 C0OS C1OS 2 ¾ ¾ 1 ¾ ¾ 0 C0HYEN C1HYEN Comparator Registers List Comparator Interrupt Each also possesses its own interrupt function. When any one of the changes state. Ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level.30 142 October 4. they following register table applies to both registers. This can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. one for each comparator. hysteresis functions and power down control. As the comparator inputs approach their switching level. output polarity. then a jump to its relevant interrupt vector will be executed. its relevant interrupt flag will be set. If the microcontroller is in the SLEEP or IDLE Mode and the Comparator is enabled. the user may wish to consider disabling it before the SLEEP or IDLE Mode is entered. unavoidable input offsets introduce some uncertainties here. As corresponding bits in the two registers have identical functions. The hysteresis function. however as it will consume a certain amount of power. hysteresis etc. If it is required to disable a wake-up from occurring. and if the corresponding interrupt enable bit is set. some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. then if the external input lines cause the Comparator output to change state. Comparator Registers There are two registers for overall comparator operation. These functions offer flexibility via their register controlled features such as power-down. if enabled. Rev. Programming Considerations If the comparator is enabled. one assigned to each comparator. Note that it is the changing state of the C0OUT or C1OUT bit and not the output pin which generates an interrupt. The comparator output is recorded via a bit in their respective control register. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused. the resulting generated interrupt flag will also generate a wake-up. however. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Comparators Two independent analog comparators are contained within these devices.

The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C0POL bit. 1. If the bit is zero then the C0OUT bit will reflect the non-inverted output condition of the comparator. Bit 6 C0EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit.30 143 October 4. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. Bit 5 C0POL: Comparator output polarity 0: output not inverted 1: output inverted This is the comparator polarity bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. As a result. read as ²0² C0HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator. Rev. If the bit is set to ²0² and the C0SEL bit is ²1² the comparator output is connected to an external C0X pin. Bit 4 C0OUT: Comparator output bit C0POL=0 0: C0+ < C01: C0+ > C0C0POL=1 0: C0+ > C01: C0+ < C0This bit stores the comparator output bit. Bit 2~1 Bit 0 unimplemented. If the bit is high the comparator C0OUT bit will be inverted. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · CP0C Register Bit Name R/W POR Bit 7 7 C0SEL R/W 1 6 C0EN R/W 0 5 C0POL R/W 0 4 C0OUT R 0 3 C0OS R/W 0 2 ¾ ¾ ¾ 1 ¾ ¾ ¾ 0 C0HYEN R/W 1 C0SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. If the bit is set to ²1² or the C0SEL bit is ²0² the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. 2010 . as specified in the Comparator Electrical Characteristics table. Bit 3 C0OS: Output path select 0: C0X pin 1: Internal use This is the comparator output path select control bit.

these two pins will lose their I/O pin functions. Bit 3 C1OS: Output path select 0: C1X pin 1: Internal use This is the comparator output path select control bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. If the bit is high the comparator C1OUT bit will be inverted. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. Bit 4 C1OUT: Comparator output bit C1POL=0 0: C1+ < C11: C1+ > C1C1POL=1 0: C1+ > C11: C1+ < C1This bit stores the comparator output bit. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. If the bit is set to ²0² and the C1SEL bit is ²1² the comparator output is connected to an external C1X pin. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C1POL bit. 1. As a result. 2010 . If the bit is set to ²1² or the C1SEL bit is ²0² the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. as specified in the Comparator Electrical Characteristics table. read as ²0² C1HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator. Bit 5 C1POL: Comparator output polarity 0: output not inverted 1: output inverted This is the comparator polarity bit.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · CP1C Register Bit Name R/W POR Bit 7 7 C1SEL R/W 1 6 C1EN R/W 0 5 C1POL R/W 0 4 C1OUT R 0 3 C1OS R/W 0 2 ¾ ¾ ¾ 1 ¾ ¾ ¾ 0 C1HYEN R/W 1 C1SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit.30 144 October 4. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. Bit 6 C1EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero then the C1OUT bit will reflect the non-inverted output condition of the comparator. Bit 2~1 Bit 0 unimplemented. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. Rev.

Pins SDI and SDO are the Serial Data Input and Serial Data Output lines. named SIM2~SIM0. 1. in the SIMC0 register. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins. · SPI Interface Operation The SPI interface is a full duplex synchronous serial data link.30 145 October 4. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected using a configuration option. these serial interface types allow the microcontroller to interface to 2 external SPI or I C based hardware such as sensors.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Serial Interface Module . the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits. which includes both the four line SPI interface or the two line I2C interface types. the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. It is a four line interface with pin names SDI. Flash or EEPROM memory. The communication is full duplex and operates as a slave/master type. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. After the SPI configuration option has been configured it can also be additionally disabled or enabled using the SIMEN bit in the SIMC0 register. and also if the SIM function is enabled. set CSEN bit to ²0² the SCS pin will be floating state. SCK and SCS. These pull-high resistors of the SIM pin-shared I/O are selected using pull-high control registers. If the master needs to control multiple slave devices from a single master. S P I M a s te r S C K S D O S D I S C S S P I S la v e S C K S D I S D O S C S SPI Master/Slave Connection D a ta B u s S IM D S D I P in S D O E n a b le /D is a b le B u s y S ta tu s C o n fig u r a tio n O p tio n W C O L F la g T R F F la g P in T x /R x S h ift R e g is te r C K E N b it C K P O L B b it S C K P in fS fT Y S B C C lo c k E d g e /P o la r ity C o n tro l T M 0 C C R P m a tc h fre q u e n c y /2 S C S P in C S E N C lo c k S o u r c e S e le c t b it C o n fig u r a tio n O p tio n E n a b le /D is a b le SPI Block Diagram Rev. The Master also controls the clock signal. SDO. 2010 . the master can use I/O pin to select the slave devices. where the device can be either master or slave. SCK is the Serial Clock line and SCS is the Slave Select line. Originally developed by Motorola. to allow an easy method of communication with external peripheral hardware. set CSEN bit to ²1² to enable SCS pin function. Although the SPI interface specification can control multiple slave devices from a single master. The SCS pin is controlled by software. As both interface types share the same pins and registers. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors. Flash or EEPROM memory devices etc.SIM These devices contain a Serial Interface Module. the SPI interface must first be enabled by selecting the SIM enable configuration option and setting the correct bits in the SIMC0 and SIMC2 registers. etc. but this device provided only one SCS pin. Having relatively simple communication protocols. As the device only contains a single SCS pin only one slave device can be utilized.

Any transmission or reception of data from the SPI bus must be made via the SIMD register. After the data is received from the SPI bus. Before the device writes data to the SPI bus. SPI Registers There are three internal registers which control the overall operation of the SPI interface.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 The SPI function in this device offers the following features: ¨ ¨ ¨ ¨ ¨ ¨ Full duplex synchronous data transfer Both Master and Slave modes LSB first or MSB first data transmission modes Transmission complete flag Rising or falling active clock edge WCOL and CSEN bit enabled or disable select There are several configuration options associated with the SPI interface. One of these is to enable the SIM function which selects the SIM pins rather than normal I/O pins. Another two SPI configuration options determine if the CSEN and WCOL bits are to be used. Register Name SIMC0 SIMD SIMC2 Bit 7 SIM2 D7 D7 6 SIM1 D6 D6 5 SIM0 D5 CKPOLB 4 PCKEN D4 CKEG 3 PCKP1 D3 MLS 2 PCKP0 D2 CSEN 1 SIMEN D1 WCOL 0 ¾ D0 TRF SIM Registers List The SIMD register is used to store the data being transmitted and received. Note 2 that the SIMC1 register is only used by the I C interface. 1. the device can read it from the SIMD register.30 146 October 4. · SIMD Register Bit Name R/W POR 7 D7 R/W x 6 D6 R/W x 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Rev. The same register is used by both the SPI and I2C functions. These are the SIMD data register and two registers SIMC0 and SIMC2. 2010 . Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no effect. The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. the actual data to be transmitted must be placed in the SIMD register.

PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. HAAS. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. SDO. or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. read as ²0² Bit 4 Bit 3~2 Bit 1 Bit 0 Rev. the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF. SIMC0 and SIMC2. they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. only by the I2C function. When the SIMEN bit is cleared to zero to disable the SIM interface. Although not connected with the SPI function. SRW and RXAK will be set to their default states. SPI clock is fSYS/16 010: SPI master mode. As well as selecting if the I2C or SPI function. SCK and SCS. HBB. SPI clock is fSYS/64 011: SPI master mode. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. The SIMC1 register is not used by the SPI function. the SIMC0 register is also used to control the Peripheral Clock Prescaler. PCKEN: PCK Output Pin Control 0: Disable 1: Enable PCKP1. 1. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 There are also two control registers for the SPI interface. SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. 2010 . · SIMC0 Register Bit Name R/W POR Bit 7~5 7 SIM2 R/W 1 6 SIM1 R/W 1 5 SIM0 R/W 1 4 PCKEN R/W 0 3 PCKP1 R/W 0 2 PCKP0 R/W 0 1 SIMEN R/W 0 0 ¾ ¾ ¾ SIM2. Register SIMC2 is used for other control functions such as LSB/MSB selection. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. unimplemented. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. SIM1.30 147 October 4. the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. write collision flag etc. SPI clock is fSYS/4 001: SPI master mode. the SDI. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high. SPI clock is fTBC 100: SPI master mode. SIM0: SIM Operating Mode Control 000: SPI master mode. When the bit is high the SIM interface is enabled.

Note that using the CSEN bit can be disabled or enabled via configuration option. either MSB or LSB first. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. but must set to ²0² by the application program. CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. It can be used to generate an interrupt. Bit 4 Bit 3 MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred. If the bit is high the SCS pin will be enabled and used as a select pin. CKPOLB: Determines the base condition of the clock line 0: the SCK line will be high when the clock is inactive 1: the SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line. if the bit is high. WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. if the bit is high. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. When the CKPOLB bit is low. then the SCK line will be low when the clock is inactive.30 148 October 4. When the CKPOLB bit is low. then the SCK line will be low when the clock is inactive. This writing operation will be ignored if data is being transferred. Setting the bit high will select MSB first and low for LSB first. 2010 . If this bit is low. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. then the SCK line will be high when the clock is inactive. then the SCS pin will be disabled and placed into a floating condition. Bit 2 Bit 1 Bit 0 Rev. Note that using the WCOL bit can be disabled or enabled via configuration option.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · SIMC2 Register Bit Name R/W POR Bit 7~6 Bit 5 7 D7 R/W 0 6 D6 R/W 0 5 CKPOLB R/W 0 4 CKEG R/W 0 3 MLS R/W 0 2 CSEN R/W 0 1 WCOL R/W 0 0 TRF R/W 0 Undefined bit This bit can be read or written by user software program. TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set ²1² automatically when an SPI data transmission is completed. then the SCK line will be high when the clock is inactive. The CKPOLB bit determines the base condition of the clock line. CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. 1. The bit can be cleared by the application program.

In the Slave Mode. The SPI will continue to function even in the IDLE Mode. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. C K E G = 0 ) S C K (C K P O L B = 1 . but must be cleared using the application program. When the data transfer is complete. when the clock signal from the master has been received. any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided.30 149 October 4. then in the Master Mode. C K E G = 1 ) S C K (C K P O L B = 0 . C K E G = 1 ) S D O S D O (C K E G = 0 ) (C K E G = 1 ) D 7 /D 0 D 7 /D 0 D 6 /D 1 D 6 /D 1 D 5 /D 2 D 5 /D 2 D 4 /D 3 D 4 /D 3 D 3 /D 4 D 3 /D 4 D 2 /D 5 D 2 /D 5 D 1 /D 6 D 1 /D 6 D 0 /D 7 D 0 /D 7 S IM E N . S IM E N = 1 .H ig h ) S C S S C K (C K P O L B = 1 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SPI Communication After the SPI interface is enabled by setting the SIMEN bit high. 2010 . C S E N = 0 ( E x te r n a l P u ll. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. transmission/reception will begin simultaneously.CKEG=0 Rev. 1. the TRF flag will be set automatically. C K E G = 0 ) S C K (C K P O L B = 0 . when data is written to the SIMD register. C S E N = 1 S D I D a ta C a p tu re W r ite to S IM D SPI Master Mode Timing S C S S C K (C K P O L B = 1 ) S C K (C K P O L B = 0 ) S D O S D I D a ta C a p tu re W r ite to S IM D ( S D O d o e s n o t c h a n g e u n til fir s t S C K e d g e ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 SPI Slave Mode Timing .

0 1 1 o r 1 0 0 S IM [2 :0 ]= 1 0 1 N N C o n fig u r e C K P O L B .30 150 October 4. SPI Slave Mode Timing .CKEG=1 A S P I tra n s fe r C le a r W C O L W r ite D a ta in to S IM D M a s te r m a s te r o r s la v e ? S la v e Y W C O L = 1 ? S IM [2 :0 ]= 0 0 0 . C S E N a n d M L S T r a n s m is s io n c o m p le te d ? (T R F = 1 ? ) Y S IM E N = 1 R e a d D a ta fro m S IM D A C le a r T R F T ra n s fe r F in is h e d ? N Y E N D SPI Transfer Control Flowchart Rev.0 1 0 . C K E G . 0 0 1 . if S IM E N = 1 a n d C S E N = 0 . S P I is a lw a y s e n a b le d a n d ig n o r e s th e S C S le v e l. 1. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 S C S S C K (C K P O L B = 1 ) S C K (C K P O L B = 0 ) S D O S D I D a ta C a p tu re W r ite to S IM D ( S D O c h a n g e s a s s o o n a s w r itin g o c c u r s . S D O is flo a tin g if S C S = 1 ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 N o te : F o r S P I s la v e m o d e .

There are several configuration options associated with the I2C interface. SIMD. a serial data line. The SIMD register. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 I2C Interface The I C interface is used to communicate with external peripheral devices such as sensors. it is a two line low speed serial interface for synchronous serial data transfer. The debounce time. the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus. When two devices communicate with each other on the bidirectional I2C bus. For this reason it is necessary that external pull-high resistors are connected to these outputs. Another configuration option determines the debounce time of the I2C interface. one is known as the master device and one as the slave device. For these devices. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Note that if the configuration option does not select the SIM function then the SIMEN bit in the · I2C Registers There are three control registers associated with the I2C bus. SDA. SIMC0. and serial clock line. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. Originally developed by Philips. it is the master device that has overall control of the bus. Note that no chip select line exists. One of these is to enable the function which selects the SIM pins rather than normal I/O pins. is used to store the data being transmitted and received on the I2C bus. the microcontroller can read it from the SIMD register. the slave transmit mode and the slave receive mode. relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. S T A R T s ig n a l fro m M a s te r S D A S C L D e v ic e S la v e D e v ic e M a s te r D e v ic e S la v e I2C Master Slave Bus Connection · I2C Interface Operation The I2C serial interface is a two line interface. The advantage of only two lines for communication. can be chosen to be either 1 or 2 system clocks.30 151 October 4. SIMC1 and SIMA and one data register. EEPROM memory etc. their outputs are both open drain types. Both master and slave can transmit and receive data. as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. however. As many devices may be connected together on the same bus. there are two methods of transferring data on the I2C bus. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. A configuration option exists to allow a clock other than the system clock 2 to drive the I C interface. if selected. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Before the microcontroller writes data to the I2C bus. which is shown in the above SPI section. V D D S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r 2 SIMC0 register will have no effect. which only operates in slave mode. 2010 . Register Name SIMC0 SIMC1 SIMD SIMA Bit 7 SIM2 HCF D7 IICA6 6 SIM1 HAAS D6 IICA5 5 SIM0 HBB D5 IICA4 4 PCKEN HTX D4 IICA3 3 PCKP1 TXAK D3 IICA2 2 PCKP0 SRW D2 IICA1 1 SIMEN IAMWU D1 IICA0 0 ¾ RXAK D0 D0 I2C Registers List Rev. SCL.

HBB. HAAS. SIM0: SIM Operating Mode Control 000: SPI master mode. SRW and RXAK will be set to their default states. 2010 . The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. SPI clock is fTBC 100: SPI master mode.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · SIMC0 Register Bit Name R/W POR Bit 7~5 7 SIM2 R/W 1 6 SIM1 R/W 1 5 SIM0 R/W 1 4 PCKEN R/W 0 3 PCKP1 R/W 0 2 PCKP0 R/W 0 1 SIMEN R/W 0 0 ¾ ¾ ¾ SIM2. When the SIMEN bit is cleared to zero to disable the SIM interface. SDO. the SDI. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high. the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. PCKEN: PCK Output Pin Control 0: Disable 1: Enable PCKP1. SPI clock is fSYS/16 010: SPI master mode. read as ²0² Bit 4 Bit 3~2 Bit 1 Bit 0 Rev. SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF. As well as selecting if the I2C or SPI function. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. If the SIM is configured to operate as an SPI interface via SIM2~SIM0 bits. 1. SIM1. or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. SCK and SCS. unimplemented. SPI clock is fSYS/64 011: SPI master mode. SPI clock is fSYS/4 001: SPI master mode. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. they are used to control the SPI Master/Slave selection and the SPI Master clock frequency.30 152 October 4.

When the slave device in the transmit mode. it means that a acknowledge signal has been received at the 9th clock. if there is no match then the flag will be low. so the slave device should be in transmit mode. 1. the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. This flag will be zero when data is being transferred. HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. the master is requesting to read data from the bus. therefore the slave device should be in receive mode to read this data. HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. this bit will be transmitted to the bus on the 9th clock from the slave device. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. This flag is used to determine if the slave device address is the same as the master transmit address. 2010 . After the slave device receipt of 8-bits of data. HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HASS flag is the address match flag. If the SRW flag is high. When the transmitted address and slave address is match. The slave transmitter will therefore continue sending out data until the RXAK flag is ²1². The slave device must always set TXAK bit to ²0² before further data is received. after 8 bits of data have been transmitted. When the SRW flag is zero.30 153 October 4. The flag will be set to ²0² when the bus is free which will occur when a STOP signal is detected. If the addresses match then this bit will be high. SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I2C Slave Read/Write flag. When this occurs.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · SIMC1 Register Bit Name R/W POR Bit 7 7 HCF R 1 2 6 HAAS R 0 5 HBB R 0 4 HTX R/W 0 3 TXAK R/W 0 2 SRW R 0 1 IAMWU R/W 0 0 RXAK R 1 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. that is when the HAAS flag is set high. the master will write data to the bus. When the RXAK flag is ²0². This flag will be ²1² when the I2C bus is busy which will occur when a START signal is detected. the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. IAMWU: I2C Address Match Wake-up Control 0: Disable 1: Enable This bit should be set to ²1² to enable I2C address match wake up from SLEEP or IDLE Mode.

2010 .30 154 October 4. Any transmission or reception of data from the SPI bus must be made via the SIMD register. When a master device. D a ta B u s I2C D a ta R e g is te r (S IM D ) S la v e A d d r e s s R e g is te r (S IM A ) A d d re s s C o m p a ra to r A d d re s s M a tc h H A A S B it H T X B it S C L P in S D A P in M U X D ir e c tio n C o n tr o l S h ift R e g is te r I2C In te rru p t D a ta in L S B D a ta O u t M S B R e a d /w r ite S la v e S R W B it E n a b le /D is a b le A c k n o w le d g e T r a n s m it/R e c e iv e C o n tr o l U n it 2 8 . The same register is used by both the SPI and I2C functions. The SIMA register is the location where the 7-bit slave address of the slave device is stored.b it D a ta C o m p le te D e te c t S ta rt o r S to p H C F B it H B B B it I C Block Diagram Rev. After the data is received from the SPI bus. Bit 0 is not defined. sends out an address. the actual data to be transmitted must be placed in the SIMD register. Bit 0 Undefined bit This bit can be read or written by user software program. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 The SIMD register is used to store the data being transmitted and received. Before the device writes data to the SPI bus. the device can read it from the SIMD register. · SIMD Register Bit Name R/W POR · SIMA Register 7 D7 R/W x 6 D6 R/W x 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Bit Name R/W POR Bit 7~1 7 IICA6 R/W x 6 IICA5 R/W x 2 5 IICA4 R/W x 4 IICA3 R/W x 3 IICA2 R/W x 2 IICA1 R/W x 1 IICA0 R/W x 0 ¾ ¾ ¾ ²x² unknown IICA6~ IICA0: I C slave address IICA6~ IICA0 is the I2C slave address bit 6~ bit 0. the slave device will be selected. Bits 7~ 1 of the SIMA register define the device slave address. The SIMA register is also used by the SPI interface but has the name SIMC2. which matches the slave address in the SIMA register. which is connected to the I2C bus. 1.

To determine which slave device the master wishes to communicate with. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. this indicates that the I2C bus is busy and therefore the HBB bit will be set. the device must be placed in either the transmit mode and then write data to the SIMD register. 1. If the address sent out by the master matches the internal address of the microcontroller slave device. The next bit following the address. note that after the 7-bit slave address has been transmitted. after receiving this 7-bit address data. The acknowledge signal will inform S E T S IM [2 :0 ]= 1 1 0 S E T S IM E N W r ite S la v e A d d re s s to S IM A N o C L R S IM E P o ll S IM F to d e c id e w h e n to g o to I2C B u s IS R I2C B u s In te rru p t= ? Y e s S E T S IM E a n d M F n E W a it fo r In te r r u p t G o to M a in P r o g r a m G o to M a in P r o g r a m I2C Bus Initialisation Flow Chart Rev. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. When detected. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address. Before any transfer of data to or from the I2C bus. the address of the slave device will be sent out immediately following the START signal. The first seven bits of the data will be the slave address with the first bit being the MSB. the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. Step 2 Write the slave address of the device to the I C bus address register SIMA. a data transmission and finally a STOP signal.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 I2C Bus Communication Communication on the I2C bus requires four separate steps. When a START signal is placed on the I2C bus. If the address of the slave device matches that of the transmitted address. therefore the slave device must be setup to read data from the I2C bus as a receiver. S ta rt 2 I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. a slave device address transmission. defines the read/write status and will be saved to the SRW bit of the SIMC1 register. If the SRW flag is ²1² then this indicates that the 2 master device wishes to read data from the I C bus. therefore the slave device must be setup to send data to the I2C bus as a transmitter. as the 9th bit. or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. When a slave address is matched. whose own internal address matches the calling address. the following bit. is the read/write bit whose value will be placed in the SRW bit. The slave device will also set the status flag HAAS when the addresses match. This START signal will be detected by all devices connected to the I2C bus. Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. which is the 8th bit. the microcontroller must initialise the bus. a START signal. 2010 . all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. After entering the interrupt service routine. will compare it with their own 7-bit slave address. Slave Address The transmission of a START signal by the master will 2 be detected by all devices on the I C bus.30 155 October 4. must generate an acknowledge signal. As an I2C bus interrupt can come from two sources. If the SRW flag is ²0² then this indicates that the master wishes to send data to the I2C bus. when the program enters the interrupt subroutine. which is the 8th bit. The slave device will then transmit an acknowledge bit. the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. During a data transfer. then an internal I2C bus interrupt signal will be generated. any slave device on the I2C bus. All slave devices. the HAAS bit in 2 the SIMC1 register will be set and an I C interrupt will be generated. which is a low level. the following are steps to achieve this: Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to ²1² to enable the I2C bus.

the receiver must transmit an acknowledge signal.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 the master that a slave device has accepted its calling address. the slave device must first write the data to be transmitted into the SIMD register. the slave device must read the transmitted data from the SIMD register. If the slave transmitter does not receive an acknowledge bit signal from the master receiver. The slave device. After receipt of 8-bits of data. If the SRW flag is low. known as TXAK. If the SRW flag is high. which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte. I2C Communication Timing Diagram Rev. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. it must generate an acknowledge bit. The corresponding data will be stored in the SIMD register. If setup as a transmitter. level ²0². I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to ²0². 1. T X A K b it fo r r e c e iv e r 1 b it) b it) S R M D A D A S S A S R M D A D A P Note: * When a slave address is matched. S C L S ta rt S la v e A d d r e s s S R W A C K S D A 1 0 1 1 0 1 0 1 0 S C L D a ta A C K S to p 1 S D A S = S S A = S R = M = S D = D A = A P = S S ta rt (1 S la v e S R W la v e d a ta (8 C K (R to p (1 S A 0 0 1 0 1 0 0 b it) A d d r e s s ( 7 b its ) b it ( 1 b it) e v ic e s e n d a c k n o w le d g e b it ( 1 b it) b its ) X A K b it fo r tr a n s m itte r . When the slave receiver receives the data byte. the device must be placed in either the transmit mode and then write data to the SIMD register. before it can receive the next data byte. the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. When the HAAS flag is high. the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to ²1². If setup as a receiver. on the 9th clock. then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. 2010 . if not then it will release the SDA line and await the receipt of a STOP signal from the master.30 156 October 4. or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 S ta rt N o H A A S = 1 ? Y e s Y e s Y e s N o N o R e a d fro m S IM D to r e le a s e S C L lin e H T X = 1 ? S R W = 1 ? S E T H T X C L R H T X C L R T X A K R E T I Y e s R X A K = 1 ? N o C L R H T X C L R T X A K W r ite d a ta to S IM D r e le a s e S C L L in e W r ite d a ta to S IM D to r e le a s e S C L L in e D u m m y re a d fro m S IM D to r e le a s e S C L L in e R E T I R E T I D u m m y re a d fro m S IM D to r e le a s e S C L L in e R E T I R E T I I2C Bus ISR Flow Chart Rev.30 157 October 4. 2010 . 1.

they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. is shared with I/O line. The Peripheral Clock function is controlled using the SIMC0 register. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. PCK.30 158 October 4. SIM0: SIM operating mode control 000: SPI master mode. or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. SPI clock is fSYS/16 010: SPI master mode. the SDI. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. Note that when the SIMEN bit changes from low to high the contents of the SPI control registers will be in an unknown condition and should therefore be first initialised by the application program. SPI clock is fSYS/4 001: SPI master mode. When the SIMEN bit is cleared to zero to disable the SIM interface. the required pin function is chosen via PCKEN in the SIMC0 register. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. The PCKEN bit in the SIMC0 register is the overall on/off control. SPI clock is fTBC 100: SPI master mode. 1. · SIMC0 Register Bit Name R/W POR Bit 7~5 7 SIM2 R/W 1 6 SIM1 R/W 1 5 SIM0 R/W 1 4 PCKEN R/W 0 3 PCKP1 R/W 0 2 PCKP0 R/W 0 1 SIMEN R/W 0 0 ¾ ¾ ¾ SIM2. If the device enters the SLEEP Mode this will disable the Peripheral Clock output. setting PCKEN bit to ²1² enables the Peripheral Clock. SPI clock is fSYS/64 011: SPI master mode. read as ²0² Bit 4 Bit 3~2 Bit 1 Bit 0 Rev. As well as selecting if the I2C or SPI function.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. 2010 . unimplemented. Peripheral Clock Operation As the peripheral clock output pin. setting PCKEN bit to ²0² disables it. SCK and SCS. PCKEN: PCK output pin control 0: Disable 1: Enable PCKP1. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. PCKP0: select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 SIMEN: SIM control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. SIM1. SDO. When the bit is high the SIM interface is enabled. The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal fSYS clock.

then the (optional) number of that interrupt followed by either an ²E² for enable/disable bit or ²F² for request flag. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Interrupts Interrupts are an important part of any microcontroller system. which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program. Finally there is an INTEG register to setup the external interrupt trigger edge type. Comparators. located in the Special Purpose Data Memory. LVD. is controlled by a series of registers. while the internal interrupts are generated by various internal functions such as the TMs. as shown in the accompanying table. 2010 . SIM and the A/D converter. Time Base. their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention. EEPROM. Interrupt Registers Overall interrupt control. The number of registers depends upon the device chosen but fall into three categories. The external interrupts are generated by the action of the external INT0~INT3 and PINT pins. Function Global Comparator INTn Pin A/D Converter Multi-function Time Base SIM LVD EEPROM PINT Pin Enable Bit EMI CPnE INTnE ADE MFnE TBnE SIME LVE DEE XPE TnPE TM TnAE TnBE Request Flag ¾ CPnF INTnF ADF MFnF TBnF SIMF LVF DEF XPF TnPF TnAF TnBF n = 0~3 Notes ¾ n = 0 or 1 n = 0~3 ¾ n = 0~5 n = 0 or 1 ¾ ¾ ¾ ¾ Interrupt Register Bit Naming Conventions · Interrupt Register Contents ¨ HT66F20 Bit Name 7 INTEG INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 ¾ ¾ ADF MF3F ¾ ¾ DEF 6 ¾ CP0F MF1F TB1F ¾ ¾ LVF 5 ¾ INT1F MF0F TB0F T0AF T1AF XPF 4 ¾ INT0F CP1F MF2F T0PF T1PF SIMF 3 INT1S1 CP0E ADE MF3E ¾ ¾ DEE 2 INT1S0 INT1E MF1E TB1E ¾ ¾ LVE 1 INT0S1 INT0E MF0E TB0E T0AE T1AE XPE 0 INT0S0 EMI CP1E MF2E T0PE T1PE SIME Rev. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The first is the INTC0~INTC3 registers which setup the primary interrupts. 1. the second is the MFI0~MFI3 registers which setup the Multi-function interrupts. The device contains several external interrupt and internal interrupts functions.30 159 October 4.

2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F30 Bit Name 7 INTEG INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 ¾ ¾ ADF MF3F ¾ ¾ DEF 6 ¾ CP0F MF1F TB1F ¾ T1BF LVF 5 ¾ INT1F MF0F TB0F T0AF T1AF XPF 4 ¾ INT0F CP1F MF2F T0PF T1PF SIMF 3 INT1S1 CP0E ADE MF3E ¾ ¾ DEE 2 INT1S0 INT1E MF1E TB1E ¾ T1BE LVE 1 INT0S1 INT0E MF0E TB0E T0AE T1AE XPE 0 INT0S0 EMI CP1E MF2E T0PE T1PE SIME ¨ HT66F40 Bit Name 7 INTEG INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 ¾ ¾ ADF MF3F T2AF ¾ DEF 6 ¾ CP0F MF1F TB1F T2PF T1BF LVF 5 ¾ INT1F MF0F TB0F T0AF T1AF XPF 4 ¾ INT0F CP1F MF2F T0PF T1PF SIMF 3 INT1S1 CP0E ADE MF3E T2AE ¾ DEE 2 INT1S0 INT1E MF1E TB1E T2PE T1BE LVE 1 INT0S1 INT0E MF0E TB0E T0AE T1AE XPE 0 INT0S0 EMI CP1E MF2E T0PE T1PE SIME ¨ HT66F50 Bit Name 7 INTEG INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 MFI3 ¾ ¾ ADF MF3F T2AF ¾ DEF ¾ 6 ¾ CP0F MF1F TB1F T2PF T1BF LVF ¾ 5 ¾ INT1F MF0F TB0F T0AF T1AF XPF T3AF 4 ¾ INT0F CP1F MF2F T0PF T1PF SIMF T3PF 3 INT1S1 CP0E ADE MF3E T2AE ¾ DEE ¾ 2 INT1S0 INT1E MF1E TB1E T2PE T1BE LVE ¾ 1 INT0S1 INT0E MF0E TB0E T0AE T1AE XPE T3AE 0 INT0S0 EMI CP1E MF2E T0PE T1PE SIME T3PE Rev. 1.30 160 October 4.

read as ²0² INT1S1. INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges INT0S1. 2010 . 1.30 161 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F60 Bit Name 7 INTEG INTC0 INTC1 INTC2 INTC3 MFI0 MFI1 MFI2 MFI3 INT3S1 ¾ MF0F ADF MF5F T2AF ¾ DEF ¾ 6 INT3S0 INT2F CP1F MF3F TB1F T2PF T1BF LVF ¾ 5 INT2S1 INT1F CP0F MF2F TB0F T0AF T1AF XPF T3AF 4 INT2S0 INT0F INT3F MF1F MF4F T0PF T1PF SIMF T3PF 3 INT1S1 INT2E MF0E ADE MF5E T2AE ¾ DEE ¾ 2 INT1S0 INT1E CP1E MF3E TB1E T2PE T1BE LVE ¾ 1 INT0S1 INT0E CP0E MF2E TB0E T0AE T1AE XPE T3AE 0 INT0S0 EMI INT3E MF1E MF4E T0PE T1PE SIME T3PE · INTEG Register ¨ HT66F20/HT66F30/HT66F40/HT66F50 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 INT1S1 R/W 0 2 INT1S0 R/W 0 1 INT0S1 R/W 0 0 INT0S0 R/W 0 Bit 7~4 Bit 3~2 unimplemented. INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 1~0 Rev.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F60 Bit Name R/W POR 7 INT3S1 R/W 0 6 INT3S0 R/W 0 5 INT2S1 R/W 0 4 INT2S0 R/W 0 3 INT1S1 R/W 0 2 INT1S0 R/W 0 1 INT0S1 R/W 0 0 INT0S0 R/W 0 Bit 7~6 INT3S1. 1. 2010 .30 162 October 4. read as ²0² CP0F: Comparator 0 interrupt request flag 0: no request 1: interrupt request INT1F: INT1 interrupt request flag 0: no request 1: interrupt request INT0F: INT0 interrupt request flag 0: no request 1: interrupt request CP0E: Comparator 0 interrupt control 0: disable 1: enable INT1E: INT1 interrupt control 0: disable 1: enable INT0E: INT0 interrupt control 0: disable 1: enable EMI: Global interrupt control 0: disable 1: enable Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges INT0S1. INT2S0: interrupt edge control for INT2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges INT1S1. INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 5~4 Bit 3~2 Bit 1~0 · INTC0 Register ¨ HT66F20/HT66F30/HT66F40/HT66F50 Bit Name R/W POR 7 ¾ ¾ ¾ 6 CP0F R/W 0 5 INT1F R/W 0 4 INT0F R/W 0 3 CP0E R/W 0 2 INT1E R/W 0 1 INT0E R/W 0 0 EMI R/W 0 Bit 7 Bit 6 unimplemented. INT3S0: Interrupt edge control for INT3 pin 00: disable 01: rising edge 10: falling edge INT2S1.

read as ²0² INT2F: INT2 interrupt request flag 0: no request 1: interrupt request INT1F: INT1 interrupt request flag 0: no request 1: interrupt request INT0F: INT0 interrupt request flag 0: no request 1: interrupt request INT2E: INT2 interrupt control 0: disable 1: enable INT1E: INT1 interrupt control 0: disable 1: enable INT0E: INT0 interrupt control 0: disable 1: enable EMI: Global interrupt control 0: disable 1: enable Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.30 163 October 4. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F60 Bit Name R/W POR 7 ¾ ¾ ¾ 6 INT2F R/W 0 5 INT1F R/W 0 4 INT0F R/W 0 3 INT2E R/W 0 2 INT1E R/W 0 1 INT0E R/W 0 0 EMI R/W 0 Bit 7 Bit 6 unimplemented.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · INTC1 Register ¨ HT66F20/HT66F30/HT66F40/HT66F50 Bit Name R/W POR 7 ADF R/W 0 6 MF1F R/W 0 5 MF0F R/W 0 4 CP1F R/W 0 3 ADE R/W 0 2 MF1E R/W 0 1 MF0E R/W 0 0 CP1E R/W 0 Bit 7 ADF: A/D Converter Interrupt Request Flag 0: n request 1: interrupt request MF1F: Multi-function Interrupt 1 Request Flag 0: no request 1: interrupt request MF0F: Multi-function Interrupt 0 Request Flag 0: no request 1: interrupt request CP1F: Comparator 1 Interrupt Request Flag 0: no request 1: interrupt request ADE: A/D Converter Interrupt Control 0: disable 1: enable MF1E: Multi-function Interrupt 1 Control 0: disable 1: enable MF0E: Multi-function Interrupt 0 Control 0: disable 1: enable CP1E: Comparator 1 Interrupt Control 0: Disable 1: Enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1. 2010 .30 164 October 4.

1.30 165 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F60 Bit Name R/W POR 7 MF0F R/W 0 6 CP1F R/W 0 5 CP0F R/W 0 4 INT3F R/W 0 3 MF0E R/W 0 2 CP1E R/W 0 1 CP0E R/W 0 0 INT3E R/W 0 Bit 7 MF0F: Multi-function Interrupt 0 Request Flag 0: no request 1: interrupt request CP1F: Comparator 1 Interrupt Request Flag 0: no request 1: interrupt request CP0F: Comparator 0 Interrupt Request Flag 0: no request 1: interrupt request INT3F: INT3 Interrupt Request Flag 0: no request 1: interrupt request MF0E: Multi-function Interrupt 0 Control 0: disable 1: enable CP1E: Comparator 1 Interrupt Control 0: disable 1: enable CP0E: Comparator 0 Interrupt Control 0: disable 1: enable INT3E: INT3 Interrupt Control 0: disable 1: enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 2010 .

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · INTC2 Register ¨ HT66F20/HT66F30/HT66F40/HT66F50 Bit Name R/W POR 7 MF3F R/W 0 6 TB1F R/W 0 5 TB0F R/W 0 4 MF2F R/W 0 3 MF3E R/W 0 2 TB1E R/W 0 1 TB0E R/W 0 0 MF2E R/W 0 Bit 7 MF3F: Multi-function Interrupt 3 Request Flag 0: no request 1: interrupt request TB1F: Time Base 1 Interrupt Request Flag 0: no request 1: interrupt request TB0F: Time Base 0 IInterrupt Request Flag 0: no request 1: interrupt request MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request MF3E: Multi-function Interrupt 3 Control 0: disable 1: enable TB1E: Time Base 1 Interrupt Control 0: disable 1: enable TB0E: Time Base 0 Interrupt Control 0: disable 1: enable MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1. 2010 .30 166 October 4.

1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F60 Bit Name R/W POR 7 ADF R/W 0 6 MF3F R/W 0 5 MF2F R/W 0 4 MF1F R/W 0 3 ADE R/W 0 2 MF3E R/W 0 1 MF2E R/W 0 0 MF1E R/W 0 Bit 7 ADF: A/D Converter Interrupt Request Flag 0: no request 1: interrupt request MF3F: Multi-function Interrupt 3 Request Flag 0: no request 1: interrupt request MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request MF1F: Multi-function Interrupt 1 Request Flag 0: no request 1: interrupt request ADE: A/D Converter Interrupt Control 0: disable 1: enable MF3E: Multi-function Interrupt 3 Control 0: disable 1: enable MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable MF1E: Multi-function Interrupt 1 Control 0: disable 1: enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 2010 .30 167 October 4.

30 168 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · INTC3 Register ¨ HT66F60 Bit Name R/W POR 7 MF5F R/W 0 6 TB1F R/W 0 5 TB0F R/W 0 4 MF4F R/W 0 3 MF5E R/W 0 2 TB1E R/W 0 1 TB0E R/W 0 0 MF4E R/W 0 Bit 7 MF5F: Multi-function interrupt 5 request flag 0: no request 1: interrupt request TB1F: Time Base 1 interrupt request flag 0: no request 1: interrupt request TB0F: Time Base 0 interrupt request flag 0: no request 1: interrupt request MF4F: Multi-function interrupt 4 request flag 0: no request 1: interrupt request MF5E: Multi-function interrupt 5 control 0: disable 1: enable TB1E: Time Base 1 interrupt control 0: disable 1: enable TB0E: Time Base 0 interrupt control 0: disable 1: enable MF4E: Multi-function interrupt 4 control 0: disable 1: enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 · MFI0 Register ¨ HT66F20/HT66F30 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 T0AF R/W 0 4 T0PF R/W 0 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T0AE R/W 0 0 T0PE R/W 0 Bit 7~6 Bit 5 unimplemented. 1. 2010 . read as ²0² T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable Bit 4 Bit 3~2 Bit 1 Bit 0 Rev. read as ²0² T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request unimplemented.

2010 . 1. read as ²0² T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable Bit 4 Bit 3~2 Bit 1 Bit 0 Rev. read as ²0² T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request T1PF: TM1 Comparator P match interrupt request flag 0: no request 1: interrupt request unimplemented.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 T2AF R/W 0 6 T2PF R/W 0 5 T0AF R/W 0 4 T0PF R/W 0 3 T2AE R/W 0 2 T2PE R/W 0 1 T0AE R/W 0 0 T0PE R/W 0 Bit 7 T2AF: TM2 Comparator A match interrupt request flag 0: no request 1: interrupt request T2PF: TM2 Comparator P match interrupt request flag 0: no request 1: interrupt request T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request T2AE: TM2 Comparator A match interrupt control 0: disable 1: enable T2PE: TM2 Comparator P match interrupt control 0: disable 1: enable T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 · MFI1 Register ¨ HT66F20 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 T1AF R/W 0 4 T1PF R/W 0 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T1AE R/W 0 0 T1PE R/W 0 Bit 7~6 Bit 5 unimplemented.30 169 October 4.

read as ²0² T1BE: TM1 Comparator P match interrupt control 0: disable 1: enable T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 · MFI2 Register Bit Name R/W POR Bit 7 7 DEF R/W 0 6 LVF R/W 0 5 XPF R/W 0 4 SIMF R/W 0 3 DEE R/W 0 2 LVE R/W 0 1 XPE R/W 0 0 SIME R/W 0 Bit 6 Bit 5 Bit 4 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request LVF: LVD interrupt request flag 0: No request 1: Interrupt request XPF: External peripheral interrupt request flag 0: No request 1: Interrupt request SIMF: SIM interrupt request flag 0: No request 1: Interrupt request DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable LVE: LVD Interrupt Control 0: Disable 1: Enable XPE: External Peripheral Interrupt Control 0: Disable 1: Enable SIME: SIM Interrupt Control 0: Disable 1: Enable Bit 3 Bit 2 Bit 1 Bit 0 Rev.30 170 October 4. read as ²0² T1BF: TM1 Comparator B match interrupt request flag 0: no request 1: interrupt request T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request T1PF: TM1 Comparator B match interrupt request flag 0: no request 1: interrupt request unimplemented. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F30/HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 ¾ ¾ ¾ 6 T1BF R/W 0 5 T1AF R/W 0 4 T1PF R/W 0 3 ¾ ¾ ¾ 2 T1BE R/W 0 1 T1AE R/W 0 0 T1PE R/W 0 Bit 7 Bit 6 unimplemented. 1.

If immediate service is desired. if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. such as a TM Comparator P. the request flag will still be recorded. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode. This will prevent any further interrupt nesting from occurring. the relevant interrupt request flag will be set. although the interrupt will not be immediately serviced. The microcontroller will then fetch its next instruction from this interrupt vector. will be transferred onto the stack. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If an interrupt requires immediate servicing while the program is already in another interrupt service routine. 1. The global interrupt enable bit. read as ²0² T3AF: TM3 Comparator A match interrupt request flag 0: no request 1: interrupt request T3PF: TM3 Comparator P match interrupt request flag 0: no request 1: interrupt request unimplemented. Rev. the stack must be prevented from becoming full. which stores the address of the next instruction to be executed. until the Stack Pointer is decremented. However. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. If the enable bit is set high then the program will jump to its relevant vector. In case of simultaneous requests. if other interrupt requests occur during this interval. even if the related interrupt is enabled. the EMI bit should be set after entering the routine. When an interrupt is generated. Here is located the code to control the appropriate interrupt. If the stack is full. EMI bit will be cleared automatically. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The interrupt service routine must be terminated with a ²RETI². all the other interrupts will be blocked.30 171 October 4. however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. to allow interrupt nesting. together with their associated request flags. are shown in the accompanying diagrams with their order of priority. Once an interrupt subroutine is serviced. The instruction at this vector will usually be a ²JMP² which will jump to another section of program which is known as the interrupt service routine. the Program Counter. Comparator A or Comparator B match or A/D conversion completion etc. read as ²0² T3AE: TM3 Comparator A match interrupt control 0: disable 1: enable T3PE: TM3 Comparator P match interrupt control 0: disable 1: enable Bit 4 Bit 3~2 Bit 1 Bit 0 Interrupt Operation When the conditions for an interrupt event occur. 2010 . the interrupt request will not be acknowledged. will disable all interrupts.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · MFI3 Register ¨ HT66F50/HT66F60 Bit Name R/W POR 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 T3AF R/W 0 4 T3PF R/W 0 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T3AE R/W 0 0 T3PE R/W 0 Bit 7~6 Bit 5 unimplemented. if cleared to zero. as the global interrupt enable bit. which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits. the accompanying diagram shows the priority that is applied.

2 MF2F MF2E EMI 20H Time Base 0 Time Base 1 TB0F TB1F TB0E TB1E EMI EMI 24H 28H LVD EEPROM LVF DEF LVE DEE M.HT66F20/HT66F30 Rev. 2010 . 1. Funct. Funct. 1 CP0F CP1F CP0E CP1E EMI EMI 0CH 10H M. 0 Comp. 3 MF3F MF3E EMI 2CH Low Interrupts contained within Multi-Function Interrupts HT66F30 only Interrupt Structure .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 EMI auto disabled in ISR Legend xxF xxF xxE Request Flag – no auto reset in ISR Request Flag – auto reset in ISR Enable Bit Interrupt Request Flags Name INT0 Pin INT1 Pin INT0F INT1F Enable Bits INT0E INT1E Master Enable EMI EMI Vector 04H 08H Priority High Interrupt Name TM0 P TM0 A Request Flags T0PF T0AF Enable Bits T0PE T0AE Comp. Funct. 0 MF0F MF0E EMI 14H TM1 P TM1 A TM1 B T1PF T1AF T1BF T1PE T1AE M. Funct. 1 MF1F MF1E EMI 18H A/D T1BE ADF ADE EMI 1CH SIM PINT Pin SIMF XPF SIME XPE M.30 172 October 4.

Funct. 3 MF3F MF3E EMI 2CH Low Interrupts contained within Multi-Function Interrupts HT66F50 only Interrupt Structure .30 173 October 4. Funct. Funct. 2010 . 2 MF2F MF2E EMI 20H Time Base 0 TB0F TB0E EMI 24H LVD EEPROM LVF DEF LVE DEE Time Base 1 TB1F TB1E EMI 28H M. 0 MF0F MF0E EMI 14H TM1 P TM1 A TM1 B T1PF T1AF T1BF T1PE T1AE T1BE A/D ADF ADE EMI 1CH M.HT66F40/HT66F50 Rev. 1. 1 MF1F MF1E EMI 18H TM3 P TM3 A T3PF T3AF T3PE T3AE SIM PINT Pin SIMF XPF SIME XPE M. 1 CP0F CP1F CP0E CP1E EMI EMI 0CH 10H M. 0 Comp. Funct.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 EMI auto disabled in ISR Legend xxF xxF Request Flag – no auto reset in ISR Request Flag – auto reset in ISR Interrupt Name INT0 Pin INT1 Pin Request Flags INT0F INT1F Enable Bits INT0E INT1E Master Enable EMI EMI Vector 04H 08H Priority High xxE Enable Bit Interrupt Name TM0 P TM0 A TM2 P TM2 A Request Flags TP0AF TP0AF T2PF T2AF Enable Bits T0PE T0AE T2PE T2AE Comp.

4 MF4F MF4E EMI 30H Time Base 0 Time Base 1 TB0F TB1F TB0E TB1E EMI EMI 34H 38H LVD EEPROM LVF DEF LVE DEE M. Funct.HT66F60 Rev. 0 MF0F MF0E EMI 1CH TM1 P TM1 A TM1 B T1PF T1AF T1BF T1PE T1AE T1BE M.30 174 October 4. Funct. Funct. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 EMI auto disabled in ISR Interrupt Name Legend Request Flags INT0F INT1F INT2F INT3F Enable Bits INT0E INT1E INT2E INT3E Master Enable EMI EMI EMI EMI Vector 04H 08H 0CH 10H Priority High INT0 Pin INT1 Pin INT2 Pin xxF xxF xxE Request Flag – no auto reset in ISR Request Flag – auto reset in ISR Enable Bit INT3 Pin Interrupt Name Request Flags Enable Bits Comp. Funct. 1 CP0F CP1F CP0E CP1E EMI EMI 14H 18H TM0 P TM0 A T0PF T0AF T0PE T0AE M. 3 MF3F MF3E EMI 28H 2CH A/D ADF ADE EMI SIM PINT Pin SIMF XPF SIME XPE M. 0 Comp. 2 MF2F MF2E EMI 24H M. Funct. 1 MF1F MF1E EMI 20H TM2 P TM2 A TM3 P TM3 A T2PF T2AF T3PF T3AF T2PE T2AE T3PE T3AE M. 2010 . Funct. 5 MF5F MF5E EMI 3CH Low Interrupts contained within Multi-Function Interrupts Interrupt Structure .

Multi-function Interrupt Within these devices there are up to six Multi-function interrupts. the global interrupt enable bit.30 175 the TM Interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. ADE. EMI. 2010 . INT0E~INT3E. When the interrupt is serviced. will be automatically reset and the EMI bit will be cleared to disable other interrupts.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT3. CP0F or CP1F. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. a situation that will occur when the comparator output changes state. However. must first be set. whose type is chosen by the edge select bits. although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced. the stack is not full and the comparator inputs generate a comparator output transition. which will occur when a transition. the A/D Converter Interrupt flag. As the external interrupt pins are pin-shared with I/O pins. a subroutine call to the external interrupt vector. When the interrupt is serviced. a subroutine call to their respective vector locations will take place. When these happens their respective interrupt request flags. When the interrupt is enabled. the related Multi-Function request flag. the stack is not full and the correct transition type appears on the external interrupt pin. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. The INTEG register is used to select the type of active edge that will trigger the external interrupt. a subroutine call to one of the Multi-function interrupt vectors will take place. these interrupts have no independent source. when the Multi-function interrupt is enabled and the stack is not full. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag. the global interrupt enable bit. namely Rev. the global interrupt enable bit. When the interrupt is enabled. The EMI bit will also be automatically cleared to disable other interrupts. EMI. ADF. a subroutine call to the comparator interrupt vector. but rather are formed from other existing interrupt sources. When the interrupt is serviced. SIM Interrupt. a subroutine call to the A/D Converter Interrupt vector. INT0F~INT3F. will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. the external interrupt request flags. will be automatically cleared. To allow the program to branch to their respective interrupt vector addresses. October 4. and A/D Interrupt enable bit. Unlike the other independent interrupts. TB0F or TB1F will be set. To allow the program to branch to its respective interrupt vector address. An external interrupt request will take place when the external interrupt request flags. LVD interrupt and EEPROM Interrupt. Note that the INTEG register can also be used to disable the external interrupt function. MF0F~MF5F are set. it must be noted that. TB0F or TB1F. will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. EMI and Time Base enable bits. To allow the program to branch to its respective interrupt vector address. LVD interrupt and EEPROM Interrupt will not be automatically reset and must be manually reset by the application program. the global interrupt enable bit. To allow the program to branch to its respective interrupt vector address. namely the TM Interrupts. must first be set. 1. External Peripheral Interrupt. ADF. When the interrupt is enabled. and comparator interrupt enable bits. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. is set. TB0E or TB1E. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. the request flags from the original source of the Multi-function interrupts. and respective external interrupt enable bit. must first be set. SIM Interrupt. CP0E and CP1E. the respective interrupt request flag. must first be set. the external interrupt request flags. they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. INT0F~INT3F. The pin must also be setup as an input by setting the corresponding bit in the port control register. appears on the external interrupt pins. and either one of the interrupts contained within each of Multi-function interrupt occurs. EMI. will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. They are controlled by the overflow signals from their respective timer functions. When the interrupt is serviced. To allow the program to branch to its respective interrupt vector address. the stack is not full and the Time Base overflows. will take place. When the interrupt is serviced. which occurs when the A/D conversion process finishes. are set. the stack is not full and the A/D conversion process has ended. are set. Comparator Interrupt The comparator interrupt is controlled by the two internal comparators. will take place. When the interrupt is enabled. will take place. External Peripheral Interrupt. A comparator interrupt request will take place when the comparator interrupt request flags. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags.

2010 . The clock source that generates fTB. can originate from several different sources. as shown in the System Operating Mode section. · TBC Register Bit Name R/W POR Bit 7 7 TBON R/W 0 6 TBCK R/W 0 5 TB11 R/W 1 4 TB10 R/W 1 3 LXTLP R/W 0 2 TB02 R/W 1 1 TB01 R/W 1 0 TB00 R/W 1 TBON: TB0 and TB1 Control 0: Disable 1: Enable TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 TB11~TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB LXTLP: LXT Low Power Control 0: Disable 1: Enable TB02~TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB Bit 6 Bit 5~4 Bit 3 Bit 2~0 T B 0 2 ~ T B 0 0 L X T M U L IR C X C o n fig u r a tio n O p tio n fS Y S /4 M B C fT U X fT B ¸ 2 8 ~ 2 1 5 T im e B a s e 0 In te r r u p t ¸ 2 1 2 ~ 2 1 5 T im e B a s e 1 In te r r u p t T B C K B it T B 1 1 ~ T B 1 0 Time Base Interrupt Rev.30 176 October 4. Their clock sources originate from the internal clock source fTB. the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. This fTB input clock passes through a divider. 1. which in turn controls the Time Base interrupt period.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods.

is set. and associated Multi-function interrupt enable bit. however only the Multi-function interrupt request flag will be also automatically cleared. the EMI bit will be automatically cleared to disable other interrupts. it has to be cleared by the application program. All of the TM interrupts are contained within the Multi-function Interrupts. is contained within the Multi-function Interrupt. a situation which occurs when a TM comparator P. the EMI bit will be automatically cleared to disable other interrupts. EEPROM Interrupt The EEPROM Interrupt. EMI. 2010 . As the LVF flag will not be automatically cleared. When the interrupt is enabled. however only the related MFnF flag will be automatically cleared. the stack is not full and a byte of data has been transmitted or received by the SIM interface. When the Serial Interface Interrupt is serviced. however only the Multi-function interrupt request flag will be also automatically cleared. When the Low Voltage Interrupt is serviced. A SIM Interrupt request will take place when the SIM Interrupt request flag. a subroutine call to the relevant Multi-function Interrupt vector locations. When the interrupt is enabled. must first be set. A TM interrupt request will take place when any of the TM request flags are set. it has to be cleared by the application program. will take place. a subroutine call to the respective Multi-function Interrupt vector. must first be set. DEF. it has to be cleared by the application program. must first be set. MFnE. must first be set. DEE.30 177 October 4. To allow the program to branch to its respective interrupt vector address. When the interrupt is enabled. As the SIMF flag will not be automatically cleared. TnAF and TnBF and three enable bits TnPE. while the Enhanced Type TM has three interrupts. TM Interrupts The Compact and Standard Type TMs have two interrupts each. An LVD Interrupt request will take place when the LVD Interrupt request flag. External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function Interrupt. A Peripheral Interrupt request will take place when the External Peripheral Interrupt request flag. To allow the program to branch to its respective interrupt vector address. the stack is not full and a low voltage condition occurs. however only the Multi-function interrupt request flag will be also automatically cleared. respective TM Interrupt enable bit. will take place. XPF. the stack is not full and a TM comparator match situation occurs. and Muti-function interrupt enable bits. is contained within the Multi-function Interrupt. EMI. which occurs when a negative edge transition appears on the PINT pin. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. the global interrupt enable bit. As the TM interrupt request flags will not be automatically cleared. When the interrupt is enabled. the global interrupt enable bit. and relevant Multi-function Interrupt enable bit. To allow the program to branch to its respective interrupt vector address. As the XPF flag will not be automatically cleared. will take place. When the External Peripheral Interrupt is serviced. which occurs when the Low Voltage Detector function detects a low power supply voltage. Low Voltage Interrupt enable bit. EEPROM Interrupt enable bit. the EMI bit will be automatically cleared to disable other interrupts. EMI. LVF. Rev. SIMF. must first be set. a subroutine call to the Multi-function Interrupt vector. When the interrupt is enabled.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Serial Interface Module Interrupt The Serial Interface Module Interrupt. will take place. When the TM interrupt is serviced. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. A or B match situation happens. will take place. and associated Multi-function interrupt enable bit. is set. the EMI bit will be automatically cleared to disable other interrupts. is set. it has to be cleared by the application program. which occurs when an EEPROM Write or Read cycle ends. a subroutine call to the respective Multi-function Interrupt. the global interrupt enable bit. the global interrupt enable bit. a subroutine call to the respective Multi-function Interrupt vector. also known as the SIM interrupt. the stack is not full and a negative transition appears on the External Peripheral Interrupt pin. When the EEPROM Interrupt is serviced. SIME. XPE. EMI. 1. TnAE and TnBE. they have to be cleared by the application program. To allow the program to branch to its respective interrupt vector address. which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address. The external peripheral interrupt pin is pin-shared with several other pins with different functions. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag. the stack is not full and an EEPROM Write or Read cycle ends. It must therefore be properly configured to enable it to operate as an External Peripheral Interrupt pin. As the DEF flag will not be automatically cleared. For the Enhanced Type TM there are three interrupt request flags TnPF. however only the Multi-function interrupt request flag will be also automatically cleared. is set. and the Serial Interface Interrupt enable bit. the global interrupt enable bit. EMI. and associated Multi-function interrupt enable bit. the EMI bit will be automatically cleared to disable other interrupts. external peripheral interrupt enable bit. LVE.

It is recommended that programs do not use the ²CALL² instruction within the interrupt service subroutine. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. however. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. a requested interrupt can be prevented from being serviced. Therefore. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. status register or other registers are altered by the interrupt service program. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode. their contents should be saved to the memory at the beginning of the interrupt service routine. Where a certain interrupt is contained within a Multi-function interrupt. then when the interrupt service routine is executed. 1. the individual request flag for the function needs to be cleared by the application program. even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. as only the Multi-function interrupt request flags. 2010 . if the contents of the accumulator. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Programming Considerations By disabling the relevant interrupt enable bits. Care must therefore be taken if spurious wake-up situations are to be avoided.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. The interrupt enable bits have no effect on the interrupt wake-up function. once an interrupt request flag is set. then when the interrupt is serviced. either a RET or RETI instruction may be executed. MF0F~MF5F. Interrupts often occur in an unpredictable manner or need to be serviced immediately.30 178 October 4. To return from an interrupt subroutine. will be automatically cleared. Rev. the wake up being generated when the interrupt request flag changes from low to high. As only the Program Counter is pushed onto the stack. If only one stack is left and the interrupt is not well controlled. situations such as external edge transitions on the external interrupt pins.

if the device is woken up by a WDT overflow. the interrupt which woke-up the device will not be immediately serviced. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the ²HALT² instruction. · The I/O ports will maintain their present condition. in which case the program will resume execution at the instruction following the ²HALT² instruction. When this instruction is executed. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. the other flags remain in their original status. will be set and the Watchdog time-out flag. The other situation is where the related interrupt is enabled and the stack is not full. will be cleared. but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. as there may be unbonbed pins. Care must also be taken with the loads. and causes a wake-up that only resets the Program Counter and Stack Pointer. TO. perhaps only in the order of several micro-amps. · The Data Memory contents and registers will maintain their present condition. the actual source of the wake-up can be determined by examining the TO and PDF flags. This also applies to devices which have different package types. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. The TO flag is set if a WDT time-out occurs.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Power Down Mode and Wake-up Entering the IDLE or SLEEP Mode There is only one way for the device to enter the SLEEP or IDLE Mode and that is to execute the ²HALT² instruction in the application program. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current. it can be woken up from one of various sources listed as follows: · An external reset · An external falling edge on Port A · A system interrupt · A WDT overflow program will stop at the ²HALT² instruction. a Watchdog Timer reset will be initiated. there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Also note that additional standby current will also be required if the configuration options have enabled the LIRC oscillator. in which case the regular interrupt response takes place. however. the wake-up function of the related interrupt will be disabled. 1. then two possible situations may occur. Although both of these wake-up methods will initiate a reset operation. the Power Down flag. In this situation. PDF. the device will experience a full system reset.30 179 October 4. If the system is woken up by an interrupt. which are setup as outputs. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full. · The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock source and the WDT is enabled. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode. Special attention must be made to the I/O pins on the device. The WDT will stop if its clock source originates from the system clock. · In the status register. When a Port A pin wake-up occurs. such as other CMOS inputs. If the system is woken up by an external reset. which are connected to I/O pins. the program will resume execution at the instruction following the ²HALT² instruction. 2010 . Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible. Rev. the following will occur: · The system clock will be stopped and the application Wake-up After the system enters the SLEEP or IDLE Mode.

The LVDEN bit is used to control the overall on/off function of the low voltage detector. an important consideration in power sensitive battery powered applications. it may be desirable to switch off the circuit when not in use. The Low Voltage Detector also has the capability of generating an interrupt signal.3V 110: 3. 1. As the low voltage detector will consume a certain amount of power.LVD Each device has a Low Voltage Detector function. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. also known as LVD. A low voltage condition is indicated when the LVDO bit is set. as it allows an early warning battery low signal to be generated. · LVDC Register Bit Name R/W POR Bit 7~6 Bit 5 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 LVDO R 0 4 LVDEN R/W 0 3 ¾ ¾ ¾ 2 VLVD2 R/W 0 1 VLVD1 R/W 0 0 VLVD0 R/W 0 unimplemented. Setting the bit high will enable the low voltage detector. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages. This enabled the device to monitor the power supply voltage. VLVD2~VLVD0. and provide a warning signal should it fall below a certain level. VDD.0V 001: 2.30 180 October 4.6V 111: 4.2V 010: 2. If the LVDO bit is low. 2010 .4V Bit Bit 3 Bit 2~0 Rev.0V 101: 3. read as ²0² VLVD2 ~ VLVD0: Select LVD Voltage 000: 2. Three bits in this register. this indicates that the VDD voltage is above the preset low voltage value.7V 100: 3. are used to select one of eight fixed voltages below which a low voltage condition will be detemined. read as ²0² LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect LVDEN: Low Voltage Detector Control 0: Disable 1: Enable unimplemented.4V 011: 2. Clearing the bit to zero will switch off the internal low voltage detector circuits.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Low Voltage Detector .

The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation.4V. PC6 ~ PC7 pins as common pins and using other output ports lines as segment pins. Note also that as the VDD voltage may rise and fall rather slowly. falls below this pre-determined value. causing an interrupt to be generated if VDD falls below the preset LVD voltage.0V and 4. In this case. however this bit is used in conjunction with the COMnEN bits to select which Port C pins are used for LCD driving. SCOM Function for LCD The devices have the capability of driving external LCD panels. This will cause the device to wake-up from the SLEEP or IDLE Mode. the LVDO bit will be set high indicating a low power supply voltage condition. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register. After enabling the Low Voltage Detector. 1. are pin shared with certain pin on the PC0~ PC3 or PC0 ~ PC1. Rev. the LVF interrupt request flag will be set.30 181 October 4. V D D V L V D LCD Operation An external LCD panel can be driven using this device by configuring the PC0~PC3 or PC0 ~ PC1. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. with a pre-specified voltage level stored in the LVDC register. V D D S C O M V D D o p e r a tin g c u r r e n t S C O M 0 ~ S C O M 3 C O M n E N S C O M E N L V D E N L V D O tL V D S /2 LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-function interrupts. VDD. The common pins for LCD driving. at the voltage nears that of VLVD.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage. in addition to polling the LVDO bit. LCD COM Bias SCOMEN 0 1 1 COMnEN X 0 1 Pin Function I/O I/O SCOMn O/P Level 0 or 1 0 or 1 VDD/2 Output Control LCD Bias Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. This has a range of between 2. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. PC6 ~ PC7 port. The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. When the power supply voltage. a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. there may be multiple bit LVDO transitions. however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. VDD. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. providing an alternative means of low voltage detection. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. The LCD signals (COM and SEG) are generated using the application program. 2010 . SCOM0~ SCOM3. This enables the LCD COM driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation.

2010 . 1.bit must not be set high ISEL1. ISEL0: ISEL1 ~ ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25mA 01: 50mA 10: 100mA 11: 200mA SCOMEN: SCOM module Control 0: Disable 1: Enable COM3EN: PC3 or SCOM3 selection 0: GPIO 1: SCOM3 COM2EN: PC2 or SCOM2 selection 0: GPIO 1: SCOM2 COM1EN: PC1 or SCOM1 selection 0: GPIO 1: SCOM1 COM0EN: PC0 or SCOM0 selection 0: GPIO 1: SCOM0 Bit 6~5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev.bit must be reset to zero for correct operation 1: Unpredictable operation .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · SCOMC Register ¨ HT66F20 Bit Name R/W POR 7 D7 R/W 0 6 ISEL1 R/W 0 5 ISEL0 R/W 0 4 SCOMEN R/W 0 3 COM3EN R/W 0 2 COM2EN R/W 0 1 COM1EN R/W 0 0 COM0EN R/W 0 Bit 7 Reserved Bit 0: Correct level .30 182 October 4.

bit must be reset to zero for correct operation 1: Unpredictable operation . ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25mA 01: 50mA 10: 100mA 11: 200mA SCOMEN: SCOM module control 0: disable 1: enable COM3EN: PC7 or SCOM3 selection 0: GPIO 1: SCOM3 COM2EN: PC6 or SCOM2 selection 0: GPIO 1: SCOM2 COM1EN: PC1 or SCOM1 selection 0: GPIO 1: SCOM1 COM0EN: PC0 or SCOM0 selection 0: GPIO 1: SCOM0 Bit 6~5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev.30 183 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 ¨ HT66F30/HT66F40/HT66F50/HT66F60 Bit Name R/W POR 7 D7 R/W 0 6 ISEL1 R/W 0 5 ISEL0 R/W 0 4 SCOMEN R/W 0 3 COM3EN R/W 0 2 COM2EN R/W 0 1 COM1EN R/W 0 0 COM0EN R/W 0 Bit 7 Reserved Bit 0: Correct level . 2010 .bit must not be set high ISEL1. 1.

2. ERC 3. 2 instructions 7 LVR Options 8 LVR Function: 1. these options are selected using the HT-IDE software development tools. 8MHz 3. 2010 .fS: 1. HXT 2. Disable CLRWDT Instructions Selection: 1. 1.55V 3. I/O pin Watchdog Options 6 Watchdog Timer Function: 1. Enable 2. the details of which are shown in the table. LXT 2. During the development process. fSUB 2. As these options are programmed into the device using the hardware programming tools. LIRC WDT Clock Selection . Enable 2. 12MHz Options 1 2 3 4 Note: The fSUB and the fTBC clock source are LXT or LIRC selection by the fL configuration option. Reset Pin Options 5 PB0/RES Pin Options: 1. All options must be defined for proper system function. once they are selected they cannot be changed later using the application program.30 184 October 4. No. Oscillator Options High Speed System Oscillator Selection .15V 4.fH: 1. 1 instructions 2. RES pin 2. fSYS/4 HIRC Frequency Selection: 1.10V 2.20V 9 Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. 3. HIRC Low Speed System Oscillator Selection . Disable LVR Voltage Selection: 1. 2. 4.fL: 1. 4MHz 2.

No debounce 2.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 No. Disable SPI .0 1 m F * * D D V D D R e s e t C ir c u it R E S A N 0 ~ A N 1 1 P B 5 ~ P B 7 V S S P C 0 ~ P C 7 P D 0 ~ P D 7 P E 0 ~ P E 5 P F 2 ~ P F 7 P G 0 ~ P G 1 X T 1 X T 2 0 . Rev. 4 system clock debounce Options 11 12 13 Application Circuits V 0 . Enable 2.30 185 October 4.1 ~ 1 m F O S C C ir c u it S e e O s c illa to r S e c tio n O S C C ir c u it S e e O s c illa to r S e c tio n O S C 1 O S C 2 Note: ²*² It is recommended that this component is added for added ESD protection.CSEN bit: 1. Disable I2C Debounce Time Selection: 1. Enable 2. Disable SPI .1 m F 1 N 4 1 4 8 * 1 0 k W ~ 1 0 0 k W 3 0 0 W * 0 .WCOL bit: 1. Enable 2. 2 system clock debounce 3. SIM Options 10 SIM Function: 1. 1. 2010 . ²**² It is recommended that this component is added in environments where power line noise is significant.

Even.RX pin is high impedance when the UART receive module is disabled · CMOS clock input. Universal Asynchronous Receiver and .Transmit and Receive Multiple Interrupt Transmitter (UART) communication .Support for interrupt on address detect . odd or no parity options .4-byte deep FIFO receiver data buffer Generation Sources: ¨ Transmitter Empty ¨ Transmitter Idle ¨ Receiver Full ¨ Receiver Overrun ¨ Address Mode Detect . CLKI.Baud rate generator with 8-bit prescaler .8 or 9 bit character length .last character bit=1 . Possible applications could include data communication networks between microcontrollers. portable and battery operated device communication. factory automation and process control to name but a few.Parity. noise and overrun error detection .One or two stop bits . up to 20MHz at 5V operating voltage UART Module Overview The device contains a fully embedded full-duplex asynchronous serial communications UART interface that enables data transmission and data reception with external devices. UART Module Block Diagram U A R T M o d u le S D I S D O S C K V D D S P I In te rfa c e U A R T In te rfa c e T X R X S C S C L K I IN T V D D G N D Rev.TX pin is high impedance when the UART transmit module is disabled .Address Detect Interrupt . 1.Transmitter and receiver enabled independently .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 UART Module Serial Interface UART Module Features · Interconnected to Holtek MCU via SPI interface · Full-duplex. framing. low-cost data links between PCs and peripheral devices.30 186 October 4. 2010 .

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Pin Assignment P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S P A 0 /C 0 X /T P 0 _ 0 /A N 0 V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S N C N C N C N C 9 8 7 6 5 4 3 2 1 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 0 1 1 1 2 1 5 1 4 1 3 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F R X T X N C N C P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C N 7 N 6 E F 1 2 3 4 5 6 7 8 9 1 0 N C N C N C N C T X R X C S C L D A D O ] ] ] 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 ] N C N C P D P D P C P C P C P C P E P E 5 4 /[T 5 /[T 6 /[T 7 /[T 0 /T 1 /T 4 /[T P 2 _ P 0 _ P 0 _ P 1 A P 1 B P 1 B P 1 B 1 ] 0 ]/S ]/S C _ 0 /S _ 1 /S _ 2 ] 1 ] C O O M C O C O M 2 3 M 0 M 1 N 3 N 2 N 1 N 0 1 X ] N 5 N 4 H T 6 6 F U 4 0 4 0 Q F N -A 2 6 2 5 2 4 2 3 2 2 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 H T 6 6 F U 3 0 2 4 S K D IP -A /S O P -A /R E S & A V /O S C /O S C /X T 1 /X T 2 & A V /[IN T /[IN T /[C 0 X S S 0 ] 1 ] ] D D 2 1 P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 2 3 4 5 6 7 8 9 P F 1 /[C 1 X ] P F 0 /[C 0 X ] P E 7 /[IN T 1 ] P E 6 /[IN T 0 ] V S S & A V S S P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 V D D & A V D D P B 0 /R E S P E 5 P E 4 /[T P 1 B _ 2 ] P C 1 /T P 1 B _ 1 /S C O M 1 P C 0 /T P 1 B _ 0 /S C O M 0 N C P C 7 /[T P 1 A ]/S C O M 3 P C 6 /[T P 0 _ 0 ]/S C O M 2 P E 3 P E 2 P E 1 N C N C 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 P A 1 /T P 1 A /A N 1 P A 2 /T C K 0 /C 0 + /A N 2 P A 3 /IN T 0 /C 0 -/A N 3 P A 4 /IN T 1 /T C K 1 /A N 4 P A 5 /C 1 X /S D O /A N 5 P A 6 /S D I/S D A /A N 6 P A 7 /S C K /S C L /A N 7 P B 5 /S C S /V R E F P B 6 /[S D O ] P B 7 /[S D I/S D A ] P D 6 /[S C K /S C L ] P D 7 /[S C S ] N C N C N C P C 2 /T C K /P C K /C 1 + P C 3 /P IN T /T P 2 _ 0 /C 1 N C R X T X N C P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C P F 0 /[C E F N 7 N 6 N 5 N 4 N 3 N 2 N 1 N 0 1 X ] 0 X ] 1 2 3 4 5 6 7 8 1 0 1 1 9 N C N C N C N C N C T X R X C S C L D A D O ] ] 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 ] ] 3 3 3 2 3 1 3 0 H T 6 6 F U 4 0 4 4 L Q F P -A 2 9 2 8 2 7 2 6 2 5 2 4 2 3 N C P D P D P E P E P E P E P C P C P C P C 0 1 2 3 4 /[T P 2 _ 1 ] 5 /[T P 0 _ 1 ] 6 /[T 7 /[T 0 /T 1 /T P 0 _ P 1 A P 1 B P 1 B 0 ]/S ]/S C _ 0 /S _ 1 /S C O O M C O C O M 2 3 M 0 M 1 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 /R E & A /O S /O S /X T /X T & A /[IN /[IN S V D D C 1 C 2 1 2 V S S T 0 ] T 1 ] P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S /[T P 1 B _ 2 ] N C N C N C N C N C N C N C N C N C T X R X C S C L D A D O H T 6 6 F U 4 0 4 8 S S O P -A P B 5 /S C S /V P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 N R E /A N /A N /A N /A N /A N /A N /A N /A N N P F 1 /[C 1 C F 7 5 4 3 1 0 2 8 1 0 1 1 1 2 9 7 6 1 2 ] 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 ] ] 3 6 3 5 4 5 3 4 3 3 3 2 ] N C P D P D P E P E P E P E P C P C 0 1 2 3 P 0 _ 0 ]/S C O M 2 P 1 A ]/S C O M 3 P 1 B _ 0 /S C O M 0 P 1 B _ 1 /S C O M 1 4 /[T P 2 _ 1 ] 5 /[T P 0 _ 1 ] 6 H T 6 6 F U 4 0 4 8 Q F N -A 3 1 3 0 2 9 2 8 2 7 2 6 C X ] 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 6 /[T 7 /[T N C P C 0 /T P C 1 /T P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /R E S & A V /O S C /O S C /X T 1 /X T 2 & A V /[IN T /[IN T /[C 0 X S S 0 ] 1 ] ] D D 1 2 /[T P 1 B _ 2 ] Rev. 1. 2010 .30 187 October 4.

1.30 188 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S N C N C N C N C N C T X R X C S C L D A D O ] ] ] 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 N C N C N C N C N C N C T X R X C S C L D A D O ] ] ] ] ] N R E /A N /A N /A N /A N /A N /A N /A N /A N N P F 1 /[C 1 C F 6 4 3 2 1 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 9 1 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 2 3 3 6 3 5 4 3 4 5 6 7 3 3 3 2 P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C P F 0 /[C N 5 N 4 N 3 N 2 N 1 N 0 1 X ] 0 X ] N 7 N 6 E F 3 3 3 2 3 1 3 0 H T 6 6 F U 5 0 4 4 L Q F P -A 2 9 2 8 2 7 2 6 2 5 2 4 2 3 N C P D P D P E P E P E P E P C P C P C P C 0 1 2 4 /[T P 2 _ 1 ] 5 /[T P 0 _ 1 ] 3 /[T 6 /[T 7 /[T 0 /T 1 /T P 3 _ P 0 _ P 1 A P 1 B P 1 B 1 ] 0 ]/S ]/S C _ 0 /S _ 1 /S C O O M C O C O M 2 3 M 0 M 1 P B 5 /S C S /V P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 7 5 H T 6 6 F U 5 0 4 8 Q F N -A 3 1 3 0 2 9 2 8 2 7 2 6 2 5 0 C X ] N C P D P D P E P E P E P E P C P C 0 1 2 4 /[T P 2 _ 1 ] 5 /[T P 0 _ 1 ] N C P C 0 /T P 1 B _ 0 /S C O M 0 P C 1 /T P 1 B _ 1 /S C O M 1 3 /[T P 3 _ 1 ] 6 /[T P 0 _ 0 ]/S C O M 2 7 /[T P 1 A ]/S C O M 3 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 /[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S & A V D D /O S C 1 /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ] /[IN T 1 ] P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S N C N C N C N C T X R X C S C L D A D O ] ] 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S & A V D D /O S C 1 /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ] /[IN T 1 ] /[C 0 X ] P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S N C N C N C N C N C T X R X C S C L D A D O ] ] ] ] ] ] N C N C P D P D P C P C P C P C P E P E 4 /[T 5 /[T 6 /[T 7 /[T 0 /T 1 /T 4 /[T 5 /[T P 2 _ P 0 _ P 0 _ P 1 A P 1 B P 1 B P 1 B P 3 _ 1 ] 0 ]/S ]/S C _ 0 /S _ 1 /S _ 2 ] 0 ] 1 ] C O O M C O C O M 2 3 M 0 M 1 P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C 1 X ]/A N P F 0 /[C 0 X ]/A N E F 1 2 3 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 9 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 P B 5 /S C S /V R P A 7 /S C K /S C L /A P A 6 /S D I/S D A /A P A 5 /C 1 X /S D O /A P A 4 /IN T 1 /T C K 1 /A P A 3 /IN T 0 /C 0 -/A P A 2 /T C K 0 /C 0 + /A P A 1 /T P 1 A /A P A 0 /C 0 X /T P 0 _ 0 /A P F 1 /[C 1 X ]/A N N 7 N 6 N 5 N 4 N 3 N 2 N 1 N 0 1 1 E F H T 6 6 F U 6 0 4 0 Q F N -A 2 6 2 5 2 4 2 3 2 2 2 1 N 5 N 4 N 3 N 2 N 1 N 0 1 1 1 0 N 7 N 6 H T 6 6 F U 6 0 4 4 L Q F P -A 2 9 2 8 2 7 2 6 2 5 2 4 2 3 N C P D P D P E P E P E P E P C P C P C P C 4 /[T P 5 /[T P 0 /[IN 1 /[IN 2 /[IN 3 /[T P 6 /[T P 7 /[T P 0 /T P 1 /T P 2 _ 1 ] 0 _ 1 ] T 0 ] T 1 ] T 2 ] 3 _ 1 ] 0 _ 0 ]/S 1 A ]/S C 1 B _ 0 /S 1 B _ 1 /S C O O M C O C O M 2 3 M 0 M 1 P B 5 /S C S /V P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 R /A /A /A /A /A /A /A /A P F 1 /[C 1 X ]/A N N C E F N 7 N 6 N 5 N 4 N 3 N 2 N 1 N 0 N C 1 1 1 2 3 4 5 6 7 8 1 0 1 1 1 2 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /R E S & A V /O S C /O S C /X T 1 /X T 2 & A V /[IN T /[IN T /[C 0 X S S 0 ]/A N 8 1 ]/A N 9 ]/A N 1 0 P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S N C N C N C N C N C N C T X R X C S C L D A D O ] ] H T 6 6 F U 6 0 4 8 L Q F P -A /Q F N -A ] 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 /[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S & A V D D /O S C 1 /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ]/A N 8 /[IN T 1 ]/A N 9 D D 1 2 P D 7 /[S P D 6 /[S C K /S P B 7 /[S D I/S P B 6 /[S N C N C N C N C N C T X R X C S ] C L ] D A ] D O ] P F 5 P F 4 ] N C P D P D P E P E P E P E P C P C N C P C 0 /T P 1 B _ 0 /S C O M 0 P C 1 /T P 1 B _ 1 /S C O M 1 4 /[T 5 /[T 0 /[IN 1 /[IN 2 /[IN 3 /[T 6 /[T 7 /[T P 2 _ 1 ] P 0 _ 1 ] T 0 ] T 1 ] T 2 ] P 3 _ 1 ] P 0 _ 0 ]/S C O M 2 P 1 A ]/S C O M 3 P F 3 P F 2 P B 5 /S C S /V R E F P A 7 /S C K /S C L /A N 7 P A 6 /S D I/S D A /A N 6 P A 5 /C 1 X /S D O /A N 5 P A 4 /IN T 1 /T C K 1 /A N 4 P A 3 /IN T 0 /C 0 -/A N 3 P A 2 /T C K 0 /C 0 + /A N 2 P A 1 /T P 1 A /A N 1 P A 0 /C 0 X /T P 0 _ 0 /A N 0 P F 1 /[C 1 X ]/A N 1 1 P F 0 /[C 0 X ]/A N 1 0 1 2 3 4 5 6 7 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 8 H T 6 6 F U 6 0 5 2 Q F P -A 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 N C P D P D P E P E P E P E P F P F P G P G P C P C 6 7 4 /[T 5 /[T 0 /[IN 1 /[IN 2 /[IN 3 /[T 0 /[C 1 /[C 6 /[T 7 /[T P 2 _ 1 ] P 0 _ 1 ] T 0 ] T 1 ] T 2 ] P 3 _ 1 ] 0 X 1 X P 0 P 1 ] ] _ 0 ]/S C O M 2 A ]/S C O M 3 P C 0 P C 1 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P E 4 P E 5 P B 0 V D D P B 1 P B 2 P B 3 P B 4 V S S P E 6 P E 7 P F 0 /[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S & A V D D /O S C 1 /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ]/A N 8 /[IN T 1 ]/A N 9 /[C 0 X ]/A N 1 0 /T P 1 B _ 0 /T P 1 B _ 1 /[T P 1 B _ 2 /[T P 3 _ 0 ] /R E S & A V D D /O S C 1 /O S C 2 /X T 1 /X T 2 & A V S S /[IN T 0 ]/A /[IN T 1 ]/A /S C O M 0 /S C O M 1 ] N 9 N 8 Rev. 2010 .

0 Rev. SDI=H. then RX is the UART serial data input If UARTEN=0 or RXEN=0.0 4. SCK=fCLKI/4. SCK=fCLKI/4.5 10.6 mA VIL VIH IOL 0 0.0 ¾ ¾ 5. Output no load ¾ ¾ 3. UART disabled) 5. then RX is high impedance External UART TX serial data output pin If UARTEN=1 and TXEN=1. SCS=VDD. Ta=25°C Unit mA mA mA mA ISTB Standby Current * (SPI disabled.0V RX Port Source Current 5. SCK=fCLKI/4. Output no load fCLKI=12MHz.0V TXEN=1. Typ.0V Conditions fCLKI=12MHz.0 0.0 -8. Output no load fCLKI=6MHz.0V VO=0. RXEN=1. Max. UARTEN=0. 5. then TX is high impedance Internal Slave SPI Serial Data In Input Signal Internally connected to the MCU Master SPI SDO output signal Internal Slave SPI Serial Data Out Output Signal Internally connected to the MCU Master SPI SDI input signal Internal Slave SPI Serial Clock Input Signal Internally connected to the MCU Master SPI SCK output signal Internal Slave SPI Device Select Input Signal Internally connected to the MCU Master SPI SCS output signal -. 2010 .0V 2.0V 5.0 -3.0 2.7VDD 2.2 4.3VDD VDD ¾ ¾ ¾ ¾ V V mA mA mA mA IOH 3.0V IDD1 Operating Current * (SPI Enabled.0V VO=0. UART enabled) 5. SCK=fCLKI/4.C.1VDD ¾ ¾ ¾ ¾ 0.5 -5. Characteristics Test Conditions Symbol Parameter VDD 3.0 25. 1. TX O SDI SDO SCK I O I SCS I CLKI I INT NC O ¾ Notes: The pin description for all pins with the exception of the UART TX and RX pins are described in the preceding MCU section. RX=H. Output no load fCLKI=16MHz.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 UART Module Pin Description Pin Name RX I/O I Description External UART RX serial data input pin If UARTEN=1 and RXEN=1.30 189 October 4. SCK=fCLKI/4.8 Min. UART Module D.2V IDD2 Operating Current * (SPI enabled. Output no load ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 1.connected to pull high resistor Internal Clock Input Signal Internally connected to the MCU Master PCK output signal Internal UART Interrupt Output Signal Internally connected to the MCU Master PINT input signal A UART related interrupt will generate a low pulse signal on this line Implies that the pin is ²Not Connected² and can therefore not be used.9VDD -1. then TX is the UART serial data output If UARTEN=0 or TXEN=0. UART disabled) Input Low Voltage for RX Ports Input High Voltage for RX Ports TX Port Sink Current fCLKI=16MHz.

the standby current shown above should be taken into account. VDD Conditions ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 62. If the UART module is enabled. either IDD1 or IDD2 should be added to calculate the relevant operating current of the device for different conditions. Characteristics Symbol Parameter tCP SCK Period (tCH + tCL) tCH 3.0V SCK Low Time 5.0V SCS High Pulse Width 5.5 50. 2010 . Unit UART Module A. Max. Typ.0V Typ.0V Note: Conditions ¾ 20 10 60 30 100 50 kW kW Min.0V Pull-high Resistance for SCS only 5.0V 5. Ta=25°C Test Conditions Min.0V 3. Similarly.C.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Test Conditions Symbol Parameter VDD RPH 3. Max.0V SCS to SCK Setup Time SCS to SCK Hold Time SDI to SCK Setup Time SDI to SCK Hold Time SPI Output Rise Time SPI Output Fall Time SPI Data Output Delay Time ¾ ¾ ¾ ¾ ¾ ¾ ¾ tCL tCSW tCSS tCSH tSDS tSDH tR tF tW Rev. To calculate the standby current for the whole device.0 28 22 28 22 500 400 100 0 100 0 ¾ ¾ 0 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 10 10 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.30 190 October 4. 1.0V SCK High Time 5. the operating current IDD2 here is the additional current consumed when both the slave SPI interface and UART interface are enabled.0V 3. Unit ²*² The operating current IDD1 listed here is the additional current consumed when the slave SPI interface in the UART module is enabled and the UART interface is disabled.

UART Module Internal Signal In addition to the TX and RX external pins described above there are other MCU to UART Module interconnecting lines that are described in the following table. that is returned to a high level before the 16-bit data transaction is completed. If SCS is de-asserted.30 191 October 4. When the first 8 bits of data are transmitted. The UART function control is executed by the MCU using its SPI Master serial interface. For write operations. The SPI interface on this device is comprised of four signals: SCS (SPI Chip Select). asserts SCS by pulling it low to start the data transaction cycle. SCS must remain at a low level until the whole 16-bit data transaction is completed. Each transaction consists of a command phase and a data phase. Note that these lines are internal to the device and are not bonded to external pins. The SPI master. All data transmissions and receptions between MCU and UART module including UART commands are conducted along this interconnected SPI interface. V D D UART Module SPI Interface The MCU communicates with the UART Module via an internal SPI interface. which is the MCU. as the device will latch the SDI status on the next SCK rising edge. When SCS is high. After a complete transaction has been implemented. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The input data bit on SDI should be stable before the next SCK rising edge.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 UART Module Functional Description The embedded UART Module is full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. Regarding the SDO line. the MCU master SPI needs to pull SCS to a low level first and then also pull SCK low. V D D S C K S D O M C U S D I S C S P IN T P C K G N D S C K S D I S D O S C S IN T C L K I V D D R X U A R T M o d u le T X G N D MCU to UART Internal Connection Rev. The UART module contains its own independent interrupt which can be used to indicate when a data reception occurs or when a data transmission has terminated. SPI Timing Both read and write operations are conducted along the SPI common interface with the following format: · Write Type Format: 8-bit command input + 8-bit data input · Read Type Format: 8-bit command input + 8-bit data output To initiate a data transaction. SCK (SPI Clock). the SPI interface is disabled and SDO will be set to a high impedance state. the master needs to set SCS to a high level in preparation for the next data transaction. all data bits will be discarded by the UART Module SPI slave. SDI (Serial Data Input) and SDO (Serial Data Output). the output data bit will be updated on the SCK falling edge. 1. Instead. 2010 . which requires 16 SCK clock cycles. There are 16 bits of data transmitted and/or received by the SPI interface for each transaction. the device will begin to execute the command only after it receives a 16-bit serial data sequence and when the SCS has been set high again by the master. Interconnection between the MCU and the UART module is implemented by internally connecting the MCU Master SPI interface to the UART Slave SPI interface. The master needs to obtain the line status before the next SCK falling edge. SCS should not return to a high level.

This shared register known as the TXR/RXR register is used for both data transmission and data reception. LSB first. the Receiver Shift Register is not mapped into the Data Memory area and is inaccessible to the application program.30 192 October 4. 1. the master can de-assert the SCS pin to abort the transaction at any time which will cause any data transactions to be abandoned. Only the RXR register is accessible to the application program. The TX pin is the UART transmitter serial data output pin if the corresponding control bits named UARTEN in UCR1 register and TXEN in UCR2 register are set to 1. although referred to in the text. UART Module External Pin Interfacing To communicate with an external serial interface. only exists as a single shared register physically. as separate TXR and RXR registers. When the shift register is full. The actual data to be transmitted from the MCU is first transferred SCS SCK SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO Writing Type Format: 8-bit Command Input + 8-bit Data Input SCS SCK tw SDI A7 A6 A5 A4 A3 A2 A1 A0 SDO D7 D6 D5 D4 D3 D2 D1 D0 Reading Type Format: 8-bit Command Input + 8-bit Data Output Transmitter Shift Register (TSR) MSB LSB Receiver Shift Register (RSR) MSB LSB Buffer 3 Buffer 2 Buffer 1 RX Register (RXR) TX Pin RX Pin TX Register (TXR) Baud Rate Generator Data to be transmitted Data received UART Data Transfer Scheme Rev. If the control bit UARTEN or TXEN is equal to zero. the TX pin is in the state of high impedance. If necessary. Similarly. the data will then be transferred from the shift register to the internal RXR register. UART Data Transfer Scheme The following block diagram shows the overall data transfer structure arrangement for the UART. the device will begin to execute the command only after it receives an 8-bit read command after which it will be ready to output data. Only the TXR register is accessible to the application program. the RX pin is in the state of high impedance. the RX pin is the UART receiver serial data input pin if the corresponding control bits named UARTEN and RXEN in UCR1 and UCR2 registers are set to 1. and in application programs. onto the TX pin at a rate controlled by the Baud Rate Generator. 2010 . LSB first. to the TXR register by the application program. where it is buffered and can be manipulated by the application program. from where it is shifted in. The data will then be transferred to the Transmitter Shift Register named TSR from where it will be shifted out. the Transmitter Shift Register is not mapped into the Data Memory area and is inaccessible to the application program.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 For read operations. to the Receiver Shift Register named RSR at a rate controlled by the Baud Rate Generator. Data to be received by the UART is accepted on the external RX pin. It should be noted that the actual register for data transmission and reception. the internal UART has two external pins known as TX and RX. If the control bit UARTEN or RXEN is equal to zero.

The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The USR. When the flag is ²1². All flags within the USR register are read only. it indicates that the parity of the received word is incorrect. A[2:0] 00H 01H 02H 03H 04H 05H~ 07H Name USR UCR1 UCR2 BRG UCR3 Unused Reset 0000 1011 0000 0X00 0000 0000 XXXX XXXX 0--. For reading and writing to registers both command and address information is contained within a single byte. UCR2 and UCR3 registers control the overall function of the UART module. 2010 . 1. The actual data to be transmitted and received on the serial interface is managed through the TXR/RXR data register. while the BRG register controls the Baud rate. When this read only flag is ²0². Command Type Read FIFO Read Register Write FIFO Write Register Bit 7 0 0 0 0 Bit 6 0 0 0 0 Bit 5 0 0 0 0 Bit 4 0 1 0 1 Bit 3 0 0 1 1 Bit 2 X A2 X A2 Bit 1 X A1 X A1 Bit 0 X A0 X A0 Note: ²X² here stands for ²don¢t care² UART Status and Control Registers There are six registers associated with the UART function. UCR1. When the flag is ²1². NF: Noise flag 0: no noise is detected 1: noise is detected The NR flag is the noise flag.---Bit 7 PERR UARTEN TXEN BRG7 URST Bit 6 NF BNO RXEN BRG6 ¾ Bit 5 FERR PREN BRGH BRG5 ¾ Bit 4 OERR PRT ADDEN BRG4 ¾ Reserved UART Register Summary Bit 3 RIDLE STOPS WAKE BRG3 ¾ Bit 2 RXIF TXBRK RIE BRG2 ¾ Bit 1 TIDLE RX8 TIIE BRG1 ¾ Bit 0 TXIF TX8 TEIE BRG0 ¾ · USR Register The USR register is the status register for the UART. The format for reading and writing is shown in the following table. it indicates no noise condition.------. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Further explanation on each of the flags is given below: Bit Name R/W POR Bit 7 7 PERR R 0 6 NF R 0 5 FERR R 0 4 OERR R 0 3 RIDLE R 1 2 RXIF R 0 1 TIDLE R 1 0 TXIF R 1 PERR: Parity error flag 0: no parity error is detected 1: parity error is detected The PERR flag is the parity error flag. Bit 6 Rev. When this read only flag is ²0². which can be read by the application program to determine the present status of the UART.30 193 October 4. This error flag is applicable only if Parity mode (odd or even) is selected.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 UART Commands There are both read and write commands for the UART Module. it indicates that the UART has detected noise on the receiver input. it indicates a parity error has not been detected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register.

RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. which is a read to the status register USR followed by an access to the RXR data register. an interrupt is generated if RIE=1 in the UCR2 register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. When the flag is ²1². and/or PERR are set within the same clock cycle. The flag is cleared by a software sequence. FERR. followed by a read from the RXR register. TXIF: Transmit TXR data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When TIDLE is equal to ²1².30 194 October 4. When the flag is ²1². and if the RXR register has no data available.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Bit 5 FERR: Framing error flag 0: no framing error is detected 1: framing error is detected The FERR flag is the framing error flag. it indicates that there is no overrun error. If one or more errors are detected in the received word. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1. When the flag is ²1². it indicates that the RXR read data register contains new data. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. it indicates that there is no framing error. it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. OERR: Overrun error flag 0: no overrun error is detected 1: overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. This flag will be set to ²1² when the TXIF flag is ²1² and when there is no transmit data or break character being transmitted. When this read only flag is ²0². Between the completion of the stop bit and the detection of the next start bit. it indicates that the receiver is idle. RIDLE: Receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. it indicates that the RXR read data register is empty. it indicates that a framing error has been detected for the current character. The flag is not generated when a data character or a break is queued and ready to be sent. When the flag is ²1². the appropriate receive-related flags NF. When the flag is ²1². it indicates that the transmitter shift register has received a character from the TXR data register. the RIDLE bit is ²1² indicating that the UART receiver is idle and the RX pin stays in logic high condition. 2010 . When the contents of the shift register are transferred to the RXR register. When this read only flag is ²0². it indicates that a transmission is in progress. The RXIF flag is cleared when the USR register is read with RXIF set. the TXIF flag bit will also be set since the transmit data register is not yet full. When this read only flag is ²0². When this read only flag is ²0². the TX pin becomes idle with the pin state in logic high condition. When this read only flag is ²0². When this read only flag is ²0². Note that when the TXEN bit is set. it indicates that the character is not transferred to the transmitter shift register. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. TIDLE: Transmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag.

30 195 October 4. RXIF. PERR and NF bits will be cleared. then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. When this bit is equal to ²1². When the bit is equal to ²1². TXIF and RIDLE bits will be set. which can have a choice of either 8-bit or 9-bit format. while the TIDLE. the UART will be disabled and the RX pin as well as the TX pin will be in the state of high impedance. TXBRK. In addition. odd parity type will be selected. all pending transmissions and receptions will be terminated and the module will be reset as defined above. then an 8-bit data length format will be selected. there are transmit break characters and the transmitter will send logic zeros. it will restart in the same configuration.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function such as overall on/off control. When this bit is ²0². RXEN. OERR. If the UART is disabled. 2010 . the parity function will be enabled. TXBRK: Transmit break character 0: no break character is transmitted 1: break characters transmit The TXBRK bit is the Transmit Break Character bit. PRT: Parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator This bit is the parity type selection bit. When the bit is ²1². then even parity type will be selected. If this bit is equal to ²0². If the bit is equal to ²0². If the bit is equal to ²0². Also the TXEN. If the UART is active and the UARTEN bit is cleared. FERR. then only one stop bit is used. When this bit is equal to ²1². all error and status flags will be reset. When the UART is disabled. the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. after the buffered data has been transmitted. TX and RX pins are in the state of high impedance 1: enable UART. 1. If the bit is equal to ²0². then the parity function will be disabled. When this bit is equal to ²0². When this bit is equal to ²1². Further explanation on each of the bits is given below: Bit Name R/W POR Bit 7 7 UARTEN R/W 0 6 BNO R/W 0 5 PREN R/W 0 4 PRT R/W 0 3 STOPS R/W 0 2 TXBRK R/W 0 1 RX8 R X 0 TX8 W 0 ²x² unknown UARTEN: UART function enable control 0: disable UART. Other control bits in UCR1. UCR2 and BRG registers will remain unaffected. STOPS: Number of Stop bits selection 0: one stop bit format is used 1: two stop bits format is used This bit determines if one or two stop bits are to be used. the value of the baud rate counter will be reset. the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When this bit is equal to ²1². When the UART is re-enabled. data transfer bit length. If 9-bit data length format is selected. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Rev. parity control. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to ²1². there are no break characters and the TX pin operates normally. a 9-bit data length format will be selected. etc. BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format. it will empty the buffer so any character remaining in the buffer will be discarded. two stop bits are used. PREN: Parity function enable control 0: parity function is disabled 1: parity function is enabled This is the parity enable bit.

the low speed mode is selected. This bit.30 196 October 4. has a value of ²1². the high speed mode is selected. When this bit is equal to ²0². the transmitter will be enabled and the TX pin will be controlled by the UART. together with the value placed in the baud rate register BRG. The register also serves to control the baud rate speed. an interrupt request will be generated each time the received word has the address bit set. rather than data. When it occurs. In addition the receive buffers will be reset. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. the transmitter will be disabled with any pending data transmissions being aborted. When this bit is equal to ²1². in which case this bit location will store the 9th bit of the received data known as RX8. If the address bit known as the 8th or 9th bit of the received word is ²0² with the address detect function being enabled. BRGH: Baud Rate speed selection 0: low speed baud rate 1: high speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. an interrupt will not be generated and the received data will be discarded. in which case this bit location will store the 9th bit of the transmitted data known as TX8. controls the Baud Rate of the UART. 2010 . 1. If this bit is equal to ²1². In this situation the TX pin will be in the state of high impedance. the RX pin will be in the state of high impedance. which corresponds to RX7 if BNO=0 or the 9th bit. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. If this situation occurs. RXEN: UART Receiver enable control 0: UART receiver is disabled 1: UART receiver is enabled The bit named RXEN is the Receiver Enable Bit. If the TXEN bit is equal to ²1² and the UARTEN bit is also equal to ²1². In this situation the RX pin will be in the state of high impedance. One of its main functions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. the TX pin will be in the state of high impedance. In addition the buffers will be reset. if the 8th bit. the receiver will be disabled with any pending data receptions being aborted. the address detect function is enabled. which corresponds to RX8 if BNO=1. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. When this bit is equal to ²0². ADDEN: Address detect function enable control 0: address detect function is disabled 1: address detect function is enabled The bit named ADDEN is the address detect function enable control bit. If the bit is equal to ²0². If the RXEN bit is equal to ²1² and the UARTEN bit is also equal to ²1². TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used. then the received word will be identified as an address.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used. the receiver will be enabled and the RX pin will be controlled by the UART. If the corresponding interrupt is enabled. which is the 8th or 9th bit depending on the value of BNO. If this situation occurs. Bit 0 · UCR2 register The UCR2 register is the second of the UART control registers and serves several purposes. Further explanation on each of the bits is given below: Bit Name R/W POR Bit 7 7 TXEN R/W 0 6 RXEN R/W 0 5 BRGH R/W 0 4 ADDEN R/W 0 3 WAKE R/W 1 2 RIE R/W 0 1 TIIE R 1 0 TEIE W 1 TXEN: UART Transmitter enable control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. Bit 6 Bit 5 Bit 4 Rev. receiver wake-up function enable and the address detect function enable.

2010 . If this bit is equal to ²1² and when the receiver overrun flag OERR or receive data available flag RXIF is set.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Bit 3 WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or disables the receiver wake-up function. If this bit is equal to ²0² and the MCU is in IDLE or SLEEP mode. When this bit is equal to ²0². the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. any edge transitions on the RX pin will not wake-up the device. Bit 2 Bit 1 Bit 0 · UCR3 register The UCR3 register is the last of the UART control registers and controls the software reset operation of the UART module. the UART operates normally. If this bit is equal to ²1² and the MCU is in IDLE or SLEEP mode. 1. TEIE: Transmitter Empty interrupt enable control 0: transmitter empty interrupt is disabled 1: transmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. due to a transmitter idle condition. The only one available bit named URST in the UART control register UCR3 is the UART software reset control bit. If this bit is equal to ²1² and when the transmitter empty flag TXIF is set. When this situation occurs. The UART registers including the status register and control registers will keep the POR states shown in the above UART registers table after the reset condition occurs. TIIE: Transmitter Idle interrupt enable control 0: transmitter idle interrupt is disabled 1: transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. Bit Name R/W POR Bit 7 7 URST R/W 0 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 ¾ ¾ ¾ 0 ¾ ¾ ¾ URST: UART software reset 0: no action 1: UART reset occurs unimplemented. read as ²0² Bit 6~0 Rev. RIE: Receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to ²1². the UART interrupt request flag will be set. the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. the UART interrupt request flag will be set. the UART interrupt request flag will not be influenced by the condition of the TXIF flag. If this bit is equal to ²0². the transmitter and receiver will be reset. the whole UART module will be reset. If this bit is equal to ²1² and when the transmitter idle flag TIDLE is set. If this bit is equal to ²0². a falling edge on the RX input pin will wake-up the device. If this bit is equal to ²0².30 197 October 4. the UART interrupt request flag will be set. due to a transmitter empty condition.

2 38.300 1. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode.8 9. UCR2 BRGH Bit Baud Rate (BR) 0 fCLKI [64 (N+1)] 1 fCLKI [16 (N+1)] · Calculating the baud rate and error values For a clock frequency of 4MHz.00 0.929 20.202 2. the UART function contains its own dedicated baud rate generator.83 1.90 ¾ -2. the period of which is determined by two factors.16 0. a decimal value of 12 should be placed into the BRG register. The baud rate is controlled by its own internal free running 8-bit timer.0208 (4800x 64) To obtain the closest value.808 8.930 ¾ Error (%) 0.00 -0.432 4.90 -2.6 19.4 4.16% By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Baud Rate Generator To setup the speed of the serial data communication. the required baud rate can be setup.1 = 12.190 2.830 ¾ 62. which in turn determines the formula that is used to calculate the baud rate.661 9.300 1.6 115.99 8.159MHz Kbaud 0. 1.321 18.51 ¾ 8. and with BRGH set to ²0² determine the BRG register value N. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2.90 -2. Baud Rates for BRGH=0 Baud Rate K/BPS BRG 0. N.3 1.30 198 October 4.90 ¾ Baud Rates and Error Values for BRGH = 0 Rev.4 57.2 2. placed in the BRG register. This gives an actual or 4000000 = 4808 calculated baud rate value of BR= [64(12+1)] 4 8 0 8 Therefore the error is equal to 4 8 0 0 4 8 0 0 = 0.500 ¾ Error (%) 0. The following tables show the actual values of baud rate and error values for the two value of BRGH.16 -6. 2010 . the actual baud rate and the error value for a desired baud rate of 4800.16 0.32 -2. From the above table the desired baud rate BR = fCLKI [64 (N+1)] Re-arranging this equation gives N = Giving a value for N = fCLKI -1 (BRx64) 4000000 . The following example shows how the BRG register value N and the error value can be calculated.2 207 51 25 12 6 2 1 0 ¾ fCLKI=4MHz Kbaud 0. Note that because the actual baud rate is determined using a discrete value. there will be an error associated between the actual and requested value.51 ¾ BRG 185 46 22 11 5 2 1 0 ¾ fCLKI=7.643 ¾ 55.404 4. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. The value N in the BRG register which is used in the following baud rate calculation formula determines the division factor.

Rev.16 -6.90 ¾ Baud Rates and Error Values for BRGH = 1 · BRG Register Bit Name R/W POR Bit 7~0 7 BRG7 R/W x 6 BRG6 R/W x 5 BRG5 R/W x 4 BRG4 R/W x 3 BRG3 R/W x 2 BRG2 R/W x 1 BRG1 R/W x 0 BRG0 R/W x ²x²: unknown BRG7~BRG0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register.90 -2.16 0.406 4.404 4.6 19. the required baud rate can be setup.760 9.30 199 October 4.286 55.6 115.930 111.2 250 ¾ 207 103 51 25 12 6 3 1 0 fCLKI=4MHz Kbaud ¾ 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Baud Rates for BRGH=1 Baud Rate K/BPS BRG 0.5 125 250 Error (%) ¾ 0.90 -2. 2010 .727 18.4 4.99 8.643 37.16 0.83 1.203 2.23 0.32 -2.202 2.16 0.714 62.86 ¾ Error (%) ¾ 0.51 8.8 9.51 0 BRG ¾ 185 92 46 22 11 5 3 1 ¾ fCLKI=7.808 9.2 2.16 0.159MHz Kbaud ¾ 1.23 -0.615 19.3 1.2 38.90 -2. 1.231 35.4 57.

PERR and NF being cleared while bits TIDLE. In all cases stop bits will be used for data transmission. If the UARTEN bit in the UCR1 register is cleared while the UART is active. format. If the UARTEN. The PRT bit controls the choice if odd or even parity. FERR. Start Bit Data Bits Address Bits Parity Bits Stop Bit The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. then these two UART pins will act as normal TX output pin and RX input pin respectively. TXIF and RIDLE will be set. Parity is supported by the UART hardware and can be setup to be even. 8 data bits along with no parity and one stop bit. If no data is being transmitted on the TX pin. Example of 8-bit Data Formats 1 1 1 8 7 7 0 0 1 0 1 0 1 1 1 Example of 9-bit Data Formats 1 1 1 9 8 8 0 0 1 0 1 0 1 1 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. odd or no parity. is independent of the data length. OERR. then it will default to a logic high value. The PREN bit controls the parity on/off function. This is composed of one start bit. parity on/off. along with the parity. The number of stop bits. RXIF. P a r ity B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 S to p B it N e x t S ta rt B it 8 -B it D a ta F o r m a t P a r ity B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 B it 8 S to p B it N e x t S ta rt B it 9 -B it D a ta F o r m a t Rev. the buffer will be reset to an empty condition. Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be in the state of high impedance. N. PREN and STOPS bits in the UCR1 register. Although the transmitter and receiver of the UART are functionally independent. 1. TXBRK. Disabling the UART will also reset the enable control. address bits and the number of stop bits. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator. 1. The BNO bit controls the number of data bits which can be set to either 8 or 9.30 200 October 4. · Enabling/Disabling the UART then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. The number of data bits and stop bits. When the UART function is disabled. which is the setting at power-on. the error and status flags with bits TXEN. PRT. are setup by programming the corresponding BNO. 2010 . TXEN and RXEN bits are set.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 UART Module Setup and Control For data transfer. they both use the same data format and baud rate. These factors are determined by the setup of various bits within the UCR1 register. · Data. The remaining control bits in the UCR1. which can be either one or two. at the same time discarding any remaining residual data. UCR2 and BRG registers will remain unaffected. RXEN. is used as the default setting. the UART function utilizes a non-return-to-zero. The address detect mode control bit identifies the frame as an address character. parity type. For the most common data format. denoted as 8. parity and stop bit selection The format of the data to be transferred is composed of various factors such as data bit length. it will restart again in the same configuration. The STOPS bit decides whether one or two stop bits are to be used. more commonly known as NRZ. eight or nine data bits and one or two stop bits. If the UART is then subsequently re-enabled. while the data is transmitted and received LSB first. The following table shows various formats for data transmission.

the transmission will immediately cease and the transmitter will be reset. the TIDLE bit will be set. At the transmitter core lies the Transmitter Shift Register. and the TXIF bit being immediately set. Break character transmission consists of a start bit. which will be copied to the shift register at the end of the present transmission. the transmission can also be initiated by first loading data into the TXR register. data will be inhibited from being written to the TXR register. a write instruction to the TXR register will place the data into the TXR register. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. the data is shifted on the TX pin from the shift register. the TSR can then be loaded with new data from the TXR register. followed by 13´N ²0² bits. As soon as this stop bit has been transmitted. then the TXIF flag will generate an interrupt. the TSR is normally empty. When BNO bit is set. ¨ ¨ Rev. During a data transmission. The TX output pin will then return to the high impedance state. It should be noted that when TXIF=0. 2. then the MSB will be taken from the TX8 bit in the UCR1 register. needs to be stored in the TX8 bit in the UCR1 register. To clear the TIDLE bit the following software sequence is used: 1. If the TEIE bit is set. A USR register access 2. 1. Clearing the TXIF flag is always achieved using the following software sequence: 1. whose data is obtained from the transmit data register. A USR register access 2. in which case a transfer to the TXR register will result in an immediate transfer to the TSR. Access the USR register and write the data that is to be transmitted into the TXR register. after which the TXEN bit can be set. but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. If the TXBRK bit is continually kept at a logic high level. Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a UART transmitter pin. PREN and STOPS bits to define the required word length. However. the word length will be set to 9 bits. parity type and number of stop bits. then the transmitter circuitry will transmit continuous break characters. The data to be transmitted is loaded into this TXR register by the application program. PRT. which is the MSB. An actual transmission of data will normally be enabled when the TXEN bit is set. In the transmit mode. if a break character is to be transmitted. When there is no data transmission in progress. Transmitting a break character will not generate a transmit interrupt. more commonly known as the TSR. which is known as the TXR register. · Transmitting break When the UART is transmitting data. 2010 . A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. It should be noted that if 9-bit data format has been selected. the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. ¨ If the TXBRK bit is set. resulting in the commencement of data transmission. Setup the BRG register to select the desired baud rate. After the application program has cleared the TXBRK bit. if it is available. When a transmission of data begins. where N=1. If during a transmission the TXEN bit is cleared. In this case the 9th bit. is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. with the least significant bit LSB first. the TXR register forms a buffer between the internal bus and the transmitter shift register.30 201 October 4. unlike many other registers. then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. When a frame transmission is complete. The steps to initiate a data transfer can be summarized as follows: ¨ Make the correct selection of the BNO. It should be noted that the TSR register. then the break characters will be sent on the next transmission. · Transmitting data This sequence of events can now be repeated to send additional data. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. Note that this step will clear the TXIF bit. a write instruction to the TXR register will place the data directly into the shift register. which happens after stop bits are sent or after the break frame. etc. Note that a break condition length is at least 13 bits long.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · UART transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence.

zeros are loaded into the receive data register. The RXR register is a four byte deep FIFO data buffer. · Receiving data The RXIF bit can be cleared using the following software sequence: 1. which is the MSB. The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. the receiver must wait for a valid stop bit before looking for the next start bit. if the register is empty. In between the reception of a stop bit and the detection of the next start bit. When a character is received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. At this point the receiver will be enabled which will begin to look for a start bit. ¨ ¨ Rev. · Receiver interrupt The RXIF bit in the USR register will be set then RXR register has data available. If a long break signal has been detected and the receiver has received a start bit. When BNO bit is set. the receiver status flag in the USR register. When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. the word length will be set to 9 bits. then the error flags can be set. Setup the BRG register to select the desired baud rate. The OERR. will be cleared. a frame error. which indicates the receiver is in an idle condition. which sets the FERR flag. Note that the application program must ensure that the data is read from RXR before the 5th byte has been completely shifted in. In this case the 9th bit. An overrun error can also generate an interrupt if RIE=1. Make the correct selection of the BNO. with the least significant bit LSB first. when a word is transferred from the Receive Shift Register. The reception of a break character on the UART registers will result in the following: ¨ ¨ ¨ The framing error flag. at least three more character can be read. otherwise known as the RIDLE flag. the reception will be considered as complete after the number of bit times specified by BNO and STOPS. An interrupt is generated if RIE=1. The receiver will not make the assumption that the break condition on the line is the next start bit. is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. 2010 . The RXIF bit is set. The steps to initiate a data transfer can be summarized as follows: ¨ Any break character received by the UART will be managed as a framing error. A RXR register read execution · Receiving break When the UART receiver is receiving data. then an interrupt will be generated. PERR. otherwise the 5th byte will be discarded and an overrun error OERR will be subsequently indicated.30 202 October 4. where four bytes can be held in the FIFO while the 5th byte can continue to be received. while the main receive serial shifter operates at the baud rate. At the receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. will have a zero value. The receive data register. NF. FERR is set. interrupts are generated if appropriate and the RIDLE bit is set. RSR. · Idle status ¨ Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. to the Receive Data Register. the received data in RSR is transferred to the receive data register. RXR.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · UART receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. the RIDLE flag will have a high value. If during reception. RXR. unlike many other registers. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register. will be set. which means it will be in between the detection of a start bit and the reading of a stop bit. A break is regarded as a character that contains only zeros with the FERR flag set. parity type and number of stop bits. the following sequence of events will occur: ¨ ¨ When the receiver is reading data. The data recovery block operating speed is 16 times that of the baud rate. will be stored in the RX8 bit in the UCR1 register. parity error or an overrun error has been detected. 1. If the break is much longer than 13 bit times. PREN and STOPS bits to define the required word length. RIDLE or RXIF flags will possibly be set. FERR. A USR register access 2. the data bits and the invalid stop bit. noise error. After the RX pin is sampled for the stop bit. PRT. the data is serially shifted in on the external RX input pin to the shift register. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits.

while the two receiver interrupt conditions have a shared enable control bit. FERR. commonly known as the System Start-up Time. the details of which are given in the UART register section. does not have an associated flag. the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Before the 5th byte has been entirely shifted in. address detect and an RX pin wake-up. Note that in the event of an RX wake-up interrupt occurring. These enable bits can be used to mask out individual UART interrupt sources. is set if the parity of the received word is incorrect. 1. NF.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Managing Receiver Errors Several types of reception errors can occur within the UART module. if its corresponding interrupt control is enabled and the stack is not full. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. PERR. If this is not done. odd or even. It is cleared on any reset. there will be a certain period of delay. If two stop bits are selected.OERR flag UART Module Interrupt Structure Several individual UART conditions can generate a UART interrupt. the following will occur: ¨ The read only noise flag. Note that the USR register flags are read only and cannot be cleared or set by the application program.PERR flag The read only parity error flag. is set if a zero is detected instead of stop bits. 2010 . The two transmitter interrupt conditions have their own corresponding enable control bits.FERR flag ¨ The read only framing error flag. does not have an associated flag. the following will happen: ¨ ¨ ¨ ¨ The OERR flag in the USR register will be set. which is also a UART interrupt source. in the USR register. These conditions are a transmitter data register empty. as is the case for some of the other interrupts. An RX pin wake-up. but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. but will generate a UART interrupt if the microcontroller is woken up by a falling edge on the RX pin. · Framing Error . The RXR register is composed of a four byte deep FIFO data buffer. while a 5th byte can continue to be received. ¨ No interrupt will be generated. the following section describes the various types and how they are managed by the UART. Otherwise the FERR flag will be set. An interrupt will be generated if the RIE bit is set. In the event of an overrun error occurring. The flags will be cleared automatically when certain actions are taken by the UART. both stop bits must be high. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. in the USR register. receiver overrun.30 203 October 4. receiver data available. · Overrun Error . Data will be transferred from the shift register to the RXR register. · Parity Error . it should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. The shift register will be overwritten. and if the parity type. The address detect condition. When these conditions exist. PREN=1.NF flag Over-sampling is used for data recovery to identify valid incoming data and noise. a low pulse will be generated on the INT line to get the attention of the microcontroller. which is also a UART interrupt source. is selected. If noise is detected within a frame. the overrun error flag OERR will be consequently indicated. transmitter idle. if the WAKE and RIE bits in the UCR2 register are set. the data should be read from the RXR register. where four bytes can be held in the FIFO register. The FERR flag is buffered along with the received data and is cleared in any reset. The read only PERR flag is buffered along with the received data bytes. neither will they be cleared when the program jumps to the corresponding interrupt servicing routine. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. · Noise Error . in the USR register will be set on the rising edge of the RXIF bit. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. When any of these conditions are created. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. The RXR contents will not be lost. for the oscillator to restart and stabilize before the system resumes normal operation. This error flag is only applicable if the parity function is enabled. Rev.

If the ADDEN bit is equal to ²0². 2010 . The address detect and parity functions are mutually exclusive functions. The highest address bit is the 9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. The UART Module can be powered up by the MCU by first clearing the SCS line to zero and then setting the UARTEN bit. note that the USR. irrespective of the data last but status. an interrupt will only be generated. A Data Available interrupt will be generated every time the last bit of the received word is set. ADDEN. then the reception of data will likewise be terminated. the parity function should be disabled by resetting the parity function enable bit PREN to zero. The UART Module contains a receiver RX pin wake-up function. transmit and receive registers. in the UCR2 register. then to ensure correct operation. This is implemented by first clearing the UARTEN bit in the UCR1 register to disable the UART Module circuitry after which the SCS internal line can be set high to disable the SPI interface circuits. 1. If this bit is set to ²1². along with the UART enable bit named UARTEN. which is requested by the RXIF flag. Therefore if the address detect function is enabled. UCR2. then a falling edge on the RX pin will wake up the MCU from its power down condition. The UART Module must be powered down before the MCU is powered down. which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit. then when the data is available. as well as the BRG register will not be affected. UCR1. ADDEN 0 1 0 1 1 ADDEN Bit Function Bit 9 if BNO=1. are all set before the MCU and UART module are is powered down. the receiver enable bit named RXEN and the receiver interrupt enable bit named RIE. if the highest received bit has a high value. if the UART circuits is powered down while receiving data. Note Rev. When the UART and SPI interfaces are powered down.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 U S R R e g is te r U C R 2 R e g is te r T E IE 1 0 T r a n s m itte r E m p ty F la g T X IF T r a n s m itte r Id le F la g T ID L E T IIE 1 R IE 1 0 0 IN T T o M C U P IN T in te r r u p t in p u t R e c e iv e r O v e r r u n F la g O E R R O R R e c e iv e r D a ta A v a ila b le R X IF A D D E N 1 0 0 1 R X P in W a k e -u p W A K E 1 0 R X 7 if B N O = 0 R X 8 if B N O = 1 U C R 2 R e g is te r UART Module Interrupt Structure · Address detect mode Setting the Address Detect function enable control bit. then the received word will be defined as an address rather than data. In a similar way.30 204 October 4. the SCK and CLKI clock sources to the UART module will be disabled. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. then a Receive Data Available interrupt will be generated each time the RXIF flag is set. If the ADDEN bit is equal to ²1². UART Interrupt Bit 8 if BNO=0 Generated 0 Ö Ö X Ö UART Module Power-down and Wake-up The MCU and UART Module are powered down independently of each other. When the UART circuits is powered down. The method of powering down the MCU is covered in the previous MCU section of the datasheet. then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt. then the transmission will be terminated and the external TX transmit pin will be forced to a logic high level. UCR3. enables this special function. If the highest bit is high. If the UART circuits is powered down while a transmission is still in progress.

SPI clock is fSYS/4 001: SPI master mode. SPI clock is fSYS/16 010: SPI master mode. To correctly connect the MCU Master SPI to the UART Module Slave SPI. in the SIMC0 register have to be configured to enable the SIM to operate in the SPI master mode with a different SPI clock frequency. 2010 . For a UART wake-up interrupt to occur. several important steps must be implemented to ensure that the UART module operates normally: · The SPI pin-remapping function must be properly 000: SPI master mode. 10. ¨ PCK output frequency selection bits PCKP1~PCKP0 in the SIMC0 Register Bit Name Value 3 PCKP1 2 PCKP0 11. 1.30 205 October 4. the global interrupt enable control and the related interrupt enable control bits must also be set. the relevant UART interrupt will not be serviced until this period of delay time has elapsed. Note also that as it takes a period of delay after a wake-up before normal microcontroller resumes. any data received during this time on the RX pin will be ignored. SPI clock is fSYS/64 011: SPI master mode. ¨ put as the clock source for the UART baud rate generator with various PCK output frequencies determined by the PCKP1 and PCKP0 bits in the SIMC0 Register. ¨ SIM operating mode control bits SIM2~SIM0 in the SIMC0 Register Bit Name value 7 SIM2 6 SIM1 5 SIM0 100.PCK and PINT pin-remap setup Bit Name Setting value 2 SIMPS1 1 1 SIMPS0 1 0 PCKPS 1 Rev. 010. the MCU can enable the SIM interface by setting the SIMEN bit high. If these two bits are not set. SPI clock is fTBC 100: SPI master mode. The detailed MCU Master SPI functional description is provided within the Serial Interface Module section of the MCU datasheet. the SIM pin-remapping settings for PCK and PINTB in the MCU PRM0 register should be the same as the values listed in the following table.PCK and PINT pin-remap setup Bit Name Setting value 1 SIMPS0 1 0 PCKPS 1 ¨ 00: PCK output frequency is fSYS 01: PCK output frequency is fSYS/4 10: PCK output frequency is fSYS/8 11: PCK output frequency is TM0 CCRP match frequency/2 PCK output enable control bit PCKEN in the SIMC0 Register Bit Name Value 0: Disable PCK output 1: Enable PCK output After the above setup conditions have been implemented. The MCU can then begin communication with external UART connected devices using its SPI interface. in addition to the bits for the wake-up enable control and Receive interrupt enable control being set. 01 or 00 HT66FU30 PRM0 Register . 011. 4 PCKEN 1 ¨ HT66FU40/HT66FU50 PRM0 Register .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 that as it takes a certain period of time known as the System Start-up Time for oscillator to restart and stabilize after a wake-up. · The SIM operating mode control bits SIM2~SIM0. 001 or 000 Using the UART Function To use the UART function. SPI clock is TM0 CCRP match frequency/2 101~111: must not be used · The PCK control bit is set to 1 to enable the PCK out- configured when the SPI functional pins of the microcontroller are used to control the UART module and for data transmission and data reception. then only a wake-up event will occur and no interrupt will be serviced.PCK and PINT pin-remap setup Bit Name Setting value 2 SIMPS1 0 1 SIMPS0 1 0 PCKPS 1 ¨ HT66FU60 PRM0 Register .

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Application Circuit with UART Module V 0 .0 1 m F * * D D V D D R e s e t C ir c u it R E S I/O V S S A N x P o rts 0 . Rev. ²**² It is recommended that this component is added in environments where power line noise is significant.1 m F 1 N 4 1 4 8 * 1 0 k W ~ 1 0 0 k W 3 0 0 W * 0 . 1.1 ~ 1 m F O S C C ir c u it S e e O s c illa to r S e c tio n O S C C ir c u it S e e O s c illa to r S e c tio n O S C 1 O S C 2 T X R X X T 1 X T 2 R S 2 3 2 T r a n s c e iv e r T IN R O U T T o / F ro m R S 2 3 2 B u s Note: ²*² It is recommended that this component is added for added ESD protection.30 206 October 4. 2010 .

the zero flag may be set if the result of the operation is zero. In the case of a JMP instruction. the program must return to the instruction immediately when the subroutine has been carried out. For easier understanding of the various instruction codes. CALL. The exceptions to this are branch. 1. DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. In the case of Holtek microcontroller. Instruction Timing Most instructions are implemented within one instruction cycle. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller a p p l i c at i o n s . RRC and RLC which provide a simple means of rotating one bit right or left. They differ in the sense that in the case of a subroutine call. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. Examples of such instructions would be ²CLR PCL² or ²MOV PCL. RET. For the case of skip instructions. a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. the program will continue with the next instruction or skip over it and jump to the following instruction. therefore in the case of an 8MHz system oscillator. Although instructions which require one more cycle to implement are generally limited to the JMP. As instructions which change the contents of the PCL will imply a direct jump to that new address. Logical and Rotate Operations The standard logical operations such as AND. RETI and table read instructions. most instructions would be implemented within 0. Another form of logical data manipulation comes from the rotate instructions such as RR. Making use of three kinds of MOV instructions. In all logical data operations. Different rotate instructions exist depending on program requirements. Another application where rotate data operations are used is to implement multiplication and division calculations. data must pass through the Accumulator which may involve additional programming steps. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. INCA.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Instruction Set Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. As with the case of most instructions involving data manipulation. XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. W i t h i n t h e H o l t e k microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Rev. data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. they have been subdivided into several functional groupings. OR. or table read instructions where two instruction cycles are required. Depending upon the conditions. call.30 207 October 4. if no skip is involved then only one cycle is required. The increment and decrement instructions INC. which is a set of program instruction codes that directs the microcontroller to perform certain operations. it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle.5ms and branch or call instructions would be implemented within 1ms. RL. the program simply jumps to the desired location. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. one more cycle will be required. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. One special and extremely useful set of branch instructions are the conditional branches. 2010 . A². These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. One instruction cycle is equal to 4 system clock cycles. Here a decision is first made regarding the condition of a certain data memory or individual bits. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low.

C.[m] XORM A. However. AC.[m] ORM A. C. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. when working with large amounts of fixed data.i² or ²CLR [m]. OV Z. OV Z.[m] DAA [m] Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry.[m] XOR A. The feature removes the need for programmers to first read the 8-bit output port. the volume involved often makes it inconvenient to store the fixed data in the Data Memory. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Arithmetic ADD A. AC. C.[m] OR A.[m] ADDM A.[m] ANDM A. OV Z. C. C. OV Z. Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored.[m] ADD A.[m] SUBM A. C. Table Read Operations Data storage is normally implemented by using registers.[m] ADCM A. C. result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z. For their relevant operations. AC. OV Z.i² instructions respectively. OV Z. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the ²SET [m]. 2010 . AC. refer to the functional related sections. To overcome this problem. C. AC. AC.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. Other Operations In addition to the above functional instructions.30 208 October 4.x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rev.x OR A.x XOR A.x ADC A. C.[m] SBCM A. OV Z.[m] SBC A. a range of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. OV Z.[m] AND A. This read-modify-write process is taken care of automatically when these bit operation instructions are used.x SUB A. OV Z. AC.[m] SUB A. AC. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. 1. C. OV C Logic Operation AND A. AC. AC.

1. 3. 2010 .x Bit Operation CLR [m]. 2. if the result of the comparison involves a skip then two cycles are required. PDF None None TO.A MOV A. Rev. PDF TO.i SET [m]. For skip instructions.i SNZ [m].30 209 October 4. PDF TO. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the execution status.i Branch JMP addr SZ [m] SZA [m] SZ [m].HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions are consecutively executed.x RETI Table Read TABRD [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A. if no skip takes place only one cycle is required.[m] MOV [m]. Otherwise the TO and PDF flags remain unchanged. PDF Read table to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected 1.

Accumulator and the carry flag are added. 2010 .x Description Operation Affected flag(s) ANDM A. Z.[m] Description Operation Affected flag(s) AND A. The result is stored in the Accumulator. C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added.[m] Description Operation Affected flag(s) ADCM A.[m] Description Operation Affected flag(s) ADD A. The result is stored in the Data Memory. The result is stored in the Accumulator. Z. [m] ¬ ACC ²AND² [m] Z 210 October 4. [m] ¬ ACC + [m] OV. Z.[m] Description Operation Affected flag(s) ADD A.x Description Operation Affected flag(s) ADDM A. AC. AC. AC. The result is stored in the specified Data Memory. Z. 1. [m] ¬ ACC + [m] + C OV. ACC ¬ ACC + [m] + C OV. The result is stored in the specified Data Memory. ACC ¬ ACC + x OV. AC. C Add ACC to Data Memory with Carry The contents of the specified Data Memory. Accumulator and the carry flag are added.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Instruction Definition ADC A. AC. The result is stored in the Accumulator. ACC ¬ ACC + [m] OV. ACC ¬ ACC ²AND² [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation.30 Add Data Memory to ACC with Carry The contents of the specified Data Memory.[m] Description Operation Affected flag(s) AND A. The result is stored in the Accumulator. C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. Z. ACC ¬ ACC ²AND² x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Accumulator. C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation.[m] Description Operation Affected flag(s) Rev.

Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Stack ¬ Program Counter + 1 Program Counter ¬ addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. PDF Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m]. [m] ¬ 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. PDF flags and the WDT are all cleared. WDT cleared TO ¬ 0 PDF ¬ 0 TO. As this instruction requires an additional operation. PDF Pre-clear Watchdog Timer The TO. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. WDT cleared TO ¬ 0 PDF ¬ 0 TO. it is a two cycle instruction. PDF Pre-clear Watchdog Timer The TO.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address.i ¬ 0 None Clear Watchdog Timer The TO. 2010 . The specified address is then loaded and the program continues execution from this new address.30 211 October 4.i Description Operation Affected flag(s) CLR WDT Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) Rev. WDT cleared TO ¬ 0 PDF ¬ 0 TO. [m]. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. PDF flags and the WDT are all cleared. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. 1. PDF flags and the WDT are all cleared.

Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100. [m] ¬ ACC + 00H or [m] ¬ ACC + 06H or [m] ¬ ACC + 60H or [m] ¬ ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1.1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. 2010 . Bits which previously contained a 1 are changed to 0 and vice versa. The WDT and prescaler are cleared. [m] ¬ [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1¢s complement). The contents of the Data Memory and registers are retained. ACC ¬ [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. the decimal conversion is performed by adding 00H. 1. 60H or 66H depending on the Accumulator and flag conditions.1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1¢s complement). then a value of 6 will be added to the high nibble. [m] ¬ [m] . The contents of the Data Memory remain unchanged.30 212 October 4. ACC ¬ [m] . The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. TO ¬ 0 PDF ¬ 1 TO. The result is stored in the Accumulator. Bits which previously contained a 1 are changed to 0 and vice versa. If the low nibble is greater than 9 or if AC flag is set. If the high nibble is greater than 9 or if the C flag is set. Essentially. Otherwise the low nibble remains unchanged. PDF Operation Affected flag(s) DAA [m] Description Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description Operation Affected flag(s) Rev. 06H. The power down flag PDF is set and the WDT time-out flag TO is cleared. it allows multiple precision decimal addition. then a value of 6 will be added to the low nibble.

30 213 October 4. ACC ¬ [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator.[m] Description Operation Affected flag(s) MOV A. Program execution then continues from this new address. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. ACC ¬ ACC ²OR² [m] Z Operation Affected flag(s) MOV A.x Description Operation Affected flag(s) MOV [m]. [m] ¬ ACC None No operation No operation is performed. [m] ¬ [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. Program Counter ¬ addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. As this requires the insertion of a dummy instruction while the new address is loaded. it is a two cycle instruction. 1. ACC ¬ x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory.A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A. Execution continues with the next instruction. The result is stored in the Accumulator. 2010 . The result is stored in the Accumulator. ACC ¬ [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1.[m] Description Operation Affected flag(s) Rev. The contents of the Data Memory remain unchanged.

(i = 0~6) [m].i.0 ¬ [m]. EMI is the master interrupt global enable bit. the pending Interrupt routine will be processed before returning to the main program. (i = 0~6) ACC.7 None Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) Rev. [m] ¬ ACC ²OR² [m] Z Return from subroutine The Program Counter is restored from the stack. Program Counter ¬ Stack EMI ¬ 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Program Counter ¬ Stack ACC ¬ x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit.(i+1) ¬ [m]. ACC ¬ ACC ²OR² x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. ACC. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. 1. Program execution continues at the restored address.(i+1) ¬ [m].[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A. The result is stored in the Accumulator. 2010 .30 214 October 4.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 OR A.x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. [m]. Program Counter ¬ Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.x Description Operation Affected flag(s) ORM A. If an interrupt was pending when the RETI instruction is executed.7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.0 ¬ [m].i.

Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0.i. (i = 0~6) [m].(i+1).HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit.7 ¬ C C ¬ [m].i.0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7.7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit.(i+1). ACC. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0.30 215 October 4. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.(i+1). [m].(i+1) ¬ [m].0 ¬ C C ¬ [m].i ¬ [m].i ¬ [m].7 ¬ [m]. 1.(i+1). 2010 .0 ¬ C C ¬ [m].i ¬ [m].7 ¬ [m]. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. ACC. (i = 0~6) [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. (i = 0~6) ACC. (i = 0~6) ACC. [m]. ACC.0 C Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) Rev.(i+1) ¬ [m]. (i = 0~6) ACC.i ¬ [m]. [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.7 ¬ C C ¬ [m]. (i = 0~6) [m]. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7.

ACC ¬ ACC .[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. the C flag will be cleared to 0.C OV. 2010 .[m] . Z. As this requires the insertion of a dummy instruction while the next instruction is fetched. Note that if the result of subtraction is negative. [m] ¬ ACC . If the result is not 0. AC.1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. ACC ¬ [m] . The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. 1. the C flag will be cleared to 0.[m] . the program proceeds with the following instruction. AC. If the result is 0. it is a two cycle instruction. it is a two cycle instruction. the following instruction is skipped. otherwise if the result is positive or zero.i ¬ 1 None Operation Affected flag(s) SBCM A. Z. the C flag will be set to 1. Note that if the result of subtraction is negative. [m] ¬ [m] . C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SBC A. [m]. If the result is 0 the following instruction is skipped. otherwise if the result is positive or zero. C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1.1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. [m] ¬ FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. The result is stored in the Data Memory.30 216 October 4.[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) SDZA [m] Description Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m]. the C flag will be set to 1. The result is stored in the Accumulator. If the result is not 0 the program proceeds with the following instruction. As this requires the insertion of a dummy instruction while the next instruction is fetched.C OV.i Description Operation Affected flag(s) Rev.

the following instruction is skipped.x Description Operation Affected flag(s) Rev. the C flag will be set to 1.[m] OV.[m] Description Operation Affected flag(s) SUBM A. If the result is not 0 the program proceeds with the following instruction. the C flag will be cleared to 0. C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. the C flag will be set to 1. [m] ¬ ACC .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. C Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m]. Z. otherwise if the result is positive or zero. ACC ¬ ACC . As this requires the insertion of a dummy instruction while the next instruction is fetched. Note that if the result of subtraction is negative.30 217 October 4. As this requires the insertion of a dummy instruction while the next instruction is fetched. As this requires the insertion of a dummy instruction while the next instruction is fetched.[m] Description Operation Affected flag(s) SUB A. Note that if the result of subtraction is negative. AC. 1. The result is stored in the Accumulator. If the result is 0. it is a two cycle instruction.x OV. If the result is not 0 the program proceeds with the following instruction. 2010 . [m] ¬ [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. ACC ¬ [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0. Note that if the result of subtraction is negative. Z. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. If the result is 0 the program proceeds with the following instruction.i Description Operation Affected flag(s) SUB A. the following instruction is skipped. the C flag will be set to 1. If the result is 0.[m] OV. the C flag will be cleared to 0. the following instruction is skipped. Z. C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. ACC ¬ ACC . The result is stored in the Data Memory. AC.i ¹ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. otherwise if the result is positive or zero. Skip if [m]. The result is stored in the Accumulator. otherwise if the result is positive or zero. AC. it is a two cycle instruction. the C flag will be cleared to 0. it is a two cycle instruction.

2010 .7 ~ [m]. 1. ACC. the following instruction is skipped.7 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0.3 ~ [m].7 ~ ACC.30 218 October 4. If the value is zero. the following instruction is skipped.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched. As this requires the insertion of a dummy instruction while the next instruction is fetched.i = 0 None Read table to TBLH and Data Memory The program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. it is a two cycle instruction. ACC ¬ [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0. If the result is not 0.0 ¬ [m].i Description Operation Affected flag(s) TABRD [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) Rev.4 ¬ [m]. The result is stored in the Accumulator.3~[m]. The contents of the Data Memory remain unchanged.0 « [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. [m] ¬ program code (low byte) TBLH ¬ program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.3 ~ ACC. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. [m] ¬ program code (low byte) TBLH ¬ program code (high byte) None Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m]. If the result is not 0 the program proceeds with the following instruction.4 ACC. the program proceeds with the following instruction. it is a two cycle instruction. Skip if [m]. If the result is not 0 the program proceeds with the following instruction. As this requires the insertion of a dummy instruction while the next instruction is fetched. it is a two cycle instruction. [m].

ACC ¬ ACC ²XOR² [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation.[m] Description Operation Affected flag(s) XORM A. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 XOR A. [m] ¬ ACC ²XOR² [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. The result is stored in the Accumulator. ACC ¬ ACC ²XOR² x Z Rev. The result is stored in the Data Memory.[m] Description Operation Affected flag(s) XOR A.x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation.30 219 October 4. 2010 .

115 0.100 ¾ ¾ Dimensions in mm Min. 1/2 Lead Packages · MS-001d (see fig1) Symbol A B C D E F G H I Dimensions in inch Min.35 7.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Package Information 16-pin DIP (300mil) Outline Dimensions A 1 6 9 1 6 A 9 8 B B 8 1 1 H C D E F G I D E F G C H I Fig1.325 0.280 0.240 0.014 0.150 0.10 2.62 ¾ Nom.115 0.300 ¾ Nom. 1.95 3. 22. 0.780 0.022 0.195 0.92 Max.36 1.430 Symbol A B C D E F G H I Rev.30 220 October 4.045 ¾ 0.92 2.14 ¾ 7.78 ¾ 8.070 ¾ 0.81 0.11 4.26 10.56 1.81 6. 19.880 0.54 ¾ ¾ Max.92 0. Full Lead Packages Fig2. 0. ¾ ¾ ¾ ¾ ¾ ¾ 0. 2010 . ¾ ¾ ¾ ¾ ¾ ¾ 2.

95 3.54 ¾ ¾ Max.150 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · MS-001d (see fig2) Symbol A B C D E F G H I Dimensions in inch Min.11 4.56 1. ¾ ¾ ¾ ¾ ¾ ¾ 0.240 0.735 0.92 Max.325 0.430 Symbol A B C D E F G H I Rev. 2010 .26 10.10 2.045 ¾ 0. 1.67 6.78 ¾ 8.100 ¾ ¾ Dimensions in mm Min.92 0.62 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 2.014 0.30 221 October 4.195 0.022 0.81 0. 18. 19.300 ¾ Nom.115 0.92 2.115 0. 0.070 ¾ 0.775 0. 0.69 7.14 ¾ 7.280 0.36 1.

300 ¾ Nom.100 ¾ ¾ Dimensions in mm Min.120 0.060 ¾ 0.92 6.045 ¾ 0. ¾ ¾ ¾ ¾ ¾ ¾ 0. 0.79 0.30 222 October 4.92 Max.022 0.325 0.150 0.62 ¾ Nom.36 1.54 ¾ ¾ Max. 0.05 2.110 0.52 ¾ 8.26 10.014 0.150 0.745 0.81 0.81 3.430 Symbol A B C D E F G H I Rev. 2010 .295 0.49 3.785 0.14 ¾ 7.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · MO-095a (see fig2) Symbol A B C D E F G H I Dimensions in inch Min.99 3. ¾ ¾ ¾ ¾ ¾ ¾ 2. 18.94 7. 1.275 0.56 1. 19.

010 8° Rev.25 1.402 0.010 0.244 0.80 ¾ ¾ 0.21 1.016 0. ¾ ¾ ¾ ¾ ¾ 0.007 0° Nom. 0.20 3.51 10.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 16-pin NSOP (150mil) Outline Dimensions A 1 1 6 9 8 B C C ' G H D E F a · MS-012 Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min.012 0.050 0. 6.004 0.10 0.25 8° Max.81 0.050 ¾ ¾ ¾ ¾ Dimensions in mm Min. 2010 .27 ¾ ¾ ¾ ¾ Max.228 0.18 0° Nom.157 0. 1.99 0. 5.150 0.069 ¾ 0.30 223 October 4.386 ¾ ¾ 0.75 ¾ 0. ¾ ¾ ¾ ¾ ¾ 1.79 3.41 0. 0.27 0.020 0.30 9.

79 3.028 0. 0.25 8° Max.30 5.010 0.00 1.99 0.30 224 October 4. 2010 . ¾ ¾ ¾ ¾ ¾ 0. 5. 0.025 ¾ ¾ ¾ ¾ Dimensions in mm Min. ¾ ¾ ¾ ¾ ¾ 0.060 ¾ 0.244 0.189 0.007 0° Nom.80 1.20 3.150 0.197 0.18 0° Nom. 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 16-pin SSOP (150mil) Outline Dimensions 1 6 A 9 B 1 8 C C ' G H D E F a Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min.25 0.004 0.10 0.71 0.20 4.228 0.64 ¾ ¾ ¾ ¾ Max.52 ¾ 0.008 0.56 0.81 0.012 0.022 0.37 ¾ 0.054 ¾ 0.157 0. 6.010 8° Rev.

2010 .26 ¾ Max.92 Max. 0. ¾ ¾ ¾ ¾ ¾ ¾ 2.56 1.36 1.92 0.150 0.11 4. 24. 1/2 Lead Packages Symbol A B C D E F G H I Dimensions in inch Min.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 20-pin DIP (300mil) Outline Dimensions A A 1 1 1 0 1 2 0 1 1 1 0 1 B 2 0 B H C D E F G I E D F G C H I Fig1.115 0.430 Dimensions in mm Min.300 ¾ Nom.92 2.54 ¾ 10.81 0.060 0. Full Lead Packages · MS-001d (see fig1) Fig2.14 ¾ 7.95 3.62 ¾ Nom. 1.045 ¾ 0.115 0.78 ¾ 8.30 225 October 4.980 0.195 0.070 ¾ 0.89 6.10 2.014 0.92 7.325 ¾ Symbol A B C D E F G H I Rev. ¾ ¾ ¾ ¾ ¾ ¾ 0.280 0.100 ¾ 0.240 0. 1.022 0. 26.

54 ¾ 10.30 226 October 4.56 1.36 1. 0.02 7.275 0.49 3.150 0.045 ¾ 0.99 3.110 0. ¾ ¾ ¾ ¾ ¾ ¾ 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · MO-095a (see fig2) Symbol A B C D E F G H I Dimensions in inch Min.945 0.81 3.295 0. 1.92 Max.26 ¾ Max.05 2.325 ¾ Symbol A B C D E F G H I Rev.430 Dimensions in mm Min.52 ¾ 8.150 0.62 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 2.79 0.060 ¾ 0.022 0. 25.100 ¾ 0.985 0. 0. 2010 . 24.81 0.014 0.120 0.14 ¾ 7.00 6.300 ¾ Nom.

1.30 1.51 13.98 6.496 ¾ ¾ 0.27 0.64 ¾ 0.30 12.50 0.33 8° Max. ¾ ¾ ¾ ¾ ¾ 1.004 0.013 8° Rev. ¾ ¾ ¾ ¾ ¾ 0.300 0.050 0.62 0.393 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 20-pin SOP (300mil) Outline Dimensions 2 0 A 1 1 B 1 C C ' 1 0 G H D E F a · MS-013 Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min.20 0° Nom.008 0° Nom.10 0.60 ¾ ¾ 0.419 0.012 0.016 0. 0. 2010 .020 0.104 ¾ 0.512 0.00 2.050 ¾ ¾ ¾ ¾ Dimensions in mm Min.64 7.012 0.27 ¾ ¾ ¾ ¾ Max.30 227 October 4. 0.256 0.41 0. 10. 9.

¾ ¾ ¾ ¾ ¾ 0. 2010 .27 0.38 0.015 0.30 8.228 0.012 0. 0.150 0. 0.244 0.24 ¾ 0. 1.81 1.25 8° Max.004 0. 6.65 ¾ 0.18 0° Nom.79 3.049 ¾ 0.25 1.065 ¾ 0.050 0.20 4.30 228 October 4.010 8° Rev. 5.008 0.010 0.347 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 20-pin SSOP (150mil) Outline Dimensions 2 0 A 1 1 B 1 C C ' 1 0 G H D E F a Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min. ¾ ¾ ¾ ¾ ¾ 0.10 0.01 0.51 1.20 8.64 ¾ ¾ ¾ ¾ Max.007 0° Nom.158 0.335 0.025 ¾ ¾ ¾ ¾ Dimensions in mm Min.81 0.

150 0.115 0.045 ¾ 0.14 ¾ 7. 1.195 0. Full Lead Packages Fig2.95 3.24 6.92 2.240 0.11 4.30 229 October 4.280 0.51 7.10 2. 1. ¾ ¾ ¾ ¾ ¾ ¾ 2. 1/2 Lead Packages · MS-001d (see fig1) Symbol A B C D E F G H I Dimensions in inch Min.26 ¾ Max. ¾ ¾ ¾ ¾ ¾ ¾ 0.81 0. 32.115 0.92 Max.54 ¾ 10.36 1.56 1.78 ¾ 8.62 ¾ Nom.300 ¾ Nom. 2010 .325 ¾ Symbol A B C D E F G H I Rev.100 ¾ 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 24-pin SKDIP (300mil) Outline Dimensions A A 1 3 1 2 1 B 2 4 B 1 2 4 1 3 1 2 H C D E F G I E F D G C H I Fig1. 31.022 0.430 Dimensions in mm Min.280 0.014 0.92 0.070 ¾ 0. 1.230 0.

26 ¾ Max.325 ¾ Symbol A B C D E F G H I Rev. 1.14 ¾ 7.300 ¾ Nom.35 7.195 0. 1.56 1.115 0.30 230 October 4.045 ¾ 0.92 2.430 Dimensions in mm Min. ¾ ¾ ¾ ¾ ¾ ¾ 0.100 ¾ 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · MS-001d (see fig2) Symbol A B C D E F G H I Dimensions in inch Min.115 0.022 0.92 Max. 30.78 ¾ 8.54 ¾ 10.240 0. 1.070 ¾ 0.81 0.160 0.95 3.62 ¾ Nom.46 6.195 0.014 0. ¾ ¾ ¾ ¾ ¾ ¾ 2.92 0. 2010 .280 0.150 0.10 2.11 4. 29.36 1.

¾ ¾ ¾ ¾ ¾ ¾ 2.022 0.100 ¾ 0.300 ¾ Nom.30 231 October 4.08 6. 30.145 0.56 1.275 0.430 Dimensions in mm Min.014 0.54 ¾ 10.120 0.150 0.79 0.325 ¾ Symbol A B C D E F G H I Rev.49 3.150 0.14 ¾ 7. 1. 2010 .99 3.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 · MO-095a (see fig2) Symbol A B C D E F G H I Dimensions in inch Min.05 2.81 3.81 0.110 0. 1. ¾ ¾ ¾ ¾ ¾ ¾ 0.26 ¾ Max. 29.92 Max.10 7.295 0. 1.36 1.045 ¾ 0.52 ¾ 8.060 ¾ 0.185 0.62 ¾ Nom.

¾ ¾ ¾ ¾ ¾ 0.050 0.30 1.050 ¾ ¾ ¾ ¾ Dimensions in mm Min.393 0. ¾ ¾ ¾ ¾ ¾ 1.27 ¾ ¾ ¾ ¾ Max.51 15.41 0.012 0.64 ¾ 0.419 0.33 8° Max.020 0. 10.008 0° Nom.57 2. 1.013 8° Rev.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 24-pin SOP (300mil) Outline Dimensions 2 4 A 1 3 B 1 1 2 C C ' G H D E F a · MS-013 Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min.30 232 October 4.19 ¾ ¾ 0.64 7.50 0.598 ¾ ¾ 0.20 0° Nom.27 0.30 15.62 0.10 0.004 0.016 0. 9.300 0. 2010 .104 ¾ 0.256 0.012 0.98 6.613 0. 0. 0.

37 ¾ 0. ¾ ¾ ¾ ¾ ¾ 0.71 0.30 233 October 4.79 3.025 ¾ ¾ ¾ ¾ Dimensions in mm Min.060 ¾ 0.012 0. 5.25 8° Max.244 0.008 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 24-pin SSOP (150mil) Outline Dimensions 2 4 A 1 3 B 1 1 2 C C ' G H D E F a Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min.335 0.52 ¾ 0.18 0° Nom.346 0.010 8° Rev. 0.79 1.007 0° Nom.157 0. 0.022 0.81 0.20 3. ¾ ¾ ¾ ¾ ¾ 0. 2010 .30 8.004 0.51 1.028 0.56 0.10 0. 6.99 0.64 ¾ ¾ ¾ ¾ Max.25 0.010 0.054 ¾ 0.150 0.228 0.20 8. 1.

020 0.135 0.375 0.070 ¾ 0.050 ¾ 0. 34.53 Max.016 0.100 ¾ 0. 1.27 ¾ 7.51 1.298 0.06 3.295 ¾ Nom.49 ¾ Nom.43 3. ¾ ¾ ¾ ¾ ¾ ¾ 2.30 234 October 4. 1.315 ¾ Symbol A B C D E F G H I Rev.00 ¾ Max.41 1. 35.78 ¾ 8.18 3.68 0.54 ¾ 9.57 3.278 0.18 0.145 0. 2010 .125 0.93 7. ¾ ¾ ¾ ¾ ¾ ¾ 0. 1.125 0.43 7.395 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 28-pin SKDIP (300mil) Outline Dimensions A 2 8 1 5 1 4 1 B H C D E F G I Symbol A B C D E F G H I Dimensions in inch Min.375 Dimensions in mm Min.

9.050 ¾ ¾ ¾ ¾ Dimensions in mm Min.004 0.300 0. 1.393 0.41 0. 0.11 2. 10.30 17.70 ¾ ¾ 0.64 7.33 8° Max.016 0.62 0.013 8° Rev.713 0.012 0.020 0.64 ¾ 0.20 0° Nom.50 0.012 0.27 0. 2010 .HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 28-pin SOP (300mil) Outline Dimensions 2 8 A 1 5 B 1 1 4 C C ' G H D E F a · MS-013 Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min.98 6.050 0.30 1.008 0° Nom.27 ¾ ¾ ¾ ¾ Max.30 235 October 4.419 0. 0. ¾ ¾ ¾ ¾ ¾ 0.10 0.104 ¾ 0.256 0. ¾ ¾ ¾ ¾ ¾ 1.51 18.697 ¾ ¾ 0.

25 8° Max. 5.012 0.80 1.010 8° Rev.56 0. 2010 .37 ¾ 0.007 0° Nom.028 0.025 ¾ ¾ ¾ ¾ Dimensions in mm Min. ¾ ¾ ¾ ¾ ¾ 0.060 ¾ 0.71 0.004 0.394 0. 0.054 ¾ 0.20 9. ¾ ¾ ¾ ¾ ¾ 0.157 0.244 0.008 0.30 236 October 4.10 0.228 0.150 0.81 0. 0.01 1.64 ¾ ¾ ¾ ¾ Max.30 10.022 0. 1.25 0.386 0.010 0. 6.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 28-pin SSOP (150mil) Outline Dimensions 2 8 A 1 5 B 1 C C ' 1 4 G H a F D E Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min.18 0° Nom.99 0.79 3.20 3.52 ¾ 0.

¾ ¾ 0.020 ¾ ¾ ¾ ¾ Dimensions in mm Min.128 0.18 ¾ ¾ ¾ 1.80 0. 2010 .00 5.25 0.70 0.50 ¾ ¾ ¾ ¾ Max.008 ¾ 0.002 ¾ 0.25 0.197 0.197 0.30 ¾ Nom.30 237 October 4.05 ¾ 0.30 ¾ ¾ ¾ 3.028 0. 0. 0.000 ¾ 0.128 0.049 0.20 ¾ 5. 1.007 ¾ ¾ ¾ 0.25 1.50 ¾ Max.00 0. 0.012 ¾ ¾ ¾ 0.012 ¾ Nom.00 ¾ 0.031 0.25 3. 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions D 2 5 b E e A 1 A 3 L A 1 7 1 6 2 4 D 2 3 2 1 E 2 8 9 K Symbol A A1 A3 b D E e D2 E2 L K Dimensions in inch Min.020 ¾ Symbol A A1 A3 b D E e D2 E2 L K Rev. ¾ ¾ 0.049 0.

018 ¾ Symbol A A1 A3 b D E e D2 E2 L K Rev.012 ¾ ¾ ¾ 0.25 6.20 Nom. 2010 .179 0.35 0. 0.00 6.014 0.008 0. 0.50 0.236 0.70 0.18 ¾ ¾ ¾ 4.010 0.173 0.179 0.000 ¾ 0.030 0.00 ¾ 0. 0.75mm) QFN Outline Dimensions D 3 1 b 3 0 D 2 4 0 1 E e 2 1 A 1 A 3 A L K 2 0 1 1 1 0 E 2 · GTK Symbol A A1 A3 b D E e D2 E2 L K Dimensions in inch Min.173 0.20 0.008 Nom. 0.30 ¾ ¾ ¾ 4.001 0.00 0.177 0.007 ¾ ¾ ¾ 0.05 ¾ 0.020 0. 0. 0.45 ¾ Max.55 4.80 0.016 ¾ Dimensions in mm Min.031 0.50 4.30 238 October 4.55 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SAW Type 40-pin (6mm´6mm for 0.028 0.40 4.002 ¾ 0.02 0.50 4.75 0.177 0.40 0.40 ¾ Max. 1.236 0.

35 ¾ 0.394 0.40 10.30 239 October 4.012 0.25 1.40 10.520 0.520 0.057 0.90 13.010 0.008 7° Rev. 2010 .35 0.60 0.055 ¾ ¾ 0.004 0. 0.512 0.031 0.00 0.10 ¾ ¾ 1.047 ¾ ¾ Dimensions in mm Min.041 0.30 1. 1.390 ¾ ¾ 0.45 1.512 0.053 0.05 0.00 9.063 0.398 0.10 1.20 10.00 9.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 44-pin LQFP (10mm´10mm) (FP3.004 0° Nom.90 ¾ ¾ 1. 13.2mm) Outline Dimensions C D G 2 3 I 3 4 2 2 F A B E 4 4 1 2 K 1 1 1 a J 3 3 H Symbol A B C D E F G H I J K a Symbol A B C D E F G H I J K a Dimensions in inch Min.20 ¾ ¾ Max.40 ¾ ¾ 1. 0.528 0.00 13.10 0° Nom.10 13.528 0.25 7° Max.80 0. 13.394 0.20 10. 0.398 ¾ ¾ 0.053 ¾ 0.390 0. 13.

¾ ¾ ¾ ¾ ¾ 0.57 2.30 16.012 0.008 0.67 7.64 0.035 0.10 0.20 15.10 0° Nom.004 0° Nom.637 0. 0.291 0.613 0.16 ¾ 0.30 240 October 4. 1.010 0.51 ¾ 0.025 ¾ ¾ ¾ ¾ Dimensions in mm Min.395 0.085 ¾ 0.004 0.18 2.39 0.025 0. 10.89 0. 2010 . 0.25 0.64 ¾ ¾ ¾ ¾ Max. ¾ ¾ ¾ ¾ ¾ 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 48-pin SSOP (300mil) Outline Dimensions 4 8 A 2 5 B 1 C C ' 2 4 G H a F D E Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min.012 8° Rev.099 ¾ 0.59 0. 10.420 0.30 8° Max.03 7.299 0.

50 4.020 ¾ ¾ ¾ ¾ Dimensions in mm Min. ¾ ¾ 0.203 ¾ 7.177 0.50 0.30 0.00 ¾ 0.20 Nom.75 5.000 ¾ 0.227 0.70 0.007 ¾ ¾ ¾ 0.012 ¾ ¾ ¾ 0. 2010 .002 ¾ 0.031 0.008 Nom. 0. ¾ ¾ 0.30 ¾ ¾ ¾ 5.05 ¾ 0. 1.028 0.227 0.0 0.020 ¾ Symbol A A1 A3 b D E e D2 E2 L K Rev.177 0. 0.276 0.30 241 October 4. 0.276 0.008 ¾ 0.80 0.75 0.18 ¾ ¾ ¾ 4.50 ¾ ¾ ¾ ¾ Max. 0.0 7.50 ¾ Max.012 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SAW Type 48-pin (7mm´7mm) QFN Outline Dimensions D 3 7 b 3 6 D 2 4 8 1 E e 2 5 A 1 A 3 A L K 2 4 1 3 1 2 E 2 Symbol A A1 A3 b D E e D2 E2 L K Dimensions in inch Min.

10 ¾ ¾ 1.30 242 October 4.280 ¾ ¾ 0.20 7° Max.90 6. 9.063 ¾ 0. 0.75 0.057 0.35 ¾ ¾ 0.018 0.358 0. 1.350 0.272 ¾ ¾ 0.004 ¾ ¾ ¾ Dimensions in mm Min. ¾ ¾ ¾ ¾ 0.020 0.10 9.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 48-pin LQFP (7mm´7mm) Outline Dimensions C D 3 6 2 5 G H I 3 7 2 4 F A B E 4 8 1 3 K 1 1 2 a J Symbol A B C D E F G H I J K a Symbol A B C D E F G H I J K a Dimensions in inch Min.358 0. ¾ ¾ ¾ ¾ 0.10 ¾ ¾ ¾ Max.272 0.20 ¾ ¾ 0.50 0.90 8.45 0. 8.004 0° Nom.008 ¾ ¾ 0. 0.008 7° Rev.45 1.350 0.280 0.10 7.60 ¾ 0.90 ¾ ¾ 1.10 0° Nom.10 7. 2010 .90 6.030 0.053 ¾ ¾ 0.

689 0.039 0.547 ¾ ¾ 0.004 0° Nom.555 0.30 243 October 4.90 ¾ ¾ 2.20 7° Max.029 0. 1.10 0° Nom.73 0.00 0.555 ¾ ¾ 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 52-pin QFP (14mm´14mm) Outline Dimensions C D 3 9 2 7 G H I 4 0 2 6 F A B E 5 2 1 4 K J 1 1 3 Symbol A B C D E F G H I J K a Symbol A B C D E F G H I J K a Dimensions in inch Min. 17.40 ¾ 1.10 3.50 14.004 ¾ ¾ ¾ Dimensions in mm Min.10 ¾ ¾ ¾ Max. 2010 .689 0.016 ¾ ¾ 0. ¾ ¾ ¾ ¾ 0.008 7° Rev.098 ¾ ¾ 0.50 14. 0. 0.10 17. 17.30 13.30 13.10 ¾ ¾ 3.041 0. ¾ ¾ ¾ ¾ 1.40 ¾ ¾ 0.90 17.03 0.122 0.134 ¾ 0.681 0.50 ¾ ¾ 0.547 0.681 0.

0±1.8 +0.0 +0.5 13.2±0.0 100.0±0. SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.2±0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Product Tape and Reel Specifications Reel Dimensions T 2 D A B C T 1 SOP 16N (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.0 100.0±1.2 22.0±0.0 +0.3/-0.30 244 October 4.2 Rev.5 16.5/-0.2 SOP 20W.0±1.5 13.2 2. SOP 24W.2 30. 1.2 2. 2010 .0±1.5 24.3/-0.5/-0.8 +0.

3/-0.2 2. 2010 .0 +0.0 100.5 12.0 100.2 +0.2 Rev.2 2.0 +0.5 13.5 13.2±0.0±1.5/-0.0±1.30 245 October 4.3/-0.0±0.2±0.0 100. 1.2 SSOP 20S (150mil).1 13. SSOP 24S (150mil).8 +0.8 +0.5/-0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SSOP 16S Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.0 16.0±0.5 32.3/-0.0±1. SSOP 28S (150mil) Symbol A B C D T1 T2 SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.5 +0.0±0.2 18.2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.0±1.2 38.2 22.2 2.5/-0.0±1.0±0.2±0.

30±0. SOP 16N (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C SOP 20W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 24.3±0.75±0. 1.05 21.1 1.5±0.1 1.25/-0.30 246 October 4.5±0.3 8.1 10.3/-0.1 2.1 0.1 Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.25/-0.55 1.00 +0.0±0.10 11.1 3.5±0.05 13.30±0.5 1.00 4.1 0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Carrier Tape Dimensions D E F W C P 0 P 1 t B 0 D 1 P A 0 K 0 R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .0 +0.1 7.1 6.1/-0.3±0.1 13.0±0.75±0.0 +0.0±0.8±0.1 Rev. 2010 .1 1.1±0.2±0.1 2.1 2.50 +0.1 1.0±0.00 4.3±0.0±0.1 10.3±0.50 +0.0±0.0±0.1 12.10/-0.

1 2.5±0. 2010 .25/-0.0±0.75±0.5 1.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SOP 24W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.75±0.10 0.1 11.97±0.1 1.25/-0. 1.1 1.5±0.3 12.1 Rev.0±0.1 3.00 4.1 1.9±0.10 11.00 +0.1 0.0±0.1 10.01 21.3 12.1 2.10 18.34±0.35±0.10/-0.0 +0.50 +0.1±0.1/-0.0±0.30 247 October 4.1 1.3±0.9±0.0±0.00 4.10 2.1 SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.1 15.85±0.0±0.3±0.55 1.0±0.05 21.1 10.0±0.50 +0.35±0.

1 1.1 6.1 9.1 1.1 1.3±0.0 +0.1 2.00 4.1 Rev.1 2.0±0.5±0.75±0.0±0.75±0.25/-0.1 0.2±0.5±0.50 +0.3±0.00 4.10 7.0±0.1 0.1 2.0±0.0±0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SSOP 16S Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12.3/-0. 1.10 1.5 1.1 8.1 2.0 +0.30±0.1 8.05 9.50 +0.05 13.30 248 October 4.10 5.1 6. 2010 .3±0.1 5.1 SSOP 20S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.30±0.0±0.55±0.0 +0.1/-0.5±0.4±0.25/-0.1±0.0±0.3/-0.1 1.

1 2.10 7.0±0.1 8.1 0.75±0.00 4. 2010 .25/-0.1 Rev.1 1.25/-0.0±0.05 13.0±0.75±0.00 4.55 1. 1.3/-0.5+0.30 249 October 4.3±0.1/-0.10/-0.1 6.1 10.3±0.50 +0.30±0.5±0.0±0.30±0.0 1.0+0.0±0.0±0.3 8.1 1.50+0.5±0.05 13.1±0.1 1.1 2.5±0.1 0.1 7.1 9.00 +0.1 6.1 1.5±0.1 SSOP 28S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.5±0.1±0.0±0.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 SSOP 24S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.1 2.1 2.3±0.

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Carrier Tape Dimensions D E F W C B 0 P 0 P 1 t D 1 P K 2 A 0 K 1 R e e l H o le ( C ir c le ) IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .1 12.35±0.75±0.5±0.4±0.1 2.1 2.1 0.1 2 Min.00 4.10 14. R e e l H o le ( E llip s e ) SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.25/-0.3 16. 1. 1.1 3.1 Rev.2±0.0±0.05 25.0±0.0±0.1 16.2±0.0±0.30 250 October 4.2±0.1 1.50 +0. 2010 .0±0.

1. No. Nanshan District. (Headquarters) No. Rev. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification. Holtek reserves the right to alter its products without prior notification. (Taipei Sales Office) 4F-2. 2010 ..tw.com. YuanQu St. 3-2. Productivity Building. CA 94538. Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www. Holtek assumes no responsibility arising from the use of the specifications described.30 251 October 4. USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www. Fremont. Creation Rd.5 Gaoxin M 2nd Road.holtek.3. However. China 518057 Tel: 86-755-8616-9908.holtek. Shenzhen.holtek. Inc. No.HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Holtek Semiconductor Inc.com Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.. Science Park. 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA). (North America Sales Office) 46729 Fremont Blvd. Nankang Software Park.tw Holtek Semiconductor Inc. nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. For the most up-to-date information. The information appearing in this Data Sheet is believed to be accurate at the time of publication. Unit A. II. please visit our web site at http://www. Taipei 115.com. Hsinchu. Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F. Holtek¢s products are not authorized for use as critical components in life support devices or systems.

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