Lecture 2 Basic MOS Theory, SPICE Simulation, CMOS Fabrication

Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London

URL: http://cas.ee.ic.ac.uk/~kostas E-mail: k.masselos@imperial.ac.uk
MOS Theory, SPICE, Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 - 1

Based on slides/material by…
P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html “Digital Integrated Circuits: A Design Perspective”, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html Weste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, Addison Wesley

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Lecture 2 - 2

Recommended Reading
J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”: Chapter 2 (2.1 – 2.3), Chapter 3 (3.3) Weste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”: Chapter 2, Chapter 3 (3.2), Chapter 5.

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Lecture 2 - 3

SPICE.Outline MOS transistors SPICE simulation CMOS fabrication process Layout rules MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .4 .

MOS Theory.MOS Transistor Shown here is the cross-section of an n-channel enhancement transistor: Substrate is moderately doped with p-type material. The source and drain regions are heavily doped with n-type material through diffusion. These are often referred to as the diffusion regions. Substrate in digital circuit is usually connected to VGnd (ground). Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.5 .

substrate) enhances the number of carriers in the channel. Threshold voltage Vtn denotes the gate-to-source voltage above which conduction occurs.r. and increases conduction. Vtn is positive. MOS Theory.6 . For enhancement mode devices. A positive gate voltage (w. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . for depletion mode devices.t.Conduction Characteristics of MOS Transistors (for fixed Vds) MOS transistors are majority-carrier devices. except that all voltages and currents are in opposite polarity. p-channel devices are similar to n-channel devices. the majority carriers are electrons conducted through a channel. Vtn is negative. SPICE. For n-channel transistors.

7 . SPICE.Cross-Section of CMOS Technology MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .8 .MOS transistors .Types and Symbols D D G S NMOS Enhancement G NMOS Depletion S D D G PMOS Enhancement S G S B NMOS with Bulk Contact MOS Theory.

9 . SPICE.Threshold Voltage: Concept S - + V GS G D n+ n+ n-channel p-substrate B Depletion Region MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

Due to geometric symmetry.MOS transistor (1) Between the diffusion regions is the gate area form from a layer of polycrystaline silicon (known as polysilicon). The channel is conducting when a suitable electric field is applied to the gate. SPICE. However. Underneath the thin oxide and between the n+ regions is the channel. no current flows between the drain and source because of the two reverse biased diodes shown in the diagram. there are no distinctions between the source and drain regions. The drain and source are therefore isolated from each other. these two diode should never become forward bias under normal operation. we usually refer the terminal with more positive voltage the drain (for n-type) and less positive voltage the source. MOS Theory. Assuming that the substrate is always at the most negative supply voltage. This is separated from the substrate by a layer of thin oxide (made of silicon dioxide). Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .10 . For a zero gate bias and a positive VDS. Polysilicon is reasonable conductor and form the gate electrode.

Contrast this with the p-n junction between the source (or drain) and the substrate. This diode junction is field induced. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . As larger bias is applied to the gate the inversion layer becomes thicker An other p-n junction exists between the inversion layer and the substrate. providing a conduction path between the source and drain. The surface is known as the inversion layer. the area under the gate changes from p-type to n-type. an electric field is produced across the substrate which attracts electrons toward the gate. The surface underneath the gate under this condition is said to be inverted.11 .MOS transistor (2) When a positive voltage is applied to the gate. SPICE. MOS Theory. Eventually. which is created by a metallurgical process. The gate-source voltage VGS when a channel starts to form under that gate is called the threshold voltage VT.

12 . SPICE.The Threshold Voltage 0 MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .13 . SPICE.Current-Voltage Relations S V GS G V DS D n+ L x ID n+ – V(x) + p-substrate B MOS transistor and its bias conditions MOS Theory.

Current-Voltage Relations MOS Theory.14 . SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

V T D G S n+ - VG S .Transistor in Saturation VG S V DS > VGS .VT + n+ MOS Theory.15 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.

If VDS < VGS .VT. ID increases linearly with (VGS .16 . then VGS < VT and no inversion layer can exist at the drain terminal. Furthermore. The channel is said to be 'pinched-off'. The transistor is said to be operating in its linear or resistive region. The transistor is operating in the saturation region. then the drain current Id is a function of both VGS and VDS. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .VT. the inversion layer becomes thinner at the drain terminal due to interaction between VG and VD. MOS Theory. If VDS > VGS . where the drain current is dependent on VGS and is almost independent of VDS.VT). SPICE.MOS transistor (3) As a voltage is applied between the source and drain. for a given VDS.

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .I-V Relation MOS Theory.17 . SPICE.

A model for manual analysis

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Lecture 2 - 18

Dynamic Behavior of MOS Transistor
G

CGS S

CGD D

CSB

CGB

CDB

B
MOS Theory, SPICE, Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 - 19

The Gate Capacitance

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Lecture 2 - 20

Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions Most important regions in digital design: saturation and cut-off MOS Theory.21 . SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

SPICE.Issues concerning Sub-Micron MOS Transistors Threshold Variations Parasitic Resistances Velocity Saturation Mobility Degradation MOS Theory.22 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

23 .Threshold Variations VT Long-channel threshold Low VDS threshold L Threshold as a function of the length (for low VDS) Drain-induced barrier lowering (for low L) MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.

24 . SPICE.Parasitic Resistances MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .25 .Velocity Saturation (1) MOS Theory. SPICE.

0 I D (mA) VGS = 4 VGS = 3 0.26 .0 VDS (V) 4.0 2. Linear Dependence on VGS MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .0 V G S (V) 3.Velocity Saturation (2) 1.0 2.5 VGS = 5 1.0 5.0 (a) I D as a function of V DS (b) ID as a function of V G S (for VDS = 5 V). SPICE.0 3.0 Linea r Dependence 0.0 1.0 1.5 ID (mA) 0 0.5 VGS = 2 VGS = 1 0.

0 2. SPICE.0 VGS (V) 3.Sub-Threshold Conduction 10−2 10−4 ln(ID) (A) 10−6 10−8 10−10 10−12 0.0 Subthreshold exponential region Linear region VT 1. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .27 .0 MOS Theory.

substrate and the p+ source of the n-transistor forms another parasitic npn transistor T2. the n-well and the p. There exists two resistors Rw and Rs due to the resistive drop in the well area and the substrate area. the p.Latch-up problem (1) The p+ region of the p-transistor.substrate form a parasitic pnp transistor T1. MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . The n.28 . SPICE.well.

To avoid latch-up. both transistors will remain conducting due to the voltage drop across Rw and Rs. T1 or T2 are forced to conduct. SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . This condition is known as latch-up. and for some reason (power-up.29 . The only way to get out of this mode is to turn the power off.Latch-up problem (2) T1 and T2 form a thyristor circuit. MOS Theory. current spike etc). Vdd will be shorted to Gnd through the small resistances and the transistors. This has the effect of shorting out Rw and Rs. Once the circuit is 'fired'. substrate-taps (tied to Gnd) and well-taps (tied to Vdd) are inserted as frequently as possible. If Rw and/or Rs are not 0.

Outline MOS transistors SPICE simulation CMOS fabrication process Layout rules MOS Theory.30 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.

originally from Berkeley. Dependent sources (V. It supports the following: • Textual input to specify circuit & simulation commands • Text or graphical output format for simulation results You can use SPICE to specify these circuit components: • • • • • • • • Resistors. SPICE uses numerical techniques to solve nodal analysis of circuit. BJTs. I). non-linear transient linear a. Inductors Independent sources (V.c. MOSFETS) non-linear d. Capacitors.What is SPICE Circuit Simulator? SPICE is a widely-used circuit-level simulator. I) Transmission lines Active devices (diodes.31 You can use SPICE to perform the following types circuit analysis: MOS Theory. Fabrication . Noise & temperature Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.c. JFETS.

Very Simple Level 2: Physical Model .SPICE MODELS Level 1: Long Channel Equations . SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Simple and Popular MOS Theory.Based on curve fitting to measured devices Level 4 (BSIM): Em perical .Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical .32 .

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .MAIN MOS SPICE PARAMETERS MOS Theory. SPICE.33 .

SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .34 .SPICE Parameters for Parasitics MOS Theory.

35 . SPICE.SPICE Transistors Parameters MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .36 . SPICE.Fitting level-1 model for manual analysis Region of matching ID Short-channel I-V curve V GS = 5 V Long-channel approximation V DS = 5 V V DS Select k ’ and λ such that best matching is obtained @ V gs = V ds = V DD MOS Theory.

Vt must decrease to maintain device performance But this causes exponential increase in OFF leakage Major future challenge MOS Theory.Technology Evolution VDD decreases • Save dynamic power • Protect thin gate oxides and short channels • No point in high value because of velocity sat. SPICE.37 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

38 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.Outline MOS transistors SPICE simulation CMOS fabrication process Layout rules MOS Theory.

CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step.39 . SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process MOS Theory.

40 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors Vi Qn VDD Qp Vo A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1 MOS Theory. SPICE.

Fabrication Introduction to Digital Integrated Circuit Design well tap Lecture 2 . SPICE.Well and Substrate Taps Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps A GND Y VDD p+ n+ n+ p substrate p+ n well p+ n+ substrate tap MOS Theory.41 .

Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line A Y GND nMOS transistor substrate tap MOS Theory. SPICE.42 . Fabrication Introduction to Digital Integrated Circuit Design VDD pMOS transistor well tap Lecture 2 .

43 .Detailed Mask Views Six masks • • • • • • n-well Polysilicon n+ diffusion p+ diffusion Contact Metal n well Polysilicon n+ Diffusion p+ Diffusion Contact Metal MOS Theory. SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well • • • • Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2 p substrate MOS Theory. SPICE.44 .

SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .45 .Oxidation Grow SiO2 on top of Si wafer • 900 – 1200 C with H2O or O2 in oxidation furnace SiO2 p substrate MOS Theory.

46 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Photoresist Spin on photoresist • Photoresist is a light-sensitive organic polymer • Softens where exposed to light Photoresist SiO2 p substrate MOS Theory. SPICE.

SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Lithography Expose photoresist through n-well mask Strip off exposed photoresist Photoresist SiO2 p substrate MOS Theory.47 .

48 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.Etch Etch oxide with hydrofluoric acid (HF) • Seeps through skin and eats bone. nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist SiO2 p substrate MOS Theory.

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Strip Photoresist Strip off remaining photoresist • Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step SiO2 p substrate MOS Theory. SPICE.49 .

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .n-well n-well is formed with diffusion or ion implantation Diffusion • Place wafer in furnace with arsenic gas • Heat until As atoms diffuse into exposed Si Ion Implantation • Blast wafer with beam of As ions • Ions blocked by SiO2. only enter exposed Si SiO2 n well MOS Theory. SPICE.50 .

51 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps n well p substrate MOS Theory. SPICE.

Polysilicon Deposit very thin layer of gate oxide • < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer • Place wafer in furnace with Silane gas (SiH4) • Forms many small crystals called polysilicon • Heavily doped to be good conductor Polysilicon Thin gate oxide n well p substrate MOS Theory. SPICE.52 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

Polysilicon Patterning Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide n well p substrate MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .53 . SPICE.

54 . SPICE. drain.Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source. and n-well contact n well p substrate MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing n+ Diffusion n well p substrate MOS Theory.55 .

N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion n+ n+ n well p substrate n+ MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .56 . SPICE.

SPICE.57 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . Strip off oxide to complete patterning step n+ n+ n well p substrate n+ MOS Theory.N-diffusion cont.

58 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .P-diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p+ n+ n+ p substrate p+ n well p+ n+ MOS Theory. SPICE.

Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Contact Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+ MOS Theory.59 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 . SPICE.

SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .60 . leaving wires M e ta l Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+ MOS Theory.Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal.

Outline MOS transistors SPICE simulation CMOS fabrication process Layout rules MOS Theory.61 . SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .3 μm in 0. and power) Feature size f = distance between source and drain • Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of λ = f/2 • E. cost.62 . SPICE.g.Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed.6 μm process MOS Theory. λ = 0.

Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width • scalable design rules: lambda parameter • absolute dimensions (micron rules) MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .63 . SPICE.

n) Active Area (n+. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .p+) Select (p+.64 .CMOS Process Layers Layer Color Representation Well (p. SPICE.n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Yellow Green Green Red Blue Magenta Black Black Black MOS Theory.

SPICE.65 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Intra Layer Design Rules Same Potential 0 or 6 10 3 Active 3 2 Select Different Potential 9 Polysilicon 2 Metal1 Contact or Via Hole 2 2 Metal2 3 2 Well 3 3 4 MOS Theory.

Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .66 .Transistor Layout Transistor 1 3 2 5 MOS Theory. SPICE.

67 .Via’s and Contacts 2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4 2 2 MOS Theory. SPICE. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .

SPICE.68 .Select Layer 2 3 2 1 3 3 Select 2 5 Substrate MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Well Lecture 2 .

SPICE.CMOS Inverter Layout GND In VD D A A’ Out (a) Layout A p-substrate n + A’ n p + Field Oxide (b) Cross-Section along A-A’ MOS Theory. Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .69 .

70 . Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 .Summary MOS transistor: majority carrier device – building block of integrated circuits SPICE: popular circuit level simulator that applies nodal analysis of circuit CMOS transistors are fabricated on silicon wafer • Lithography process • Different materials are deposited or etched in each step Layout rules: contract between IC designer and process engineer • Guidelines for constructing process masks MOS Theory. SPICE.

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