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(Established under section 3 of UGC Act, 1956)
Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai - 119.
SYLLABUS MASTER OF ENGINEERING PROGRAMME IN EMBEDDED SYSTEMS (4 SEMESTERS) REGULATIONS 2010
FACULTY OF ELECTRONICS ENGINEERING
SATHYABAMA UNIVERSITY REGULATIONS – 2010
Effective from the academic year 2010-2011 and applicable to the students admitted to the Master of Engineering / Technology / Architecture /Science (Four Semesters) 1. Structure of Programme 1.1 Every Programme will have a curriculum with syllabi consisting of theory and practical such as: (i) (ii) (iii) (iv) 1.2 General core courses like Mathematics Core course of Engineering / Technology/Architecture / Science Elective course for specialization in related fields Workshop practice, Computer Practice, laboratory Work, Industrial Training, Seminar Presentation, Project Work, Educational Tours, Camps etc.
Each semester curriculum shall normally have a blend of lecture course not exceeding 7 and practical course not exceeding 4.
1.3 The medium of instruction, examinations and project report will be English. Duration of the Programme A student is normally expected to complete the M.E/M.Tech./M.Arch/M.Sc Programme in 4 semesters but in any case not more than 8 consecutive semesters from the time of commencement of the course. The Head of the Department shall ensure that every teacher imparts instruction as per the number of hours specified in the syllabus and that the teacher teaches the full content of the specified syllabus for the course being taught.
Requirements for Completion of a Semester A candidate who has fulfilled the following conditions shall be deemed to have satisfied the requirement for completion of a semester. 3.1 3.2 He/She secures not less than 90% of overall attendance in that semester. Candidates who do not have the requisite attendance for the semester will not be permitted to write the University Exams.
Examinations The examinations shall normally be conducted between October and December during the odd semesters and between March and May in the even semesters. The maximum marks for each theory and practical course (including the project work and Viva Voce examination in the Fourth Semester) shall be 100 with the following breakup. (i) Theory Courses
Internal Assessment : University Exams : 20 Marks 80 Marks
Internal Assessment : University Exams : - 100 Marks
M.E. (EMBEDDED SYSTEMS)
FACULTY OF ELECTRONICS ENGINEERING
Passing requirements (i) A candidate who secures not less than 50% of total marks prescribed for the course (For all courses including Theory, Practicals and Project work) with a minimum of 40 marks out of 80 in the University Theory Examinations, shall be declared to have passed in the Examination. If a candidate fails to secure a Pass in a particular course, it is mandatory that he/she shall reappear for the examination in that course during the next semester when examination is conducted in that course. However the Internal Assessment marks obtained by the candidate in the first attempt shall be retained and considered valid for all subsequent attempts.
Eligibility for the Award of Degree A student shall be declared to be eligible for the award of the M.E/M.Tech./M.Arch./M.Sc degree provided the student has successfully completed the course requirements and has passed all the prescribed examinations in all the 4 semesters within the maximum period specified in clause 2.
Award of Credits and Grades All assessments of a course will be done on absolute marks basis. However, for the purpose of reporting the performance of a candidate, Letter Grades will be awarded as per the range of total marks (out of 100) obtained by the candidate as given below:
RANGE OF MARKS FOR GRADES
Range of Marks 90-100 80-89 70-79 60-69 50-59 00-49 ABSENT Grade A++ A+ B++ B+ C F W Grade Points (GP) 10 9 8 7 6 0 0
CUMULATIVE GRADE POINT AVERAGE CALCULATION
The CGPA calculation on a 10 scale basis is used to describe the overall performance of a student in all courses from first semester to the last semester. F and W grades will be excluded for calculating GPA and CGPA.
CGPA = Σi C i GP i Σ i Ci
where Ci - Credits for the subject
GP i - Grade Point for the subject Σi - Sum of all subjects successfully cleared during all the semesters
M.E. (EMBEDDED SYSTEMS)
he/she shall be liable for punitive action as prescribed by the University from time to time. securing a CGPA not less than 7. the break of study during the programme. If a student indulges in malpractice in any of the University theory / practical examination. 3.50 CGPA ≥ 5. shall be considered to have appeared in that examination for the purpose of classification of degree.0 CGPA ≥ 7. scheme of examinations and syllabi from time to time.0 CGPA ≥ 6.5 shall be declared to have passed the examination in First Class with Distinction. A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive semesters after commencement of study.00 First Class . within 1 week from the declaration of results. M.0 shall be declared to have passed the examination in Second Class.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING 8. amend or change the regulations. Revaluation is not permitted for practical courses and for project work.E. 9. A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters within a maximum period of 4 consecutive semesters after commencement of study securing a CGPA not less than 6. A candidate who is absent in semester examination in a course/project work after having registered for the same. The Controller of Examination will arrange for the revaluation and the result will be intimated to the candidate concerned through the Head of the Department. (EMBEDDED SYSTEMS) iii REGULATIONS 2010 . Classification of the Degree Awarded 1 A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive semesters after commencement of study securing a CGPA not less than 9. if found necessary. A candidate can apply for revaluation of his/her semester examination answer paper in a theory course.0 shall be declared to have passed the examination in First Class – Exemplary. Revision of Regulations and Curriculum The University may revise.0 CGPA. 2.50 < 9.0 shall be declared to have passed the examination in First Class. on payment of a prescribed fee along with prescribed application to the Controller of Examinations through the Head of Department.Exemplary First Class with Distinction First Class Second Class Minimum CGPA requirements for award of Degree is 5. 10. All other candidates who qualify for the award of the Degree having passed the examination in all the courses of all the 4 semesters within a maximum period of 8 consecutive semesters after his/her commencement of study securing a CGPA not less than 5. will be counted for the purpose of classification of degree.00 < 6.00 < 7. Discipline Every student is required to observe disciplined and decorous behaviour both inside and outside the University and not to indulge in any activity which will tend to bring down the prestige of the University. For all the above mentioned classification of Degree. 4 5 6 Final Degree is awarded based on the following : CGPA ≥ 9.
(EMBEDDED SYSTEMS) iv REGULATIONS 2010 . II 0 0 4 2 13 TOTAL CREDITS: 18 SECX5003 SECX5004 SECX5005 DSP Processors Real Time Operating System Embedded System Design Elective-I Elective-II 3 3 3 3 3 0 1 0 0 0 0 0 0 0 0 3 4 3 3 3 6 7 8 SUBJECT CODE SUBJECT TITLE L T P C Page No. THEORY 1. 4. 4. 0 0 4 2 12 TOTAL CREDITS: 18 SECX5006 SECX5007 SECX5031 Programming in Matlab and Labview Embedded Networking Cryptography and Network Security Elective-III Elective-IV 3 3 3 3 3 0 1 0 0 0 0 0 0 0 0 3 4 3 3 3 9 10 11 SUBJECT CODE SUBJECT TITLE L T P C Page No. 5. 5. PRACTICAL 6. SEMESTER II Sl. SECX6502 Embedded Systems Lab. PRACTICAL 6.EMBEDDED SYSTEMS REGULATIONS 2010 . 3. 2.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING M. SECX6512 Design Project Lab. 3.No.E . PRACTICAL 6. THEORY 1.CURRICULUM SEMESTER I Sl. THEORY 1. 2. SECX6501 Embedded Systems Lab I 0 0 4 2 12 TOTAL CREDITS : 19 SECX5016 SECX5017 SECX5018 SECX5001 SECX5002 Transforms and Probability for Electronics Engineering Advanced Digital System Design VLSI Design Microcontrollers System Design Embedded C 3 3 3 3 3 1 0 0 1 0 0 0 0 0 0 4 3 3 4 3 1 2 3 4 5 SUBJECT CODE SUBJECT TITLE L T P C Page No. 4.No.No. SEMESTER III Sl. 3.E. 2. M. 5.
2. 13. 8. 6. 12. 7. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 L – Lecture hours. T – Tutorial hours.No. 10. 11. C – Credits M. SUBJECT CODE SECX5021 SECX5008 SECX5031 SECX5084 SECX5085 SECX5009 SECX5010 SECX5011 SECX5079 SECX5012 SICX5010 SECX5013 SECX5086 SECX5014 SECX5069 SUBJECT TITLE Advanced Digital Signal and Image Processing Embedded Processor and Peripherals Electromagnetic Interference and Compatibility Fuzzy Logic and Neural Network Blue Tooth Technology Mixed Signal Embedded System Data Compression Techniques Advanced Embedded Systems Wireless Sensor Networks Embedded Communication Software Design Advanced Robotics and Automation DSP Integrated Circuits Wireless and Mobile Communication Embedded Control Systems Analysis and Modeling of Digital System Using VHDL L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Page No. P – Practical hours.E.No. 1. 3. 1. 15. SUBJECT CODE S88XPROJ SUBJECT TITLE Project work & Viva Voce L 0 T 0 P 30 C 15 TOTAL CREDITS FOR THE COURSE: 70 LIST OF ELECTIVE SUBJECTS Sl. (EMBEDDED SYSTEMS) v REGULATIONS 2010 . 4.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SEMESTER IV Sl. 14. 5. 9.
“Probability and random process with application to signal processes”. continues types -2D variable random variables – marginal. Discrete Sine. 3 rd Edition.V. Review of Fourier analysis . joint probability distribution .Two dimensional random variables . Embedded. 30 marks Part B: 5 Questions from each of the five units of internal choice. John Wodds. ”Discrete Time Signal Processing”. Raghuveer M. Woods.Theory) M. conditional.DFT . Harr wavelet and Shannon wavelet-– Fast Wave let transform – Wavelet Packets. each carrying 10 marks. Alan V. Wavelet transform .Problems. UNIT IV PROBABILITY AND RANDOM VARIABLES 10 hrs.moment generating function . 2. 3rd Edition.CWT.properties .regression system . (EMBEDDED SYSTEMS) 1 REGULATIONS 2010 . Springer Publication. “Discrete and continuous boundary problems”. Notion of stochastic processes. 1st Edition. “Digital Image Processing”.Hilbert transform UNIT II 2D TRANSFORMS 10 hrs. and Eddins. Prentice Hall. NanoTech. Academic Press Inc. Hadamard.DTFT . Prentice Hall. Schafer. Poisson.Convolution – review of Z transform.1D & 2D Wavelet transform . Slant.F. 50 marks (40% . Ajit S.discrete types.2009.simulation of white noise – low pass filtering of white noise. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice.A.Time and frequency decompositions .M. “Probability and information”. Bopardikar. DCT. 2001. uniform.Analysis of different periodic & non periodic waveforms – Sampling Theorem DFS . Yaglon. 1983. 2008. W. 60% .STFT .Random variable . Haar. Need for transform – 2D Orthogonal and Unitary transform and its properties – 2D DFT – Properties – FFT – Statement. Rao. 1998. co variance – scalar product – energy of discrete signals – parseval. TEXT BOOK: 1. “Wavelet Transforms: Introduction to Theory & Applications”.FFT – radix r algorithm – DIT FFT & DIF FFT . 3. REFERENCE BOOKS: 1.E. Prentice Hall. Oppenheim. UNIVERSITY EXAM QUESTION PAPER PATTERN Max.) L 3 T 1 P 0 Credits 4 Total Marks 100 UNIT I ID TRANSFORMS 10 hrs.Continues and discrete . Prentice Hall.inverse DFT. 5. 4.power spectral density function – properties . 1998.Binomial. proof and properties of Separable transforms – Walsh.transformation of random variables .Discrete random process – expectations – variance. Gonzalez. SVD & KL transforms UNIT III WAVELET TRANSFORMS 10 hrs.response of linear discrete systems to white noise .SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5016 TRANSFORMS & PROBABILITY FOR ELECTRONICS ENGINEERING (Common to VLSI. Ronald W.s theorem – Wiener Khintchine relation – Discrete random signal processing by linear systems . Auto Correlation – Cross Correlation – WSS – Ergodicity . normal and Exponential distributions UNIT V RANDOM PROCESS 10 hrs. Atkinson. DWT. Probability concepts. Volume 8.
3. 30 marks Part B: 5 Questions from each of the five units of internal choice. Nripendra N Biswas.Complex PLD’s(CPLD)-System design using PLD’s-Design of combinational and sequential circuits using PLD’s. Structure of standard PLD’s. (EMBEDDED SYSTEMS) 2 REGULATIONS 2010 . Embedded. Input/Output Block (IOB)-Programmable Interconnect Point(PIP). State table minimization. UNIT III ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 10 hrs. Incompletely specified sequential machines. “Logic Design Theory”. each carrying 10 marks.ASM Realization. 40% . 2.Design of state machine using Algorithmic State Machines(ASM) chart as design tool.Introduction to ACT2 family and Xilinx XC4000 families.) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I SEQUENTIAL LOGIC CIRCUITS 10 hrs. State diagrams. Tata Mc Graw Hill. UNIT V STUDY OF FPGA AND XILINX 10 hrs. Basic concepts. programming technologies. Moore machine. Analysis of clocked synchronous sequential Networks (CSSN). “Digital Principles and Design”. Configurable Logic Blocks (CLB). Design of synchronous and asynchronous sequential logic circuits working in fundamental and pulse mode. 2004. Thomson Learing. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. Programmable Logic Element(PLE). “Digital Logic Applications and Design”. 50 marks (60% . Appl.Programmable Logic Array(PLA).Problems. Prentice Hall of India. Introduction to Field Programmable Gate Arrays-Types of FPGA –Xilinx XC3000 series. Logic Cell Array(LCA). REFERENCE BOOKS: 1. Elec. Analysis of Asynchronous sequential Circuits (ASC)-Flow table reduction -Races in ASC--State assignmentProblem and the Transition table-Design of ASC-Static and Dynamic hazards-Data synchronizers-Designing of Vending machine controller-Mixed operating mode Asynchronous circuits. Trivial/Reversible/Isomorphic sequential machines. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice.Givone. Charles H Roth Jr. UNIT II SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 10 hrs.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5017 ADVANCED DIGITAL SYSTEM DESIGN (Common to VLSI. Programmable Array Logic(PAL).Theory) M. Design examples. Donald G.ASM Chart. 2001. UNIT IV PROGRAMMABLE LOGIC DEVICES 10 hrs. “Fundamentals of Logic Design”. 2002. Mealy machine. TEXT BOOK: 1.E. John M Yarbrough. Thomson Learning. 2001. State assignments.Programmable PAL device using PALASM. Modeling of CSSN-State table assignment and reduction – Design of CSSN-Design of iterative circuits.
2000. (EMBEDDED SYSTEMS) 3 REGULATIONS 2010 . CMOS static flip-flops-dynamic sequential circuits – CMOS Logic – NORA CMOS . NanoTech) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I 10 hrs.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5018 VLSI DESIGN (Common to VLSI. 5. 1994. Geigar and Allence. Review of MOS electrical properties – Expression for threshold voltage and drain current .Theory. “Introduction to VLSI Design”. Franco Maloberti.NMOS and CMOS design rules – stick diagram and layout. REFERENCES BOOKS: 1.Enhancement load and depletion-load inverters – CMOS inverter – CMOS inverter logic levels – Inverter device sizing – combinational logic implementation using NMOS and CMOS inverters . 3.Resistance and performance UNIT V 10 hrs. 10% . dynamic.Problems) M. Steering logic design – programmable logic arrays – Folded PLA‘s – structured gate arrays – Dynamic MOS storage circuits – performance of Dynamic logic – clocked CMOS logic UNIT IV 10 hrs. Manchester carry chain. Randall L. Kluwer Academic Publishers. 30 marks Part B: 5 Questions from each of the five units of internal choice. UNIT II 10 hrs. 1990. 2001. 2.True single phase clocked logic – Capacitors and performance in CMOS – driving large capacitance . UNIT III 10 hrs. “Basic VLSI Design”. Basic inverter . Kluwer. 50 marks (90% . UNIVERSITY EXAM QUESTION PAPER PATTERN Max. each carrying 10 marks. “VLSI Design for Analog and Digital circuits”.carry look ahead adder – multipliers : Baugh wooley. Mc Graw Hill. “Low-Power Digital VLSI Design: Circuits and Systems”. Academic Publishers. “Analog design for CMOS VLSI systems”.Energy band structure and band bending in the different region of operation .Secondary effects of MOSFET review of CMOS and bipolar technologies. carry bypass adder. Pearson Education Ltd. 2003. Prentice Hall. Douglas A. Jan M. 1990. Pucknell.Inverter Device sizing . CSA. Booth Multiplier – Barrel shifter – NOR and NAND ROMs – operations in CMOS SRAM – Sence amplifiers TEXT BOOK: 1. Fabricious E Design.E. Abdellatif Bellaouar. Embedded. Design of order Static. 4. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. Mc Graw Hill. Rabaey “Digital Integrated Circuits”.
register banks. Ayala. 2004. Sensor. 1st Edition. Reset. A. Project. Introduction-Intel 8051 architecture-Counters and Timers-Serial interface-Interrupts-Interfacing to external memory and 8255-Instruction set-Addressing modes. Keyboard and LCD. Assembler. 2nd Edition.E. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. "Microcontrollers: theory and applications". 2. UNIT II 8051 ALP AND APPLICATIONS 10 hrs. PIC Architecture.ARM organization and implementation . Select Development Mode and Device Type. program memory paging. UNIT IV PIC HARDWARE 10 hrs. MPLAB overview: Using MPLAB. Introduction: PIC microcontroller features.ARM CPU cores. interrupts. 2000. Person Education.Destination Designator (d). REFERENCES BOOKS: 1. Bit-Oriented Instructions.chip architecture". Assembly language programming-Timers and Counters programming-DAC. ports-interrupts-I2C Bus-A/D converter. 2nd Edition.. 4. ARM: The ARM architecture . V. 3.Basic ARM Assembly language program . clock. Steave Furber. Control Instructions (CALL and GOTO). Literal Instructions. Instruction set. 2004. watchdog timer. 30 marks Part B: 5 Questions from each of the five units of internal choice. Ports. TEXT BOOK: 1. (EMBEDDED SYSTEMS) 4 REGULATIONS 2010 . Addressing Modes. Deshmukh.Peatman. "Design with Microcontrollers". Instruction Format. Text Editor. 2000.on . "ARM system .SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5001 MICROCONTROLLERS SYSTEM DESIGN L 3 T 1 P 0 Credits 4 Total Marks 100 UNIT I 8-BIT MICROCONTROLLER 10 hrs. MPLAB Operations. 2nd Edition. Janice Gillispie Mazidi. each carrying 10 marks.The thumb instruction set . 50 marks M. John. "The 8051 Microcontroller and Embedded systems". ADC. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. 12th reprint. 2005. Thomson. Muhammad Ali Mazidi. UNIT V HIGH PERFORMANCE RISC ARCHITECTURE 10 hrs. control registers. sleep mode. power up timer. Addison Wesley. Kenneth. Timer and Counter. Byte-Oriented Instructions. Tata Mc Graw Hill. Person Education.The ARM instruction set . Toolbars.B. "The 8051 Microcontroller". UNIT III PIC MICROCONTROLLER 10 hrs. Program memory.
Reading switches-using the serial interface-meeting real time constraints-creating hardware delay using timers-creating loop timeouts. UNIT II 10 hrs. "Embedded C".pointers.Communication with Matlab and Labview. 2002. 1st Edition. TEXT BOOK: 1. 30 marks Part B: 5 Questions from each of the five units of internal choice. 2005. O’Reilly Media. UNIT III 10 hrs. Introduction-basic features-data types-input and output statement-if statement-else if-switch statement-for loop-while loop-do while loop. System programming Vs.structures and unions-functions and macros-pre-processor-C compilation system-file handling. “Programming with C“. Application programming-option of C for embedded programming-review of C language with embedded perspective. REFERENCE BOOKS: 1. UNIT V 10 hrs. Addison-Wesley. each carrying 10 marks. Michael J Pont. Tata Mc Graw-Hill. 2nd Edition. "Designing embedded hardware". Bitwise operators-pointers arithmetic-bit fields-mixing assembly and C-Memory Management in C-Optimization techniques-testing and debugging. Case study: Intruder Alarm System. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. K R Venugopal and Sudeep R Prasad. 2003. 2. UNIVERSITY EXAM QUESTION PAPER PATTERN Max.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5002 EMBEDDED C L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I 10 hrs. (EMBEDDED SYSTEMS) 5 REGULATIONS 2010 . 1st Edition. 50 marks M. Arrays-strings . UNIT IV 10 hrs. John catsoulis.E.
Oppenheim and R. "Digital Signal Processing: Principles. UNIT IV ANALOG DEVICES PROCESSORS FOR DSP 10 hrs. 1st Edition. 4. Dimitris.W. 2. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. Tata Mc Graw-Hill. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. Prentice Hall. UNIT III TEXAS PROCESSORS FOR DSP Architecture -Addressing modes -Instruction set -Programming -Peripherals -Memory -Applications.E. Computational units. John G. Schafer. Venkatramani. 30 marks Part B: 5 Questions from each of the five units of internal choice.com. Lawrence R. A.Manolakis. BernardGold. Algorithms and Applications". processor memory architecture. 10 hrs.Interpolation by an integer Factor -Discrete Fourier transform – properties – Fast Fourier transform –– periodogram estimator.Welch estimation.Bartlett spectrum estimation. 2001. DAG. 2009. "Digital Signal Processors". Prentice Hall.com. TEXT BOOK: 1. Prentice Hall. Website: www.V.www. Architecture . 3rd Edition. Architecture of BF533. 3. each carrying 10 marks. Peripherals."Theory And Application Of Digital Signal Processing".Proakis.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5003 DSP PROCESSORS L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I FOURIER TRANSFORM AND SPECTRUM ESTIMATION 10 hrs. UNIT II FILTERS 10 hrs. 3rd Edition. REFERENCE BOOKS: 1. Program sequencer.Rabiner. (EMBEDDED SYSTEMS) 6 REGULATIONS 2010 .Addressing modes .Instruction set – Data address generator-PMD-DMD Bus exchange unit-ALU-MAC-Barrel Shifter – Memory . 2006. Sampling of Band Pass signals-Sampling rate conversion-Decimation by an integer factors. UNIT V BLACKFIN PROCESSORS 10 hrs. "Discrete-Time Signal Processing". FIR Filter – windowing technique – optimum equiripple linear phase FIR filter – IIR filter – Bilinear transformation technique – impulse invariance method – Butterworth filter – chebyshev filter. 4th edition.ADC and DAC interfacing. 50 marks M.ti.analog. G. 2009.
1999. RTOS for image processing . Hermann K. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice.Embedded RTOS for voice over IP-RTOS for fault tolerant applications . "Real time systems-design principles for distributed embedded Applications".L. "Real time Systems".A.J.RTOS for control systems TEXT BOOK: 1. 2. Shin. Introduction to POSIX and OSEK standards UNIT V RTOS AND APPLICATION DOMAINS 10 hrs.A design oriented approach". Bailey.RTOS porting to a target .Pettrinet models .Design and implementation of processes-Communication between processes .Kang G.E. (EMBEDDED SYSTEMS) 7 REGULATIONS 2010 . UNIT III REAL TIME MODELS AND LANGUAGES 10 hrs. CM Krishna. Mc Graw Hill. 1st Edition. Prentice Hall International.Graph models . UNIVERSITY EXAM QUESTION PAPER PATTERN Max. each carrying 10 marks. UNIT IV REAL TIME KERNEL 10 hrs.Comparison and Study of RTOS .Polled loop systems . Elec. Principles . Buhr.Interrupt processing-Synchronization . "An introduction to real time operating systems". Basic Principles-system calls-Files-Processes . 30 marks Part B: 5 Questions from each of the five units of internal choice. Appl. 50 marks M.operating system structures. Springer.) L 3 T 1 P 0 Credits 4 Total Marks 100 UNIT I REVIEW OF OPERATING SYSTEMS 10 hrs. Event based – Process based. 2.. 3.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5004 REAL TIME OPERATING SYSTEM (Common to Embedded.RT scheduling . Charles Crowley "operating systems . UNIT II DISTRIBUTED OPERATING SYSTEMS Topology-Network Types-Communication-RPC-Client server model-Distributed file systems 10 hrs. 1st Edition.VxWorks and mCoS. 1999. 1st Edition. Tata Mc Graw Hill. 1997. Raymond J. "An introduction to real time systems" Prentice Hall International. REFERENCE BOOKS: 1. 1997.Control blocks-Memory requirements. Donald L Baily. 2009. R. D.RTOS tasks .A.
Jean J.control system and industrial automationbiomedical-data communication system-network information appliances. Pearson education.design and implementation of digital multimeter. E&C. 1999. Embedded.system integration.design with microprocesors development-ADC.system integration. 1999.IVR systems. (EMBEDDED SYSTEMS) 8 REGULATIONS 2010 . REFERENCE BOOKS: 1. “Computers as components”. “Embedded system design”.round robin with interrupt architecture. Morgan Kaufmann publishers.DAC interfacing LED/LCD interfacing.characteristics of embedded system. TEXT BOOK: 1.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5005 EMBEDDED SYSTEM DESIGN (Common to VLSI. Embedded system.trends in embedded system. CMP books. 50 marks M.CPU-memeory-I/O Devices.implementation of communication bridge. CMP books.structural and behavioral description smart cards.UART-IEEE 1394-IRDA-USB-PCI development tools.block schematic of a typical hardware architecture. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice.EPROM ERASER-signature validator.hardware and software partition. UNIT V OVERVIEW OF DESIGN TECHNOLOGIES 10 hrs. 2nd Edition. UNIT III HARDWARE ARCHITECTURE 10 hrs.system analysis and architecture design.categories of embedded system.GPS systems. Elec.challenges and design issues of embedded system.applications of embedded system. 2. “Specifications and design of embedded systems”. Narayan and gong.designing hardware and software components. 30 marks Part B: 5 Questions from each of the five units of internal choice. 3. Development of software architecture – simple round robin architecture.E. 2001. UNIT IV EMBEDDED SYSTEM PLATFORM AND DEVELOPMENT TOOLS 10 hrs.Labrosse. 2008. 2nd Edition.RTOS architecture. 1st Edition.accelerated design for video accelerator. Wayne wolf. Appl.requirements of embedded systems. Design methodologies and tools.16 bit and 32 bit processor-DSP processor. UNIVERSITY EXAM QUESTION PAPER PATTERN Max.) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION 10 hrs. “Embedded system building blocks”. Inter process communication.function queue scheduling architecture. Arnold berger. each carrying 10 marks. 2nd Edition. Case study of processor. UNIT II DEVELOPMENT OF SOFTWARE ARCHITECTURE 10 hrs. Hardware architecture.
30 marks Part B: 5 Questions from each of the five units of internal choice. Arithmetic. string. 20% . 2009. FILE I/O AND INSTRUMENT CONTROL 10 hrs. Jim Kring. Rudra Pratap. Raj kumar Bansal. UNIT IV INTRODUCTION TO LABVIEW 10 hrs. TEXT BOOK: 1. Ashok kumar Goel. matrix manipulations – Cell Array – Structure Array -Strings – function Script files . (80% . front panel. SWITCH CASE. Relational and logical operators .each carrying 10 marks. 2nd Edition. case structure. Matlab environment–types of files-constants and variables.Control statements IF. (EMBEDDED SYSTEMS) 9 REGULATIONS 2010 . Jeffrey Travis. State Space Modeling. 4th Edition. Formula node. block diagram. BREAK. Thomson learning. “Getting Started with MATLAB”.Programs) 50 marks M. Stephen J.Simulink-Simulink Modelling. 2. Data Import/Export. data acquisition in Labview.Simulating a Model. REFERENCE BOOKS: 1.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5006 PROGRAMMING IN MATLAB AND LABVIEW L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION TO MATLAB 10 hrs. Introduction to Virtual Instrumentation. 2009. 3rd Edition. expression node charts. file input output. Pearson Education. loops. arrays.Matrices and Vectors. Basic 2D plots – modifying line styles – markers and colors – grids – placing text on a plot – Various / Special Mat Lab 2D plot types – Semilogx – Semilogy – Log Log – Polar – Comet –Multiple Plots-Subplots. CONTINUE – FOR loop – While loop – Matlab Debugger – polynomials. creating sub VIs. UNIT II PROGRAMMING IN MATLAB 10 hrs. UNIT V STRUCTURES. UNIT III PLOTTING AND SIMULINK 10 hrs. 1999. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice.E. flat sequence.Theory. loading and saving VIs. “Matlab Programming for Engineers”. shift registers. instrument control in labview. GRAPHS. advantages. 1st edition.Input and Output statements – File input and output – Opening & Closing – Writing & Reading data from files. “Labview for Everyone: Graphical Programming Made Easy and Fun”.Chapmen. Manoj kumar Sharma. Oxford University press. UNIVERSITY EXAM QUESTION PAPER PATTERN Max.debugging techniques. Creating Sub-Systems. “Matlab and its applications in engineering”. 3. 2008. clusters and graphs. architecture of a Virtual Instrument. VIs.
Feiffer. “CANopen: Implementation Made Simple”. each carrying 10 marks. REFERENCE BOOKS: 1. Andrew Ayre and Christian Keyold “Embedded Networking with CAN and CAN open”. Research Studies Press. Controller Area Network – Underlying Technology CAN Overview – Selecting a CAN Controller – CAN development tools. Mohammad Farsi. Springer. (EMBEDDED SYSTEMS) 10 REGULATIONS 2010 . Konrad Etschberger. CAN open configuration – Evaluating system requirements choosing devices and tools – Configuring single devices – Overall network configuration – Network simulation – Network Commissioning – Advanced features and testing. 2001. Implementing CAN open Communication layout and requirements – Comparison of implementation methods – Micro CAN open – CAN open source code – Conformance test – Entire design life cycle. Implementation issues – Physical layer – Data types – Object dictionary – Communication object identifiers – Emerging objects – Node states. Embedded System Academy.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5007 EMBEDDED NETWORKING L 3 T 1 P 0 Credits 4 Total Marks 100 UNIT I 10 hrs.1997.E. chips and applications”. Glaf P. IXXAT Press. Manuel Bernardo Barbosa. protocols. UNIT II 10 hrs. UNIT III 10 hrs. UNIT IV 10 hrs. 1st edition. 2008. UNIVERSITY EXAM QUESTION PAPER PATTERN Max.1999. “Controller area network : basics. Embedded networking – code requirements – Communication requirements – Introduction to CAN open – CAN open standard – Object directory – Electronic Data Sheets & Device – Configuration files – Service Data Objectives – Network management CAN open messages – Device profile encoder. 30 marks Part B: 5 Questions from each of the five units of internal choice. 3. UNIT V 10 hrs. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice.1st edition. Wolfhard Lawrenz. TEXT BOOK: 1. 1st edition. 2. 50 marks M. “ CAN System Engineering: From Theory to Practical Applications”.
30 marks Part B: 5 Questions from each of the five units of internal choice. UNIT II ENCRYPTION – SYMMETRIC TECHNIQUES 10 hrs.Asymmetric techniques. 2007.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SCSX5031 CRYPTOGRAPHY AND NETWORK SECURITY (Common to VLSI. 2007. Wade Trappe and Lawrence C. TEXT BOOK 1. “Security in Computing”. Pearson Education. “Modern Cryptography – Theory and Practice”. “Cryptography Theory and Practice ”. Authentication Protocols Principles – Authentication protocols for Internet Security – SSH Remote logic protocol – Kerberos Protocol – SSL & TLS – Authentication frame for public key Cryptography – Directory Based Authentication framework – Non . 2006. REFERENCE BOOKS: 1. 50 marks M. Substitution Ciphers . Pearson Education. 4th Edition. UNIT V SECURITY PRACTICES 10 hrs.Directory Based Public-Key Authentication framework. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. each carrying 10 marks.Data Integrity techniques – Symmetric techniques . “Intrduction to Cryptography with Coding Theory” 2nd Edition. Chapman & Hall/CRC.E. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. Beginning with a simple communication game – wresting between safeguard and attack – Probability and Information Theory . 3rd Edition.2006.Algebraic foundations – Number theory. 1st Edition. (EMBEDDED SYSTEMS) 11 REGULATIONS 2010 .Transposition Ciphers . Pfleeger. Douglas R. UNIT III ENCRYPTION –ASYMMETRIC TECHNIQUES AND DATA INTEGRITY TECHNIQUES 10 hrs. Protecting Programs and Data – Information and the Law – Rights of Employees and Employers – Software Failures – Computer Crime – Privacy – Ethical Issues in Computer Security.Classical Ciphers – DES – AES – Confidentiality Modes of Operation – Key Channel Establishment for symmetric cryptosystems. Diffie-Hellman Key Exchange protocol – Discrete logarithm problem – RSA cryptosystems & cryptanalysis – ElGamal cryptosystem – Need for stronger Security Notions for Public key Cryptosystems – Combination of Asymmetric and Symmetric Cryptography – Key Channel Establishment for Public key Cryptosystems . 2. UNIT IV AUTHENTICATION 10 hrs. 3. Charles B. Shari Lawrence Pfleeger. Stinson. Washington. Pearson Education. Embedded) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION AND MATHEMATICAL FOUNDATION 10 hrs. Wenbo Mao.
Make LEDs blink 3. Mini projects using the above tools. Read input from switches 11.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX6501 EMBEDDED SYSTEMS LAB . Different types of Encryption and Decryption schemes 5.E. Display message in LCD display 8. DSP processor. Matlab & Labview. RTOS. Experiments using VHDL/Verilog. Read data from temperature sensor and display values in PC SECX6512 DESIGN PROJECT LAB L 0 T 0 P 4 Credits 2 Total Marks 100 1. Read data from temperature sensor and display values in PC 6. Set time in RTC and display on LCD Using PIC Microcontroller 9. Using PWM facility control a DC motor 14. Make LEDs blink 10.I L 0 T 0 P 4 Credits 2 Total Marks 100 LIST OF EXPERIMENTS Using 89S52 Microcontroller 1. (EMBEDDED SYSTEMS) 12 REGULATIONS 2010 . M. Display message in LCD 12. Simulate an elevator movement 7. 2. Simulate RTC and display in seven segment LEDs 13. Write a program for serial communication to communicate with PC 4. Read input from switches and display on LEDs 2. Rotate a stepper motor with different speeds 15.
Implement OS Real Time Multitasking by writing a multitasking program with the tasks a. 11. Write a Program for a. Write a Simple Assembly Program for a. b. Addition b. 9. Buzzer Interface. Write a Program for I2-C Device Interface a. 2. 4. 8-Bit Digital Output (LED Interface). Real Time Clock 7. Write a Program for Analog to Digital Conversion (On chip ADC) 6. b. M.E. 8-Bit Digital Inputs (Switch Interface). Subtraction b.II L 0 T 0 P 4 Credits 2 Total Marks 100 Programs Using ARM Processor 1. 3. Serial EEPROM b. Multiplication d. b. Interface RTC and Display on LCD First Line Continuously b. Implement OS Real Time Multitasking by Implementing the tasks. (EMBEDDED SYSTEMS) 13 REGULATIONS 2010 . Stepper Motor Interface Hands on Exercise Based on RTOS. (b) Write a Simple Program with Two Separate LED Blinking Tasks. c.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX6502 EMBEDDED SYSTEMS LAB . 4 × 4 Matrix Keypad Interface. Write a Program for character based LCD Interface. Interfacing with Temperature Sensor 8. Division. 10. (a) Study and Implement Multitasking. Write a Program for a. Study and Implement Priority Scheduling and OS TimeDelay Functions by writing 3 different UART Transmitting Tasks. Read the Key input and display on seven segment LED. Interface ADC and Display on LCD second line Continuously 12. 5. a. Relay Interface. Read the ADC Analog input and Plot the Corresponding signal on a LCD. Seven Segment LED Display Interface c.
Newton steepest descent method – widrow hoff LMS adaptive algorithm.filter bank implementation.direct digtal domain approach. Pearson Prentice Hall.edge crispening.constrained and unconstrained restoration. (EMBEDDED SYSTEMS) 14 Exam Duration: 3 hrs 30 marks 50 marks REGULATIONS 2010 .CCITT and JPEG standards.predictive techniques. Mc. UNIVERSITY EXAM QUESTION PAPER PATTERN Max.variable length coding.periodogram estimator.adaptive noise cancellation.sample auto correlation. Marks: 80 Part A: 6 Questions of 5 marks each – No choice. IIR. each carrying 10 marks.interpolation by an integer factor.pixel coding. “Statistical digtal signal processing and modeling”. FIR adaptive filter.image enhancement and restoration-Spatial domain method. Monson H. Pearson Prentice Hall.diagonalization of Circulant and Block Circu.adaptive channel equalization.fundamental coding theorem shannon’s coding. UNIT V IMAGE DATA COMPRESSION 10 hrs. 4. Huffman coding. 2nd Edition. M. UNIT III MULTI RATE SIGNAL PROCESSING 10 hrs.forward backward prediction. consistant estimator.continuous time model. 2008.image compression model.histogram processing.unbiased.decimation by an integer factor. filters-Signal analysis using Fourier Transform . Review of FIR. “Adaptive filter theory”.application to sub band coding. 3.Graw Hill.co variance estimator.single and multi stage realization-poly phase realization. NanoTech. 1998.elements of visual perception.structure of human eyeMonochrome vision model. UNIT IV IMAGE ENHANCEMENT AND RESTORATION 10 hrs. zonal and threshold coding. 2002. image compression standard.E.Hayes.AR. John Wiley Sons.least mean square error criterion. Anil K Jain.levinson recursion algorithm for solving toeplitz system of equations UNIT II ADAPTIVE FILTERS 10 hrs. “Fundamental of Digtal image processing”.adaptive echo cancellor.model based approach.transform coding.Welch estimation.RLS adaptive filter.sum decomposition theorem.lossy and loseless predictive coding. Part B: 5 Questions from each of the five units of internal choice. REFERENCE BOOKS: 1.Periodogram. 1989.ant Matrices-Algebraic Approach to restoration. Gonzalez R.correlation method. Mathematical description of change of sampling rate. Prentice Hall. “Digtal image processing”. bit plane coding. John G Proakis.interpolation.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5021 ADVANCED DIGITAL SIGNAL AND IMAGE PROCESSING (Common to VLSI.Bartlett spectrum estimation.homomorphic filtering – degradation model.parameter estimation using yule walker method..MA. Simon Haykin. Fundamentals of coding.C. Embedded) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I SPECTRUM ESTIMATION & PREDICTION 10 hrs.simplified IIR LMS adaptive filter.decimation.interpolation.spatial filtering.inverse filtering and wiener filter-Image morphology.ARMA signal modeling.Wiener filter-linear prediction. Elements of digital image processing systems. “Digtal signal processing”. 2.spectral factorization theorem. TEXT BOOK: 1. 2007.non parametric method.
2006. 3. UNIT II ANALOG DSP 10 hrs. display specification. LCD controller pins. architecture. architecture. Analog DSP “Blackfin” Processor – introduction. interface to LCD panel signal reset values. UNIT IV OPEN MULTIMEDIA APPLICATION PLATFORM 10 hrs. applications. features.and applications. 2006. Introduction to Processor and peripherals – keyboards – Multiplexed LED Displays –Character LCD modules – Time of Day Clock – Timer Manager – Discrete Inputs and Outputs – Fixed point Math – Analog Math. UNIT V CASE STUDY 10 hrs. UNIT III ARM PROCESSOR 10 hrs. Audio/video and VOIP application for multimedia application using OMAP TI-5012 – TI OMAP Applications Processor . TEXT BOOK: 1. Jean J Labrose. ARM reference manual from Texas Instruments. each carrying 10 marks. applications -instruction-set architecture and hardware micro architecture – ADSP 2100 – introduction. Introduction. Lookup palette. Technical documents from Texas Instruments Hall for OMAP TI – 5012. addressing modes. second edition. addressing modes. instruction set. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. 2. architecture. output FIFO. color dithering. CMP Books. Introduction.OMAP2420 and OMAP1710 – architecture. 30 marks Part B: 5 Questions from each of the five units of internal choice. architecture. OMAP reference manual from Texas Instruments.E. REFERENCE BOOKS: 1. “Embedded Systems Building Blocks”. applications – Palm One OS5-based device with ARM processor – ARM application processor – ARM720T and ARM920T.2005. features. 2006. 50 marks M. LCD controller operation.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5008 EMBEDDED PROCESSORS AND PERIPHERALS L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION 10 hrs. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. LCD controller registers. features. (EMBEDDED SYSTEMS) 15 REGULATIONS 2010 . applications – OMAP5910 –module overview. instruction set.
connectors and UNIT V EMC DESIGN OF PCB 10 hrs. Measurements and Technologies". REFERENCES BOOKS: 1. 2001. Embedded.Ott.Lightning – Standards of EMI. Society of EMC Engineers (India). DonWhite consultant incorporate. Wiley & sons. IEEE Press. Henry W. "Engineering EMC Principles. Elec. (EMBEDDED SYSTEMS) 16 REGULATIONS 2010 . UNIT III EMI SPECIFICATION/STANDARDS AND MEASUREMENTS 10 hrs. Kodali V.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5031 ELECTROMAGNETIC INTERFERENCE & COMPATIBILITY (Common to VLSI. UNIT II EMI Coupling 10 hrs. “Noise reduction Techniques in Electronics systems”. each carrying 10 marks. 3. 2.” Principles of Electromagnetic Compatibility”. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. EMI from apparatus and circuits: Introduction-Electromagnetic emission-Appliances-noise from relays and switches-nonlinearities in circuits-Passive inter modulation-Cross talk in transmission lines-Transmission in power supply lines-Electromagnetic interference. UNIT IV EMI CONTROL TECHNIQUE Shielding technique-Filter techniques-Grounding components-Isolation transformer-Transient suppressor. 5. Artech house. “Introduction to EMC”.Basics of EMI measurements-EMI measurement tools-TEM cell-measurement using TEM cell-Reverberating chamber-GTEM cell-Anechoic chamber-Open area test site-RF absorbers-conducted interference measurements-conducted EMI from equipments-Experimental setup for measuring conducted EMI-Measurement of DM interferences. Designing for EMC:Introduction-Different techniques involved in designing for EMC-EMC guide lines for PCB designs-EMC design guide line for audio and control circuit design-EMC guide lines for RF design-EMC guidelines for power supply design-Mother board designs and propagation delay performance models TEXT BOOK: 1. 2006. 2003. “Basics of Electro Magnetic Compatibility”. Units of specification-civilian standards and military standards. 3rd Edition. Appl..E. Johnwiley and sons. techniques-Bonding techniques-Cable 10 hrs. Vol 1-1985 Clayton R. Sathyamurthy S. Bernhard Keiser. New York.P.) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I EMI ENVIRONMENT 10 hrs. 30 marks Part B: 5 Questions from each of the five units of internal choice. 1986. 50 marks M. Introduction to EMI/EMC-Basics of electro Magnetic interference(EMI)Fundamentals of electromagnetic compatibility(EMC)-Radiation hazards Transients and other EMI sources. Paul. Handbook of EMI/EMC”. Transients. 1976. 4.. Electrostatics discharge (ESD) Tempest ..
Introduction to fuzzy set theory –– membership function .BAM – Structure – types – encoding and retrieving – Adaptive resonance theory – Introduction to optical neural network – Cognitron & Neocognitron UNIT III APPLICATION OF ANN – Traffic control – routing and scheduling –Articulation Controller . Introduction – Neuron Physiology – Specification of the brain – Eye neuron model .E. Back propagation training algorithm – Counter propagation network – structure & operation – training – applications of BPN & CPN -Statistical method – Boltzmann training – Cauchy training – Hop field network and Boltzmann machine – Travelling sales man problem . 1994. Elec) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I FUNDAMENTALS OF ANN 10 hrs. (EMBEDDED SYSTEMS) 17 REGULATIONS 2010 . 1991.Yagnanarayana. “Neural Networks”. 1992. “Neural Networks”. Simon Haykin.Neural Acceleration Chip ( NAC ) 10 hrs. 2006. Hand written and character recognition – Visual Image recognition –.Fuzzy logic controller – Fuzzification & defuzzification interface.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5084 FUZZY LOGIC AND NEURAL NETWORK (Common to VLSI.M. J. Appl. West.Zurada. each carrying 10 marks. Embedded.Theory. B. UNIVERSITY EXAM QUESTION PAPER PATTERN Max.Communication systems – call processing – Switching UNIT IV INTRODUCTION TO FUZZY LOGIC 10 hrs. Prentice Hall of India. 3. 20% . classical set Vs fuzzy set – properties of fuzzy set – fuzzy logic control principles – fuzzy relations – fuzzy rules – Defuzzification – Time dependent logic – Temporal Fuzzy logic ( TFC ) – Fuzzy Neural Network (FANN) . 30 marks Part B: 5 Questions from each of the five units of internal choice.Fundamentals of ANN – Biological neurons and their artificial models – Learning processes –different learning rules – types of activation functions – training of ANN – Perceptron model ( both single & multi layer ) – training algorithm – problems solving using learning rules and algorithms – Linear seperability limitation and its over comings UNIT II ANN ALGORITHM 10 hrs. Freeman & Skapura. TEXT BOOK: 1. Macmillan. Application of fuzzy logic to washing machine – Vaccum cleaner – Water level controller – temperature controller Adaptive fuzzy systems – Fuzzy filters – Sub band coding – Adaptive fuzzy frequency hoping. “Artificial Neural Networks”. Wesley. UNIT V APPLICATION OF FUZZY LOGIC 10 hrs.basic concepts of fuzzy sets – Operations on fuzzy sets and relations. (80% . Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. 2. REFERENCE BOOKS: 1.Problems) 50 marks M. Addison. “Introduction to Artificial Neural Systems”.
UNIT III CONNECTION ESTABLISHMENT PROCEDURE 10 hrs. Prentice Hall.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5085 BLUETOOTH TECHNOLOGY (Common to VLSI. Bluetooth Radio: Type of Antenna. cable replacement protocol. Introduction to Bluetooth: Specification. 2004. Introduction to Wireless technologies: WAP services. 2.Molisch. UNIVERSITY EXAM QUESTION PAPER PATTERN Max.SDA. Antenna Parameters. devices roles and states. UNIT IV HARDWARE Hardware: Bluetooth implementation. 50 marks M.obex package:interfaces. UNIT II BLUETOOTH RADIO AND NETWORKING 10 hrs. “Adaptive Antennas for wireless Communication”. Connection establishment procedure. REFERENCE BOOKS: 1. TFM. profile and usage model: Generic access profile (GAP).Pfleeger. “Wideband wireless Digital Communication”. notable aspects of connection establishment. “Security in computing”. J2ME architecture. Andreas F. (EMBEDDED SYSTEMS) 18 REGULATIONS 2010 . Wireless LANs. TEXT BOOK: 1.Reddi. Asynchronous and synchronous communication.Prabhu and A.Tsoulous. “Bluetooth Technology”. packet format. George. exceptions. logical link control Adaptation protocol.E.R. Baseband overview. Bluetooth Security. Secondary Bluetooth profile. Mode of connection.P. 30 marks Part B: 5 Questions from each of the five units of internal choice.Javax. Security architecture. Bluetooth services overview of IRDA. Protocol implementation: link manager protocol. Home RF. IEEE Press. Host control interface. Frequency hoping Bluetooth Networking: Wireless networking. 2001. Embedded) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION 10 hrs. serial and parallel Communication. Security level of services. classes. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. protocol interaction with layers. Programming with Java: Java Programming. Spread spectrum technology. JINI.serial profile.V. adhoc network. each carrying 10 marks. 2003. UNIT V APPLICATIONS 10 hrs. Wireless network types.Bluetooth package interface. Buffers. 3.S. 2001. Transmission 10 hrs. C. Prentice Hall PTR. Prentice Hall of India. EDM. core protocols. Javax. scatter net. Charels P. classes.
clock feed . Tata Mc Graw Hill. “Continuous-Time Sigma Delta Modulations for A/D Conversion”.through . UNIT IV DATA CONVERTERS 10 hrs. Behzad Razavi. Kluwer. 2003.Switched Capacitor amplifiers Switched Capacitor Integrators . UNIT V PHASE LOCKED LOOPS 10 hrs.Two stage open loop comparators . Allen. Breems.Switched Capacitor filters. (EMBEDDED SYSTEMS) 19 REGULATIONS 2010 .Nyquist rate converters – Over sampling converters .2004. “Analysis and Design of Analog Integrated Circuits”.Pipelined/parallel converters .offset cancellation .Design of PLL and Frequency Synthesizers –PLL with voltage driven oscillator – PLL with current driven oscillator – ETPLL – PLL synthesizer oscillator by MC14046B. “Analog Circuit Design”. Design & Verification – Applications Challenges .Analog CMOS circuits . “Design of Analog CMOS integrated circuit”.Bandgap References.High speed ADC design. Jacob Baker. “CMOS Analog Circuit Design”.2002. 50 marks M. 2. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice.Discrete time comparators . Opamps . Gray & Meyer. 2.High-speed comparators. Wiley. 2004. each carrying 10 marks. Switched Capacitor (SC) Introduction . 2005. “CMOS Mixed-Signal Circuit Design”. TEXT BOOKS: 1.Current Mirrors Current and Voltage References . Tata Mc Graw Hill. UNIT III SWITCHED CAPACITOR CIRCUITS 10 hrs. “Design of Analog CMOS Integrated Circuit”. REFERENCE BOOKS: 1.E. UNIT II CMOS AMPLIFIERS 10 hrs. Oxford. Michelle Steyaert. Introduction . 3. Introduction . 2004. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. 2004. Behzad Razavi. 5.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5009 MIXED SIGNAL EMBEDDED SYSTEMS L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION TO ANALOG AND MIXED SIGNAL CIRCUITS 10 hrs. 30 marks Part B: 5 Questions from each of the five units of internal choice.Kluwer.Market Perspective . Wiley. High speed DAC design and Mixed signal design for radar application . 4.Frequency Synthesizers .High Performance CMOS amplifiers – Comparators – Characterization .ADC and DAC modules used for LIGO.
Taxonomy of compression techniques – Overview of source coding. Audio compression techniques .SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5010 DATA COMPRESSION TECHNIQUES L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION 10 hrs.. “Introduction to Data Compression”. Khalid Sayood. DVI technology – PLV performance – DVI real time compression. Ze-Nian Li. Mark S. each carrying 10 marks. Huifang Sun. 2003.JBIG.ì.Design of Filter banks – Wavelet based compression . Predictive techniques – DM. 2. Algorithms & Standards”. Special features of Multimedia – Graphics and Image Data Representations –Fundamental Concepts in Video and Digital Audio – Storage requirements for multimedia applications -Need for Compression . 2004. speech compression techniques – Formant and CELP Vocoders. CRC press. Springer Verlag New York Inc.E. 2nd Edition. REFERENCE BOOKS: 1.Law companding. Packet Video. Compaction techniques – Huffmann coding. 30 marks Part B: 5 Questions from each of the five units of internal choice. David Salomon.Fundamentals. UNIT V VIDEO COMPRESSION 10 hrs. UNIT IV IMAGE COMPRESSION 10 hrs.261 Standard.Implementation using filters – EZW.Shi. Arithmatic coding. PCM. scalar and vector quantization theory – Evaluation techniques – Error analysis and methodologies UNIT II TEXT COMPRESSION 10 hrs. Frequency domain and filtering – Basic sub-band coding – Application to speech coding – G. “Image and Video Compression for Multimedia Engineering .MPEG – 1 and 2– MPEG Video Coding II MPEG – 4 and 7 – Motion estimation and compensation techniques – H.Law and A.722 – Application to audio coding – MPEG audio. DPCM: Optimal Predictors and Optimal Quantization– Contour based compression – Transform Coding – JPEG Standard – Sub-band coding algorithms . (EMBEDDED SYSTEMS) 20 REGULATIONS 2010 . Mc Graw Hill. 2. SPIHT coders – JPEG 2000 standards . 2000. “Fundamentals of Multimedia”. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. 1st Edition. 3. 2003. Yun Q. Morgan Kauffman Harcourt India.Drew. Shannon-Fano coding. JBIG2 standards. Video compression techniques and standards – MPEG Video Coding I . Prentice Hall International. 2nd Edition. 2001. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. TEXT BOOK: 1. Peter Symes. 50 marks M. source models. Dictionary techniques. Adaptive Huffmann Coding. “Digital Video Compression”. 1st Edition. “Data Compression –The Complete Reference”. UNIT III AUDIO COMPRESSION 10 hrs. LZW family algorithms. progressive encoding for audio – Silence compression.
E. John Wiley & sons. Steve Heath. 2. counters and watch dog timers – UART – Pulse width modulator – LCD controllers – Key pad controllers – Stepper motor controllers – A/D converters – Real time clock. REFERENCES BOOKS: 1. Automation synthesis – Hardware software co-simulation – IP cores – Design Process Model. 2nd Edition. Custom single purpose processors: Hardware – Combination Sequence – Processor design – RT level design – optimising software: Basic Architecture – Operation – Programmers view – Development Environment – ASIP – Processor Design – Peripherals – Timers. Task and Task states – Task and data – Semaphore and shared data operating system services – Message queues timing functions – Events – Memory management – Interrupt routines in an RTOS environment – Basic design using RTOS. 2001. (EMBEDDED SYSTEMS) 21 REGULATIONS 2010 . 2004. 30 marks Part B: 5 Questions from each of the five units of internal choice. Modes of operation – Finite state machines – Models – HCFSL and state charts language – state machine models – Concurrent process model – Concurrent process – Communication among process –Synchronization among process – Implementation – Data Flow model.Simon “An Embedded Software Primer”. Design technology. SOFTWARE AND PERIPHERALS 10 hrs. UNIT V CONCURRENT PROCESS MODELS AND HARDWARE SOFTWARE CO-DESIGN 10 hrs. 2002. David. TEXT BOOK: 1. Memory: Memory write ability and storage performance – Memory types – composing memory – Advance RAM interfacing communication basic – Microprocessor interfacing I/O addressing – Interrupts – Direct memory access – Arbitration multilevel bus architecture – Serial protocol – Parallel protocols – Wireless protocols – Digital camera example. UNIT II REAL TIME OPERATING SYSTEM 10 hrs. Terminology – Gates – Timing diagram – Memory – Microprocessor buses – Direct memory access – Interrupts – Built interrupts – Interrupts basis – Shared data problems – Interrupt latency . Newnes. “Embedded System Design”. each carrying 10 marks.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5011 ADVANCED EMBEDDED SYSTEMS L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION AND REVIEW OF EMBEDDED HARDWARE 10 hrs. UNIT IV MEMORY AND INTERFACING 10 hrs. 50 marks M. UNIT III EMBEDDED HARDWARE. “Embedded System Design”. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. E.Embedded system evolution trends – Round-Robin – Round Robin with interrupt function – Rescheduling architecture – algorithm. Pearson Education. Frank Vahid and Tony Gwargie.
node level software platforms.15. localization and identity management. UNIT II ADDRESSING AND SYNCHRONISATION 10 hrs. Power Management: per node. trace routing data centric. sender-receiver and receiver-receiver synchronization. 802.. Applications. Data Gathering: Tree construction algorithms and analysis . triangulation. Feng Zhaoand Leonidas J Guibas. scheduling and coverage issues.4 standard. UNIT IV ROUTING TECHNIQUES 10 hrs. Tiny OS operating system. role of energy in routing decisions. programming beyond individual nodes. Sivalingam.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5079 WIRELESS SENSOR NETWORKS (Common to CSE. Sensor node hardware. anchoring. error analysis. multi-hop localization and error analysis. “Wireless Sensor Networks” Morgan Kaufmann Publishers and imprint of Elsevier. energy efficient routing Querying: Data collection and processing. 30 marks Part B: 5 Questions from each of the five units of internal choice. Security: Privacy issues .E. Walking GPS. John Wiley and Sons. publish-subscribe topologies. Appl. location-based. contention-based protocols. system-wide. energy management. collaborative information processing and group connectivity. 2nd Edition. range free solutions. Distributed Computation: Detection.Asymptotic capacity. Node Localization: absolute and relative localization. (EMBEDDED SYSTEMS) 22 REGULATIONS 2010 . Taieb F.Attacks and counter measures. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. 2. target tracking. Single node architecture: hardware and software components of a sensor node. Naming and addressing: Addressing services. scheduling sleep cycles. geographic localization. Embedded) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I SENSOR NETWORK ARCHITECTURE Concept of sensor network: Introduction. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice.Energy-efficient distributed algorithms UNIT V SENSOR NETWORK PLATFORMS AND TOOLS 10 hrs. 50 marks M. 2005. sentry services. Andreas Willig. data relaying strategies. schedule-based protocols. Routing: Agent-based routing. Clock Synchronization: clustering for synchronization. “Wireless Sensor Networks”. random walk. C.Lifetime optimization formulations. self configuration and topology control. programming challenges. estimation and classification problems . Springer. “Protocols and Architectures for Wireless Sensor Networks”. aggregation. nesC language. Elec. each carrying 10 marks. 2004. sensors 10 hrs. Deployment & Configuration: Sensor deployment. 2004. node level simulators. S. Wireless Sensor Network architecture: typical network architectures. hierarchical.Storage and retrieval. REFERENCES: 1. MAC layer strategies: MAC layer protocols. 3. Krishna M. sensing coverage UNIT III LOCALIZATION 10 hrs. Znati. Holger Karl. Raghavendra.
each carrying 10 marks. 2003. Labrosse. (EMBEDDED SYSTEMS) 23 REGULATIONS 2010 .SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5012 EMBEDDED COMMUNICATION SOFTWARE DESIGN L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I 10 hrs. 30 marks Part B: 5 Questions from each of the five units of internal choice. 2009 2.T. Shuvra S. TEXT BOOK: 1. Colin Walls. 50 marks M. Bhattacharyya. Software Partitioning – Limitation of strict Layering – Tasks & Modules – Modules and Task Decomposition – Layer2 Switch – Layer3 Switch / Routers – Protocol Implementation – Management Types – Debugging Protocols. CRC Press. “Embedded multiprocessors”. Sundararajan Sriram. Unit V 10 hrs.Test Tools. Robert Oshana. Jean J. Keith Curtis. 2nd Edition. UNIT II 10 hrs. Unit III 10 hrs. OSI Reference Model – Communication Devices – Communication Echo System– Design Consideration – Host Based Communication – Embedded Communication System – OS Vs RTOS. “Designing Embedded Communication Software” CMP Books.E. 1st Edition. Tables & other Data Structures – Partitioning of Structures and Tables – Implementation – Speeding Up access – Table Resizing – Table access routines – Buffer and Timer Management – Third Party Protocol Libraries. Multi Board Communication Software Design – Multi Board Architecture – Single control Card and Multiple line Card Architecture – Interface for Multi Board software – Failures and Fault – Tolerance in Multi Board Systems – Hardware independent development – Using a COTS Board – Development Environment . Tammy Noergaard. Unit IV 10 hrs.” Embedded Software”. 2007. Sridhar. Newnes. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. Management Software – Device Management – Management Schemes – Router Management – Management of Sub System Architecture – Device to manage configuration – System Start up and configuration. REFERENCE BOOKS: 1.
Marks: 80 Exam Duration: 3 hrs Part A : 6 Questions of 5 marks each – No Choice.S. 1983. ‘Industrial Robots. 50 marks M.manipulators . John Wiley and sons. R. E&C. C.P. (EMBEDDED SYSTEMS) 24 REGULATIONS 2010 . 3. joint velocities . 1986. Wesley E Snyder R.Euler formulation. Elec. 1986.. Fu. 1968 (II printing)..SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SICX5015 ADVANCED ROBOTICS AND AUTOMATION (Common to Appl.internal and external sensors . 30 marks Part B : 5 Questions from each of the five units of Internal choice.C.Euler angle representation homogeneous transformation . UNIT III ROBOT ARM DYNAMICS 10 hrs.Denavit Hattenberg representation and various arm configurations. “Robot technology” Vol. “Robot analysis and Control”. Mc Graw Hill. Prentice Hall International Edition. Tata Mc Graw Hill. “Robotics” (Control. General Consideration in robot material handling transfer applications – Machine loading and unloading. Groover M. and Lee. Computer Interfacing and Control’. K.potential energy and motion equations . Vision and Intelligence). each carrying 10 marks. Assembly and robotic assembly automation – Parts presentation methods – assembly operation – Compliance and the Remote Center Compliance(RCC) device – Assembly system Configurations – Adaptable.G.control systems .composite rotation matrices .robot programming languages and applications .Gonazlez. UNIT IV ROBOT APPLICATONS Material Transfer & Machine Loading / Unloading 10 hrs. Prentice Hall Inc. 4. 1988.drive systems . UNIVERSITY EXAM QUESTION PAPER PATTERN Max. Direct and Inverse Kinematics .rotation matrices .generalized D’Alembert equations of motion. Sensing.S.end effectors .II (Modelling and control). UNIT V ASSEMBLY AND INSPECTION 10 hrs. Embedded) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION 10 hrs.E.Introduction to robotic vision. Processing Operations Spot welding – Continuous arc welding .kinetic energy . Asada and Slotine. Geometric configuration of robots . Philippe Coiffet.Mitchell Weiss “Industrial Robotics Technology Programming and Applications”. REFFERENCE BOOKS: 1. 2. UNIT II ROBOT ARM KINEMATICS 10 hrs. 5.spray coating – other processing operations using robots. Programmable assembly system – Designing for robotic assembly – Inspection automation. Lagrange .
Specifications of IIR filters. FIR chips.. Shared memory architecture with Bit – serial PEs. Frequency response. 3rd Edition. MOS logic. Oppenheim A. FIR filter structures. DFT-The Discrete Fourier Transform. DSP systems. Standard digital signal processors. Shared memory architectures. Multirate filters. Sampling of analog signals. 2nd Edition. Discrete cosine transforms. UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES 10 hrs. 3. 30 marks Part B: 5 Questions from each of the five units of internal choice. Barrie W. Systolic and Wave front arrays. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. 2009. Signal flow graphs. Jervis. New York. Filter structures. Interpolation with an integer factor L. Selection of sample frequency. Image coding. DSP system design. “Discrete-time Signal Processing” Pearson education. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. Reducing the memory size. “VLSI digital Signal Processing Systems design and Implementation”. FFT-The Fast Fourier Transform Algorithm. (EMBEDDED SYSTEMS) 25 REGULATIONS 2010 . Coefficient sensitivity. Round-off noise. FIR filters. Mapping of analog filter structures.E. each carrying 10 marks. 2nd Edition. Improved shift-accumulator. Power. “DSP Integrated Circuits”. Emmanuel C.Parhi. MOS transistors. Basic shift accumulator.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5013 DSP INTEGRATED CIRCUITS (Common to Appl. Ideal DSP architectures. Layout of VLSI circuits. 50 marks M. Measuring round-off noise. Pearson Edition. UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS 10 hrs. Scaling of signal levels. Ifeachor. John Wiley & Sons. 2. Finite word length effects -Parasitic oscillations. Bit-parallel and Bit-Serial arithmetic. Multirate systems. DCT processor and Interpolator as case studies. Embedded) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I DSP INTEGRATED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES 10 hrs. Sensitivity and noise. Residue Number System.V. Implementation based on complex PEs. Digital signal processing. Adaptive DSP algorithms. Application specific IC’s for DSP. Lars Wanhammer. Mapping of analog transfer functions. Transfer functions. IIR filters. Multiprocessors and multicomputers. Keshab K. REFERENCE BOOKS: 1. Mapping of DSP algorithms onto hardware. 2009. Standard DSP architecture. Redundant Number system. Elec. Sampling rate change with a ratio L/M. “ Digital signal processing – A practical approach”. FFT processor. Academic press. Conventional number system. Trends in CMOS technologies. 1999. TEXT BOOK: 1. DSP system architectures. 1999. UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN 10 hrs. VLSI process technologies. UNIT II DIGITAL SIGNAL PROCESSING 10 hrs. Signal-processing systems. Complex multipliers. Integrated circuit design.
Leon Garcia. Prentice Hall. IS-41 Network Signaling: Signaling System No. WAP: WAP model – WAP Gateway – WAP Protocols – WAP UAProf and Caching. Radio Link Transfer: Link transfer types – Hard Handoff – Soft Handoff. “Principles of Wireless Networks”. “Communication Networks”.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5086 WIRELESS AND MOBILE COMMUNICATIONS L 3 T 0 P 0 Credits 3 Total Marks 100 Unit I 10 hrs. William Stallings. Unit IV 10 hrs. 1st Edition. “Wireless and Mobile Network Architectures”. Tata Mc Graw Hill.Prasanth Krishnamurthy. GSM System – GSM Architecture – Location tracking and Call Setup – Security – Data services – GSM Network Signaling GSM Mobility Management: GSM Location Update – Mobility Databases – VLR Identification Algorithm – VLR Overflow Control. UNIT II 10 hrs. 2000. 3G Mobile Services: W-CDMA and CDMA 2000 – Improvement on Core Network – Quality of Service – Wireless Operating System – 3G Systems Wireless Local Loop: Architecture – WLL Technologies – WLL OAM Functions. (EMBEDDED SYSTEMS) 26 REGULATIONS 2010 . 3. Wiley. Widjaja. TEXT BOOK: 1. PACS Network Signaling: Network Elements – Network Interfaces – AIN / ISDN Internetworking – Registration – Call Origination – Call Termination – Intersystem Handoff – Feature Interactions. REFERENCE BOOKS: 1. 30 marks Part B: 5 Questions from each of the five units of internal choice. New Delhi. Kaveth Pahlavan. 50 marks M. UNIT III 10 hrs. each carrying 10 marks.E. 2000. “Wireless Communications and Networks”. Pearson Education Asia. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. GPRS: GPRS Functional Groups – GPRS Architecture – GPRS Network Nodes – GPRS Interfaces – GPRS Procedures – GPRS Billing. Yi-Bing Lin.7 – Interconnection and Message Routing – Mobility Management using TCAP – PCN / PSTN Call control using ISUP – Intersystem Handoff. Unit V 10 hrs. Introduction: PCS Architecture – Cellular Telephony – Cordless telephony Mobility Management: Handoff – Roaming Management – Roaming Management under SS7– Roaming Management for CT2 Handoff Management: Detection and Assignment: Handoff Detection – Strategies for Handoff Detection –Channel Assignment. K. 2002. 2002 2. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. Imrich Chlamtac.
Ball S. digital values . 2nd Edition. “Real Time Systems – Design for distributed Embedded Applications”. UNIT IV ASYNCHRONOUS SERIAL COMMUNICATION 10 hrs. “Embedded Systems Building Blocks: Complete and Ready-To-Use Modules in C”. Multiple closure problems – Basic outputs with PPI – Controlling motors – Bi-directional control of motors – H bridge – Telephonic systems – Stepper control – Inventory control systems. REFERENCE BOOKS: 1. “Embedded microprocessor Systems – Real World Design”.Port offsets .Automatic.Capturing analog information in the timer interrupt service routine . UNIVERSITY EXAM QUESTION PAPER PATTERN Max. “Fundamentals of Embedded Software where C and Assembly meet”..Interrupt service routines – IRQ . 3. Herma K. 1st Edition. 1996. Marks: 80 Exam Duration: 3 hrs Part A: 6 Questions of 5 marks each – No choice. UNIT II INPUT-OUTPUT DEVICES 10 hrs.E. Prentice Hall. 2nd Edition. 2.Recording and playing back voice . Keyboard basics – Keyboard scanning algorithm – Multiplexed LED displays – Character LCD modules – LCD module display – Configuration – Time-of-day clock – Timer manager .R..Triangle waves analog vs. 50 marks M. Controlling the hardware with software – Data lines – Address lines .ISR .ADC0809 – Auto port detect .SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5014 EMBEDDED CONTROL SYSTEMS (Common to Appl.Elec. Power. TEXT BOOK: 1.Interrupt-driven pulse width modulation. R 2R ladder . UNIT III D/A AND A/D CONVERSION 10 hrs. Daniel W. 2002.Interrupts . Lewis. Labrosse. 2009. Kluwer Academic. 1997. Prentice Hall of India.Interrupt vector or dispatch table multiple-point . 30 marks Part B: 5 Questions from each of the five units of internal choice. Embedded) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I INTRODUCTION 10 hrs. 2nd Edition. (EMBEDDED SYSTEMS) 27 REGULATIONS 2010 .Ports – Schematic representation – Bit masking – Programmable peripheral interface – Switch input detection – 74 LS 244. Jean J. Asynchronous serial communication – RS-232 – RS-485 – Sending and receiving data – Serial ports on PC – Low-level PC serial I/O module . CMP. each carrying 10 marks. UNIT V CASE STUDIES: EMBEDDED C PROGRAMMING 10 hrs.Resistor network analysis . multiple channel analog to digital data acquisition.Buffered serial I/O.
each carrying 10 marks. UNIT III SUBPROGRAMS AND PACKAGES 10 hrs. Part B: 5 Questions from each of the five units of internal choice. UNIT V ADTS AND FILES 10 hrs. REFERENCE BOOKS: 1.Case Study: Queuing Networks. San Francisco. UNIT II COMPOSITE DATA TYPES AND BASIC MODELING CONSTRUCTS 10 hrs.Aliases for data objects – Aliases for Non-Data Items. Zainalabedin Navabi. Marks: 80 Part A: 6 Questions of 5 marks each – No choice. James M.SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING SECX5069 ANALYSIS AND MODELING OF DIGITAL SYSTEM USING VHDL (Common to Power. COMPONENTS AND CONFIGURATIONS 10 hrs. TEXT BOOK: 1. UNIT IV SIGNALS. 2nd Edition.E. Case Study: A pipelined Multiplier Accumulator. Arrays – Unconstrained Array types – Array Operations and Referencing – Records – Basic Modeling Constructs – Entity Declarations – Architecture Bodies – Behavioral Descriptions – Structural Descriptions – Design Processing. Kluwer Academic Publishers. Second Edition. Morgan Kaufmann Publishers. M. 1999. 1998. 2nd Edition. Fundamental Concepts – Modeling Digital Systems – Domains and Levels of Modeling – Modeling Languages – VHDL Modeling concepts – Scalar Data Types and Operations – Constants and variables – Scalar Types – Type Classification – Attributes and Scalar types – Expressions and operators – Sequential Statements – If statements – Case statements – Null Statements – Loop statements – Assertion and Report statements.Ashenden. “Verilog Quick start”. 2001. “The Designer’s Guide to VHDL”.Lee. (EMBEDDED SYSTEMS) 28 Exam Duration: 3 hrs 30 marks 50 marks REGULATIONS 2010 . Mc Graw Hill International Editions. Procedures – Procedure Parameters – Concurrent Procedure Call Statements – functions – Overloading – Visibility of Declarations – Packages and Use Clauses – Package declarations – Package bodies – Use Clauses – The predefined – Aliases . Case Study: A Bit-Vector Arithmetic Package. 2. Embedded) L 3 T 0 P 0 Credits 3 Total Marks 100 UNIT I VHDL FUNDAMENTALS 10 hrs. “VHDL Analysis and Modeling of Digital Systems”. UNIVERSITY EXAM QUESTION PAPER PATTERN Max. Case Study: The DLX Computer System. Access Types – Linked Data structures – Abstract Data Types using Packages – Files and Input/Output – Files – The Package Textio – Verilog. Peter J. Basic Resolved signals – IEEE Std_Logic_1164 Resolved subtypes – Resolved signal parameters – Generic Constants – Parameterizing behavior – Parameterizing structure – Components and Configurations – Components – Configuring component Instances – Configuration Specification – Generate Statements – generating iterative structure – Conditionally generating structures – Configuration of generate Statements.
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