The unprecedented growth of the computer and the Information technology industry is demanding Very Large Scale Integrated (VLSI) circuits with increasing functionality and performance at minimum cost and power dissipation. VLSI circuits are being aggressively scaled to meet this Demand, which in turn has some serious problems for the semiconductor industry.

Additionally heterogeneous integration of different technologies in one single chip (SoC) is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable.

3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip (SoC). The multi-layer chip industry opens up a whole new world of design. With the Introduction of 3-D ICs, the world of chips may never look the same again.

There is a saying in real estate; when land get expensive, multi-storied buildings are the alternative solution. We have a similar situation in the chip industry. For the past thirty years, chip designers have considered whether building integrated circuits multiple layers might create cheaper, more powerful chips.

Performance of deep-sub micrometer very large scale integrated (VLSI) circuits is being increasingly dominated by interconnects due to increasing wire pitch and increasing die size. Additionally, heterogeneous integration of

 Capacitors and resistors have lower maximum values. each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs). The three dimensional (3-D) chip design strategy exploits the vertical dimension to alleviate inter connect related problems and to facilitate heterogeneous integration of technologies to realize system on a chip (SoC) design.  Limited power dissipation.  Poor high frequency performance. Limitations of 2D ICs  Functions at fairly low voltage. In the 3-Ddesign architecture. and each block is placed on a separate layer of Si that is stacked on top of each other. By simply dividing a planar chip into separate blocks.  Difficult to achieve low noise and high voltage operation. significant improvement in performance and reduction in wire-limited chip area can be achieved. . an entire chip is divided into a number of blocks.different technologies on one single chip is becoming increasingly desirable. for which planar (2-D) ICs may not be suitable.

A significant fraction of the total power consumption can be due to the wiring network used for clock distribution. which is usually realized using long global wires. This is due to the ever growing demand for functionality and high performance. Small feature sizes have dramatically improved device performance. As interconnect scaling continues. Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing inter connect delays. smaller wire pitch. RC delay is . increasing drive for the integration of disparate signals (digital. requiring more and more transistors to be closely packed and connected. resulting in a significant increase in signal propagation (RC) delay. for which existing planner (2-D) IC design may not be suitable. which causes increased complexity of chip design. The impact of this miniaturization on the performance of interconnect wire. and so on) is introducing various SoC design concepts. RF) and technologies (SOI. and longer line to traverse larger chips have increase the resistance and capacitance of these lines. however.MOTIVATION FOR 3-D ICs The unprecedented growth of the computer and the information technology industry is demanding Very Large Scale Integrated (VLSI) circuits with increasing functionality and performance at minimum cost and power dissipation. SiGe. GaAs. chip size is continuously increasing despite reductions in feature size made possible by advances in IC technology such as lithography and etching. Smaller wire cross sections. has been less positive. INTERCONNECT LIMITED VLSI PERFORMANCE In single Si layer (2-D) ICs. analog. Furthermore.

analog. which comprise about 10% of total wiring in current architectures. Therefore.increasingly becoming the dominant factor determining the performance of advanced IC’s. Also. Further reduction in interconnect delay is not possible. This will result in an increase in complexity. including such diverse combinations as embedded DRAM. PHYSICAL LIMITATIONS OF Cu INTERCONNECTS At 250 nm technology node. RF. reliability and cost. it is apparent that material limitations will ultimately limit the performance improvement as technology scales. SYSTEM – ON – A – CHIP DESIGN System – on – a –chip (SoC) is a broad concept that refers to the integration of nearly all aspects of a system design on a single chip. which in turn will severely limit the chip performance.).below 130nm technology node. This problem is especially acute for global interconnects. FPGAs. programmable platforms (software. However . etc. Flash. . substantial interconnect delays would result in spite of introducing these new materials. high – performance and low-power logic. These chips are often mixed-signal and/or mixed-technology designs. Cu with low-k dielectric was introduced to alleviate the adverse effect of increasing interconnect delay. the problem of long lossy lines cannot be fixed by simply widening the metal lines and by using thicker interlayer dielectric. since this will lead to an increase in the number of metal layers.

There are several challenges to effective SoC designs: 1. automated drug delivery. aircraft/automobile control and safety. 2. several high performance SoC designs involve very high I/O pin counts . and non invasive internal scanning and diagnosis. medical applications including remote surgery. These designs form the basis for numerous novel electronic applications in the near future. fully automated industrial control systems. 4. 3. The noise generated by the interference between different embedded circuit blocks containing digital and analog circuits becomes a challenging problem. and passive components in SoC applications introduces significant complexity in materials and process integration. logic. Although SoC designs typically reduce the number of I/O pins compared to a system assembled on a printed circuit board(PCB). These wires can lead to unacceptable signal transmission delays and increase the power consumption by increasing the total capacitance that needs to be driven by the gates. and home security and entertainment systems. chemical and biological hazard detection.SoC designs are often driven by the ever-growing demand for increased system functionality and compactness at minimum cost. to name a few. and time to market. Integration of disparate technologies such as embedded DRAM. power consumption. which can increase the cost per chip . in areas such as wired and wireless multimedia communications including high speed internet applications. Large scale integration of functionalities and disparate technologies on a single chip dramatically increases the chip area. which necessitates the use of numerous long global wires.

3D ARCHITECTURE Fig: Architecture of 3D IC Three-dimensional integration to create multilayer Si ICs is a concept that can significantly improve interconnect performance . Additionally 3D ICs can be very effective large scale on chip integration of different systems. Integration of mixed technologies on a single die requires novel design methodologies and tools .5. and reduce chip area and power dissipation. and entire (2D) chips is divided into a number of blocks is placed on separate layer of Si that are stacked on top of each other.with design productivity being a key requirement.increase transistor packing density. . In 3D design architecture.

Heterogeneous 3D IC: Fig: Heterogeneous 3D IC A 3D chip is compromised of 2 or more layers of semiconductor devices. logic gates on a critical path can be placed very close to each other using multiple active layers. . bonded and interconnected to form a Monolithic circuit. ADVANTAGES OF 3D ARCHITECTURE The 3D architecture offers extra flexibility in system design. For instance. placement and routing.Each Si layer in the 3D structure can have multiple layer of inter connects (VILICs) and common global interconnects. These layers are thinned. This would result in a significant reduction in RC delay and can greatly enhance the performance of logical circuits.

mixed-technology assimilation could be made less complex and more cost effective by fabricating such technologies on separate substrates followed by physical bonding. OVERVIEW OF 3-D IC TECHNOLOGY Beam Re crystallization : A very popular method of fabricating a second active layer (Si) on top of an existing substrate (oxidized Si wafer) is to deposit poly silicon and fabricate thin film transistors (TFT). an intense laser or electron beam is used to induce re crystallization of the poly silicon film to reduce or even eliminate most of the grain boundaries.  Additionally the digital and analog components in the mixed-signal systems can be placed on different Si layers thereby achieving better noise performance due to lower electromagnetic interference between such circuits blocks. To enhance the performance of such transistors.  The 3D integration can reduce the wiring .  From an integration point of view.thereby reducing the capacitance. The 3D chip design technology can be exploited to build SoCs by placing circuits with different voltage and performance requirements in different layers. . power dissipation and chip area and therefore improve chip performance.

Disadvantage 1. This technique. may not be very practical for 3-D devices because of the high temperature involved during melting of the poly silicon. Difficulty in controlling the grain size variations. however. MOS on transistors fabricated on poly silicon exhibit very low surface mobility values [of the order of 10 cm/Vs]. . 2. 2.Advantage 1. MOS transistors fabricated on poly silicon have high threshold voltages (several volts) due to the high density of surface states (several 10 cm ) present at the grain boundaries.

The lack of precision restricts the inter chip communication to global metal lines. Advantage 1. For applications where each chip is required to perform independent processing before communicating with its neighbor. Since all chips can be fabricated separately and later bonded. .PROCESSED WAFER BONDING: An attractive alternative is to bond two fully processed wafers on which devices are fabricated on the surface. SILICON EPITAXIAL GROWTH Another technique for forming additional Si layers is to etch a hole in a passivated wafer and epitaxially grow a single crystal Si seeded from open window in the ILD. there is independence of processing temperature. this technology can prove attractive. The Si crystal grows vertically and then laterally to cover the ILD. Inter chip vias are etched to electrically connect both wafers after metallization and prior to the bonding process at 400 degree Celsius. such that the wafers completely overlap. 2. including some interconnects. Disadvantage 1. Devices on all active levels have similar electrical properties.

since the grown layer is single crystal with few defects. SOLID PHASE CRYSTALLIZATION (SPC) In this technique. local crystallization can be induced using low temperatures processes (<600C) such as using patterned seeding of germanium. For this purpose. Ge seeds implanted in narrow . Disadvantage 1. In this method. The quality of devices fabricated on these epitaxial layer can be as good as those fabricated underneath on the seed wafer surface. The high temperatures involved in this process cause significant degradation in the quality of devices on lower layers. Device performance can be enhanced by eliminating the grain boundaries in the poly silicon film. a layer of amorphous Si is crystallized on top of the lower active layer devices. The amorphous film is randomly crystallized to form a poly silicon film.Advantage: 1.

both switching energy and cycle time are expected to be reduced . Advantages 1. CMOS transistors can then be fabricated within these islands to give SOI like performance. which are nearly single crystal.patterns made on amorphous Si can be used to include lateral crystallization. This technique offers flexibility of creating multiple active layers 2. This results in the formation of small islands. This is a low temperature technique Performance Characteristics • Timing Variability • Energy • With shorter interconnects in 3D ICs.

Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performance. timing is interconnect driven.Energy dissipation decreases with the number of layers used in the design. Energy performance: Wire length reduction has an impact on the cycle time and the energy dissipation.The graph below shows the results of a reduction in wire length due to 3D routing.Timing: Graph: Interconnect timing for 3D IC placement In current technologies.Following graphs are based on the 3D tool described later in the presentation: .


Layout of Critical Paths and Microprocessor Design: Fig: Microprocessor Design layout Once again interconnect delay dominates in 2D design.With 3D technology repeaters can be placed on the second layer and reduce area for the first layer.These top layer buffers require large routing area and can reach up to 10.000 for high performance designs in 100nm technology.At top layers inverter sizes 450 times min inverter size for the relevant technology.Implications on Circuit Design and Architecture:  Buffer Insertion  Layout of Critical Paths  Microprocessor Design  Mixed Signal IC’s  Physical design and Synthesis Buffer Insertion: Use of buffers in 3D circuits to break up long interconnects. Logic blocks on the critical path need to communicate with each other but due to placement and .

. Computational modules which access the cache are distributed all over the chip while the cache is in the corner. Cache can be placed on a second layer and connected to these modules using (VILICs). Mixed Signal ICs and Physical Design: Digital signals on chip can couple and interfere with RF signals.With multiple layers RF portions of the system can be separated from their digital counterparts. Physical Design needs to consider the multiple layers of Silicon available. Placement and routing algorithms need to be modified.design constraints are placed far away from each other. With a second layer of Si these devices can be placed on different layers of Si and thus closer to each other using(VILICs).In Microprocessor design most critical paths involve on chip caches on the critical path.

Flash and other non volatile memories are much more rugged.  performance due to lower electromagnetic interference between such circuit blocks. battery efficient compact and require no bulky drive technologies. power dissipation and chip area and therefore improve chip performance. Accidentally dropping a drive or scratching a disk can cause significant damage and the potential loss of valuable pictures and data.  The 3D integration can reduce the wiring. but they requires drives that are expensive bulky fragile and consume a lot of battery power. ADVANTAGES OF 3-D MEMORY Disks are inexpensive.  From an integration point of view.  Additionally the digital and analog components in the mixed-signal systems can be placed on different Si layers thereby achieving better noise . thereby reducing the capacitance. .ADVANTAGES OF 3D ICs  The 3D chip design technology can be exploited to build SoCs by placing circuits with different voltage and performance requirements in different layers. mixed-technology assimilation could be made less complex and more cost effective by fabricating such technologies on separate substrates followed by physical bonding.

To date. Both the devices and consumable media are extremely price sensitive with high volumes coming only with the ability to hit low price points.Dropping them is not a problem they are however much more expensive. . Manufacturers of memory driven devices can now reach price points previously inaccessible and develop richer. Portable devices all require small form factors. Both require the use of a pc. Existing mask ROM and NAND flash non volatile technology force designers and product planners to make the difficult choice between low cost or field programmability and flexibility. and reliability. APPLICATIONS OF 3D ICs Portable electronic digital cameras. These applications share characters beyond rapid market growth. and is as convenient as 35 mm film and audiotape. digital audio players. creating the marketing opportunity for ultra low cost internal and external memory. battery efficiency. The ideal solution is a 3-D memory that leverages all the benefits of non volatile media. Device designers often trade application richness to meet tight cost targets. smart cellular phones. one of the largest constraints to growth has been affordable storage. PDAs. and handheld gaming devices are among the fastest growing technology market for both business and consumers. easier to use products. robustness. The potential to dramatically lower the cost of digital storage weapons many more markets than those listed above. Consumers value the convenience and ease of views of readily available low cost storage. costs as little as a disk.

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