L5981

1 A step-down switching regulator
Features
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1 A DC output current 2.9 V to 18 V input voltage Output voltage adjustable from 0.6 V 250 kHz switching frequency, programmable up to 1 MHz Internal soft-start and inhibit Low dropout operation: 100 % duty cycle Voltage feed-forward Zero load current operation Overcurrent and thermal protection VFQFPN8 3 mm x 3 mm package VFQFPN8 3 mm x 3 mm

Description
The L5981 is step-down switching regulator with 1.5 A (min.) current limited embedded power MOSFET, so it is able to deliver in excess of 1 A DC current to the load depending on the application condition. The input voltage can range from 2.9 V to 18 V, while the output voltage can be set starting from 0.6 V to VIN. Having a minimum input voltage of 2.9 V, the device is suitable also for 3.3 V bus. Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The VFQFPN8 package with exposed pad allows reducing the RthJA down to approximately 60 °C/W.

Applications
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Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors Industrial: chargers, PLD, PLA, FPGA Networking: XDSL, modems, DC-DC modules Computer: optical storage, hard disk drive, printers, audio/graphic cards LED driving Application circuit

Figure 1.

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Contents

L5981

Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 4

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 4.2 4.3 4.4 4.5 4.6 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 5.2 5.3 5.4 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.1 5.4.2 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.5 5.6 5.7

Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 7 8
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Doc ID 13004 Rev 6

L5981

Pin settings

1
1.1

Pin settings
Pin connection
Figure 2. Pin connection (top view)

OUT SYNCH INH COMP

VCC GND FSW FB

1.2

Pin description
Table 1.
Pin n° 1

Pin description
Type OUT Regulator output Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period respect to the power turn on is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal, with zero phase shift. Connecting together the SYNCH pin of two devices, the one with higher frequency works as master and the other one as slave; so the two powers turn on have a phase shift of half a period. A logical signal (active high) disable the device. With INH higher than 1.9 V the device is OFF and with INH lower than 0.6 V the device is ON. Error amplifier output to be used for loop frequency compensation Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from Vout to FB pin. The switching frequency can be increased connecting an external resistor from FSW pin and ground. If this pin is left floating the device works at its free-running frequency of 250 kHz. Ground Unregulated DC input voltage Description

2

SYNCH

3 4 5

INH COMP FB

6 7 8

FSW GND VCC

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1 Maximum ratings Absolute maximum ratings Table 2. Absolute maximum ratings Parameter Input voltage Output DC voltage Value 20 -0.5.3 to 1.5 1. SYNCH Analog pin INH FB PTOT TJ Tstg Inhibit pin Feedback voltage Power dissipation at TA < 60 °C Junction temperature range Storage temperature range 2.2 Thermal data Table 3.Maximum ratings L5981 2 2.3 to 4 -0. COMP. -40 to 150 -55 to 150 W °C °C V Unit Symbol Vcc OUT FSW. Package mounted on demonstration board.3 to VCC -0. Thermal data Parameter Maximum thermal resistance junction-ambient (1) VFQFPN Value 60 Unit °C/W Symbol RthJA 1.3 to VCC -0. 4/37 Doc ID 13004 Rev 6 .

4 30 mA μA Doc ID 13004 Rev 6 5/37 . RFSW = 33 kΩ 7.5 10 μA 0.L5981 Electrical characteristics 3 Electrical characteristics TJ = 25 °C. Table 4.9 7.593 0.8 220 2.2 2 9.4 8.6 V Quiescent current Total stand-by quiescent current Duty cycle = 0.1 ms INH = 0 1.9 0.5 1.9 (1) 225 FSW VFSW D FADJ Switching frequency FSW pin voltage Duty cycle Adjustable switching frequency RFSW = 33 kΩ 0 (1) 250 275 kHz 275 220 1.175 140 0.6 0.8 V 20 2. VCC = 12 V. unless otherwise specified. VFB = 0.254 V 100 % kHz 1000 Dynamic characteristics VFB Feedback voltage 2.3 170 mΩ 140 1.9 V < VCC < 18 V (1) 0.607 V DC characteristics IQ IQST-BY Inhibit Device ON level INH threshold voltage Device OFF level INH current Soft-start FSW pin floating TSS Soft-start duration FSW = 1 MHz.1 A V Unit VCC VCCON VCCHYS RDS(on) ILIM Oscillator (1) (1) (1) 2. Symbol Electrical characteristics Values Parameter Operating input voltage range Turn on VCC threshold VCC UVLO hysteresis MOSFET on resistance Maximum limiting current Test condition Min Typ Max 18 2.

Specification in the -40 to +125 °C temperature range are assured by design. VCOMP=1 V (2) 3 V 0.7 2 3.8 V VFB = 0.7 V. characterization and statistical correlation.6 V VFB = 0 V to 0.3 V 1 0.6 V VFB > 0. Symbol L5981 Electrical characteristics (continued) Values Parameter Test condition Min Typ Max Unit Error amplifier VCH VCL IFB High level output voltage Low level output voltage Bias source current VFB < 0. VCOMP=1 V VFB = 0. 6/37 Doc ID 13004 Rev 6 .1 1 20 25 100 μA mA mA dB IO SOURCE Source COMP pin IO SINK GV Sink COMP pin Open loop voltage gain Synchronization function High input voltage Low input voltage Slave sink current Master output amplitude Output pulse width Input pulse width Protection IFBDISC TSHDN FB disconnection source current Thermal shutdown Hystereris 1 150 °C 30 μA VSYNCH = 2.5 mA SYNCH floating 70 2. Guaranteed by design.Electrical characteristics Table 4.0 110 ns 0. 2. Specification refered to TJ from -40 to +125 °C.9 V ISOURCE = 4.5 V.9 mA V 1.

constant frequency control. Its switching frequency can be adjusted by and external resistor. A voltage regulator and internal reference. A thermal shutdown block. to handle over load and short circuit conditions. The peak current limit sensing block. The voltage mode error amplifier The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch. It supplies internal circuitry and provides a fixed internal reference. The main internal blocks are shown in the block diagram in Figure 3. Doc ID 13004 Rev 6 7/37 . Block diagram ● ● ● ● ● ● ● ● Figure 3. A voltage monitor circuitry (UVLO) that checks the input and internal voltages. compared to a fixed frequency sawtooth. The soft-start circuitry to limit inrush current during the start up phase. to prevent thermal run away. The voltage and frequency feed forward are implemented.L5981 Functional description 4 Functional description The L5981 is based on a “voltage mode”. The high-side driver for embedded p-channel power MOSFET switch. controls the on and off time of the power switch. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that. They are: ● A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal.

Figure 4.1 Oscillator and synchronization Figure 4 shows the block diagram of the oscillator circuit. the device with higher oscillator frequency works as master. To minimize the change of the PWM gain. This pre-adjusting of the frequency will change the sawtooth slope in order to get negligible the truncation of sawtooth. This changing has to be taken into account when the loop stability is studied. 8/37 Doc ID 13004 Rev 6 . The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor externally connect to FSW pin.b) in order to keep the PWM gain constant versus the switching frequency (see Section 5.c). changing the PWM gain (Figure 5. so the slave device switches at the frequency of the Master but with a delay of half a period. On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180° with respect to the clock. Oscillator circuit block diagram Clock FSW Clock Generator Synchronization SYNCH Ramp Generator Sawtooth The device can be synchronized to work at higher frequency feeding an external clock signal.a). the free running frequency should be set (with a resistor on FSW pin) only slightly lower than the external clock frequency. The synchronization changes the sawtooth amplitude.4 for PWM gain expression). the voltage feed forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 5. it can be increased as shown in Figure 6 by external resistor connected to ground. To improve the line transient performance keeping the PWM gain constant versus the input voltage. The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. This delay is useful when two devices are synchronized connecting the SYNCH pin together. In this way a frequency feed forward is implemented (Figure 5. This minimizes the RMS current flowing through the input capacitor [see L5988D data sheet]. In case the FSW pin is left floating the frequency is 250 kHz. due to the external synchronization.Functional description L5981 4. When SYNCH pins are connected.

Functional description Sawtooth: voltage and frequency feed forward. Oscillator frequency versus FSW pin resistor Doc ID 13004 Rev 6 9/37 . external synchronization Figure 6.L5981 Figure 5.

So the soft-start time and then the output voltage slew rate depend on the switching frequency. It avoids inrush current surge and makes the output voltage increases monothonically. Soft-start scheme Soft-start time results: Equation 2 32 ⋅ 64 SS TIME = ----------------Fsw For example with a switching frequency of 250 kHz the SSTIME is 8 ms. The time base of one step is of 32 clock cycles.2 Soft-start The soft-start is essential to assure correct and safe start up of the step-down converter. 10/37 Doc ID 13004 Rev 6 . Figure 7.6 V.5 mV each one. So the output voltage slew rate is: Equation 1 SR OUT = SR VREF ⋅ ⎛ 1 + R1⎞ ------⎝ R2⎠ where SRVREF is the slew rate of the non-inverting input while R1 and R2 the resistor divider to regulate the output voltage (see Figure 7). from 0 V to 0. The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error amplifier. The soft-start stair case consists of 64 steps of 9.Functional description L5981 4.

3 Error amplifier and compensation The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation.6 V voltage reference. the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. a type III compensation network has to be used (see Chapter 5. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance. Uncompensated error amplifier characteristics Error amplifier Low frequency gain GBWP Slew rate Output voltage swing Maximum source/sink current Value 100 dB 4.3 V 25 mA/40 mA In continuos conduction mode (CCM). while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. Its non-inverting input is internally connected to a 0.L5981 Functional description 4.5 MHz 7 V/μs 0 to 3. Otherwise. The uncompensated error amplifier characteristics are the following: Table 5. Doc ID 13004 Rev 6 11/37 . Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin.4 for details about the compensation network selection). In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used.

(see Figure 8. While.Functional description L5981 4. After this time. Soft-start phase. 12/37 Doc ID 13004 Rev 6 .b) 2. See Figure 32. the device can skip pulses in order to keep the output current constant and equal to the current limit. Output voltage in regulation. This mechanism is repeated and the device can skip up to seven pulses. under over current condition. So the over current protection can be summarized as an “hiccup” intervention when the output is in regulation and a constant current during the soft-start phase. the power MOSFET is turned off and it will skip one pulse. two different behaviors are possible depending on the operating condition.4 Overcurrent protection The L5981 implements the over current protection sensing current flowing through the power MOSFET. the power MOSFET is switched off and the internal reference (VREF). If the over current limit is reached the power MOSFET is turned off implementing the pulse by pulse over current protection. the number of skipped cycles is decreased of one unit. that biases the non-inverting input of the error amplifier. If the output is shorted to ground when the output voltage is on regulation.a). for short circuit behavior. The masking time is about 200 ns. At the end of soft-start phase the output voltage is in regulation and if the over current persists the behavior explained above takes place. at the next switching on at the end of the "masking time" the current is still higher than the threshold. 1. a new soft-start phase takes place and the internal reference begins ramping (see Figure 8. If. the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. the over current is triggered and the device starts cycling with a period of 2048 clock cycles between “hiccup” (power MOSFET off and no current to the load) and “constant current” with very short on-time and with reduced switching frequency (up to one eighth of normal switching frequency). the device will skip two pulses. This interval is generally known as “masking time” or “blanking time”. When the over current is detected. is set to zero and kept in this condition for a soft-start time (TSS. 2048 clock cycles). If at the end of the "masking time" the current is higher than the over current threshold. Due to the noise created by the switching activity of the power MOSFET. if at the end of the "masking time" the current is lower than the over current threshold. During the soft-start phase. When the over current is sensed.

the device is enabled. Once the junction temperature goes back to about 130 °C.5 Inhibit function The inhibit feature allows to put in stand-by mode the device. The pin is also VCC compatible.L5981 Figure 8. the device restarts in normal operation.6 V. With INH pin lower than 0. Doc ID 13004 Rev 6 13/37 .9 V the device is disabled and the power consumption is reduced to less than 30 μA. 4.6 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. Overcurrent protection strategy Functional description 4. If the INH pin is left floating. The sensing element is very close to the PDMOS area.With INH pin higher than 1. so ensuring an accurate and fast temperature detection.

Application information L5981 5 5. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 3 2 ⋅ D. The maximum and minimum duty cycles can be calculated as: Equation 4 V OUT + V F D MAX = -----------------------------------V INMIN – V SW and Equation 5 V OUT + V F D MIN = ------------------------------------V INMAX – V SW Where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across the internal PDMOS. D is the duty cycle.DI RMS = I O ⋅ D – -------------. Considering η = 1.5 and it is equal to Io/2.1 Application information Input capacitor selection The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. So the input capacitor must have a RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. affecting the overall system efficiency.+ -----η2 η 2 2 Where Io is the maximum DC output current. This function has a maximum at D = 0. the RMS value of which is dissipated over its ESR. In Table 6 some multi layer ceramic capacitors suitable for this device are reported Table 6. η is the efficiency. Input MLCC capacitors Series GRM31 MURATA GRM55 TDK C3225 10 10 25 25 Cap value (μF) 10 Rated voltage (V) 25 Manufacturer 14/37 Doc ID 13004 Rev 6 .

7 27 to 47 10 to 22 1. the higher is the average output current that can be delivered.4 1.⋅ T ON = --------------------------.⋅ ---------------------ΔI MAX F SW where FSW is the switching frequency.5 10 to 18 10 to 22 1.9 Manufacturer Wurth Doc ID 13004 Rev 6 15/37 . VIN = 12 V. PK = I O + ------2 So if the inductor value decreases.65 to 2. The peak current through the inductor is given by: Equation 8 ΔI L I L. without reaching the current limit. 1/(TON + TOFF). Inductors Series PD M MSS1038 Coilcraft LPS6235 DRQ73 Coiltronics LD2 CDR6D28MN SUMIDA CDRH105RNP 27 to 56 1. For example for VOUT = 3.9 to 2. So fixing ΔIL = 20 % to 40 % of the maximum output current.L5981 Application information 5. The higher is the inductor value. the peak current (that has to be lower than the current limit of the device) increases. So the minimum inductance value in order to have the expected current ripple has to be selected. In the continuos current mode (CCM).47 Inductor value (μH) 10 to 18 22 to 47 Saturation current (A) 1.67 to 2. The maximum current ripple.⋅ T OFF L L Where TON is the conduction time of the internal high side switch and TOFF is the conduction time of the external diode (in CCM.40 % of the output current.1 1.3 V. Table 7. is obtained at maximum TOFF that is at minimum duty cycle (see previous section to calculate minimum duty). In the table below some inductor part numbers are listed.9 to 2.7 to 2. IO = 1 A and FSW = 250 kHz the minimum inductance value to have ΔIL = 30 % of IO is about 31 μH.2 1.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. FSW = 1 / (TON + TOFF)). The rule to fix the current ripple value is to have a ripple at 20 % .8 to 2. the inductance value can be calculated by the following equation: Equation 6 V IN – V OUT V OUT + V F ΔI L = ----------------------------. at fixed Vout. the minimum inductance value can be calculated: Equation 7 V OUT + V F 1 – D MIN L MIN = --------------------------.64 to 2.

This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). In case of not negligible ESR (electrolytic or tantalum capacitors).3 Output capacitor selection The current in the capacitor has a triangular waveform which generates a voltage ripple across it.4. if the output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR value. In the table below some capacitor series are listed.3 15 to 55 40 to 80 <5 10 to 47 10 to 22 6.Application information L5981 5. So in case of 100 μF with ESR = 40 μF. The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. So the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. In Chapter 5. So if the high slew rate load transient is required by the application the output capacitor and system bandwidth have to be chosen in order to sustain the load transient .3 V. it will be illustrated how to consider its effect in the system stability.01·VOUT. When the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. if the multi layer capacitor are adopted. the capacitor is chosen taking into account its ESR value.3 to 25 ESR (mΩ) <5 Manufacturer 16/37 Doc ID 13004 Rev 6 . Equation 9 ΔI MAX ΔV OUT = ESR ⋅ ΔI MAX + -----------------------------------8 ⋅ C OUT ⋅ f SW Usually the resistive component of the ripple is much higher than the capacitive one.3 to 25 6. The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. VIN = 12 V. Output capacitors Series GRM32 MURATA GRM31 ECJ PANASONIC EEFCD SANYO TDK TPA/B/C C3225 10 to 68 100 to 470 22 to 100 6. the resistive component of the drop dominates and the voltage ripple is 12 mV.3 <5 <5 Cap value (μF) 22 to 100 Rated voltage (V) 6. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. in order to have a ΔVOUT = 0.3 4 to 16 6. 10 μF are needed and the ESR effect on the output voltage ripple can be neglected.3 A (resulting by the inductor value). ΔIL = 0. For example with VOUT = 3. Table 8.

from the error amplifier output (COMP pin) to the OUT pin. The error amplifier. the PWM modulator and the LC output filter VCC VS VREF FB E/A COMP PWM OUT L ESR GPW0 GLC COUT The transfer function on the LC filter is given by: Doc ID 13004 Rev 6 17/37 .L5981 Application information 5. As seen in Chapter 4. results: Equation 10 V IN G PW0 = -------Vs where VS is the sawtooth amplitude.4 Compensation network The compensation network has to assure stability and good dynamic performance.= --. that is: Equation 11 V S = K ⋅ V IN In this way the PWM modulator gain results constant and equals to: Equation 12 V IN 1 G PW0 = -------.= 9 Vs K The synchronization of the device with an external clock provided trough SYNCH pin can modifies the PWM modulator gain (see Chapter 4. its bandwidth is much larger than the system one.1. that is.1 to understand how this gain changes and how to keep it constant in spite of the external synchronization). The error amplifier is a voltage operational amplifier with high bandwidth. Figure 9. the voltage feed forward generates a sawtooth amplitude directly proportional to the input voltage. The loop of the L5981 is based on the voltage mode control. The transfer function of the PWM modulator. So selecting the compensation network the E/A will be considered as ideal. The transfer functions of PWM modulator and the output LC filter are studied (see Figure 9).

so type III network is adopted to compensate the loop.Application information Equation 13 s 1 + ------------------------2π ⋅ f zESR G LC ( s ) = -----------------------------------------------------------------------s . This network introduces two zeros (fZ1. the type III compensation network is needed.. 5... with very high frequency zero. If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2π * ESR * COUT < 1 / BW). fP1.4. fP2). Multi Layer Ceramic capacitors (MLCC) have very low ESR (<1 mΩ). In the two following paragraph the guidelines to select the type II and type III compensation network are illustrated.1 Type III compensation network The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole. so increasing phase margin.2 s 1 + ---------------------------.⎞ 2π ⋅ Q ⋅ f LC ⎝ 2π ⋅ f LC⎠ L5981 where: Equation 14 1 f LC = ----------------------------------------------------------------------. ESR2π ⋅ L ⋅ C OUT ⋅ 1 + -------------R OUT 1 f zESR = ------------------------------------------2π ⋅ ESR ⋅ C OUT Equation 15 R OUT ⋅ L ⋅ C OUT ⋅ ( R OUT + ESR ) Q = ----------------------------------------------------------------------------------------. fZ2) and three poles (fP0. finally to place other poles far away the zero dB frequency. In Figure 10 the type III compensation network is shown. They expression are: Equation 16 1 f Z1 = ----------------------------------------------. 2π ⋅ C 3 ⋅ ( R 1 + R 3 ) 1 f Z2 = ----------------------------2π ⋅ R 4 ⋅ C 4 18/37 Doc ID 13004 Rev 6 .3 two different kind of network can compensate the loop. L + C OUT ⋅ R OUT ⋅ E SR V OUT R OUT = -------------I OUT As seen in Chapter 4.+ ⎛ -----------------. then to place one pole in the origin to minimize the dc error on regulated output voltage.

.L5981 Equation 17 f P0 = 0. Figure 11. Choose a gain (R4/R1) in order to have the required bandwidth (BW). 1 f P1 = ----------------------------. Type III compensation network In Figure 11 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f)) and the open loop gain (GLOOP(f)=GPW0 · GLC(f) · GTYPEIII(f)) are drawn. 2π ⋅ R 3 ⋅ C 3 Application information 1 f P2 = ------------------------------------------C4 ⋅ C5 ------------------2π ⋅ R 4 ⋅ C4 + C5 Figure 10. Open loop gain: module Bode diagram The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. 2. Choose a value for R1. usually between 1 k and 5 k. that means: Doc ID 13004 Rev 6 19/37 .

Application information Equation 18 BW ⋅ K R 4 = ----------------. For example with VOUT = 3. C 4 = 10nF. R 3 = 110Ω. Calculate C5 by placing the second pole at four times the system bandwidth (BW): Equation 20 C4 C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1 5. 20/37 Doc ID 13004 Rev 6 . 4 ⋅ BW – 1 ----------------f LC 1 C 3 = ---------------------------------------2π ⋅ R 3 ⋅ 4 ⋅ BW The suggested maximum system bandwidth is equals to the switching frequency divided by 3. Calculate C4 by placing the zero at 50 % of the output filter double pole frequency (fLC): Equation 19 1 C 4 = -------------------------π ⋅ R 4 ⋅ f LC 4.99kΩ.⋅ R 1 f LC L5981 where K is the feed forward constant and 1 / K is equals to 9. R 2 = 1. C 5 = 100pF In Figure 12 is shown the module and phase of the open loop gain. C 3 = 4. L =33 μH. the type III compensation network is: R 1 = 4. The bandwidth is about 56 kHz and the phase margin is 53 °. anyway lower than 100 kHz if the FSW is set higher than 500 kHz.5).5 (FSW / 3. Set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole: Equation 21 R1 R 3 = -------------------------. COUT = 22 μF.1kΩ. VIN = 12 V.6kΩ. 3. R 4 = 5..3 V. IO = 1 A.7nF. ESR < 1 mΩ.

L5981 Application information Figure 12. Open loop gain Bode diagram with ceramic output capacitor Doc ID 13004 Rev 6 21/37 .

Figure 13. 22/37 Doc ID 13004 Rev 6 .. Type II compensation network The singularity of the network are: 1 f Z1 = ----------------------------. Electrolytic capacitors show not negligible ESR (> 30 mΩ).4. 2π ⋅ R 4 ⋅ C 4 f P0 = 0. this zero helps stabilize the loop.2 Type II compensation network If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2π * ESR * COUT > 1 / BW).Application information L5981 5. In Figure 13 the type II network is shown. 1 f P1 = ------------------------------------------C4 ⋅ C5 2π ⋅ R 4 ⋅ ------------------C4 + C5 In Figure 14 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f)) and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)) are drawn. so with this kind of output capacitor the type II network combined with the zero of the ESR allows stabilizing the loop.

⋅ R 1 ⎝ f LC ⎠ f ESR V IN Where fESR is the ESR zero: Equation 23 1 f ESR = ------------------------------------------2π ⋅ ESR ⋅ C OUT and Vs is the saw-tooth amplitude.⋅ -------. Open loop gain: module Bode diagram Application information The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. 3. Choose a gain (R4/R1) in order to have the required bandwidth (BW).L5981 Figure 14. in order to have values of C4 and C5 not comparable with parasitic capacitance of the board. usually between 1 k and 5 k. Choose a value for R1. The voltage feed forward keeps the ratio Vs/Vin constant. Calculate C4 by placing the zero one decade below the output filter double pole: Equation 24 10 C 4 = -----------------------------2π ⋅ R 4 ⋅ f LC 4. that means: Equation 22 f ESR 2 BW V S R 4 = ⎛ -----------⎞ ⋅ ----------. Then calculate C3 in order to place the second pole at four times the system bandwidth (BW): Doc ID 13004 Rev 6 23/37 . 2.

3 V. The bandwidth is about 33 kHz and the phase margin is 46°. R 4 = 10kΩ. the type II compensation network is: R 1 = 1. COUT = 220 μF. 24/37 Doc ID 13004 Rev 6 . R 2 = 249Ω. C 4 = 10nF.Application information Equation 25 C4 C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1 L5981 For example with VOUT = 3. VIN = 12 V.1kΩ. L = 33 μH. IO = 1 A. ESR = 100 mΩ. C 5 = 100pF In Figure 15 is shown the module and phase of the open loop gain.

Open loop gain Bode diagram with electrolytic/tantalum output capacitor Doc ID 13004 Rev 6 25/37 .L5981 Application information Figure 15.

it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient.⋅ Fsw = V IN ⋅ I OUT ⋅ T SW ⋅ F SW 2 Where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn ON and turn OFF phases. calculated as: Equation 28 P Q = V IN ⋅ I Q where IQ is the quiescent current (IQ = 2.4 mA).Application information L5981 5. these are equal to: Equation 26 P ON = R DS ( on ) ⋅ ( I OUT ) ⋅ D 2 Where D is the duty cycle of the application and the maximum RDSON is 220 mΩ. The junction temperature TJ can be calculated as: Equation 29 T J = T A + Rth JA ⋅ P TOT Where TA is the ambient temperature and PTOT is the sum of the power losses just seen. as shown in Figure 16. RthJA is the equivalent thermal resistance junction to ambient of the device. these can be calculated as: Equation 27 ( T RISE + T FALL ) P SW = V IN ⋅ I OUT ⋅ -----------------------------------------. b) switching losses due to power MOSFET turn ON and OFF. but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case. For this device the typical value for the equivalent switching time is 50 ns. c) Quiescent current losses. For this device the path through the exposed pad is the one conducting the largest amount 26/37 Doc ID 13004 Rev 6 .5 Thermal considerations The thermal design is important to prevent the thermal shutdown of device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the not negligible RDS(on) of the power switch. Note that the duty cycle is theoretically given by the ratio between VOUT an VIN. TSW is the equivalent switching time.

The RthJA measured on the demonstration board described in the following paragraph is about 60 °/W. In order to minimize the EMI. Switching losses 5. Doc ID 13004 Rev 6 27/37 . so the interferences can be minimized placing the routing of feedback node as far as possible from the high current paths. To filter the high frequency noise. In a step-down converter the input loop (including the input capacitor. Figure 16. To reduce the pick up noise the resistor divider has to be placed very close to the device. the power MOSFET and the free wheeling diode) is the most critical one. the ground plane helps to reduce the thermal resistance junction to ambient.L5981 Application information of heat. a small capacitor (100 nF) can be added as close as possible to the input voltage pin of the device. This is due to the fact that the high value pulsed current are flowing through it. To filter the high frequency noise. so a large ground plane enhances the thermal performance of the converter allowing high power conversion. In Figure 17 a layout example is shown. a small capacitor can be added as close as possible to the input voltage pin of the device. this loop has to be as short as possible.6 Layout considerations The PC board layout of switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops. Thanks to the exposed pad of the device. The feedback pin (FB) connection to external resistor divider is a high impedance node.

Application information Figure 17. Layout example L5981 28/37 Doc ID 13004 Rev 6 .

1 W 0603 100 kΩ. 1 %.L5981 Application information 5. 0. 20 %. 1 %.1 kΩ.1 W 0603 180 Ω.99 kΩ. 1 %. 0. 2. 0. 1 %.1 W 0603 1.1 W 0603 3. 1 %. 25 V 15 μH. Demonstration board application circuit VIN=3. 50 V 150 pF.3nF R5 100K Table 9.9 kΩ.3V to 18V VCC OUT L1 15uH D1 STPS2L25U Vout=3. 25 V 22 μF. 25 V 3. 50 V 10 nF.99K 4 C4 10nF R4 3.2 A STMicroelectronics Wurth elektronik Manufacturer MURATA MURATA Reference C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 D1 L1 Doc ID 13004 Rev 6 29/37 .1 W 0603 STPS2L25V 7447779115 2 A.3 nF.3V 8 INH GND 1 2 SYNCH 3 L5981 L5985 7 5 6 FSW COMP FB C2 22uF C1 10uF C6 68nF R1 4.9K R3 180 R2 1. 50 V 68 nF. Component list Part number GRM31CR61E106KA12 GRM32ER61E226KE15 Description 10 μF. 0.1K C5 150pF C3 3. 25 V 4.7 Application circuit In Figure 18 the demonstration board application circuit is shown. 0. Figure 18.

PCB layout (front side) 30/37 Doc ID 13004 Rev 6 . PCB layout (component side) L5981 Figure 20. PCB layout (bottom side) Figure 21.Application information Figure 19.

3 0.3V Vo=2.6 0.2 0.7 0.8V Vo=1.4 0. Junction temperature vs output current Figure 24.3 0.7 0.8 0.8 0.3V FSW=250KHz 0.5V Vo=1.6 0.4 0.1 0.3V Vo=2.5V E ffic ie n c y [% ] E ffic ie n c y [% ] 88 86 84 82 80 78 76 0.0 Io [A] Figure 26.5 0.L5981 Application information Figure 22. Efficiency vs output current 95 90 Vo=3. Junction temperature vs output current Figure 23.5 0.1 0.2V VCC=3.9 1 85 80 75 70 65 0.5 0.3 0. Efficiency vs output current 94 92 90 Figure 27.1 0. Junction temperature vs output current Figure 25.2 0.7 Vo=2.9 1.9 1 Io [A] Io [A] Doc ID 13004 Rev 6 31/37 .0V 85 Vo=3. Efficiency vs output current 95 90 E fficiency [% ] Vo=5.6 0.8V VCC=5V FSW=250KHz Vo=1.5V VCC=12V FSW =250KHz 80 75 70 0.8 0.2 0.4 0.

6 0.3V VCC=5.5A/μs IL 500mA/div Time base 1ms/div Figure 32.4 0.35 Δ V FB /V FB [% ] ΔVFB/VFB [%] VCC=12V 0.15 0.05 0 -0.2 0. Line regulation 0.2 A to 1 A Figure 31.05 2 4 6 8 10 12 14 16 18 VCC=3. Load transient: from 0.1 0.25 0.2 0.1 0.05 0 0 0. Short circuit behavior OUT 10V/div OUTPUT SHORTED VOUT 1V/div IL 500mA/div Time base 5ms/div 32/37 Doc ID 13004 Rev 6 .4 FSW=250KHz 0.Application information L5981 Figure 28.0V Io=1A Io [A] VCC [V] Figure 30. Load regulation 0.3 0.8 1 0.25 0.2 0.15 0. Soft-start VOUT 100mV/div AC coupled VOUT 500mV/div VFB 200mV/div IL 200mA/div COUT=47μF L=15μH FSW=520KHz Time base 100μs/div Load slew rate 2.3 Figure 29.

ECOPACK® specifications. depending on their level of environmental compliance. grade definitions and product status are available at: www.st. ECOPACK® is an ST trademark. Doc ID 13004 Rev 6 33/37 . ST offers these devices in different grades of ECOPACK® packages.L5981 Package mechanical data 6 Package mechanical data In order to meet environmental requirements.com.

90 Max 1.05 1.05 2.0020 b D D2 0.0394 A 0.0157 0.05 0.0976 E E2 e L ddd 2.48 0.0878 0. Package dimensions 34/37 Doc ID 13004 Rev 6 .0031 Figure 33.40 0.0091 0. VFQFPN8 (3 x 3 x 1.02 0.1181 0.70 0.0937 0.0079 0.23 3.95 1.08 0.0354 Max 0.30 0.1200 0.00 1.65 3.0118 0.0276 0.50 3.0646 0.Package mechanical data L5981 Table 10.0118 0.0685 0.0315 inch Typ 0.0008 0.75 0.30 3.0197 0.80 A1 A2 A3 0.38 0.1181 0.0197 0.18 2.00 Min 0.0587 0. Dim.1161 0.95 2.0071 0.1161 0.70 0.1200 0.00 2.23 0.50 0.20 0.08 mm) mechanical data mm Min Typ 0.

L5981 Order codes 7 Order codes Table 11. Order codes Package VFQFPN8 (3 x 3 x 1.08 mm) Packaging Tube Tube and reel Order codes L5981 L5981TR Doc ID 13004 Rev 6 35/37 .

Revision history L5981 8 Revision history Table 12. Figure 5 on page 9. Date 21-Dec-2006 16-Oct-2007 Document revision history Revision 1 2 Initial release Document status promoted from preliminary data to datasheet Updated: Cover page. Figure 8 on page 13. Table 10 on page 34 Added: Table 3 on page 4 Updated: Table 4 on page 5 Updated: Equation 18 Updated Table 4 on page 5 and Figure 6 on page 9 Changes 27-May-2008 3 09-Sep-2008 27-Jan-2009 15-Jun-2009 4 5 6 36/37 Doc ID 13004 Rev 6 . Figure 17 on page 28. Figure 18 on page 29. Figure 2 on page 3. Table 8 on page 16.

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