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You are on page 1of 70

hereby submit this work as part of the requirements for the degree of:

Masters of Science

in:

Electrical Engineering

It is entitled:

Design Procedures for Sigma Delta Modulators

Dr. Joseph H. Nevin Chair: _______________________________ Dr. Carla Purdy _______________________________ Dr. Fred R. Beyette _______________________________

_______________________________ _______________________________

A thesis submitted to the Division of Research and Advanced Studies, University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE (Electrical Engineering) in the Department of Electrical and Computer Engineering and Computer Science, College of Engineering, University of Cincinnati August 2005 by Mohit Jain B.E (Electronics and Instrumentation), Institute of Engineering & Technology, Devi Ahilya University, Indore, India, June 2002 Thesis Advisor and Committee Chair: Dr Joseph H. Nevin

Abstract

With the emergence of complex, non- linear mixed signal systems it becomes important to devise strategies to model them accurately at the system level. Though advanced CAD tools are available for digital design, analog design is still a kind of empirical art which mainly involves selection of architecture, determining specifications for individual analog blocks and implementation of the system with minimization of non- idealities.

For a long time, most of the building block specifications and non- idealities were explored at the transistor level which involved a lot of time for each run and multiple runs to achieve the required specifications. To explore a new method for modeling of a mixed signal circuit is the main point of investigation of this thesis. In order to explore the new method of modeling, a Sigma-Delta A/D converter is considered. These converters are gaining popularity as they are insensitive to circuit imperfections and component mismatch. Design of Switched-Capacitor (SC) Sigma-Delta modulators requir ing optimization of a large set of parameters has been explored and a top-down method for design of such systems is presented. The research work deals in detail with the modeling of the converter, choosing the appropriate analog blocks at the transistor level and various trade offs in implementation of the same.

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Dedicated to My Parents

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Acknowledgements

I would like to extend my heartfelt gratitude to my thesis advisor Dr. Joseph H. Nevin for his continuous guidance and encouragement in getting the best out of this research work. It would not have been possible to move ahead without his brilliant insight in analog circuit design always stayed as my source of motivation to delve deeper in to the subject.

I would also like to thank Dr. Carla Purdy and Dr. Fred R. Beyette Jr. for being on the technical committee for my thesis defense and for providing critical suggestions to make this document better. I am very thankful to my lab mates Sanjith, Lakshminarayanan and Ravikanth, for their constant inputs to problems encountered during this work.

I am very thankful to my friends in Cincinnati especially Aditya, Kalyan, Hetal, Pranay, Pratima, Rajasundaram, Rashmi, Ratan, Vasant, Vishal and Vishesh for their support all through the Masters program and making my stay at Cincinnati a memorable one.

Last but not the least; I would like to thank my parents and my sister for their love, constant support and encouragement. I am very grateful to my parents who have been a source of inspiration for me and without their sacrifices and efforts this work would have been impossible.

TABLE OF CONTENTS

1.

Introduction............................................................................................................................. 1 1.1. Introduction..................................................................................................................... 1 1.2. Research Motivation and Objective ................................................................................ 2 1.3. Thesis Outline ................................................................................................................. 3 2. Fundamentals of Sigma-Delta Data Converters ..................................................................... 4 2.1. Introduction..................................................................................................................... 4 2.2. Quantitative analysis of Analog to Digital Conversion.................................................. 4 2.3. Limitations of Nyquist-rate ADC ................................................................................... 5 2.4. Oversampling as Compared to Nyquist rate sampling ................................................... 6 2.5. Sigma Delta Modulators and Noise Shaping .................................................................. 7 2.5.1. First and Second order Sigma Delta Modulator ..................................................... 9 2.6. Architectures of Sigma Delta Modulators .................................................................... 12 2.6.1. Single loop (Low and High order) Modulators..................................................... 12 2.6.2. Multi-stage (Cascaded) Modulators...................................................................... 13 2.6.3. Multi-bit Modulators............................................................................................. 14 2.7. Non idealities in SDM .................................................................................................. 15 2.7.1. Circuit Noise ......................................................................................................... 16 2.7.2. Operational Amplifier Non- idealities ................................................................... 17 2.7.2.1. Limited DC Gain........................................................................................... 17 2.7.2.2. Limited Bandwidth and Slew Rate ............................................................... 18 2.7.2.3. Saturation...................................................................................................... 18 2.7.3. Comparator Offset and Hysteresis ........................................................................ 18 3. System Level (Behavioral) Modeling of ? ? Modulator ...................................................... 20 3.1. Introduction................................................................................................................... 20 3.2. Modeling Approaches................................................................................................... 21 3.3. Design Methodology..................................................................................................... 23 3.3.1. Topology Selection: .............................................................................................. 23 3.3.2. Signal Scaling ....................................................................................................... 26 3.3.3. Model for switching noise .................................................................................... 27 3.3.4. Model for op-amp noise ........................................................................................ 29 3.3.5. Model for limited DC gain.................................................................................... 30 3.3.6. Model for limited BW and SR .............................................................................. 31 4. Circuit Design and Details .................................................................................................... 32 4.1. Introduction................................................................................................................... 32 4.2. Topology selection........................................................................................................ 32 4.3. Integrator design ........................................................................................................... 35 4.3.1. Clock generator..................................................................................................... 38 4.3.2. Fully Differential Folded-Cascode Op Amp ......................................................... 39

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4.3.3. Bias circuit ............................................................................................................ 41 4.3.4. Common-Mode Feedback Circuit......................................................................... 44 4.4. Regenerative Track and Latch Comparator design....................................................... 45 4.5. Simulation..................................................................................................................... 47 5. Conclusion ............................................................................................................................ 51 APPENDIX A........................................................................................................................... 53 APPENDIX B........................................................................................................................... 55 BIBLIOGRAPHY ......................................................................................................................... 57

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LIST OF TABLES

Table 3.1: Comparison of several modeling techniques ............................................................... 22 Table 4.1: Transistor sizes for Folded Cascode Op Amp ............................................................. 40 Table 4.2: Transistor W/L ratios for Bias Circuit (RB = 3k) ........................................................ 43

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LIST OF FIGURES

Figure 2.1: Quantization noise PSD for Nyquist rate and Oversampled converters ...................... 7 Figure 2.2: Block diagram of Sigma Delta Modulator ................................................................... 8 Figure 2.3: Linearized model of a Sigma Delta Modulator ............................................................ 8 Figure 2.4: First order Sigma Delta Modulator .............................................................................. 9 Figure 2.5: Second order Sigma Delta Modulator ........................................................................ 10 Figure 2.6: Magnitude vs Frequency plot for first, and higher order ? ? modulators .................. 11 Figure 2.7: Multi-stage (Cascaded) ? ? modulator ....................................................................... 14 Figure 3.1: Theoretical SNR of a (1 z-1 )n modulator ................................................................. 24 Figure 3.2: Maximum SNR achievable by modulators of order n with coincident zeroes........... 25 Figure 3.3: Second order sigma-delta modulator using Simulink ................................................ 25 Figure 3.4: Effect of scaling on integrator outputs ....................................................................... 26 Figure 3.5: Simulink model of Switching Noise .......................................................................... 28 Figure 3.6: Effect of kT/C Noise on PSD of ideal sign wave ....................................................... 29 Figure 3.7: Model for op-amp noise ............................................................................................. 29 Figure 3.8; Model for limited op-amp gain .................................................................................. 30 Figure 3.9: Effect of gain factor on SNR...................................................................................... 30 Figure 3.10: Op-Amp flow chart .................................................................................................. 31 Figure 4.1: Modified second order modulator architecture .......................................................... 33 Figure 4.2: Variation of SNR with a1 and a2 ............................................................................... 34 Figure 4.3: Output density at Integrator 1 and 2 for a1 = 0.5 and a2 varying from 0.1 to 0.9...... 34 Figure 4.4: Output density at Integrator 1 and 2 for a1 = 0.4 and a2 varying from 0.1 to 0.9...... 35 Figure 4.5: Parasitic insensitive switched-capacitor integrator ................................................. 36 Figure 4.6: Two phase non-overlapping clocking scheme ........................................................... 37 Figure 4.7: Fully differential implementation of switched capacitor integrator........................... 38 Figure 4.8: Schematic for non-overlapping clock generation....................................................... 38 Figure 4.9: Fully differential folded-cascode Op Amp................................................................. 40 Figure 4.10: Conventional cascode mirror and Wide-swing cascode current mirror ................... 42 Figure 4.11: Bias Circuit ............................................................................................................... 43 Figure 4.12: Switched capacitor common-mode feedback (CMFB) circuit ................................. 45 Figure 4.13: Regenerative feedback comparator .......................................................................... 47 Figure 4.14: AC analysis of folded cascode Op Amp showing gain and phase margin............... 49 Figure 4.15: Comparator Output .................................................................................................. 49 Figure 4.16: FFT (214 ) magnitude plot for sigma-delta modulator output.................................... 50 Figure 4.17: PSD plot for sigma-delta modulator output ............................................................. 50

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1.

Introduction

1.1.

Introduction

The emergence of powerful digital signal processing for telecommunication and multimedia applications implemented in CMOS VLSI technology creates the need for high- resolution analog-to-digital converters that can be integrated in fabrication technologies optimized for digital circuits and systems. However, the same scaling of VLSI technology that makes possible the continuing dramatic improvements in digital signal processor performance also severely constrains the dynamic range available for implementing the interfaces between the digital and analog representation of signals.

Conventional converters are becoming increasingly difficult to implement as they need precise analog components in the ir filters and conversion circuits and such conversion circuits can be very vulnerable to noise and interference. Oversampling converters on the other hand make extensive use of digital signal processing, with the fact that fine- line VLSI is better suited for providing fast digital circuits than for providing precise analog circuits.

Oversampled A/D converters based on delta-sigma modulation combine sampling at rates well above the Nyquist rate with negative feedback and digital filtering in order to exchange resolution in time for that in amplitude. These converters are especially insensitive to circuit

imperfections and component mismatch, and therefore provide a means of exploiting the enhanced density and speed of scaled digital VLSI circuits so as to avoid the difficulty of implementing complex analog circuit functions within a limited analog dynamic range.

1.2.

Choosing the specifications for an analog circuit for given design objectives is potentially a very complicated and time consuming process. This task is further made difficult by the fact that the number of specifications to deal with is usually very large, and varies over wide ranges from one application to another.

Design of an analog system primarily consists of three obstacles: [1] Selection of architecture. Determining the specifications of the analog building blocks necessary to implement the chosen architecture. Minimization of the effects of circuit non- idealities.

For a long time, most of the building block specifications and non- idealities were explored at the transistor level. This required simulation over the full range of these variations which took multiple simulations even for single architectures. With this method, the entire procedure must be carried out for each of the architectures selected, which accounts for a lot of time too.

With the constant changes in technology, it is more amenable to consider a design process that is independent of technology. In present day System-on Chip design there is an increasing demand for systematic top-down design methodology. This methodology enables the designer to choose the right parameters for the individual building blocks constituting the system, starting from the system specifications.

In the design of high- resolution Switched-Capacitor (SC) Sigma-Delta modulators we typically have to optimize a large set of parameters, including the performance of the building blocks, in order to achieve the desired signal-to- noise ratio. This work aims to suggest a design methodology which the designer can use to tackle these large parameters.

1.3.

Thesis Outline

Chapter 2 discusses the concepts and architecture of Sigma-Delta modulators long with a brief introduction to other conversion methods. This chapter further explores various noise sources that are encountered in practical implementation of the Sigma-Delta modulators and their effect on the performance. Chapter 3 deals with various design methodologies that currently exist and proposes Simulink models for modeling of electronic systems. The chapter then extends to derive the Simulink models for sigma-delta modulators. Chapter 4 presents circuit design issues of various building blocks for these modulators and aims at designing a sigma-delta modulator for prescribed performance using the methodology developed in previous chapters. A conclusion chapter gives some discussion on the future work.

2.

2.1.

Introduction

Analog-to-digital interfaces are becoming increasingly important as translators between the real analog world and efficient digital processing systems. A/D converters have existed for along time and a number of implementation techniques for them have been developed, but in the recent times sigma-delta modulators have gained popularity. This chapter examines what makes sigmadelta modulators different from other conversion techniques. Merits and de-merits of the different topologies and techniques used for high performance sigma-delta modulators are also discussed. The chapter ends with a discussion of various non- idealities encountered in practical implementation of the modulator which degrade the modulator performance.

2.2.

Analog to Digital conversion of a signal requires two operations, namely Sampling and Quantization. In the sampling process a continuous time signal is sampled at uniformly spaced times intervals (Ts). The signal can be reconstructed back to the continuous time provided the sampling frequency (f s) is at least twice the bandwidth of the signal (f b ) as per Nyquist sampling theorem.

Quantization refers to the process of mapping an infinite number of input amplitude values to a finite number of output amplitude values. Thus Quantization error refers to the difference between the original analog amplitude and the quantized digital amplitude. The quantizer in any ADC is a non- linear system. To make its analysis tractable we can linearize it by modeling it as a noise source e[n] which is added to sampled signal x[n], to produce the quantized output signal y[n], i.e. y[n] = x[n] + e[n] Equation 2-1

If x[n] is active, e[n] can be approximated as an independent random number uniformly distributed between ?/2[2]. The quantization noise may be treated as white noise with power:

1 + / 2 2 2 Pe = e de = 12 / 2

Equation 2-2

This is independent of frequency, f s. Also the spectral density of e is white (i.e. a constant over frequency) and all of its power folds into the frequency band f s/2. Then the spectral density of sampled noise is given by

E( f ) =

Pe 1 = f s 12 f s

Equation 2-3

2.3.

Performance of Nyquist rate converters is limited by the technology in which they are fabricated as the resolutions of these converters rely on the matching between the components. For an N-bit ADC, the matching should be at least 1/2N. However, matching of components to greater than 10

bits is difficult in any normal CMOS process technology. Hence, high resolution data converters are extremely difficult to attain without the use of techniques such as trimming of components or calibration.

The case where f s=2f b is known as Nyquist rate sampling and the anti-aliasing filter before the ADC should have a very sharp cut-off. This is a huge drawback especially if these ADCs are used in receiver chains as the design and integration of such analog filters is no n-trivial.

2.4.

Oversampled conversion is a technique that improves the resolution obtained from straightforward Nyquist rate conversion. Oversampling refers to acquiring signals from the analog waveform at a rate significantly higher than the Nyquist rate. Each of these samples is quantized by an N bit ADC. Since quantization is described by equation 2-1, the total amount of noise power injected into the sampled signal, x[n] is given by equation 2-2. This is the same noise power produced by a Nyquist rate converter but its frequency distribution is different because of the higher sampling rate. In the oversampled case the noise power is uniformly distributed between f s/2 to f s/2.

As shown in Figure 2.1 the noise power in the oversampled case has been spread over a bandwidth equal to sampling frequency f s which is much greater than the signal bandwidth. Only a relatively small fraction of noise power falls in the band [-f b f b ], and the noise power outside signal band can be greatly attenuated with a digital low-pass filter following the ADC. After the

low-pass filtering has been performed, the signal can be downsampled to the Nyquist rate without affecting the signal to noise ratio. The collective operation of low-pass filtering and down-sampling is known as decimation.

3H I

IV

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Figure 2.1: Quantization noise PSD for Nyquist rate and Oversampled converters

We define the oversampling ratio, OSR, as OSR = band is reduced to [3, Chapter 14]

Pe =

2 1 12 OSR

Thus every doubling of OSR decreases the quantization noise power by one-half, or equivalently 3 dB.

2.5.

As seen in the section above, the in-band noise can be substantially reduced by oversampling. Sigma-delta converters go a step ahead and use feedback in addition to oversampling to further

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suppress in-band quantization noise. This can be accomplished by what is termed as Noise Shaping, wherein the noise transfer function is made to have a high-pass filter characteristic. This decreases the in-band quantization noise but amplifies the noise outside the signal bandwidth. The noise power outside the bandwidth can then be removed by the digital decimation filter.

Figure 2.2 shows a block diagram of sigma-delta modulator and the linearized model of the same are shown in Figure 2.3. The input to the circuit feeds to the quantizer via an integrator, and the quantized output feeds back to subtract from the input signal. The feedback forces the average value of the quantized signal to track the average input. Any persistent difference between them accumulates in the integrator and eventually corrects itself. The integrator is modeled as a function H(z) and quantizer as a noise source e(n).

From the linear model in the figure above we can derive output Y (z) = H ( z) 1 .X ( z) + . E (z) 1 + H (z) 1 + H ( z)

Thus the signal experiences a different transfer function than the error.

2.5.1.

-1 STF(z) = z and Noise transfer function N (z) = 1- z-1 . Thus the input appears without any TF

change at the output (but with a delay) and noise goes through a high-pass filter. A block diagram of such a choice is shown in Figure 2.4.

For this configuration, the in-band noise power can be calculated as [3, chapter 14]

2 P Pe 3

' e

1 OSR

Where N refers to the number of bit the quantizer has. Here we see that doubling the OSR gives an SNR improvement of 9dB as compared to 3dB for oversampling without noise shaping.

Though easy to implement, the quantization noise from a first-order modulator is highly correlated [4] and the oversampling ratio needed to achieve resolution greater than 12 bits is prohibitively large.

The second order sigma-delta modulator is a widely used one. This modulator has a noise transfer function which is a second-order high pass function. For this modulator the signal transfer function STF(z) = z-1 and the noise transfer function is given by NTF(z) = (1 z-1 )2 . The block diagram implementing these functions is shown in Figure 2.5.

In a way similar to above, it can be shown that in-band noise power and SNR are,

Pe' Pe 4 1 5 OSR

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SNRmax = 6.02N + 1.76 12.9 + 50log (OSR) Thus, we see here that doubling the OSR improves the SNR for a second-order modulator by 15dB.

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In order to achieve high resolution by pushing more quantization noise outside the signal band, higher order NTFs have to be implemented. shows a magnitude vs. frequency plot for first-order to fourth-order NTF. As can be observed the in-band error decreases but the out-of-band error is amplified. The next section deals with various architectures that can be used to implement higher order NTFs.

Figure 2.6: Magnitude vs Frequency plot for first, and higher order ? ? modulators

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2.6.

With the foregoing discussion we can conclude that sigma-delta modulators give us 3 degrees of freedom, namely, the quantization level (N), the OSR and the order of the modulator. Based on these degrees of freedom, different modulator topologies can be obtained. Sigma-delta modulators can be classified into two broad groups: single-loop and multi- loop cascaded modulators.

2.6.1.

Low order sigma-delta modulators, the first and second order discussed above, offer advantage of having guaranteed stability, have a simple loop filter design and simple circuit. But these modulators have low SNR and very high oversampling ratios are required for achieving high SNR, at the same time they are more prone to idling tones. Idle tones are stable sequences output by a nonlinear network in the prolonged absence of input; they are manifested as multiple highamplitude single- frequency components in the output of the converter.

In principle, arbitrary higher-order loop filters can be configured by connecting more integrators. The high-order modulator is expected to have a high SNR even for modest oversampling ratios, provide better immunity to idling tones and, as they involve simply expanding the configuration, they have a simple circuit design. However the stability of these loops becomes precarious for loop filters of order greater than 2. Linearized analysis, which results in NTF(z) = (1 z-1 )L, is not a reliable predictor of the stability, since the 1-bit quantizer is a grossly nonlinear element whose equivalent gain varies abruptly with the value of its input. It is shown [5, chapter 3] that for

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guaranteed stability the equivalent quantizer gain must be high. Thus, with the fixed output amplitude, this will be achieved only if the quantizer input is small. To ensure this, the maximum amplitude of input must be restricted to fairly low values, so as to inversely decrease the dynamic range. In practice, the loop filter need to be carefully designed and the stability may be signal dependent.

2.6.2.

The multi-stage sigma-delta modulator consist of first and/or second order modulators stages in cascade as shown in Figure 2.7. The input to the first stage is the signal to be modulated. The consecutive stages modulate the quantization error of the previous ones. The outputs of the stages are suitably combined so that at the output of the modulator only the input signal and signal- independent noise shaped by (1- z-1 )L are present. This design gives very high SNR and is free of stability problems associated with the higher-order single stage converters as multi- stage modulators inherit the excellent stability properties of their low-order stages.

As there are no stability constraints in their design, any increase of their order by cascading more stages results to an increase of the SNR. The limit to this increase is the matching of the digital and analog parts which requires complex switched-capacitor circuits. The component of the output noise due to leakage of the lower-order shaped noise becomes relatively larger compared to the increasingly higher-order shaped noise term of the final stage.

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z 1 1 z 1

z 1 1 z 1

z 1 1 z 1

Y1 = z-1 X + (1 - z-1 ) E1 Y2 = z-1 (-E1 ) + (1 - z-1 ) E2 Y3 = z-1 (-E2 ) + (1 - z-1 ) E3 Y = z-2 Y1 + z-1 (1- z-1 ) Y2 + (1- z-1 )2 Y3 Y = z-3 X + (1 - z-1 )3 E3

2.6.3.

Multi-bit Modulators

The above mentioned configurations can be implemented using multi-bit quantizers; employing a multi-bit quantizer can increase SNR by 6 dB for every doubling in the number of quantizer levels. Thus, a multi-bit modulator can achieve resolution comparable to that of a single-bit modulator at a lower sample rate, which is a significant advantage in applications requiring high

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bandwidth such as digital video. Furthermore, if multi-bit quantizers are used in single-loop structures, the system is more stable as the hard non- linearity of the quantizer is less pronounced in this case. The extra quantization levels allow for large dither signals at the quantizer input, hence eliminating idling tones.

There are some limitations to the applicability of multi- level quantization within sigma-delta modulators. The primary limitation is that a multi-bit DAC needs to be incorporated along with an ADC. While a single-bit feedback DAC is linear, the multi-bit DAC is limited by component matching of its individual elements. Further, the error generated due to the DAC non- linearity is only shaped by STF and hence will not be suppressed by the modulator noise-shaping. Consequently the DAC linearity should be as high as the desired modulator resolution. This becomes difficult to achieve without element trimming. Another limitation stems from the fact that the digital decimation filter hardware following the multi-bit quantizer must allow for multibit inputs. Different techniques have been presented that alleviate the linearity problem encountered in multi-bit quantizer. These include like digital correlation [6], dynamic element matching [7] and mismatch shaping [8] to suppress the nonlinear DAC noise.

2.7.

The implementation of various sigma-delta modulators above assumed the use of ideal components, which is not true in practice. There are several non-idealities which generate additional noise in the practical sigma-delta modulator, on top of the quantization noise. This section discusses various non idealities and how they limit the performance of a sigma-delta

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modulator. The proper modeling of these non- idealities can help predict the performance of the modulator at the early stages of design. Here we only discuss the non-idealities and their modeling is discussed in next chapter.

2.7.1.

Circuit Noise

Intrinsic noise refers to noise that is generated in the device itself, as opposed to noise that couples in from an external interfering source, Intrinsic noise cannot be eliminated by shielding, filtering, or circuit layout, since it is a property of the device, but its value can be altered by choice of circuit topology and component size. The two major sources of noise in sigma-delta modulators are the thermal noise of the switches and the op-amp noise.

Thermal noise is caused by random fluctuation of carriers due to thermal energy and is present even at equilibrium. Because of this, it needs to be taken into account for both the switches and op-amps in a switched-capacitor circuit. Thermal noise has a white spectrum and a wide band, limited only by the time constants of the switched capacitors or the bandwidths of the op-amps. As shown in [5, chapter 11] for a sampled circuit with a resistor R and capacitor C, the noise can be found by modeling the resistor as having a noise source in series with a power source equa l to the Johnson noise 4kTR? f. The total noise power can be found by evaluating the integral

e =

2 T 0

4kTR 1 + (2fRC )

2

df =

kT C

Where k is the Boltzmanns constant and T the absolute temperature. Thus we see that the thermal noise is generated in the resistor, the total noise power depends only on the capacitor.

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The integrators of a switched capacitor modulator may include more than one input branch (typically two, input and feedback), each contributing to the total noise power.

2.7.2.

A major component of a switched capacitor sigma-delta modulator is the integrator made using an Op-Amp. An ideal integrator has infinite dc gain, infinite bandwidth, no slew rate limitation and no saturation limits. 2.7.2.1. Limited DC Gain

The ideal integrator with infinite dc gain has the transfer function z 1 H (z) = 1 z 1 But the dc is limited by the circuit constraints and hence causes integrator leak. The consequence of this integrator leak is that only a fraction of P0 of the previous output of the integrator is added to each new input sample. The integrator transfer function in this case becomes H (z) = g 0 z 1 1 P0 z 1

And the dc gain is H0 = g0 /(1-P0 ). The limited gain at low frequency reduces the attenuation of the quantization noise in the baseband and consequently results in an increase of the in-band quantization noise.

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2.7.2.2.

The integrators constructed from amplifiers with a single dominant pole are observed to have an exponential impulse response. The time constant of the response, t, can be nearly as large as the sampling period T. This constraint is considerably less stringent than requiring the integrator to settle to within the accuracy of the A/D converter. Simulation results indicate that for values of t larger than the sampling period, the modulator becomes unstable.

In typical sampled-data analog filters, the UGB of the operational amplifier must be at least an order of magnitude greater than the sampling rate. However, simulations show that for sigmadelta modulators implementation of the integrator using operational amplifiers with UGB considerably lower than this, and with correspondingly inaccurate settling, will not impair the sigma-delta modulator performance, provided that the settling process is linear.

2.7.2.3.

Saturation

The limited output swing of Op-Amps is a major concern with decreasing bias voltages. This requires use of modified architectures to make sure that the signal swing at the output of the integrators is within the limits. This is further discussed in the next chapter. 2.7.3. Comparator Offset and Hysteresis

The impact of comparator non- idealities is much lower than those of the integrator due to the position of the comparator in the modulator loop. The imperfection in the comparator can be considered as another noise source which adds to e[n], the quantization error. However, this

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noise from the extra source is subjected to noise shaping by the modulator and so its affect on SNR degradation is not significant.

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3.

3.1.

Introduction

Choosing specifications for an analog circuit is potentially a very complicated and time consuming process. Thus, in a design it is better to perform analysis at the system architectural level before starting transistor level design; this reduces the number of design iterations and helps exploring the design options better. The ultimate goal being the low level circuit parameters dictated by the selected architecture and desired performance.

Sigma-Delta Modulators being mixed-signal nonlinear circuits pose significant problem in estimation of their performance. Hence in order to achieve the performance objectives, it is required that various parameters describing the circuit performance be optimized carefully prior to and during modulator design. For a systematic design of Sigma-Delta Modulator we can enumerate the following tasks Topology and accompanying topology parameter selection Analysis of the impact of circuit non- idealities on the system performance and specification of the resulting building block performances. Design, optimization and simulation of the building blocks and the system followed by performance evaluation.

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3.2.

Modeling Approaches

Various approaches have been used for accurate modeling of Sigma-Delta Modulation which includes device models, circuit macro- models, time-domain macromodels, finite-difference equations, table- lookup models, harmonic balance methods and behavioral models [5, chapter 14].

Device models are small and large signal models of active devices used in a circuit simulation such as SPICE, though accurate, they take extremely long simulation time. Circuit macromodels as discussed in [9] are models of circuits made up of several active and passive components; it is less complex that the original circuit and uses circuit specifications as model parameters. Though this approach provides a good accuracy, the speed improvement with respect to device models is poor. Time domain macromodels [10, 11] are based on a set of time-domain equations derived for a specific circuit and use circuit specifications as control parameters but are designed strictly for transient analysis and are generally not used with a circuit simulator.

Finite-difference equations are based on the z-transform function of sampled-data circuits. Using difference equations results in small and efficient simulation programs, such as MIDAS [12] for oversampled converters and SWITCHCAP2 for switched-capacitor circuits. They provide quickest simulation of all methods but are poor in non- idealities modeling capabilities. Tablelookup models use a two-step approach to modeling. The first step is to extract a table of input and output points for the original circuit with the use of a high accuracy simulator followed by

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using the stored table of points instead of the original circuit for further transient simulations [13]. This method seems limit the simulated performance of oversampled converters to 80 dB [5, chapter 14].

Envelope following or harmonic distortion balance method [14], simulates clocked circuits in which the waveform is similar from cycle to cycle. However, the states of an oversampled converter can change significantly from cycle to cycle and the states are not periodic. Hence, the simulation of oversampled converters is an inappropriate target for the harmonic balance method. Table 13.1 gives comparison of various models [5, chapter 14]

Circuit-based macromodels

Time-domain macromodels

Difference equations

Acceptable speedup over device models; can achieve accurate modeling of static errors

Unclear how to optimize table building; only model static errors; size of table increases with the square of the circuit states; tables are not reusable

22

Thus a simulation strategy that provides good speed of simulation, modeling capabilities and reusability is needed. A way to do this is behavioral modeling where the circuit is split with multiple nonlinearities into a set of linear circuits that are solved explicitly before simulations [5, chapter 14]. During simulation, the program determines the correct linear circuit to use and applies the pre-solved equation to calculate the next piece of the transient response.

This chapter proposes a top down design methodology for design of Sigma-Delta Modulators which involves choosing the initial topology followed by behavioral modeling to select appropriate circuit parameters. The program Simulink has emerged as a powerful tool for mathematical analysis in recent times, but its use to simulate electronic circuits has been very limited. The method used here uses Simulink for behavioral modeling of electronic components and overcomes the disadvantages of the other methods by providing an accurate, fast and flexible method with good user interface for simulating non- linear mixed signal like Sigma-Delta Modulators.

3.3.

Design Methodology

3.3.1.

Topology Selection:

The following formula gives a relationship among SNR, OSR and Modulator order for a SDM with a one-bit quantizer, assuming an input amplitude equal to the modulator output amplitude and a perfect differential noise transfer function of (1 z-1 )2 [3].

3 2L + 1 SNR = 10 log 10 . 2L .M 2 L +1 2

23

It can be used to as a first step in order to determine the OSR and Modulator order that will be required to obtain a particular SNR. Figure 3.1 shows the theoretical maximum SNR that could be achieved using higher order modulators for various OSR; following it is Figure 3.2 which shows the maximum SNR that can be achieved practically. The SNR can be improved a little by spreading the NTF zeros across the band of interest in a manner that minimizes the in-band noise. [5, chapter 4]

This formula needs to be used with a caution though as it gives a good indication for low OSR values but with increase in OSR the validity of the formula decreases. Figure 3.1 suggests that a SNR of 160 dB would result from a 5th order NTF at an oversampling ratio of 64, but Figure 3.2 shows that due to the limitation imposed by stability, the achievable SNR is 60 dB lower.

24

Figure 3.2: Maximum SNR achievable by modulators of order n with coincident zeroes

The next step is estimation of the maximum SNR for a given order and topology using behavioral simulations. As mentioned earlier, Simulink has been used here to perform behavioral simulations (Figure 3.3). This diagram clearly shows the advantage of this approach over others. As could be seen the implementation is easy and all basic buildings are provided in the library. The integrator has been implemented using a discrete filter block and comparator using the block sign (output =1 for input > 0 else output = -1).

25

3.3.2.

Signal Scaling

Signal scaling refers to selection of gain factors in front of each integrator. It is necessary to place an appropriate attenuation factor to avoid clipping at the integrator outputs for large input signals. The goal of signal scaling is to maximize the dynamic range by using all of the available swing without clipping [15]. Figure 3.4 shows the simulated output waveforms for a second order modulator with and without scaling. As could be seen the outputs at integrators can grow very large (which is impossible to achieve with the implementation) if scaling is not done.

A one-bit quantizer has the property that the signal gain that comes before it is unimportant, as it only detects the polarity. Improper scaling will have a tremendous impact on the dynamic range of the modulator. It is shown [16] that if the input to the quantizer is distributed between Vqi

26

and the output is 1, then the power of the quantization error is 1-Vqi+V2 qi and the distribution is not uniform for Vqi ?1. This shows that pre-quant ization gain affects the quantization error.

Different approaches have been proposed to solve this problem [17, 18, 19]. One pragmatic approach is to consider a linearized quantizer model and adjust the quantizer gain such that the total gain around the outermost feedback loop is unity. This empirical technique has little rigorous justification but simply produces analytical results that agree with simulation.

Following are the criteria that should be kept in mind while deciding upon the gain coefficients: All of the output swing of the integrators should be used without signal clipping. The number of unitary capacitors used should be minimal. The digital scaling should be easily implementable (applies for multistage and multibit modulator).

Once the order and topology is determined, various non- idealities (both intrinsic and extrinsic) that would be encountered in the implementation of the system can be incorporated to analyze their effect on the performance.

3.3.3.

The switch therma l noise is superimposed to the input voltage x(t) leading to

y (t) = x (t) +

4 KT .n (t ) Cs

27

The factor of 4 accounts for the two path through which noise is sampled (during F1 and F2) and the fully differential structure of the circuit. The n(t) denotes a Gaussian random process with unity standard deviation. If there are two input branches (to incorporate two different coefficients, one for the signal and one for the feedback), each branch has to be modeled with a separate kT/C noise.

The switching noise is modeled as shown in Figure 3.5 and is incorporated as an addition to the input to the modulator.

The effect of kT/C noise on the output PSD is shown in Figure 3.6. As could be seen the introduction of this noise raises the output noise floor and as predicted by the equation the increase of capacitance reduces the noise.

28

3.3.4.

The model shown in Figure 3.7 is used to simulate the effect of the operational amplifier noise. Then Vn represents the total RMS noise voltage of the operational amplifier referred to the input. The effect of this noise on the output PSD is similar to the above shown kT/C noise.

29

3.3.5.

The following model in Figure 3.8 shows the implementation of practical a Op-Amp with limited DC gain a. Figure 3.9 shows the effect of limited gain on the SNR for a second order modulator. H (z) = z 1 1 z 1

30

3.3.6.

The behavioral model of limited bandwidth and slew rate is implemented using the MATLAB function which calculates output y depending on the input x and value of UGB and SR. The following flow chart shows the algorithm for the same.

1 2UGB

x > SR

t1 =

x SR

Ts < t1

y = sgn( x ). SR.Ts

Ts t1

y = x 1 e Ts /

31

4.

4.1.

Introduction

The previous chapter discussed the new design methodology using Simulink and how the required circuit performance matrices could be determined using the same. This chapter focuses on the circuit design of the building blocks needed to implement the sigma-delta modulator. These include switched-capacitor integrators, operational amplifiers, comparators and the clock generation circuitry.

An experimental prototype sigma-delta modulator is designed for audio frequency range of 20 kHz to achieve a SNR of 80 dB [15] in a TSMC035 process with a single power supply of 3.3 V.

4.2.

Topology selection

Using MATLAB simulation, we can conclude that a second order modulator with an OSR of 128 should be sufficient for obtaining the result. As mentioned above, for a conventional sigma-delta modulator, the signal range required at the outputs of the two integrators is several times the full scale analog input range; thus a modified modulator architecture which reduces the signal range at the outputs of the integrator considerably is used. The modified architecture which is a slight

32

variation of the classical model is shown in Figure 4.1. It is advantageous from the circuit simplicity, noise and power dissipation to make the two gains of the first integrator equal so that sampling network can be shared between the input signal and the feedback signal. Thus keeping a1 = b1, we can derive other parameters from the MATLAB simulation as described below.

The variation of SNR with a1 and a2 is shown below in Figure 4.2. As can be seen a1 = 0.5 gives us the maximum SNR, along with Figure 4.3 showing the output density at integrator 1 and as could be seen output goes farther tha n 1.1 which is difficult to achieve in a low voltage design. Hence a1 = 0.4 was chosen which compromises a little of the SNR. Also there is no effect of a2 on the value of SNR (which is predictable as it is only the gain before the quantizer). The output density at Integrator 2 is used to determine the value of a2. Figure 4.4 shows integrator 2 output density as function of various integrator gains for a1 = 0.4. As could be seen for a2 = 0.4 the output goes a little farther than 1.1 which is acceptable [4]. In the similar way a3 is varied and there is not a huge advantage obtained by making a3 different than a2, hence a3 is made same as a2 which simplifies the circuit.

33

Figure 4.3: Output density at Integrator 1 and 2 for a1 = 0.5 and a2 varying from 0.1 to 0.9 34

Figure 4.4: Output density at Integrator 1 and 2 for a1 = 0.4 and a2 varying from 0.1 to 0.9

A fully differential architecture has been used in this design as it has superior power supply rejection ratio along with providing twice the output swing for a given supply voltage. In addition, the symmetry of a fully differential circuit provides for cancellation of even order distortion components, regardless of their cause.

4.3.

Integrator design

The most important component of a sigma-delta modulator is the integrator, the design of which is discussed below. Figure 4.5 shows a simple realization of a parasitic- insensitive single ended integrator [3, Chapter 10] which consists of an op-amp, a sampling capacitor Cs, a feedback

35

capacitor Cf and four switches S1 to S4. In the sampling mode S1 and S4 are on and S2 and S4 are off, allowing the voltage across Cs to track Vin while the op amp and Cf holds the previous value. In the transition to the integration mode, S4 turns off first, S1 turn off next and subsequently S2 and S3 are turned on. The charge stored on Cs is therefore transferred to Cf through the virtual node.

To reduce charge- injectio n effects in SC circuits, a two phase clocking scheme as shown in Figure 4.6 is used, the clocks are arranged so as to turn off S2 and S4, which are near the virtual ground node of the op-amp, slightly ahead of their counterparts. Another factor which needs to be considered during the layout of the integrator is the connection of the bottom plate of the capacitor across the op-amp. Integrated capacitors are not generally symmetrical and there is a larger parasitic capacitance to the substrate from the bottom plate than from the top plate. The capacitors should be connected such that the common plate is driven either directly or through a switch by a voltage source or the output of the op-amp. This arrangement causes the parasitic capacitance to have the least effect on the operation of the circuit. Also, substrate noise coupling is reduced by this arrangement.

36

6 W

6 W

6 W

6 W

Figure 4.6: Two phase non-overlapping clocking scheme

All the switches S1 S4 are realized using minimum sized NMOS so as to minimize parasitics, while maintaining good conduction for low enough analog common mode voltage. However transmission gates are used for the switches coupled to the input signal, since they must conduct over a wide range of voltage.

Figure 4.7 shows a fully differential implementation of the integrator which is similar to the above mentioned integrator except the difference of the feedback voltage Vref The operation of the integrator is similar to the one discussed above except that the voltage transferred to the

37

output is the difference between input voltage Vi and the feedback voltage Vref when the switches S2 and S3 are turned on.

4.3.1.

Clock generator

A simple schematic [20] is used to generate such a two-phase non-overlapping clock as shown in Figure 4.8. The outputs C1 and C2 are a pair of non-overlapping clocks, while the outputs C1A and C2A refer to slightly advanced version of C1 and C2 respectively. Similarly, the outputs C1N and C2N are complementary parts of C1 and C2.

38

4.3.2.

The operational amplifier used in the integrators is the most critical element of the modulator. The design of proper op-amp involves a great amount of theoretical calculations and empirical simulations to achieve fast speed and sufficient gain.

Different op-amp topologies were considered and the feasibility to this design was analyzed. A single stage telescopic cascode op-amp could have offered a high gain and a good bandwidth but it also has lowest output signal swing (important criteria for low-voltage designs). A two-stage amplifier can meet the gain and output swing requirements but is slower as compared to the one stage amplifiers. Thus folded-cascode op-amp as shown in Figure 4.9 is a good choice providing a good combination of swing and bandwidth with a disadvantage of being somewhat noisier than other topologies. The basic idea of folded-cascode Op Amp is to apply cascode transistors to the input differential pair but using transistors opposite in type from those used in input stage.

The following design equations can be used to choose various parameters for the device size in the Op Amp [21]. Unity Gain Frequency

t =

g m1 CL gm6 t C L1

Phase Margin

Slew Rate

SR=

39

W/L 160 / 1.5 114 / 1.0 210 / 1.5 62.5/1.2 37.0 / 1.2 37 .0/ 1. 0

40

From MATLAB behavioral simulation we obtain that the Op Amp should have gain of at least 60 dB, a UGB of 60 MHz and SR of 150V/s.

Assuming a load capacitance of 5pF, the slew rate requirement gives us the bias current equal to 1.5 mA. Overdrive voltages of 500 mV, 400 mV, 300 mV were chosen for transistor pairs M4-5, M6-7, and M8-11 respectively giving us the W/L ratios as given in the table. Using these ratios as a preliminary step and after a few iterations, the Op Amp was made to give the required gain, bandwidth and slew rate.

4.3.3.

Bias circuit

This work utilizes a constant-transconductance bias circuit using wide swing cascode current mirrors [3, Chapter 6] for generation of reference voltages. A conventional cascode current mirror is shown in Figure 4.10 (a).Although its output impedance is increased to rds1(rds2gm1), a cascode current mirror reduces the maximum output-signal swing so that the minimum allowed voltage for Vout is Vtn greater than 2Veff, where Veff is the minimum drain-source voltage needed to keep a transistor working in the saturation region. This loss of signal swing is a serious disadvantage for modern VLSI technologies.

An alternative circuit shown in Figure 4.10 (b) that does not reduce the signal swing so much while keeping high output impendence, called a wide-swing cascode current mirror, can be used. The basic idea of this is to bias the transistors at the edge of the triode region. Thus the minimum allowable voltage just needs to be greater that (n+1)Veff. If n is unity (keeping Ibias = Iin ), this

41

mirror can guarantee that all of the transistors are in the saturation region even when Vout drops to small values.

(n +1 )2

W /L

W /L n2

W /L n2

W /L

W/L

Figure 4.10: Conventional cascode mirror and Wide-swing cascode current mirror

The advantages of the wide-swing current mirror is coupled with a constant-transconductance bias circuit wherein the transistor transconductances are stabilized using resistor RB and setting (W/L)2 = 4(W/L)3 . This configuratio n causes the transconductance of M3 to be stabilized to

gm3 = 1 RB

Since all transistor currents are derived from the same biasing network and the ratios of current are mainly dependent on the geometry, the transconductance of all n-channel transistors is stabilized to

g mi =

(W / L) i I Di gm3 (W / L ) 3 I D 3

p (W / L) i I Di g m3 n (W / L) 3 I D 3

g mi =

The transistors M15 M18 have been added to act as start- up circuitry by injecting currents into the bias loop in case all the currents in the loop are zero. Once the currents are set up, the start-up circuit is disabled by M15 and M16 turning off.

42

Figure 4.11: Bias Circuit Transistor M1, M 4 M2 M3, M12 M5 M6, M 9, M10 M7, M 8, M11 M14 M13, M15, M16, M17 M18 W/L (m/ m) 15.0 /3. 2 60.0 / 2.0 15.0 / 2.0 3.5/ 3.2 45.0 /3. 2 45.0 / 3.2 15.0 /3. 2 20.0/2.0 4 / 60

Table 4.2: Transistor W/L ratios for Bias Circuit (RB = 3k)

43

4.3.4.

One requirement of using fully differential Op Amps is that a common- mode feedback (CMFB) circuit must be added to establish the common- mode output voltage. This is due to the fact that while using fully differential Op Amps in feedback applications, the feedback determines the differential signal voltages but the common mode voltage is not affected. Thus it is necessary to have a circuit to determine the output common mode voltage and to control it to some specified voltage. The CMFB ideally will keep this common- mode voltage immovable, preferably close to halfway between the power-supply voltages, even when large differential signals are present. Without it, the common- mode voltage is left to drift, since the common- mode loop gain is not typically large enough to control its value. The performance requirements on the CMFB circuitry are not nearly as stringent as for the main op amp, because the signal of interest is the difference between the main op amp outputs.

There are two typical approaches to design of CMFB circuits namely, continuous time and switched-capacitor approach. The later is popular with the switched-capacitor circuits since it introduces clock-feedthrough glitches in continuous-time applications. Figure 4.12 shows a CMFB circuit used in my work. It may be seen that capacitors CC form a voltage divider to generate the average of the op amp output voltages, which is used to generate control voltage for the Op Amp current sources. CMOS transmission gates are used to realize the switches connected to the outputs of the op amp, in order to accommodate a wider signal swing. The switched capacitors C S (20 fF) are set to about one quarter to one tenth the size s of the nonswitched capacitors CC (100 fF) so as to avoid common- mode offset voltages and op amp overload [ chapter 6]. All the switches are implemented using minimum sized n-channel 3,

44

transistors except for the switches connected to the outputs which are implemented using transmission gates.

4.4.

The second major building block in a sigma-delta modulator is the comparator which quantizes a signal in the loop and provides the output of the modulator. The principle design parameters of this comparator are speed, which must be adequate to achieve the desired sampling rate, input offset, input-referred noise and hysteresis. Since the comparator appears after the loop gain block and before the output terminal, non-idealities associated with it are shaped by the loop in the same way that the quant ization noise it produces is shaped. Therefore, the performance of the modulator is relatively insensitive to offset and hysteresis (i.e. the tendency that a comparator might have to stay in the previous direction when it should toggle to another direction) in the first-stage comparator.

45

A fast regenerative latch [22] without pre-amplification and offset cancellation, as shown in Figure 4.13, has been used to implement the comparator. It consists of discharge transistors, an n-channel flip flop with a pair of n-channel transfer gates for strobing, p-channel flip flop, and pchannel pre-charge transistors.

In this latch, the cross-coupled devices M2A M2B and M3A M3B are strobed at their drains, rather than sources. Advantages for a flip- flop strobed at drain node over a flip-flop strobed at source node exist in regard to regeneration speed and offset. Since carrier mobility is nearly twice faster at zero substrate bias than at a few volt substrate bias conditions, regeneration speed for the flip- flop is faster for the drain strobing scheme. In addition, since strobing transistors isolate the flip- flop, load capacitance becomes only the gate capacitance of the flip- flop itself. Offset voltage caused by a channel length fluctuation, which is estimated as the main source of total offset voltage, is much lower at zero volt substrate bias. Therefore, transistor channel lengths can be decreased and the flip- flop speed can be made faster as a result. An inverting buffer is connected to both the output nodes of the p-channel flip- flop to give the same loading effect to the flip- flop. Since the analysis is in discrete time, a latch is needed for holding the output during the feedback. Hence, we can use a SR latch with NOR gates.

46

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4.5.

Simulation

An important difference between conventional converters and oversampling ones involve testing and specifying their performance. With conventional converters there is a one-to-one correspondence between input and output sample values, and hence one can describe their accuracy by comparing the values of corresponding input and output samples. In contrast there is no similar correspondence in oversampling converters because they inherently include digital low-pass filters, and hence each input sample contributes to a whole train of output samples. Consequently, it has been useful to borrow techniques from communication technology to describe the performance of oversampling converters.

47

The transient analysis of the whole modulator is very time-consuming, A 1 millisecond transient simulation takes more than 72 hours to complete and equivalent time is required to extract the final data for analysis. All of the above circuits were simulated using Cadence ICFB analog simulation tool. The simulations used SPICE MOSFET models measured from a specific process run (Appendix B). Each individual block was verified followed by simulation of the comp lete second order modulator. The results of final simulation are then extracted and ported in MATLAB and analyzed.

Figure 4.14 shows the open- loop frequency response of the folded-cascode Op Amp with 10fF load capacitance. The ac analysis of the Op Amp circuit shows a dc gain of 62dB and a unity gain frequency of 65MHz, which are expected and required for good resolution of the modulator.

Figure 4.15 verifies the proper operation of the comparator (y and ybar) for a constant voltage on positive terminal and a sine wave input on the negative terminal.

Figure 4.16 shows the FFT magnitude plot (214 points) for the extracted output from the sigmadelta modulator. Following it in Figure 4.17 the power spectral density plot for the same is shown. As can be seen the output has a single tone at frequency of 10 kHz and a very little noise in the frequency of interest. The modulator gives a SNR of 75dB for an input sine wave at 10 kHz.

48

Figure 4.14: AC analysis of folded cascode Op Amp showing gain and phase margin

49

50

5.

Conclusion

This thesis dealt with mixed-signal modeling, simulation and implementation of high-speed Sigma-Delta Modulators. This work outlines a top-down design procedure that a novice designer can follow in order to develop the modulator as per the specification.

A novel method of using Simulink for modeling of electrical systems has been explored. Behavioral modeling of the modulator is performed by developing a Simulink model of the modulator and taking into account major non- idealities, such as sampling noise, operational amplifier limited gain, bandwidth and slew rate. Based on these simulations, all building-block specifications have been systematically derived. A 3.3 V, 75 dB sigma-delta modulator has been designed for audio range in TSMC 0.35 m CMOS technology using the specifications obtained from these simulations. As could be seen from the simulations the circuit performance corresponds very closely to the results obtained by behavioral modeling. Although the result is a little less than expected it could be improved by using detailed models for all components and running simulations for a longer time.

Sigma-delta modulators have been discussed here but this work is equally applicable to design of other non- linear and mixed-signal systems lke phase locked loops. In order to improve the i modeling accuracy other models for clock jitter and non- linear switch resistance can be added. Also because simulations take a lot of time, a new method which would reduce this time would

51

increase the productivity to a large extent. Since the modulator is to be incorporated with a digital filter, use of advanced analog- mixed signal simulators (AMS) for the complete performance characterization would be advantageous.

52

Resolution: The number of bits of resolution refers to the smallest analog input level to cause change in the digital output word. Thus, an n-bit resolution implies that the converter can resolve 2N distinct analog levels.

LSB (Least Significant bit): One LS B = (full-scale input voltage)/resolution. For example, with input full scale = 5V and resolution = 10bits, then 1 LSB = 5/210 = 4.9mV

Differential Nonlinearity (DNL) Error: In an ideal converter, each analog step size is equal to 1 LSB. After the offset and gain errors have been removed, DNL error is defined as the variation in analog step size away from 1 LSB. Thus, a converter with a maximum DNL of 0.5 LSB has its step size varying from 0.5 LSB to 1.5 LSB. For an ADC, when the DNL reaches 1 LSB or greater, there will be missing output codes.

Integral Nonlinearity (INL) Error: The INL is the worst-case deviation from a straight line between zero and full-scale endpoints of the converters transfer response, expressed in LSBs. An ADC is guaranteed not to have any missing codes if the maximum INL error is less than 0.5 LSB.

53

Accuracy: The absolute accuracy of a converter is defined to be the difference between the expected and actual transfer responses, which included the offset, gain, and nonlinearity errors. The relative accuracy is the accuracy after the offset and gain errors have been removed, which is usually referred to as the maximum INL error. Accuracy can be expressed as a percentage error of full-scale value, as the effective number of bits, or as a fraction of an LSB. For example, in order to achieve LSB integral linearity, an 8-bit accuracy implies 1/28 = 0.4^ matching, while a 12-bit accuracy implies 1/212 = 0.025% matching. Note that a converter may have a 12bit resolution with only 10-bit accuracy, or 10 bit resolution with 12-bit accuracy. An accuracy greater than the resolution means that the converters transfer response is very precisely controlled.

Signal-to-Noise Ratio (SNR): This is the ratio of the original input signal power to the background noise power, or equivalently, the rms ratio of the input signal amplitude to the noise amplitude. For an ideal ADC with a sinusoidal input, the SNR related to the resolution n is SNRrms = 6.02n + 1.76 dB

Dynamic Range: The dynamic range of the converter is usually specified as the ratio of the rms value of the maximum amplitude of the sinusoidal input signal to the rms output noise plus the distortion measured when the same sinusoid is present at the output. The rms output noise pulus distortion is obtained by first eliminating the sinusoid from the measured output. Dynamic range can also be expressed as an effective number of bits. Essentially, this is an indication of how far it is possible to go below the full-scale input signal without hitting the noise and/or distortion.

54

* run N88Y .MODEL tsmc35N NMOS ( +VERSION = 3.1 +XJ = 1.5E-7 +K1 = 0.5307769 +K3B = 0.2012165 +DVT0W = 0 +DVT0 = 0.112017 +U0 = 444.9381976 +UC = 7.067896E-11 +AGS = 0.2810374 +KETA = -7.8181E-3 +RDSW = 925.2701982 +WR = 1 +XL = -2E-8 +DWB = 5.851691E-9 +CIT = 0 +CDSCB = 0 +DSUB = 0.0257957 +PDIBLC2 = 1.787424E-3 +PSCBE1 = 6.973485E9 +DELTA = 0.01 +UTE = -1.5 +KT2 = 0.022 +UC1 = -5.6E-11 +WLN = 1 +WWL = 0 +LW = 0 +CAPMOD = 2 +CGBO = 0 +MJ = 0.3557696 +MJSW = 0.1 +PK2 = -4.805372E-3 ) LEVEL = TNOM NCH K2 W0 DVT1W DVT1 UA VSAT B0 A1 PRWG WINT XW VOFF CDSC ETA0 PCLM PDIBLCB PSCBE2 MOBMOD KT1 UA1 AT WW LL LWN CGDO CJ CJSW PVTH0 WKETA 11 = 27 = 1.7E17 = 0.0199705 = 2.836319E-6 = 5.3E6 = 0.2453972 = 2.921284E-10 = 1.130785E5 = 2.844393E-7 = 0 = -1E-3 = 7.186965E-8 = 0 = -0.132935 = 8.607229E-4 = 2.128321E-3 = 0.6766314 = 0 = 1.46235E-7 = 1 = -0.11 = 4.31E-9 = 3.3E4 = 0 = 0 = 1 = 1.96E-10 = 9.276962E-4 = 3.181055E-10 = -0.0252481 = -7.643187E-4

TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG PRT KT1L UB1 WL WWN LLN LWL CGSO PB PBSW PRDSW LKETA

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

7.6E-9 0.4964448 0.2963637 2.894802E-7 -0.032 -0.171915 1.773281E-18 1.1356246 5E-6 1 -1E-3 1.735515E-9 -1.712973E-8 0.5710974 0 0 1 0.7873539 0.05 0 0 -7.61E-18 0 1 1 0 1.96E-10 0.8157962 0.6869149 -96.4502805 -0.0129496

55

Tsmc35P

* run n88y .MODEL tsmc35P PMOS ( +VERSION = 3.1 +XJ = 1.5E-7 +K1 = 0.4564781 +K3B = -2.8930965 +DVT0W = 0 +DVT0 = 1.1744581 +U0 = 151.3305606 +UC = -8.97321E-12 +AGS = 0.3961954 +KETA = -9.27E-3 +RDSW = 2.30725E3 +WR = 1 +XL = -2E-8 +DWB = 1.378919E-8 +CIT = 0 +CDSCB = 0 +DSUB = 0.2436027 +PDIBLC2 = 4.256073E-3 +PSCBE1 = 1.347622E10 +DELTA = 0.01 +UTE = -1.5 +KT2 = 0.022 +UC1 = -5.6E-11 +WLN = 1 +WWL = 0 +LW = 0 +CAPMOD = 2 +CGBO = 0 +MJ = 0.5490877 +MJSW = 0.1997417 +PK2 = 1.011593E-3 ) LEVEL = TNOM NCH K2 W0 DVT1W DVT1 UA VSAT B0 A1 PRWG WINT XW VOFF CDSC ETA0 PCLM PDIBLCB PSCBE2 MOBMOD KT1 UA1 AT WW LL LWN CGDO CJ CJSW PVTH0 WKETA 11 = 27 = 1.7E17 = -0.019447 = 2.655585E-6 = 5.3E6 = 0.7631128 = 2.061211E-10 = 9.915604E4 = 6.493139E-7 = 0 = -1E-3 = 5.962233E-8 = 0 = -0.15 = 6.593084E-4 = 0.0286461 = 4.3597508 = 0 = 5E-9 = 1 = -0.11 = 4.31E-9 = 3.3E4 = 0 = 0 = 1 = 2.307E-10 = 1.420282E-3 = 4.773605E-10 = 6.58707E-3 = -0.0101398

TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG PRT KT1L UB1 WL WWN LLN LWL CGSO PB PBSW PRDSW LKETA

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

7.6E-9 -0.6636594 39.382919 1.51028E-7 -0.032 -0.1035171 1.823477E-18 1.1210053 4.273215E-6 1 0 4.30928E-9 -1.596201E-8 2 0 0 7.447024E-4 0.0120292 3.669793 0 0 -7.61E-18 0 1 1 0 2.307E-10 0.99 0.99 -93.5582228 6.027967E-3

56

BIBLIOGRAPHY

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[2] P. M. Aziz, H.V. Sorensen and J. V. Spiegel, An overview of Sigma-Delta converters, IEEE Signal Processing Magazine, vol. 13, no. 1, pp. 61 84, Jan. 1996.

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