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PicoBlaze is similar in architecture to many small microcontrollers but it is specifically designed and optimized for implementation in an Xilinx FPGA. Note there are also larger microprocessors that can be synthesized into FPGAs such as the 32-bit MicroBlaze microprocessor. PicoBlaze (and MicroBlaze) are referred to as soft core processors as they are synthesized from an HDL and use only the Programmable Logic Blocks and Routing of an FPGA for their implementation. A second type of FPGA processor termed hard core, such as the PowerPC, are physically incorporated in the architecture of some FPGAs.
The process of implementing any soft core microcontroller or microprocessor in an FPGA will be similar to that described below for PicoBlaze. This tutorial assumes that you have downloaded the PicoBlaze.zip files from the R: drive or web page and extracted all of the files into your working directory. These files include everything needed to synthesize the example program. PicoBlaze (see Figure 1) consists of two key parts: 1) The Processor Core: KCPSM3 ( which stands for Ken Chapman Programmable State Machine version 3 ) 2) The Program Memory ( from which instructions are fetched and executed by the processor core.) Note: that the program memory is referred to as an Instruction ROM or Program ROM in Xilinx PicoBlaze documentation since the processor core cannot write to the Program Memory.
Figure 1 Figure 1 shows the Input and Output Ports of KCPSM3, with their widths. These will usually correspond to internal signals within the top level module.
The KCPSM3 requires approximately 96 slices in a Spartan3.) specific to Spartan 3 and. These files are available in PicoBlaze. as a result. .As a result.exe) from your assembly language program.psm file must be 8 characters or less.vhd on the other hand.vhd) and the ROM file (tut1_rom. This ROM File is generated automatically by the Assembler ( pBlazIDE or KCPSM3. The Program Memory file.vhd) there is a VHDL file to drive the seven segment display on the S3 Starter Board and the UCF file for the S3 Board. but the Inputs and Outputs will require a Selection Statement. The toplevel file should be be mainly structural in content. instantiating the components and linking the processor to the ROM and the IO. MUX. is a VHDL ROM file which contains the user’s desired program to be executed by the PicoBlaze core. KCPSM3. as a result. Figure 2 ISE PicoBlaze Project Figure 3 PicoBlaze occupancy in an XC3S200 Figure 2 shows the Xilinx ISE Implementation Project Files for a simple PicoBlaze Project. this VHDL file should not be modified by the user. is assembled prior to synthesis. FFs etc. there are two corresponding VHDL files that are used to construct the complete PicoBlaze with program: i) The PicoBlaze file.psm file ) Note that the prefix for the .vhd is optimized for Spartan 3 by calling design primitives LUTs. ii) The program to be executed is initialised in the Block RAM during the download of the overall design (including PicoBlaze and other user logic) and. Figure 3 show how little space PicoBlaze takes up in the Spartan3 FPGA. “name_rom”. ( .) This Program Memory is implemented in a single Block RAM in the FPGA configured to function as a 1K×18-bit ROM.zip In addition to the PicoBlaze core file (kcpsm.
Figure 4 PicoBlaze.vhd’ is a library file which contains the component declarations.zip Files The Files provide . In most cases the actual programmed processor will perform as the simulator predicts. . The User Interface of this program is shown in Figure 5. S3_Board_UCF is the ucf file for the Board and maps the Ports of the VHDL entity onto the correct FPGAS pins. ‘myparts. This application is extremely useful as it allows the designer to fully simulate the assemble code and check its operation.psm file and compile it into a VHDL ROM file it is best to use the application pBlazeIDE.
Figure 5 pBlazeIDE User Interface Files .
Programming PicoBlaze Programming the processor in Assemble Language is interesting and informative.vhd) and the psm file.vhd". this is the PORT_ID allocated to the LEDs DSOUT $04 DSOUT $05 DSOUT $06 The next set-of-lines allocate the I/O Port numbers to the input and output objects on the board. "tut1_rom. BUTTONS_port SWITCHES_port char21 char43 LEDS_port DSIN DSIN $02 $03 . “tut1_rom” from the template rom file (S3_template_rom. A Block diagram of PicoBlaze is given in Figure 6. this is the PORT_ID allocated to the Switches .psm File VHDL "S3_template_ROM. this is the PORT_ID allocated to two lower SSDs . this is the PORT_ID allocated to two upper SSDs . which is also very limited (See Figure 7) can be split into seven groups: Figure 6 Figure 7 PicoBlaze Instruction Set Files Example . There are only 16 Registers and 2 Flags. 64 Byte Scratchpad RAM The Instruction Set. There are however 256 x 8 bit I/O connections.vhd) with the entity named. this is the PORT_ID allocated to the Buttons . These must correspond with the associate ports in the top level VHDL file: . "tut1_rom" This first line creates the VHDL rom file (tut1_rom. You can see that the hardware resources are very limited.vhd".
end case. if rising_edge(clk) then in_port_reg <= in_port.case port_id is when x"02" => in_port <= "0000" & btn. end if. end case. if (write_strobe='1') then case port_id is when x"04" => seg7chars(7 downto 0) <= out_port. Note the output (write strobe) port must be clocked. Figure 8 Setting the Port_ID using VHDL Case Statements in the Top Level Module . when x"06" => leds_reg <= out_port.char43 -. when x"03" => in_port <= swt. -.buttons -.switches end if. when x"05" => seg7chars(15 downto 8) <= out_port.char21 -.
LEDs_port CALL delay100ms . 00 LOAD sC. LOAD s1 with the number on the Switches (0 to FF) ? . rep05 . $01 COMP s9.) delay100ms: LOAD sA. one 'off' . 00 ADDC sC. LOAD s0 with the number on the Buttons (0 to FF) ? . repeat 6x for flashing lights at start . 01 ADDC sB. LOAD s0 with the hex number AA . OUTPUT 55 to the LEDs . Repeats if s9 NON ZERO Here is a part to output the buttons to the LEDs and output the switch value to the SSD start : IN s0. LEDS_port CALL CALL LOAD OUT CALL CALL delay100ms delay100ms s2. Note: AA is two ‘on’. two ‘off’ SUB s9. SWITCHES_port OUT s1. LOAD s2 with the hex number 55 . LEDS_port delay100ms delay100ms . $AA s2. ( As a 50 MHz Flash would be too quick for the eye. OUTPUT Switches to the lower two chars of SSD . $00 JUMP NZ. 00 RET Z JUMP delloop . $F8 delloop: ADD sA. $55 OUT s2. Note: 55 is one 'on'. Subtract 1 from s9 for number of flashes . char21 CALL CALL delay100ms start Here is a delay loop. COMPARE S9 WITH ‘0’ . 01 LOAD sB. OUTPUT s0 (Buttons) to the LED Display IN s1. OUTPUT AA to the LEDs .Here is a part of a program to Flash the LEDs six times: rep05: LOAD s9. BUTTONS_port OUT s0. $05 LOAD s2.
ADD all the files except the Template ROM and the psm files. Figure 9 Digilent S3 Starter Board Figure 11 PicoBlaze Project Tree 1. Figure 11 PicoBlaze Project Tree . The Project File tree should look like that shown in Figure 11. This should contain all the file shown in Figure 10 below: Figure 10 PicoBlaze. Open up a New Project in the Xilinx ISE Environment.PicoBlaze Tutorial This tutorial demonstrates a simple PicoBlaze processor implementation on the Digilent S3 Starter Board. You can use this as a learning exercise and as a basis for more complex designs.zip file. Download the picoblaze.zip Files 2.
4. (‘9’) All LEDs light to indicate end of computation.Simulation and Run Figure 13 Left: ‘6’ is input using Btn 1 Middle: ‘3’ is input using Btn 2 Right: Numbers are ADDed by pressing Btn3. c. Open up the psm file tut1. Synthesise and Implement the Project as it is. the Lower two Seven Segment Display digits should light with the value on the Switches and the lower four LEDs should light when the corresponding buttons are pressed. You can use the simulation capability of the pBlazeIDE to demonstrate the correct functionality. Now the task: a. Change the assembly language code so that it can remember two numbers input from the Switches and add them together.3. displaying the result on the SSD.psm using pBazeIDE. Figure 12 pBlazeIDE Assemble. . Once correct re-synthesise the Project and demonstrate the correct operation on the Board. downloading the bit into the XC3S200 FPGA on the Starter Board. b. After a dazzling display of flashing lights.
Appendix Differences between pBlazeIDE Instructions and KCPSM3 Instructions: .
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