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5 C-simulator for Bluetooth modem

This analysis of the new Bluetooth standards has been performed in order to understand its functionality and to evaluate the performance of the new modulations: /4-DQPSK and 8DPSK. To satisfy this goal, it is necessary to use a simulation program that covers the entire functionality of the modem part. The performances of the new modulations are calculated referring to the bit error rate (BER) value. In the same way, an ANSI-C Simulator program was written to simulate the previous Bluetooth standard based on GFSK modulation. The EDR standard is an improvement of the Basic Rate; in this way, the existing simulator was reused to analyse its functionality and to perform the necessary modifications in order to implement the new BT-modem parts.

5.1 C-simulators flowchart: modulator block

It should be clarified that this simulator covers the complete functionality of the modem part, considering the baseband signal only. The flow diagram of the C simulator1 is later on described, with specific regard to the EDR modifications. As shown in the figure below, the simulator structure is composed of a preliminary block aimed to read data from file. At this level, C simulator reads two kinds of information from the specified files: the various parameters used during its computations and the correct ROM filter tables. In this case, every ROM table has been stored in several files derived from a MATLAB code, prepared to be read by C program.
Some explanations of the C-simulator will not be provided in order to respect internal STMicroelectronics rules, on company confidential information.


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Input from File

Simulation Parameters ROM Filter values

Generate Data slots


Required data slot Data Type & Length Adjacent & Mirror slots


? /4-DQPSK Mapping 1 MHz


GFSK modulation

8-DPSK Mapping

Gaussian Filter 26 MHz Noise AWGN Cycle for each Data Analog Calculations

TX SRRC Filter Wanted signal Mirror signal Adjacent signal

Modulator Module

Transmission block


Reception Filter Mixer Complex BPF Gain adaptation



13 MHz 6.5 MHz


R X Filter

RX SRRC Filter

EDR Timing Recovery

Timing Recovery


Demodulator Module

GFSK Demodulation 1 MHz

/4-DQPSK Demodulation

8-DPSK Demodulation

BER evaluation

Figure 5.1 Flow Diagram of the C-simulator.


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As hinted in the previous chapter, this analysis involves three different filter lengths: [ 2T , 2T

[ ; [ 2.5T , 2.5T [

and [ 3T , 3T [ .

In addition, the used implementations can be specified: filtering through Look-up table exploiting the Odd-symmetry of the input data sequence or polyphase filter network with the filters coefficients symmetry. In this way, six different combinations may be obtained, they will be tested during the simulations. When these two parameters are fixed, the simulator then picks and reads the correct file where the related filter ROM values are stored. Furthermore, there are many input parameters that set the simulators functionality. Only a simple description of the most interesting cases is given. As mentioned in the second chapter, the modulation type is specified with the packet type inside the Header part. Due to this, the modulator block is able to recognise which modulation (GFSK, /4-DQPSK or 8DPSK) must be utilised during the next transmission. Inside the C simulator, this information is given by a parameter. For BER purpose, the interest is focussed only on the ACL data packets, and it is useful to summarise in the table here below the several bits lengths for each packet. These will be used during the next BER evaluation on Payload data only.
# slots GFSK length EDR length Payload length DM1 DH1 DM3 DH3 DM5 DH5 2-DH1 2-DH3 2-DH5 3-DH1 3-DH3 3-DH5
1 1 3 3 5 5 1 3 5 1 3 5 286 366 1126 1622 1950 2870 126 126 126 126 126 126 0 0 0 0 0 0 488 2992 5488 732 4484 8236 160 240 1000 1496 1824 2744 468 2972 5468 702 4454 8206

Table 5.1 Bits length for both GFSK and EDR parts.

The Access Code and Header is always transmitted with GFSK modulation, and the modulation block switches to the EDR part, respecting a fixed Guard Time. In


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comparison, the demodulation can begin only on receipt of a starting signal from the Baseband module. This behaviour takes place inside the C simulator along with another vital parameter, that specifying the time delay from the end of the GFSK part. The second block generates three different data slots: Wanted, Adjacent and Mirror. The wanted data slot respects the structure of the data packets (Access Code, Header and Payload) shown above. It is possible to select the kind of data to transmit inside the Payload data part, such as random bits or a determined bits sequence (that is, 0000, 1111 or 1010). In addition other methods of working, such as Lap or Whitening may be simulated, but those specifically belonging to GFSK modulation are not of interest for this scope. The adjacent and mirror data slots are introduced in order to simulate the behaviour of the modulator block under general chip working conditions. They are built using random data and during the digital modulation are combined with the wanted data slot to obtain the complete transmitted signal, as described below. Further analysis shows that the flowchart is composed of a large loop that scans every data slot. The modulator and demodulator (modem) computations are repeated for each data bit of the three different slots. As mentioned in the previous chapter with regards to the modulation part, a sampling frequency FC equal to 26MHz is used in order to satisfy the Nyquists Criterion: FC = 26 MHz >> 2 FIF + B 3MHz . (5.1)

In this case, thanks to an internal loop the modulator calculations are repeated T/TC = 26 times for each data bit. In this way, the modulated baseband signal may almost be considered as a continuous time signal. In this way a good example for the EDR modulated signal, useful for the simulations is performed. At this point, the modulator part is indeed simulated. The modifications regarding the new modulations are introduced in parallel to the previous GFSK block. As known, GFSK modulator reads only 1 bit from the data slots and performs the baseband signal through the Gaussian filtering. Furthermore, referring to the EDR modulations types, the C program covers the complete functionality of both the


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Mapping blocks and SRRC filter. Thus respects faithfully the EDR specifications that have already been completely analysed. When the modulation type is established, C simulator modulates each data slot using the correct branch. Furthermore, it is able to internally build some ideal baseband signals that are then used for comparison with regard to the simulated signals. Finally, the output filter values are sent to the transmission block and in turn its functionality is established by other input parameters. First of all, it is possible to set the power of the transmitted signal, considering the three components together (wanted, adjacent and mirror signals) or rather the power for each signal can be fixed separately. It is useful to consider relations signal and clarify their functionality. The wanted signal is built to simulate the EDR signal, modulated by the frequency carrier: Wanted signal:
I (t ) = A cos[2 (FMIS + FIF ) t + FM + K (t )] ;


This equation shows only the In-phase signal, but this general behaviour is also valid for the In-quadrature signal. Both depend on several parameters: A is used to set the signal power; FIF is the frequency carrier value and a frequency offset value is considered resulting from FMIS. Finally K(t) is the filtered signal, modulated by GFSK or EDR blocks and FM is a phase shift that may occur during RF modulation. The adjacent or interfering signal considers the effects due to the presence of other ISM signals on the adjacent channels to the frequency carrier. Its behaviour may be summarised in the next relation, considering the In-phase signal once again: Adjacent signal:
IADJ (t ) = AADJ cos[2 (FMIS + FIF + FADJ ) t + ADJ ] ;


where AADJ fixes the signal power, FADJ is the adjacent channel frequency value and ADJ is the phase delay among this signal and the wanted one. In comparison, the mirror signal involves the effects due to the signal modulated by an opposite frequency carrier value (-FIF). It considers the components belonging to the mirror signal that fall down inside the wanted signal channel.


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Mirror signal:

IMIR (t ) = AMIR cos[2 (FMIS FIF ) t + MIR ] .


In the same manner, AMIR fixes the power of the mirror signal, and MIR is the phase delay in comparison to the wanted signal. The signal (composed by the sum of the three signals, described above) is now transmitted and C program simulates the behaviour of the channel. An Additive White Gaussian Noise has been selected as channel model, with a PSD equal to: S NOISE ( f ) = NO / 2 for < f < + . (5.5)

It is an approximated characterization frequently used during analysis of modulation schemes. In this case, this model may be considered valid, because Bluetooth devices operate in short range radio links. Furthermore, it is supposed that fading does not exist. At this point, it should be clarified that the C simulator functionality can be split into three principal blocks, summarised below. The first block builds the transmitted signal for both the modulation types (GFSK or EDR), respecting the ideal case as seen above. The second block contains the algorithms used in order to implement the RF analog work. This part simulates the principal analog effects and its description is given in the following paragraph. Finally, the third block involves all the digital calculation, such as demodulation and timing recovery. These effects will be completely analysed in the next chapter.

5.2 Analog Receiver part

It is necessary to underline that this analysis simulates the chip functionality in the time domain with special regard to the several power signal values. As shown, it is possible to set the transmitted signal power, which becomes the input signal for the reception part. At this level, also setting the noise signal power as well as the Noise Figure of the receiver block means the Signal to Noise Ratio (SNR) value related to the complete demodulation system can be directly obtained. Moreover,


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the sensitivity value of the RF receiver block is calculated and will prove useful for the BER evaluation; to be further examined later. The radio front-end is usually the most costly part of a wireless network interface. In typical radio receivers, the RF filters, oscillators, and image-reject mixers process input signals at high frequencies. To keep costs down, Bluetooth recommends shifting the input signal to a lower intermediate frequency (FIF), which allows on-chip construction of low power filters. Shifting to low FIF, however, creates new problems, such as reduced receiver sensitivity.
Mixer Receiver block LP Filter

Complex BPF
1 MHz



2.4 GHz

Digital Down Mixer


Decision Block



Demodulator block

Figure 5.2 C-simulator scheme of the Reception & Demodulator block.

A description follows of the entire functionality of the reception module, as shown in the figure above. In fact, the RF transmitted signal centred on 2.4 GHz into the ISM band is received and filtered by the Reception band-pass filter. An analog Down-Mixer and a Complex BP filter are then used to achieve the bandpass signal, which occupies a 1MHz-band centred on the FIF frequency value. A Voltage Gain Adaptation (VGA) block is used in order to completely adapt the signal amplitude to the input dynamic range of the next modules. The signal is sampled with a sampling frequency FC equal to 13MHz and it is digitised using an A/D converter. As shown in the flowchart, it is also possible to simulate a demodulation block working at 6.5MHz (briefly described in the next paragraph). Finally, the baseband signal is obtained and the demodulation part may commence. As mentioned, the C program only covers the baseband signal part. Thus, the analog receiver block is simulated considering the involved effects and the functionality of the RF block is skipped. Firstly, the RF front-end device could not


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respect the power balance of the orthogonal I and Q received signals. This effect may be characterized by two input parameters for the C simulator: IQ-amplitude imbalance (), and IQ-phase mismatch (). The relations for the IQ-mismatches on the ideal I and Q signals, are given in the following equations, considering the baseband signals only: I MISM (t ) = [(1 ) cos( )] I (t ) + [(1 + ) sin ( )] Q(t ) ; QMISM (t ) = [(1 ) sin ( )] I (t ) + [(1 + ) cos( )] Q(t ) . (5.6) (5.7)

where IMISM(t) and QMISM(t) are the real and the imaginary parts of the complex IQ-mismatches signal. At this point, the C simulator through the analog calculation block implements the down-mixer, the complex BP filter and the VGA blocks, as shown. Their functionality is based on feed-back from both the timing recovery and demodulation blocks. In this case, the timing recovery block is able to modify the local oscillator frequency (FOL) value of the down-mixer. In this way, the real functionality of the mixer is simulated in order to achieve a complex signal centred on the correct FIF. Instead, the feed-back loop that involves the VGA module checks the amplitude of the input signal for the demodulation block and modifies the amplification inside the VGA block. It should be clarified that this block summarises all the gain values related to the other modules. Therefore, the Noise Figure value (see Appendix B) specified for this block is referred to the entire reception module. The A/D converter is now simulated, performing its internal functionality: the sampling block and the digital conversion. As mentioned, the modulated baseband signal is simulated with a sampled version at 26MHz. Inside the C program an input parameter that sets this sub-multiple value may be fixed, during the simulations. With regard to the digital conversion, the number of output bits for the A/D converter may be specified, in order to perform the functionality of the quantisation block. As known, this function involves some effects, such as rounding errors, which affect the performance of the demodulator block, with special regard to the BER value.


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5.3 Digital elaborations of the Demodulator part

The digitised baseband signal is now achieved thanks to the A/D converter block and it is sent to the demodulator part, where the three kinds of demodulations take place: GFSK, /4-DQPSK and 8DPSK. As the flowchart shows, the simulation of the EDR demodulator block is implemented in parallel to the GFSK case. At this point, interest is focussed on the baseband demodulator block, with special regard to the modification inserted by EDR part, as shown in the figure below.
6.5 MHz
Digital Elaboration block

FIR Filter


T delay

Digital Down Mixer

13 MHz

Demodulated Data slot


/4-DQPSK Demodulation

Vector Product block

Data stream 13 MHz / 6.5 MHz

Demodulator block

8-DPSK Demodulation

Symbols Extractor

1 MHz

Timing Recovery Algorithm

Figure 5.3 EDR Demodulator block working @ 13MHz & 6.5MHz.

The complex digitised input signal is split into the two real components: the Inphase and the In-quadrature digitised signals. At this point, each component is filtered by a SRRC filter, in order to respect the matching with the SRRC filter used in transmission. This filter behaviour has been selected by Bluetooth EDR specifications to achieve a Raised Cosine (RC) filter in order to reduce the level of Intersymbol Interference (ISI). As usual to implement these LP filters, a FIR filter structure has been chosen due to the input data may belong to a large amount of values. In this way, if an implementation through a look-up table or polyphase filter network is used, it should occupy a large chip area, without any advantage also regarding the power consumption, because every digitised data is process at


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the highest FC frequency value. Therefore, the C simulator reads the FIR filter coefficients (taps) from input data files and simulates the SRRC filtering for both the complex signal components. The problem using FIR filter architecture is depending on to the digitalisation process of the filter taps. Some rounding errors may occur, as well as it happens during the A/D quantisation process. For this reason an optimised implementation is required, also respecting the output dynamic range for both the digital filters. During the simulations, three filter lengths may be implemented: [ 2T , 2T ] ;

[ 2.5T , 2.5T ]

and [ 3T , 3T ]. It should be clarified that using a FIR filter

implementation, an uniform architecture is not required as well as in transmission (see Chapter 4), therefore the last taps corresponding to g(NT) is considered. Thus the filter sizes are achieved, as summarised in the table below:
[-2T, 2T ] FIR filter Taps 53 [-2.5T, 2.5T ] 65

[-3T, 3T ] 79

Table 5.2 FIR Filter taps using a sampling frequency of 13MHz.

With regard to the 6.5MHz case, it is clear that any sampling frequency could be used during reception module and the SRRC-Rx filters should be matched to the SRRC-Tx filter in any case. But as Figure 5.3 shows, after the SRRC-Rx filter, a sampled signal by 1MHz frequency value is required as digitised input for the demodulation block. Since an interpolation filter can not be implemented in transmission if the required frequency 1/TC of the filtered signal is not a whole multiple of the input frequency 1/T; at the same way, also the inverse function is not allowed. In this case, it should be clear that, using a simple samples-extractor inside the demodulator, the selection of the sample is allowed only if the sampling frequency is an integer multiple (M) of the output frequency value FS of 1MHz. This means that, one sample among the M samples will be selected every T
In [-2.5T, 2.5T] case, the extreme points 2.5T are not considered because are not a whole multiple of T/13 value.


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period. Therefore, the implementation of the 6.5MHz sampling frequency needs a preliminary Digital Elaboration block in order to perform an equivalent digitised signal, which is sampled using a whole multiple frequency of 1MHz. After this block, a FIR LP filter takes place. After the reception LP filter, for both the sampling frequency branches, the signal is elaborated through a Vector Product block. As shown in Figure 5.3, this module implements a particular algorithm that combines two digitised complex symbols, delayed by one T period. At first, this block was employed principally in support of the GFSK timing recovery module; but in this case, it results more useful for the EDR demodulation blocks. As analysed in the previous chapter, both the EDR modulation types are Differential. In this case, the information is carried by the phase difference among two consecutive complex symbols, transmitted every T period. In this way, if the vector product block should be able to yield directly the difference phase values, the demodulation function shall be already implemented. This solution may be carried out only using an arctangent function. As will be analysed below, this structure needs a large chip area occupation, therefore its behaviour is outside the aims of these simulations. Furthermore for the same reason, the implementation of the demodulator architecture avoids the use of arctangent function. Thanks to the 1MHz output signal of the vector product module, the demodulated signal is achieved through the Symbol-Extraction (S.E.) block. Its functionality is similar to a sampling structure: it selects one digitised symbol every T period in the position specified by the timing recovery block. This symbol is chosen among the 13 samples (or a whole number of samples, close to 6.5), belonging to the received digitised signal. Thus, the demodulated I and Q signals, composed of the phase values, are obtained and at this point a Phase Evaluation block is needed. As hinted above with regard of EDR modulation, the information is carried by the phase difference, therefore a differential phase evaluation function is required inside the demodulator block. Since an architecture based on the arctangent function to strictly evaluate the phase is not allowed; a module which demodulates


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the signal without getting an absolute value of the phase is needed. For the /4DQPSK and the 8DPSK demodulations, two different blocks to evaluate the phase difference have been implemented. Both are able to recognize in which region of the constellation points the received signal samples are located. The /4-DQPSK case uses a simple checking block, which controls in which phase quadrant the sample is located. Instead, for the 8DPSK case, eight constellation regions must be checked and the evaluation algorithm becomes more complex and more sensible to the errors may occur. Further, their works involves the demodulated output signal of the vector product block, as will be completely described in the next chapter. Finally, all these behaviour are simulated inside the C program, with special regard to the two new branches referred to 13MHz and 6.5MHz functionality. At the end of the C program computation, a BER evaluation block is implemented in order to compare the demodulated data with the transmitted data slot. This module is able to recognize the type of the used modulation (GFSK or EDR) and then checks the structure of the demodulated data slot, split in the three part: Access Code, Header and Payload. The previous GFSK block is reused to check the access code and header parts, due to are transmitter always by GFSK modulation. Finally, the simulations results are given, considering the bit errors that may occur inside only the Payload data packet. The Bit Error Rate value (BER) is defined by: # of bit errors # of transmitted bits



Therefore, the modification for the EDR BER evaluation have been introduced in this last block in order to check only the EDR-Payload data packet, without considering the Synchronous Sequence and the Trailer symbols.