PT 10

PEMP VSD534/ESE507

Routing Topology, Termination And Stack up Of High Speed Signals
Session 5 Session Speaker: Ugra Mohan Roy

© M S Ramaiah School Of Advanced Studies

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PT 10

PEMP VSD534/ESE507

Session Objectives:
To understand main issues in high speed board routing To develop best topologies and better termination techniques to over come issues on high speed boards Session deals different ways of PCB Stackups, and its advantages and disadvantages

© M S Ramaiah School Of Advanced Studies

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PT 10

PEMP VSD534/ESE507

Session Topics:
Main issues for routing
Routing topologies Rise and fall time degradation Signal Skew Line Termination

Power distribution and de-coupling PCB Stackup Return Path Discontinuities

© M S Ramaiah School Of Advanced Studies

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PT 10 PEMP VSD534/ESE507 Main Issues for Routing: Routing topologies and loading Impedance Rise and fall time degradation Signal Skew (Signal delay difference) Crosstalk Termination Signal return path © M S Ramaiah School Of Advanced Studies 4 .

PT 10 PEMP VSD534/ESE507 Point to Point Topology: This is the ideal topology but not very efficient in that it requires a lot of extra buffers. Always use this topology for critical clock trees. Use low skew clock buffers Skew can be compensated with delay lines © M S Ramaiah School Of Advanced Studies 5 .

PT 10 PEMP VSD534/ESE507 Fan / Star Topology This topology is routing efficient but put heavy load on the driver. Use drivers with low output impedance. Terminate properly at each receiver or reflections will propagate back and forth in the net. Be careful with the high power consumption of many terminated lines © M S Ramaiah School Of Advanced Studies 6 . especially where several lines fan out.

All ends (also driver) should be terminated properly for larger nets The driver will have to drive twice the amount of DC into the termination resistors.PT 10 PEMP VSD534/ESE507 T . © M S Ramaiah School Of Advanced Studies 7 .Topology This split will cause a 33% negative reflection if all lines are of same impedance.

Keep distance between loads so high that the signal can recover. Allow no stubs Keep tap load low.PT 10 PEMP VSD534/ESE507 Daisy Chain The preferred topology for high speed digital. Terminate in both ends. © M S Ramaiah School Of Advanced Studies 8 .

Since the high frequency components is damped more the signal will show slower rise times at the end of the line.PT 10 PEMP VSD534/ESE507 Rise And Fall Time Degradation Any lossy transmission line acts as a filter which filters the high frequency components first. © M S Ramaiah School Of Advanced Studies 9 .

Use only first incident clocking or better. Keeping low signal skew in a clock system is a challenge and there are several effects to consider. Keep every signal trace equally long Use low skew drivers Rise time degradation may pose a problem in calculated delay daisy chains. so trace lengths must be compensated. Poor decoupling influence rise time. reduce reflections to zero.PT 10 PEMP VSD534/ESE507 Signal skew Signal skew is the delay difference at inputs. © M S Ramaiah School Of Advanced Studies 10 .use only inner layers. Or . Signals travel faster at outer layers.

© M S Ramaiah School Of Advanced Studies 11 . Using one small via for several returns.PT 10 PEMP VSD534/ESE507 Signal Return Path The high frequency signals follow a mirror image of the trace on the ground plane. If the new reference plane is a power plane a low inductance decoupling is placed close to the signal via Using split reference planes. this may cause common mode problems. Do not degrade this return by: Changing to layers which have another ground-plane without placing a ground-ground via close to the signal via.

Keep meander lines at least 4 times the distance to ground plane apart to avoid distortion. this reduce distortion and keep inductance low.PT 10 PEMP VSD534/ESE507 How To Design Delay Lines Remember loss Use meander structure. be careful to avoid inductor effects. © M S Ramaiah School Of Advanced Studies 12 . Preferably use inner layers.

PT 10 PEMP VSD534/ESE507 Line Termination © M S Ramaiah School Of Advanced Studies 13 .

PT 10 PEMP VSD534/ESE507 Driven Line And Its Reflection Coefficients Z Z S = 30Ω 0 = 90 Ω Z L =1500Ω 1550 − 90 Γl = 1550 + 90 = 0 .9 30 − 90 Γs = = − 0 .8 30 + 90 © M S Ramaiah School Of Advanced Studies 14 .

0871 0.56 R eflec ted w 2.832 2.2768 R eflec te ‐1.995328 2.2768 ‐1.464 Γl = 0.3824 2.PT 10 Example Computation Of A Bewley Lattice Diagram PEMP VSD534/ESE507 Γs = −0.16 2.614 Γs = 30 − 90 30 + 90 Γl = 1550 − 90 1550 + 90 S ourc e end L oad end 2.895795 0.754586 0.24416 ‐1.728 1.8 2.56 1.4 T rac e1 4.0871 0.5555 2.614907 ‐0.464637 15 © M S Ramaiah School Of Advanced Studies .71664 1.55552 ‐1.9 4.832 T rac e2 R eflec ted W ‐1.4 2.75485 1.

© M S Ramaiah School Of Advanced Studies 16 .PT 10 PEMP VSD534/ESE507 Different Types Of Termination Series Termination – Resistor on driver side. Very much like a parallel termination but much better at terminating lines at 50 Ohm and below. Parallel termination – single resistor at end of line. Resistor value depends on driver output impedance and line wave impedance. Thevenin termination – Uses two resistors at the end of the line. Resistor value depend on line impedance and acts as in parallel with input impedance of receiver.

the longest unterminated line is 5cm. if using nonterminated nets do not use data before the reflections have settled. Reflections can cause double triggering. On FR-4 this mean that a 1ns rise signal. © M S Ramaiah School Of Advanced Studies 17 .PT 10 PEMP VSD534/ESE507 Why Terminate The Signals Termination is a method to match the driver line and receiver in such way that no reflections are generated. Generally the ideal would be to do a parallel termination in the line impedance Terminate critical lines that are longer than 1/3 of the rise time.

PT 10 PEMP VSD534/ESE507 Series Termination Used to match driver impedance Slow rise and fall times (Some times good. for instance to achieve low crosstalk) Absorb reflections if matched to line © M S Ramaiah School Of Advanced Studies 18 .

PT 10 PEMP VSD534/ESE507 Series Termination Series Termination: A termination is placed near the source. The disadvantage is that it loads the signal. The value of the termination Rt = Xline. © M S Ramaiah School Of Advanced Studies 19 . It could be also added within the chip.impedance(Zo)-Source output Impedance(Ro) The advantage of using this termination is that it occupies only small space of the board real estate.

© M S Ramaiah School Of Advanced Studies 20 .PT 10 PEMP VSD534/ESE507 What Happens To Reflections When You Put A Series Termination Series termination is always a compromise for CMOS drivers as the output impedance is not the same when the driver is pulling up or down. This is because the NMOS and PMOS in output buffer are not balanced.

especially for ECL.PT 10 PEMP VSD534/ESE507 Parallel Termination The termination of choice for high speed digital. PECL and other technologies intended for termination. 100% clean signals possible © M S Ramaiah School Of Advanced Studies 21 . High power consumption.

© M S Ramaiah School Of Advanced Studies 22 . The disadvantage of this termination is its power dissipation. A Thevenin equivalent could be used yet it can take more space and loads the signal further.PT 10 Parallel Termination PEMP VSD534/ESE507 Parallel Termination: It is placing a termination with value of the transmission impedance at the far end of the line.

Faster switching from 3-state Does NOT correctly terminate the line.PT 10 PEMP VSD534/ESE507 Thevenin Termination Ideal for bus termination or lines with 3-State drivers. 330 Ohm & 220 Ohm is often used. reflections will occur © M S Ramaiah School Of Advanced Studies 23 .

PT 10 PEMP VSD534/ESE507 DC Thevenin Termination. The second criteria is the Maximum current sunk by driver must be able to drive the receiver when the output voltage is a 1( high). R2 provides a DC path at the termination hence there is An additional Dc power consumption.Design Example Vdd R1 || R 2 = Z 0 R1 = Z 0 VT = Vcc Vcc R2 = Z 0 Vcc − VT VT Gnd R2 VCC R1 + R 2 R1 . © M S Ramaiah School Of Advanced Studies 24 .

max R1 R2 R1 R2 Iohl Ioll 150 150 -0.max R1 R2 (VCC − VOL ) (VoL ) − < I OL .PT 10 PEMP VSD534/ESE507 Current Driving Requirements For Thevenin Termination (VCC − VOH ) (VOH ) − > I OH .1 16.25 © M S Ramaiah School Of Advanced Studies 25 .67 165 135 -26mA 19mA 160 130 Zl=74.

Low power consumption (No DC consumption) Be careful with inductive capacitors. better for technologies not intended for termination. select capacitors with care. © M S Ramaiah School Of Advanced Studies 26 .PT 10 PEMP VSD534/ESE507 AC Termination AC or RC termination.

Larger capacitor values can lead to higher power Consumption at higher operating frequencies © M S Ramaiah School Of Advanced Studies 27 . Xc > 3Tr/Z0 . The two capacitors act as DC blocks. The capacitor value can be computed using the criteria that it should act as a DC cutoff. • This is also called a AC Thevenin termination.AC Termination – Thevenin without DC current PT 10 PEMP VSD534/ESE507 The two series capacitors allow the effectiveness of the Thevenin Termination without the DC current flow.

Outputs – Capacitance Tr 400 *10 −12 1200 −12 Xc = 3 =3 = 10 Z0 75 75 X c = 16 *10 −12 1 = 16 *10 −12 2πfC C = 16 *10 −12 * 2π * 400 *10 6 = 40212 *10 −6 C = 0. Line Impedance.04 F © M S Ramaiah School Of Advanced Studies 28 .PT 10 Capacitance Calculation for AC Termination PEMP VSD534/ESE507 Inputs – Rise time.

PT 10 PEMP VSD534/ESE507 AC Termination AC Termination: It is placing a termination at the far end in series with a capacitor. © M S Ramaiah School Of Advanced Studies 29 . Certainly the advantage of the termination would be having more output power which would could unfortunately lead to poorer signal integrity Advantages Active Termination consume less power. Diodes could be used to limit Overshoot and Undershoot. It takes less space and could be incorporated within the chip.

PT 10 PEMP VSD534/ESE507 Diode Termination Kills large over and undershoot Not generally useful in high-speed systems. (A design needing this type of termination have probably greater problems elsewhere) © M S Ramaiah School Of Advanced Studies 30 .

One terminator will terminate a minimum number of lines – say 16. • More expensive that resistors but with volume production terminator costs are less than 1 cent.PT 10 PEMP VSD534/ESE507 Active Termination Via ICs Active termination IC • Typically implemented as on–board SMTs. • The impedance and sunk current is programmable hence we have Better control of power dissipation. © M S Ramaiah School Of Advanced Studies 31 .

PT 10 Examples Of Termination Waveforms – Thevenin Vs Series Vs AC. PEMP VSD534/ESE507 SERIES TERMINATION THEVENIN TERMINATION AC PARALLEL TERMINATION © M S Ramaiah School Of Advanced Studies 32 .

© M S Ramaiah School Of Advanced Studies 33 .PT 10 PEMP VSD534/ESE507 Differential Trace Termination Differential lines also require a termination resistor if the line length exceeds the data rate The termination is placed at the destination To reduce the current consumption AC termination may be used The termination resistor [R] is selected to match the trace impedance [Zo] while the capacitor is selected by: Xc = [3 * Tr] / Zo.

PT 10

PEMP VSD534/ESE507

Power Distribution And De-coupling

How to supply the right voltage at the right place at the right time

© M S Ramaiah School Of Advanced Studies

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PT 10

PEMP VSD534/ESE507

Power Distribution
The ground and power system serves two purposes.
First to serve as a return path for the signal. Second to supply the devices with power.

The high frequency components of today is using a lot of power at a low voltage. The result is very high currents. A modern FPGA can draw several amperes the first nanosecond after switching. To meet these challenges one need a low inductance, low resistance and high capacitance power system.
© M S Ramaiah School Of Advanced Studies
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PT 10

Power Supply To PCBs

PEMP VSD534/ESE507

The system of GND and Power planes must provide stable power to all SOCs on a board. The input voltage as seen by the receiver is affected adversely by ground bounce generated especially by common path noise on the GND plane.

A B

A

Y

A B

C

Y

D SI

Q
DFF1

CLK
A B B A B D

Y

Y

© M S Ramaiah School Of Advanced Studies

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© M S Ramaiah School Of Advanced Studies 37 . Gate in the middle will switch this noise voltage to its output. When the Gate P switches the current from the battery will charge up the capacitive load. Additional inductance in power plane will generate a noise voltage across the L in power plane.PT 10 PEMP VSD534/ESE507 Impedance Between Power Pins Must Be As Low As Between GND Pins A B P A Y B Q Y A B R Y Return path is through the battery.

low inductance decoupling but it can not hold much charge.PT 10 PEMP VSD534/ESE507 Why Decoupling The high switching currents in today's components create a need for a local current supply with sufficient charge to avoid a severe voltage drop at the power pins. Closely spaced power planes give a good high frequency. © M S Ramaiah School Of Advanced Studies 38 . When these resources are exhausted on need larger supplies that are closer than the power supply.

A B A Y A B A Y A B A Y PEMP VSD534/ESE507 At DC the capacitors act as high impedance. For high frequency the Capacitors act as shorts. © M S Ramaiah School Of Advanced Studies 39 . The nearness of the GND and VDD plane also helps to supplement the bypass capacitors added.PT 10 There Must Be A Low Impedance Path Between VDD And GND The bypass capacitors and the separate Power and GND planes ensure the inductive noise will be minimized. The low impedance path between PWR and GND is provided by the bypass capacitors added.

PT 10 PEMP VSD534/ESE507 Effective Capacitance Provided by PWR and GND Planes A C = 8.5 for FR − 4 The effective Series resistance of bypass capacitors must be considered in calculating how Effective the bypasses are. Power and GND planes add an effective capacitance of 100pF/in2 between VDD and GND.  © M S Ramaiah School Of Advanced Studies 40 .854ε r pf d A Area of shared PWR − GND planes (inches 2) d separation between planes in inch ε r = Re lative permittivity 4.

13ohm A capacitor is often described with its resonance frequency Different dielectrics NPO.3nH. A 100nF capacitor can have C=84nF. R=0. X7R or Z5U have different properties. L=1. © M S Ramaiah School Of Advanced Studies 41 .PT 10 PEMP VSD534/ESE507 A Capacitor is Not a Capacitor fres = 1 2 π √ LC A capacitor is a passive device dominated by capacitance.

PT 10 PEMP VSD534/ESE507 A Capacitor is Not a Capacitor… Usually thin and wide X7R chips is the best choice for decoupling. To be sure on have to measure the inductance which is difficult To compare two capacitors of same nominal capacitance chose the one with the highest resonance frequency. So called high frequency capacitors is not necessarily less inductive © M S Ramaiah School Of Advanced Studies 42 .

the higher values (i.e.e.e. leaded capacitors is to inductive to be of any help.1µF capacitor for each power pin Use only chip capacitors.PT 10 Selecting Decoupling Capacitors PEMP VSD534/ESE507 Selecting a decoupling capacitor is not easy but some general rules apply: Select the smallest value that is sufficient to decouple the device. If you do not know what is sufficient choose one 100nF /0. 100nF) close to the power pin. © M S Ramaiah School Of Advanced Studies 43 . Decouple in levels with the smallest value (i. 10μF) evenly distributed. 47μF tantalum) close to the connector power pins. the medium values(i.

Set the via as close as possible to the capacitor. © M S Ramaiah School Of Advanced Studies 44 . it is important to keep the reference voltages steady. preferably in the pad. One capacitor for every power (and ground) pin is a good rule of thumb. Keep distance to pin very SHORT and the trace WIDE. Do not forget to place decoupling capacitors close to termination resistors.forget the capacitor.PT 10 PEMP VSD534/ESE507 Where To Place Decoupling Capacitors Get as close as possible to power and ground pins. you do not have to mount all of them in production if the system works with less. If too high . Calculate inductance.

Filters over the gap may cause problems. keep the split narrow and secure an AC return path. © M S Ramaiah School Of Advanced Studies 45 .PT 10 PEMP VSD534/ESE507 Splitting Power Planes Be very careful with splitting ground planes. Splits act as slot antennas and will radiate heavily. If you have to split. Remember that digital signals are broad band and that filters are narrow band.

1997 © M S Ramaiah School Of Advanced Studies 46 .PT 10 PEMP VSD534/ESE507 Microstrip Over a Slotted Ground Plane 1 2 3 4 IEEE Circuits & Devices Nov.

PT 10 PEMP VSD534/ESE507 PCB Stack Up © M S Ramaiah School Of Advanced Studies 47 .

A poor stack-up can increase the radiation from both of these mechanisms considerably.PT 10 PEMP VSD534/ESE507 General Aspects On Stack-up PCB stack-up is an important factor in determining the EMC performance of a product. as well as the cables attached to the board (common-mode emission). A good stack-up can be very effective in reducing radiation from the loops on the PCB (differential-mode emission). © M S Ramaiah School Of Advanced Studies 48 .

The ordering or sequence of the layers. The number and types of planes (power and/or ground) used. and The spacing between the layers. © M S Ramaiah School Of Advanced Studies 49 .PT 10 PEMP VSD534/ESE507 Board Stack-up Four factors are important with respect to board stack-up considerations: The number of layers.

the following should be considered: The number of signals to be routed and cost Frequency Will the product have to meet Class A or Class B emission requirements Will the PCB be in a shielded or unshielded enclosure The EMC engineering expertise of the design team. © M S Ramaiah School Of Advanced Studies 50 .PT 10 PEMP VSD534/ESE507 Board Stack-up (Cont…) In deciding on the number of layers.

PT 10 PEMP VSD534/ESE507 Board Stack-up (Cont…) Multi-layer boards using ground and/or power planes provide significant reduction in radiated emission over two layer PCBs. The ground plane decreases the ground impedance (and therefore the ground noise) significantly. © M S Ramaiah School Of Advanced Studies 51 . They allow signals to be routed in a microstrip (or stripline) configuration. – These configurations are controlled impedance transmission lines with much less radiation than the random traces used on a two-layer board.

5. 3.PT 10 PEMP VSD534/ESE507 Board Stack-up (Cont…) Five objectives on Multi-layer Board 1. Signal layers should be tightly coupled (close) to their adjacent planes. High-speed signals should be routed on buried layers located between planes. © M S Ramaiah School Of Advanced Studies 52 . A signal layer should always be adjacent to a plane 2. Multiple ground planes are very advantageous. since they will lower the ground (reference plane) impedance of the board and reduce the common-mode radiation. Power and Ground planes should be closely coupled together. In this way the planes can act as shields and contain the radiation from the high-speed traces. 4.

PT 10 PEMP VSD534/ESE507 Four-Layer Boards The most common four-layer board configuration is as below _____________ Sig. _____________ Ground _____________ Power _____________ Sig. The advantages of tight coupling between the signal (trace) layers and the current return planes will more than outweigh the disadvantage caused by the slight loss in interplane capacitance © M S Ramaiah School Of Advanced Studies 53 .

.) Layers are equally spaced Large separation between the signal layer and the current return plane Large separation between the power and ground planes Not sufficient inter-plane capacitance between the adjacent power and ground planes Decoupling will have to be taken care Opt for tight coupling between the signal and the current return plane © M S Ramaiah School Of Advanced Studies 54 .PT 10 PEMP VSD534/ESE507 Four-Layer Boards (cont.

PT 10 Four-Layer Boards (cont. © M S Ramaiah School Of Advanced Studies 55 .040") between the power and ground planes _____________ Sig. and use a large core (>0.010")..) PEMP VSD534/ESE507 To improve the EMC performance of a four-layer board is to space the signal layers as close to the planes as possible (<0. _____________ Ground _____________ Power _____________ Sig.

. © M S Ramaiah School Of Advanced Studies 56 .PT 10 PEMP VSD534/ESE507 Four-Layer Boards (cont.) Advantages The signal loop areas are smaller and therefore produce less differential mode radiation the tight coupling between the signal trace and the ground plane reduces the plane impedance (inductance) the close trace to plane coupling will decrease the crosstalk between traces Disadvantage For a fixed trace to trace spacing the crosstalk is proportional to the square of the trace height.

_____________ Power Advantage The planes on the outer layers provide shielding to the signal traces on the inner layers Disadvantage The ground plane may be cut-up considerably with component mounting pads on a high density PCB an exposed power plane the buried signal layers make board rework difficult if not impossible © M S Ramaiah School Of Advanced Studies 57 . _____________ Sig.. _____________ Sig.PT 10 PEMP VSD534/ESE507 Four-Layer Boards (cont.) _____________ Ground.

_____________ Sig.) _____________ Ground. The power should be routed as a grid../Pwr./Pwr. _____________ Ground Two outer planes are ground planes and power is routed as a trace on the signal planes.PT 10 PEMP VSD534/ESE507 Four-Layer Boards (cont. on the signal layers Advantages The two ground planes produce a much lower ground impedance and hence less common-mode cable radiation The two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a faraday cage © M S Ramaiah School Of Advanced Studies 58 . using wide traces. _____________ Sig.

PT 10 Four-Layer Boards (cont. PEMP VSD534/ESE507 Advantages Still provides for the low ground impedance as a result of two ground planes Disadvantage The planes however do not provide any shielding This configuration satisfies objectives (1)./Pwr.. (2)./Pwr. _____________ Ground _____________ Ground _____________ Sig. © M S Ramaiah School Of Advanced Studies 59 . and (5) but not objectives (3) or (4).) _____________ Sig.

________________Signal ________________Signal ________________Ground ________________Power ________________Signal ________________Signal One stack-up NOT to use on a six-layer board is the one shown in the above figure.PT 10 PEMP VSD534/ESE507 Six-Layer Boards Most six-layer boards consist of four signal routing layers and two planes. Why? Cont… © M S Ramaiah School Of Advanced Studies 60 .

at as many locations as possible. or better yet no signals at all (just mounting pads).PT 10 Why? PEMP VSD534/ESE507 The planes provide no shielding for the signal layers. are routed on layers 1 and 6. © M S Ramaiah School Of Advanced Studies 61 . The only time this arrangement works even moderately well is if all the high frequency signals are routed on layers 2 and 5 and only very low frequency signals. any unused area on layers 1 and 6 should be provided with "ground fill" and tied into the primary ground plane. and two of the signal layers (1 and 6) are not adjacent to a plane. with vias. If used.

Signals ________________High Freq.PT 10 Six-Layer Boards (cont…) PEMP VSD534/ESE507 With six layers available the principle of providing two buried layers for high-speed signals is easily implemented as shown ________________Mounting Pads/Low Freq. Signals ________________Ground ________________High Freq. Signals ________________Power ________________Low Freq. Signals © M S Ramaiah School Of Advanced Studies 62 .

Satisfies objectives 1.PT 10 PEMP VSD534/ESE507 Six-Layer Boards (cont…) This configuration also provides two surface layers for routing low speed signals. & 4 but not objectives 3 & 5 Disadvantages main drawback is the separation of the power and ground planes – Due to this separation there is no significant interplane capacitance between power and ground Therefore. the decoupling must be designed very carefully to account for this fact © M S Ramaiah School Of Advanced Studies 63 . 2.

but a good performing stack-up for a six-layer board is shown ________________Signal(H1) ________________Ground ________________Signal (V1) ________________Signal (H2) ________________Power ________________Signal (V2) H1 indicates the horizontal routing layer for signal 1 V1 indicates the vertical routing layer for signal 1. H2 and V2 represent the same for signal 2 © M S Ramaiah School Of Advanced Studies 64 .PT 10 PEMP VSD534/ESE507 Six-Layer Boards (cont…) Not nearly as common.

4. & • The desired board thickness made up by the use of a thicker center core This configuration satisfies objectives 1 and 2. but not 3. © M S Ramaiah School Of Advanced Studies 65 . or 5.PT 10 PEMP VSD534/ESE507 Six-Layer Boards (cont…) Advantages Orthogonal routed signals always reference the same plane Disadvantage the signals on layer one and six are not shielded • Therefore the signal layers should be placed very close to their adjacent planes.

so it is not often used © M S Ramaiah School Of Advanced Studies 66 .PT 10 PEMP VSD534/ESE507 Six-Layer Boards (cont…) Another excellent performing six-layer board is shown ________________Ground/ Mounting Pads ________________Signal ________________Ground ________________Power ________________Signal ________________Ground Advantage It provides two buried signal layers and adjacent power and ground planes and satisfies all five objectives Disadvantage It only has two routing layers -.

therefore. Ten-layers is also the largest number of layers that can usually be conveniently fabricated in a 0.062" thick board.PT 10 Ten-Layer Boards PEMP VSD534/ESE507 A ten-layer board should be used when six routing layers are required. Having more than six signal layers on a ten-layer board is not recommended. usually have six signal layers and four planes. Ten-layer boards. © M S Ramaiah School Of Advanced Studies 67 .

062" thick board.PT 10 PEMP VSD534/ESE507 Ten-Layer Boards (cont…) There are twelve-layer board fabricated as a 0. High layer count boards (ten +) require thin dielectrics (typically 0. © M S Ramaiah School Of Advanced Studies 68 .062" thick board) and therefore they automatically have tight coupling between layers.. but the number of fabricators capable of producing it are limited.006" or less on a 0. When properly stacked and routed they can meet all five objectives and will have excellent EMC performance and signal integrity.

or Pwr.PT 10 PEMP VSD534/ESE507 Ten-Layer Boards (cont…) Ideal stack-up for a ten-layer board is shown ________________Signal (low-speed signals) ________________Gnd. ________________Signal (high-speed signals & clocks) ________________Signal (high-speed signals & clocks) ________________Pwr. ________________Signal (high-speed signals & clocks) ________________Signal (high-speed signals & clocks) ________________Gnd. ________________Signal (low-speed signals) © M S Ramaiah School Of Advanced Studies 69 . ________________Gnd.

The existence of multiple ground planes. The shielding of the high-speed signal layers. as well as A tightly coupled power/ground plane pair in the center of the board. © M S Ramaiah School Of Advanced Studies 70 .PT 10 PEMP VSD534/ESE507 Ten-Layer Boards (cont…) The reason that this stack-up has such good performance is The tight coupling of the signal and return planes. High-speed signals normally would be routed on the signal layers buried between planes (layers 3-4 and 7-8 in this case).

By paring signals in this manner. © M S Ramaiah School Of Advanced Studies 71 .PT 10 PEMP VSD534/ESE507 Ten-Layer Boards (cont…) The common way to pair orthogonally routed signals in this configuration would be to pair layers 1 & 10 (carrying only low-frequency signals). as well as pairing layers 3 & 4. and layers 7 & 8 (both carrying high-speed signals). the planes on layers 2 and 9 provide shielding to the highfrequency signal traces on the inner layers. In addition the signals on layers 3 & 4 are isolated from the signals on layers 7 & 8 by the center power/ground plane pair.

against being contaminated with clock noise.PT 10 PEMP VSD534/ESE507 Ten-Layer Boards (cont…) Example High-speed clocks might be routed on one of the pairs. In this way the bus lines are protected. by the intervening planes © M S Ramaiah School Of Advanced Studies 72 . and high-speed address and data buses routed on the other pair.

is that if layers 1 and/or 10 have high frequency signals on them there is no inherent shielding provided by the PCB planes. © M S Ramaiah School Of Advanced Studies 73 . In the case of layer pairs 1 & 3 as well as 8 & 10. layers 4 & 7. this has the advantage of routing orthogonal signals with reference to the same plane. and layers 8 & 10. these signal layers should be placed very close to their adjacent plane.PT 10 PEMP VSD534/ESE507 Ten-Layer Boards (cont…) Another possibility for routing orthogonal signals on the ten-layer board is to pair layers 1 & 3. Therefore. of course. The disadvantage.

PCBs having from four to ten layers. improves signal quality. No one stack-up is best. digital logic. there is a number of viable options in each case and some compromise of objectives is usually necessary.PT 10 PEMP VSD534/ESE507 Stack Up Summary In this section we have discussed various ways to stack-up high-speed. A good PCB stack-up reduces radiation. and helps aid in the decoupling of the power bus. © M S Ramaiah School Of Advanced Studies 74 .

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