ATmega644/V77 1.

Pin Configurations

an SPI serial port 15.three flexible Timer/Counters with compare modes and PWM 9. 1149.2 USARTs 10.SPI port.4K bytes SRAM 5-32 general purpose I/O lines 6. disabling all other chip .1 compliant JTAG test interface.Real Time Counter (RTC) 8. and interrupt system to continue functioning.32 general purpose working registers 7. The Idle mode stops the CPU while allowing the SRAM 16. and programming and six software selectable power saving modes.Timer/Counters.a byte oriented 2-wire Serial Interface 11.2. The Power-down mode saves the register contents but freezes the Oscillator.a 8-channel 12.10-bit ADC with optional differential input stage with programmable gain 13. also used for accessing the On-chip Debug system.2K bytes EEPROM 4.IEEE std.64K bytes of In-System Programmable Flash with Read-While-Write capabilities 3. 14.programmable Watchdog Timer with Internal Oscillator.The ATmega644 provides the following features: 2.1 Block Diagram 1.

even if the clock is not running.2. Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port D pins that are externally pulled low will source current if the pull-up resistors are activated.8 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. even if the clock is not running. The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. The Port B pins are tri-stated when a reset condition becomes active. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC. Port A pins that are externally pulled low will source current if the pull-up resistors are activated. 2.2. As inputs.2. even if the clock is not running. to minimize switching noise during ADC conversions. A low level on this pin for longer than the minimum pulse length will generate a reset. Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). 2.functions until the next interrupt or Hardware Reset. In Extended Standby mode.2. 2.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). 2. the asynchronous timer continues to run. In Power-save mode.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).7 RESET Reset input.2. . allowing the user to maintain a timer base while the rest of the device is sleeping. The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. both the main Oscillator and the Asynchronous Timer continue to run.2. even if the clock is not running. As inputs.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. 2. The Port A pins are tri-stated when a reset condition becomes active. The Port D pins are tri-stated when a reset condition becomes active.2.2. This allows very fast start-up combined with low power consumption. the Crystal/Resonator Oscillator is running while the rest of the device is sleeping.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).2 Pin Descriptions 2. In Standby mode. As inputs.2 GND Ground. As inputs. 2. 2. The Port C pins are tri-stated when a reset condition becomes active.1 VCC Digital supply voltage. 2. even if the clock is not running.

and the electromagnetic noise of the environment. of an inverting amplifier which can be configured for use as an On-chip Oscillator. This will in many cases remove the need for using the dedicated compare instructions. 2. It should be externally connected to VCC. This must be handled by software. The optimal value of the capacitors depends on the crystal or resonator in use.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction.4. it should be connected to VCC through a low-pass filter. C1 and C2 should always be equal for both crystals and resonators. resulting in faster and more compact code. even if the ADC is not used. 5. Note that the Status Register is updated after all ALU operations. This information can be used for altering program flow in order to perform conditional operations. Oscillator and Clock The pins XTAL1 and XTAL2 are input and output.1 SREG – Status Register The AVR Status Register – SREG – is defined as: .11 AREF This is the analog reference pin for the Analog-to-digital Converter. 5. the capacitor values given by the manufacturer should be used.2. For ceramic resonators. as shown in Figure 7-2.2. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt.2.10 AVCC AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. as specified in the Instruction Set Reference. If the ADC is used. 2. Either a quartz crystal or a ceramic resonator may be used.2. respectively.9 XTAL2 Output from the inverting Oscillator amplifier. the amount of stray capacitance.

as described in the instruction set reference.• Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. 5. See the “Instruction Set Description” for detailed information. See the “Instruction Set Description” for detailed information. See the “Instruction Set Description” for detailed information. If the Global Interrupt Enable Register is cleared. See the “Instruction Set Description” for detailed information. In order to achieve the required performance and flexibility. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. The I-bit can also be set and cleared by the application with the SEI and CLI instructions. . • Bit 4 – S: Sign Bit. and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. The individual interrupt enable control is then performed in separate control registers. and is set by the RETI instruction to enable subsequent interrupts. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the “Instruction Set Description” for detailed information. The I-bit is cleared by hardware after an interrupt has occurred. none of the interrupts are enabled independent of the individual interrupt enable settings. A bit from a register in the Register File can be copied into T by the BST instruction. the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. Half Carry Is useful in BCD arithmetic.

5.Most of the instructions operating on the Register File have direct access to all registers. mapping them directly into the first 32 locations of the user Data Space. Y-register. As shown in Figure 5-2. this memory organization provides great flexibility in access of the registers. Y.5. as the X-. and most of them are single cycle instructions. The three indirect address registers X.1 The X-register. each register is also assigned a data memory address. and Z-register The registers R26. and Z are defined as described in Figure 5-3. These registers are 16-bit address pointers for indirect addressing of the data space.and Z-pointer registers can be set to index any register in the file. Y.. Although not being physically implemented as SRAM locations. .R31 have some added functions to their general purpose usage.

This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. The number of bits actually used is implementation dependent. the SPH Register will not be present. The initial value of the stack pointer is the last address of the internal SRAM.6 Stack Pointer The Stack is mainly used for storing temporary data. The ATmega644 Program Counter (PC) is 15/16 bits wide. AVR Memories This section describes the different memories in the ATmega644. For software security. and automatic decrement 5. 6. All three memory spaces are linear and regular. automatic increment. The AVR architecture has two main memory spaces. In this case. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction. and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction. This implies that a Stack PUSH command decreases the Stack Pointer. The Flash memory has an endurance of at least 10. Since all AVR instructions are 16 or 32 bits wide. the Data Memory and the Program Memory space. 6. In addition.000 write/erase cycles. Boot Program section and Application Program section. and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.1 In-System Reprogrammable Flash Program Memory The ATmega644 contains 64K bytes On-chip In-System Reprogrammable Flash memory for program storage. for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed.In the different addressing modes these address registers have functions as fixed displacement. The Stack Pointer must be set to point above 0x0100. the ATmega644 features an EEPROM Memory for data storage. thus addressing the 32/64K program memory locations. the Flash Program memory space is divided into two sections. the Flash is organized as 32/64 x 16. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The Stack Pointer Register always points to the top of the Stack. .

The five different addressing modes for the data memory cover: Direct. then 160 locations of Extended I/O memory and the next 4.352 Data Memory locations address both the Register File. For the Extended I/O space from $060 . The first 4. and Indirect with Post-increment. The first 32 locations address the Register file. and the internal data SRAM. the next 64 location the standard I/O Memory. Indirect. only the ST/STS/STD and LD/LDS/LDD instructions can be used. The direct addressing reaches the entire data space.2 SRAM Data Memory The ATmega644 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. Indirect with Displacement. registers R26 to R31 feature the indirect addressing pointer registers. Indirect with Pre-decrement. In the Register file. The Indirect with Displacement mode reaches 63 address locations from the base address given .Program Memory Map 6.096 locations address the internal data SRAM.$0FF in SRAM. Extended I/O Memory. the I/O Memory.

and the EEPROM Control Register. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions. When addressing I/O Registers as data space using LD and ST instructions. 0x20 must be added to these addresses. 64 I/O registers. and Z are decremented or incremented. the EEPROM Data Register.4 I/O Memory All ATmega644 I/Os and peripherals are placed in the I/O space. Refer to the instruction set section for more details. 6.or Z-register. . transferring data between the 32 general purpose working registers and the I/O space.0x1F are directly bit-accessible using the SBI and CBI instructions. the address registers X.0x3F must be used. reserved bits should be written to zero if accessed. The EEPROM has an endurance of at least 100. In these registers. specifying the EEPROM Address Registers. in which single bytes can be read and written. only the ST/STS/STD and LD/LDS/LDD instructions can be used. the I/O addresses 0x00 . For compatibility with future devices.by the Y. The ATmega644 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. I/O Registers within the address range 0x00 . Data Memory Map 6. 160 Extended I/O Registers and the 4096 bytes of internal data SRAM in the ATmega644 are all accessible through all these addressing modes.000 write/erase cycles. It is organized as a separate data space. When using register indirect addressing modes with automatic pre-decrement and post-increment.3 EEPROM Data Memory The ATmega644 contains 2K bytes of data EEPROM memory. The 32 general purpose working registers. When using the I/O specific commands IN and OUT.0xFF in SRAM. For the Extended I/O space from 0x60 . Y. The access between the EEPROM and the CPU is described in the following. the value of single bits can be checked by using the SBIS and SBIC instructions.

0x1F are directly bitaccessible using the SBI.4. General Purpose I/O Registers within the address range 0x00 . unlike most other AVRs. CBI. SBIS. The CBI and SBI instructions work with registers 0x00 to 0x1F only. Note that. and can therefore be used on registers containing such Status Flags. and SBIC instructions. the CBI and SBI instructions will only operate on the specified bit. . and they are particularly useful for storing global variables and Status Flags. Some of the Status Flags are cleared by writing a logical one to them. 6.Reserved I/O memory addresses should never be written. These registers can be used for storing any information.1 General Purpose I/O Registers The ATmega644 contains three General Purpose I/O Registers.