Cost and Benefit Models for Logic and Memory BIST

Juin-Ming Lu and Cheng-Wen Wu Lab. for Reliable Computing (LARC) Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan 30013 ROC

Abstract
We present cost and benefit models and analyze the economics effects of built-in self-test (BIST) for logic and memory cores. In our cost and benefit models for BIST, we take into consideration the design verification time and test development time associated with testability. Experimental results for logic BIST and memory BIST examples show that a threshold volume exists when BIST is profitable for the logic core under consideration—it is not recommended for a higher volume. However, BIST is a good choice for memory cores in general.

random pattern generator and signature analyzer techniques with scan paths [7]. MBIST, on the other hand, is normally based on the march algorithms [8, 9]. In this paper we propose economics models for estimating both the costs and benefits associated with LBIST and MBIST. We have performed experiments on these models, and the results show that a threshold volume exists when LBIST is profitable for the case we studied, i.e., it is not recommended for a volume higher than the threshold. However, MBIST is shown to be a good choice in general, except when the volume is low.

2. Models for LBIST 1. Introduction
Built-in self-test (BIST) is receiving growing attention with the advent of core-based system-on-chip (SOC) design, which is a natural sequel of deep-submicron VLSI technology. When cores from different vendors are integrated together on the system chip, the difficulty level of chip testing rapidly multiplies. Among the most apparent issues are core isolation, core access, system diagnosis, test reuse, test compaction, tester qualification, intellectual property (IP) protection, etc. For all these issues, BIST is a potentially good solution, if used properly. However, we do care about hardware overhead (area, pin, etc.), performance penalty, and extra design effort that may be associated with BIST. An economics (i.e., costs and benefits) analysis tool for weighing the costs and benefits of BIST (and other design-for-testability methodologies) is definitely helpful for the project managers and designers (see, e.g., [1, 2, 3, 4, 5, 6]). We analyze the economics effects of BIST for logic and memory cores in this paper. BIST is a relatively mature DFT methodology, but techniques used in logic BIST (LBIST) may be quite different from those used in memory BIST (MBIST). LBIST is normally based on pseudoWe consider recurring and nonrecurring costs and benefits for LBIST. In our model, the cost associated with LBIST mainly comes from area overhead. In return, reduced tester time and development time (i.e., time-to-market) represent the recurring and nonrecurring benefits, respectively.

2.1. Benefit due to Early Market Entry
Conventionally, DFT has been considered to lengthen time-to-market, since extra design effort is required. However, we have observed that the product development cycle may actually be shortened if proper DFT methodology is adopted, saving verification and debugging time (mainly in the prototyping stage) [5, 6]. We divide the product development cycle into three stages: the design stage, test development stage, and verification stage. Our development time model (Ì ) thus is

Ì

Ì × Ò · ÌØ

·

ÌÚ Ö

(1)

where Ì × Ò is the design time, ÌØ is the test development time, and ÌÚ Ö is the verification (including prototyping) time. When LBIST is adopted in a design, the development Ì × ÒÄ · ÌØ Ä · ÌÚ Ö Ä . time Ì Ä

When adding LBIST to the design. the benefit can be estimated as where ÌÚ½ is the part of the verification time that is independent of circuit testability. and ÌÚ Ö Ä . Ì Ì Å Ð is the market decline period. Our verification time model is Ì Ì Å ÖÓÛ · ¾Ì Ì ÅÑ ØÙ µÌ Ì ÅÖ Ú ¾µ ¾ ¢ Ì× Ú Ò Ì· Ì Ì Å·ÖÓÛÌ· Ì Ì ÅÑ ØÙ Ì Å ÖÓÛ Ì ÅÑ ØÙ · ´Ì Ì Å Ð ¡ Ì Ì ÅÖ Ú ¾µ ¢ Ì× Ú Ò Ì· Ì Ì Å·ÖÓÛÌ· Ì Ì ÅÑ ØÙ Ì Å ÖÓÛ Ì ÅÑ ØÙ ´´ (11) ÌÚ Ö ÌÚ½ · ¼ ¡ ÌÚ¾ (7) where Ì Ì Å ÖÓÛ is the market growth period. The amount Ê is measured in number of gates designed per day.e. is the design reusability factor. Early to the market results in extra revenue as represented by the shaded region in the figure. ÌØ Ä . and prototyping (including engineering runs).. we use Ä and Ä in Eq. design debugging. We adopt the test generation time model in [10]. Ê is the designer Ì×Ò ´½   µ´ ½   ½ µ (2) is the average number skill level. the test development time ÌØ Ä is modeled as ÊÄ ÌØ Ä ½ ¼ ¡ «Ø ¡ Ä (6) where the factor “590” represents the test length reduction ratio due to LBIST. When adding LBIST to the design. Here we assume that the test development time is in proportion to the test length. and decline period. 6] shows a market window with three periods: the growth period. which will be discussed later. i. are normalized between 0 and 1. timing and power specifications and silicon budget) of the target circuit. and will be explained later. is assumed to remain unchanged. Note however that Ì× Ú Ò is not necessarily positive. . The revenue of a product with a delay in time-to-market is Ä · ´½   µ ¢ «Ä Ö (4) To calculate Ì × ÒÄ . . The Market Life Cycle Model.. Æ Ò of engineers. our test development time model is Ê ´ Ì Ì Å ÖÓÛ · ¾Ì Ì ÅÑ ØÙ · Ì Ì Å Ð µÌ Ì ÅÖ Ú ¾ (10) The overall revenue from the product with an early time-tomarket (due to LBIST) can be estimated as [6] ÌØ «Ø ¡ (5) where «Ø is a constant factor that relates the test generation time to the IC gate count . the relation between and Ä is modeled as Time saving TTMgrow TTMmatu TTMdecl Time Figure 1. Ì Ä Ì× Ú Ò Ì (8) is ob(9) Ä ÓÖ Æ Ò ¡ Í Ò ¡ Ì× Ú Ò (13)  Ì Ä where Æ Ò is the average number of engineers and Í Ò is the average cost of an engineer per day. Therefore. . can be estimated from the complexity of the functionality and specification (e. and Ì Ì ÅÖ Ú is the maximal revenue per month at the maturity period without DFT. Figure 1 [5.g.e. the number “590” represents the saving factor in verification time due to the improvement in circuit controllability and observability. The verification time includes the time for design verification. The two variables. (2). Man-Power Benefit due to Shortened Development Time The benefit for product development man-power is tained and the amount of time saved by LBIST is ÌÚ Ö Ä ÌÚ½ · ÌÚ¾ After calculating Ì × ÒÄ . With LBIST. Our model for ÌÚ Ö Ä is therefore ÌÌÅ ÊÄ  Ê (12) 2. and . and is its complexity. Ì Ì ÅÑ ØÙ is the market maturity period. maturity period. is expected to increase when LBIST is adopted. The complexity parameter. which is used in the market life cycle model for estimating the revenue gain. Again. while ÌÚ¾ is testability dependent. i. Also.. Revenue TTMrev_DFT Ä ´½ · «Ä Ö µ (3) TTMrev where «Ä Ö represents the area overhead of LBIST.Our design time model is Æ ÒÊ where is the gate count.2.

2.2. ÍÛ Ö is the cost per wafer. Therefore. (18). According to our testability experiment which will be discussed later.e. similar to Eq. Cost due to Area Overhead Our model for the MBIST overhead is [9] Å ½· ÐÓ Ì ×Ø ÆÚ ¡ ´Í ¡ Ì   ÍÄ ÕÄ Ì× Ý Ö Ä Õ Ø Ê Ô ¡ ÌØÄ Å ËÁ Å ËÁ ¾´ µ ¢ ½ ¿¿ (22) µ (17) where ÍÄ Õ is the price of the external logic tester to access the chip without LBIST..3. As to the yield affected by the area overhead. ÍÄ ÕÄ is the price of the tester to access LBIST.e. ÊÛ Ö is the radius of the wafer.536. we adopt the Poisson yield model [11]:   ¡ (15) 3. is the memory capacity. i. Ì× Ý Ö is the number of seconds in one year (i. The testing cost savings thus can be translated to the tester cost: 3. 31. Cost due to Extra Development Effort Our model for the extra development cost in terms of man-power is is the defect density. ÍÅ Õ is the price of a memory tester. the benefit that we gain from this is ÍÄ ÕÄ where « Ö Õ is the tester frequency factor. Similarly to Eq. using self test. ÍÅ ÕÅ is the price of a logic tester to access the MBIST circuit. The silicon cost due to area overhead is Ö ÆÚ ¡ ÍÛ Ö ¾ ÊÛ Ö ¡ «ÙØ Ð Å Å   (23) 3.e.000). È « Ö Õ¡ Ä È ¡ ÍÄ Õ (18) Ì ×Ø ÆÚ  Ì Ê Ô ´Í ¡ Ì   ÍÅ Õ ¡ ÌؽŠÌ× Ý Ö Å Õ Ø Ê Ô ¢ ÍÅ ÕÅ ¢ ÌØ¾Å × Ý Ö µ (24) where ÌؽŠand ÌؾŠrepresent the amount of time the memory tester and logic tester are used for the chip with MBIST. 2. ÌØ is the tester time for the core without LBIST. Note that LBIST also can reduce test length in most cases.. (15). as compared with functional or even sequential ATPG patterns. we will also consider costs due to extra design effort and area overhead. A typical value for «ÙØ Ð is 90%. Benefit due to Reduced Testing Cost BIST reduces off-chip communication. Í Ò is the average cost of engineer per day.3. ÈÄ is the number of pins for the simple inexpensive tester to access LBIST (typically ranging from three to five if the core is tested entirely by LBIST). the pin count seems to increase. However. respectively.4. Ä ÓÖ Æ Ò ¡ Í Ò ¡ ÌÅ (21) where Æ Ò is the average number of extra engineers for MBIST. We use the same where Å ËÁ yield model as shown in Eq. the relation between ÍÅ ÕÅ and ÍÅ Õ is ÌØÄ ÌØ ¼ (19) ÍÅ ÕÅ È « Ö Õ¡ Å È ¡ ÍÅ Õ (25) .1. and benefit due to reduced testing cost. and ÌØÄ is the tester time for the core with LBIST.. Ê Ô is the annual depreciation rate of the tester. so the external tester can be greatly simplified. adding LBIST causes a reduction of ½¼ in test length. The cost per die due to the where area overhead is modeled as [10] Ö ÆÚ ¡ ÍÛ Ö ¾ ÊÛ Ö ¡ «ÙØ Ð Ä Ä   (16) where ÆÚ is the production volume. and È is the pin count of the core without LBIST. Cost due to Area Overhead The LBIST area overhead ranges from 4% to 15% in most cases [10]. With LBIST. Our model for the core area with LBIST is In summary. Benefit due to Reduced Testing Cost MBIST reduces the time that memory testers have to be used [9]. where «Ä Ö is the area overhead. the total benefit for using LBIST is ÌÌÅ · Ì ×Ø · Ä ÓÖ   Ö (20) Ä ´½ · «Ä Ö µ (14) 3. (17). the pin and frequency requirement of the tester actually is greatly reduced. Models for MBIST For MBIST. and ÌÅ is the development time associated with MBIST. and «ÙØ Ð is the utilization ratio of the wafer. i.

Fault coverage (FC) vs. for various « 4. 3. which can be modeled by  « Î ½  (27) is the factor representing the growth rate of FC.2 0. labor and time-to-market. As a result. we assume ÌؽŠÌØ ¿ and ÌؾŠ¾ÌØ ¿. The costs and benefits associated with . Figure 2. Î ) [6. a better result can be obtained by looking at the specific class of circuits under consideration. For higher ÆÚ values (above 4M). test length values. Note that the value 590 was obtained empirically from the benchmark circuits. and the default is 8 [9]). i.9 0.. 4. The testing benefit is high due to expensive memory testers and a significant reduction in memory tester time.5 0. Testability improvement ratios. 5.to high-volume products. Testability Analysis Figure 2 shows the relation between fault coverage ( ) and test length (number of vectors. 5.01 Ö (26) ²±± ²± alpha=0.1 0 0 alpha=0. the overall economics effect is dominated by nonrecurring terms. 5 10 15 20 Vector length 25 30 35 40 LBIST are calculated using our models and are shown in Fig.1 ² ¯² ¯² ¯² º ³ º µ ¹ ³ µ ô ³ ³ º ¸ ´ ± ¹ ² µ ô ³ ô ´ ô ´ ô ¶ ô · ô ¹ µ ± º ³ ´ ô ² ô ² ô ² ³ ¶ ô µ ô ¹ ô ´ ¶ ô ´ ¹ ¹ µ ¯² · ´ ¹ º · · ² ¸ ± µ ³ Figure 3. Also.where ÈÅ is the number of pins for the logic tester to access the memory core with MBIST (it normally ranges from 4 to 10. In summary. 6. Ä . The testability improvement ratio. The weighted arithmetic mean of «Ä Ø is calculated as follows: ¥¸±±­±±± ¥¶±±­±±± ÃÍâãðó ÃÕÕÎ ÄÂóæâ Ãõæôõ à ¥´±±­±±± ¥²±±­±±± «Ä Ø È ®¥²±±­±±± ²±ì ²±±ì ²Î ³Î ´¯´¹Î ô ² ´ ·Î ²±Î Ö ÈÙ Ø×´Æ ¡ where Æ is the number of nets in a circuit.4 0. MBIST is beneficial for medium. varies from one to about one thousand.7 0.6 FC 0. For practical applications. According to the result. LBIST Case We use the chip reported in [14] as a case for our LBIST model evaluation. Ö Ù Ø× Æ Ä µ ¼ (28) ®¥´±±­±±± Figure 4. where « We have experimented the model using ISCAS89 benchmark circuits [13]. When the production volume is low (less than 4M). the effect of recurring costs dominates. adding LBIST causes a reduction in test length and testing time by a factor of “590”. as has been shown previously.8 0. as shown in Fig. and the results are listed in Fig. Æ ½ . Analysis results of the LBIST case. MBIST Case We use the design reported in [9] as a case for our MBIST model evaluation.e..3 0. for s1488. the total benefit from MBIST is ²±±±± ÍÇÔÓ°ÂÕÑÈ ÑÓÑÈ°ÂÕÑÈ ²±±± óâõêð Ì ×Ø   Ä ÓÖ   1 alpha=1 0. 12].g. e.

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