IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO.

2, FEBRUARY 1998

243

IV. CONCLUSION The algorithm described by Li was examined and found to be suboptimal. However, it performs well in the region up to 12-bit word lengths. Like the optimal MAG algorithm, it is an exhaustive search method, and is therefore time consuming. The general BHM algorithm is probably a more useful suboptimal algorithm due to its speed. REFERENCES
[1] A. G. Dempster and M. D. Macleod, “Multiplication by an integer using minimum adders,” in IEE Colloquium Math. Aspects Signal Processing, Dig. No. 1994/034, Feb. 1994, pp. 11/1–11/4. , “Constant integer multiplication using minimum adders,” Proc. [2] Inst. Elect. Eng., vol. 141, pp. 407–413, Oct. 1994. [3] R. Bernstein, “Multiplication by integer constants,” Softw.—Pract. Exp., vol. 16, pp. 641–652, July 1986. [4] A. G. Dempster and M. D. Macleod, “General algorithms for reducedadder integer multiplier design,” Electron. Lett., vol. 31, pp. 1800–1802, Oct. 1995. [5] D. R. Bull and D. H. Horrocks, “Primitive operator digital filters,” Proc. Inst. Elect. Eng., vol. 138, pt. G, pp. 401–412, June 1991. [6] A. G. Dempster and M. D. Macleod, “Use of minimum-adder multiplier blocks in FIR digital filters,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 569–577, Sept. 1995. , “Use of multiplier blocks to reduce filter complexity,” in Proc. [7] ISCAS’94, London, May–June 1994, vol. 4, pp. 263–266. [8] A. G. Dempster, “Digital filter design for low-complexity implementation,” Ph.D. dissertation, Univ. Cambridge, England, June 1995.

Harmonic Distortion on Class CMOS Current Output Stages
Fig. 2. Programmable multiplier using four adders, redesigned to account for all topologies in Fig. 1.

G. Palmisano, G. Palumbo, and S. Pennisi
Abstract—Linearity performance in class AB CMOS current output stages is discussed, and simplified equations are derived for the harmonic distortion. It was found that channel-length modulation and transistor mismatches are the main sources of distortion in current output stages. A novel high-performance class AB current output stage is also presented which is based on active-gain enhanced cascoded mirrors. It overcomes the nonlinearity caused by channel-length modulation and provides a very high output resistance. The linearity performance of the proposed circuit is only limited by the fundamental constraints due to transistor mismatches.

of graphs of cost-4 that Li searches before commencing the cost-5 search. Based on Li’s Fig. 2, a hardware implementation of a four-adder multiplier, we present here in Fig. 2 the circuit that would synthesize all of the graphs in Fig. 1. This design requires eight shifts and eight switches, compared with Li’s five shifts and four switches. III. MULTIPLIERLESS DIGITAL FILTERS The motivation for Li’s paper is to the reduce the complexity of digital filters with fixed-point multipliers. For multiplierless digital filters, we have found that the graphical methods used above for single multipliers are equally applicable to the multicoefficient case [5]–[7]. This method exploits redundancy between the coefficients and has proved to be far more efficient in terms of adders than any other “multiplierless” methods we have studied [8], particularly those where products are produced by individual multipliers. The contribution made to overall complexity by the coefficient multiplications using this method is far less than that of the structural adders and delays. For instance, the example used by Li produces coefficients for an order-48 filter which requires 28 adders using discrete multipliers, designed using Li’s method or the MAG algorithm, and only 16 adders using the RAG-n algorithm of [6].

I. INTRODUCTION Circuits based on the current-mode approach [1]–[6], such as current conveyors [7]–[10], operational floating conveyors [11], [12], operational floating amplifiers [13], [14], current amplifiers [15]–[20], etc. References [1]–[3] and [21]–[25] seem to have a better signal dynamic range and closed-loop bandwidth performance than conventional voltage amplifiers [26]–[29]. Moreover, they are particularly suitable whenever the input source and/or the output are current
Manuscript received December 14, 1995; revised July 25, 1996. This paper was recommended by Associate Editor G. W. Roberts. The authors are with the Dipartimento Elettrico Elettronico e Sistemistico, Universit´ di Catania, I-95125 Catania, Italy (e-mail: a gpalmisano@dees.unict.it; gpalumbo@dees.unict.it; spennisi@dees.unict.it). Publisher Item Identifier: S 1057-7130(98)01645-0.

1057–7130/98$10.00 © 1998 IEEE

Unfortunately. provide both high output resistance and linearity. Current-mode power amplifiers use a current output stage (COS) as a final stage. and have the interesting feature of achieving a true multioutput circuit since several current output stages can be embedded. section in most analog integrated circuits with either the current or the voltage approach is the final power section that has to drive low resistive loads. simple current mirrors cannot be employed. VOL. while for low drive capability a class A COS can profitably be used [33]. 45. High-performance COS’s must exhibit high output impedance and accurate current transfer. Indeed. A COS has two main sources of nonideality which cause deviation from the ideal dc transfer characteristic and affect linearity: • the channel-length modulation error of mirroring transistors. 2. Moreover. Actually. which is the most critical block in the implementation of current amplifiers. The channel-length modulation error of the mirroring transistors can be reduced by increasing their channel length. but often necessary.244 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. Cascode mirrors. since it is not included within the feedback loop. instead. the use of current mirrors with cascoded output is mandatory in the implementation of a COS. However. therefore. NO. it is the main source of nonlinearity. FEBRUARY 1998 signals [30]–[32]. but their poor current swing makes them impractical for high-current applications. this means larger chip area and worse frequency response. a class AB COS is mandatory. Mismatches are due to transconductance gain . when large current levels have to be supplied. • the mismatches of the mirror transistors. A critical. the low-voltage cascode current mirror first proposed in [34] and further discussed in [35] does not provide a high dynamic range due to the fixed bias voltage.

and assume transistors MA1–MA3 to be ideally matched and to have the same transconductance gain (i. The value of VGA which provides such a condition is given by II. A better solution to reduce the harmonic distortion due to channel-length modulation is achieved by implementing the COS with the current mirror with improved dynamic matching shown in Fig. MA1–MA3). and threshold-voltage tolerances in the mirroring transistors [37]–[39]. and has been rearranged for class AB COS’s in Appendix A. we only consider the n-type cascoded mirror A (i. it is further increased by the body effect. 1(b).. and (c) cascoded with improved dynamic matching. 1. and if a twin-tub process is not used. Therefore. shown in Fig. HARMONIC DISTORTION DUE TO CHANNEL-LENGTH MODULATION Let us evaluate the harmonic distortion due to the channel-length modulation in the previously proposed COS’s which are shown in Fig. a novel COS is presented which exhibits better linearity performance than that of previously presented solutions. a second-order harmonic distortion appears normally negligible in the other topologies. and its value is pushed down to the fundamental limitation caused by mismatch errors. 1. A.and p-transistor threshold voltages. as proposed in [12]. and analytical results are compared with SPICE simulations.e. COS Based on Cascoded Mirrors The COS with cascoded mirrors is shown in Fig. which is set by MA3 and VGA must (VDS = VGS ) in order be set equal to the voltage VGS to guarantee in quiescent conditions an accurate matching between MA1 and MA2.. VDS . (a) (b) (c) Fig. This limitation is evaluated. It exhibits a reduced nonlinearity by a factor of 2. 1(c) and proposed in [36]. However. 1(a). 1(a). the same aspect ratio W=L). after an analytical determination of the harmonic distortion in the COS’s shown in Fig. (b) cascoded with dynamic matching. and can only be reduced by a careful layout design. the linearity could be still unsatisfactory for a high-performance current amplifier. Without loss of generality. This is dependent on the mismatches of the n. A first solution to reduce it was that of using the cascoded mirror with dynamic matching. 1. close investigation reveals that while third-order harmonic distortion is minimized. Current output stages: (a) cascoded. the channel-length modulation still limits the linearity which is primarily affected by a third-order harmonic distortion. The harmonic distortion due to channel-length modulation is reduced by a gain stage. In the COS based on cascoded mirrors which is shown in Fig.e. They give the ultimate limit to the COS linearity. A useful approach for such circuits VGA = VDS + VGS  2VTN + 2 = IQ . is suggested in [45]. In this paper. Most commonly used approaches [40]–[44] are not suitable for class AB amplifiers operating in large swing conditions since the two half circuits work alternately.

N (1) .

FEBRUARY 1998 245 where IQ is the quiescent current. 2. Hence. VOL. it follows that iA 2 = 1 + N (VGA 1 + N vGS 2 pN . 45.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. NO.

MB6 MB7.5 60/3 1500/1. MA8 MB1. 0 vGS TABLE I TRANSISTORS MA1. MA6 MA7.5 200/1. MB8 W/L 600/1. MA2. MB2.5 150/1.5 20/1.5 60/1.5 20/3 ) iA1  = N (VT N 1+ IQ 0 iA1 1 + N p N VT N + iA1 . MA3 MA4 MA5. MB3 MB4 MB5.

since the term iA1 =.N iA1 : (2) Taking the derivative of iA2 with respect to iA1 and.

N ) is usually much lower than 1. we obtain + @iA2 @iA1 2  1 + pN = .

e. ..N IQ 0 3 2 p iA1 : (3) M B 1–MB 3. and assuming the transconductance gain to be equal for both current mirrors (i.

N = .

P = .

HD2 and HD3 are calculated from (A3) and (A4) of Appendix A: Following the same steps for the p-type current mirror  HD2  N =  HD3  N = 0 P 4 + P 8 IQ . ).

IQ .

1 Unlike the circuit in Fig. Indeed. It should be noticed that with a single-well technology. it is proportional to the difference between the two channel-length modulation parameters. Harmonic distortions HD2 and HD3 are dependent upon the relative magnitude of the input signal and N and P . threshold voltages are affected by the body effect. Thanks to the common drain MA4 (MB 4). COS Based on Cascoded Mirrors With Dynamic Matching The first circuit solution to reduce harmonic distortion in COS due to channel-length modulation was presented in [12] and is shown in Fig. with a proper design. thus keeping VDS This improves the linearity performance since a better dynamic matching between MA1 (MB 1) and MA2 (MB 2) is achieved. third-order harmonic distortion is the dominant contribution which can be reduced by increasing the transconductance gain and/or the channel length of the transistors. 0VT P + IA =. 1(b). the gate–source voltage of MA4 follows that of MA3. but this effect is a second-order source of nonlinearity and can be neglected. B. the even-order harmonic distortion is very low. But a current proportional to that of the output branch is now replicated in MA5–MA7 and supplied to MA4 by means of the current mirror MA7–MA8. the drain–source voltage of MA2 accurately matches that of MA1. As expected from current mirrors with ideally matched transistors and equal transconductance gain. Assume the current mirror MA7–M A8 to be ideal. even for large input currents. 1(b). and set (4b) VSG = VGS = 0VT P + where IM is the magnitude of the sinusoidal input current..e. and hence. 1(b). the gate voltage of the common-gate transistor MA3 (MB 3) follows the gate (VDS ) constant. = VGS (i. transistors MA1–M A3 implement a cascoded mirror and transistor MA4 is a common drain performing the same function as in Fig. Therefore. voltage of MA1 (MB 1). 3 2 IM IQ IM IQ 01 (4a) 01 Considering current mirror A.

P = VT N + Setting VSG IQ =.

N ). and we get IQ n. MA1 and MA2 are matched in quiescent conditions.

P = VT N + IQ .

N (6) where n = .

A2 =.

A5 = .

A3 =.

unless we use a twin-tub process. we refer to them as circuits (a). Since iA2 and iB2 are linearly related to iA1 and iB1 . and IQ =n is the bias current of MA4. It gives only even harmonics with HD2  = jVT P j 0 VT N ) 0 P (VT N 0 jVT P j)]  (N + P )(jVT P j 0 VT N ) (8) = 3 3 2 2 [N ( which is proportional to the channel-length modulation coefficients and to the differences between VT N and VT P . It is apparent that THD decreases from circuit (a) to (c). and can heavily reduce the linearity.2-m CMOS process. and (c)] were used as the output stage in a current buffer (like that used in [36]). as expected. D. the differences between VT N and VT P depend on the body effect. the approach discussed in Appendix B has been adopted. and the output current can be approximated by iA2  [1 + N (jVT P = j 0 VT N )]iA1 : (7) There is only a gain error which is very low if the threshold voltages are about equal.A6 . (b). A similar equation holds for the p-type mirror. the circuits in Fig. The calculated and simulated harmonic distortions of the short-circuit output current for a relatively low-frequency input signal of 100 kHz are shown in Fig. Transistors MA1 and MA2 are matched in quiescent conditions. and according to (8). 6 dB better). iA2 = 1 + N (vGS 1 + N vGS + vSG 0 vGS p ) iA1 iA1 : (5)  = 1+ N p. Simulation Results In order to evaluate the accuracy of the proposed analysis. For the hand calculations 1 A positive-feedback exists which involves transitors MA6–MA8. 2.e. 2 Where a twin-tub process was assumed since bulk was connected with source. 1 [for simplicity. the THD of circuit (c)2 is almost independent of the signal amplitude.. They were biased with a current IQ equal to 200 A using the transistor aspect ratios in Table I. but its loop gain 1=(gmA4 rdA5 ) is much lower than 1. Moreover. which was simulated using SPICE and the model parameters of a 1. the THD of circuit (b) is about half that of circuit (a) (i. Moreover. respectively.

IQ 0 iA1 VT N + N 1 + N i .

. C. an improved COS was proposed which is based on cascoded current mirrors with improved dynamic matching [36]. Comparing (2) and (5). It is shown in Fig. COS Based on Cascoded Mirrors With Improved Dynamic Matching Recently. the transfer error is reduced by a factor of 2. 1(c). Hence. The current mirrors MA1–M A8 and MB 1–MB 8 provide a nominally zero transfer error. HD2 and HD3 are also reduced by a factor of 2.

VOL. 2. it follows from (A3) and (A4) of Appendix A that the harmonic distortions HD2 and HD3 of the output current are given by Fig. NO. Proposed current output stage. 2. we get @iA2 @iA1 @vDS  1 + N @iA1 = 1 + N vGS 0 @vGS1 @iA @vGS @iA1 + iA1 1 + N vGS : : (10) (11) The amplifier A1 establishes the following relationship: @vDS @iA2 @iA1 = 1+A A 1 0 1 + A @vGS Substitution of (11) into (10) yields 1+ = (1 + A) where the terms N vGS Following the same calculation for the p-type current mirror. 3. N A1 and @vGS =(1+ A) have been neglected. N p. FEBRUARY 1998 Fig.246 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. Deriving (9) and neglecting the 2 terms. 45. and assuming the transconductance gain for both current mirrors to be equal. Harmonic distortion due to channel-length modulation versus the ratio of input current IM to quiescent current IQ for circuits a). and c). b).

pIiQ 0 2piA1 (12) HD2  = HD3  = 8(1 + A) N 0 p P .

. 2IM pI0 IQ M 2 (13a) of HD.

N . and .

It was found that N  0:04 = V01 . and VTN 0 jVT P j  100 mV. and HD2 for circuit (c). 24(1 + A) N + P IQ . it = = is confirmed that HD3 is the main distortion component for circuits (a). A very good agreement between the calculations and simulations for all of the circuits was observed. (b). P  0:05 V01 .012 A/V2 . and the values of the threshold voltages and channel-length modulation coefficients were extracted from the model parameters.P were set to 0. In addition.

a COS with high linearity performance is achieved. HARMONIC DISTORTION DUE TO MISMATCHES Let us consider the effects on harmonic distortion of threshold voltage and transconductance mismatches [37]. using the output stage in Fig. whose gains are both assumed to be equal to A. MA2 and MB 1. Second. in the proposed COS. and are the dominant sources of nonlinearity for the circuit in Fig. 4 are far from the typical THD performance of a real current amplifier for two reasons. the proposed topology provides a very low-distortion COS since HD2 and HD3 are greatly reduced by the amplifier gain. 3 in a current buffer (like that used in [36]). unlike the circuits in Fig. nonlinearity in the first stage (usually implemented with a transimpedance amplifier) has to be considered. The simulated and calculated THD of the short-circuit output current is shown in Fig. the contribution to THD due to channel-length modulation is negligible. However. IM IQ 01 : (13b) HD2 and HD3 depend on the difference and the sum of N and P . Without loss of generality. The harmonic distortion was simulated with SPICE. MB 2 are almost equal. 1. the use of A1 and A2 also provides a very high output resistance given by ro  (gm rd rd A)j j(gm rd rd A). A VERY LINEAR COS The proposed COS is shown in Fig. due to the finite loop gain. The two current mirrors are composed of transistors M A1–M A3 and MB 1–MB 3 and two auxiliary voltage amplifiers A1 and A2. 3. we confine our analysis to the mismatch errors in a simple current mirror MA1–MA2. Thanks to A1 and A2. even for large input currents. and employing a single-stage differential amplifier for A1 and A2 whose gain is about 30. we can write iA2 = 1 + N vDS 1 + N vGS 0 vGS iA1 : (9) . as discussed below. First. THD is better than 070 dB up to current signals 30 times higher than the bias current. Thus. IV. III. [39]. It is made up of two complementary active-gain enhanced mirrors which base their performance on a principle quite similar to that of the gain-boosting technique [46]–[48]. It has to be pointed out that the THD in Fig. respectively. mismatch errors in the mirror transistors set the fundamental limitation of the COS linearity performance. the drain voltages of MA1. 4. Moreover. 3. = Considering the n-type current mirror. However.

we can write iA 2 = (14) where VTN and VTN are the threshold voltages of M A and MA . we get vGS vGS 0 VTN 0 VTN 2 iA1 = . and where VTN VTN 0 VTN is the threshold mismatch. 2. 4. FEBRUARY 1998 247 Fig. Mismatches of Threshold Voltage VT Neglecting the channel-length modulation and any other source of nonlinearity.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. NO. Harmonic distortion due to channel-length modulation versus the ratio of input current IM to quiescent current IQ for the proposed circuit. A. Deriving (14). 45. except that caused by mismatches in VT . VOL. respectively.

N 1VTN + iA1 .

and assuming the threshold mismatch as VTP . defining its VTP 0 VTP .N 2 2 1 = 1 Following the same steps for the p-type current mirror.

. from (A3) transconductance gains to be equal (i.e.P ). .

.

we have @iA2 @iA1 = 1 + 1VTN = .N and (A4) of Appendix A.

Comparisons between simulations and calculations are shown in Fig. Three curves are plotted for different values of the percentage error . The third-order harmonic distortion is about equal to zero according to (A4).N : iA1 (15) 1 = = is independent of the signal amplitude. and is proportional to the difference between the transconductance mismatches. 6.

which is defined by setting either . in the worst case condition.

N or .

This is obviously true not only for the proposed low-distortion COS. CONCLUSION In this paper. 1 1 1 V. They are based on the transcharacteristic of the two complementary current mirrors which implement the COS. 5(a). 5(b). unlike voltage-mode amplifiers. (b). Simulations have been performed which are in good agreement with the analytical results. and 6. From Figs. simple equations for the hand calculation of harmonic distortion in class AB CMOS current-mode output stages have been determined. it is worth noting that. but also for circuits (a). it is apparent that the distortion caused by mismatches cannot be neglected. in current-mode amplifiers. Mismatch errors similarly affect any topology. the output current iout t can be expressed as 1 8 1 HD3 = 24 HD2 = .P equal to zero. APPENDIX A HARMONIC DISTORTION FOR CLASS AB COS Let us consider the output stage of a current amplifier. It is based on two complementary active-gain enhanced mirrors. A novel COS is also proposed which greatly reduces the effect of channel-length modulation and makes it negligible. and assume a sinusoidal input current iin IM !t . The absence of third-order harmonic distortion is confirmed since the simulated THD is about equal to the calculated HD2 which is underestimated by less than 0. the dependence of the overall linearity on the mismatches of the output stage does not allow the use of such circuits in applications where high linearity performance is needed. while that due to mismatches is a fundamental limitation of current-mode circuits. and (c) in which all of the different contributions to distortion are of the same order. Channel-length modulation and mismatch errors have been found to be the source of distortion of COS’s. As a final remark.5 dB. The distortion due to channel-length modulation can be reduced by adopting proper circuit solutions. Neglecting power terms higher than third-order ones. and can only be reduced by a careful layout design.

(1VTN 0 1VTP ) IM .

In the evaluation of the harmonic distortion components. The slight deviation between the calculated and simulated curves is due to the mobility degradation effect that was neglected in our analysis. SPICE simulations and the results calculated from (16) are shown in Fig. Indeed. Three curves are plotted for different values of the percentage error VT versus the input current normalized to the bias current. It is confirmed that HD2 or HD3 are the main distortion components in one of the two cases.5 dB. since the surface mobility depends on the gate–source voltage. the transconductance parameter . VTN 0 VTP is chosen to estimate HD2 and VTN VTP to estimate HD3 . and THD is predicted with a maximum error of 4. 5. (16a) (16b) 1 pI 0 1 I M Q (1VTN + 1VTP ): 1 =1 1 In order to establish the accuracy of (16a) and (16b).

cannot be assumed to be constant. as has been done. Mismatches of Transconductance Parameter . 1 = 1 B.

Let . A second mismatch error which gives rise to harmonic distortion is the mismatch of the transconductance gain of the mirror transistors.

NA1 and .

NA2 be the transconductance gains of MA1 and MA2 . and let us neglect any other source of error. Since the output current .

N =.

it follows that =( ) = sin( ) () are the transconductance mismatches.N iA1 . considering also the p-type is given by iA2 current mirror. The second-order harmonic distortion 1 . from (B3) of Appendix B.

N 0 .

P 8 .

N .

P where 1.

N = .

N 0 .

N HD2  =  1 j1.

N j 0 j1.

P j = 8 .

N .

P and 1.

P = .

P 0 .

.P (17) iout (t) = a0 + a1 iin + a2 i2 + a3 i3 (A1) in in where parameter a0 is an offset current and the parameter a1 is defined by the mirror ratios since around the quiescent point is 1iA1 = 01iB1 = iin =2.

. 6. Parameters a2 and a3 can be calculated according to the approach proposed in [8]. assuming the following approximation for the behavior of the class AB COS: H D3 = = 1 1 a3 2 2 a3 IM IM = 4 a1 4 1 24 1 24  A1 = iin .248 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. a1 = 1). Fig. APPENDIX B ACCURATE DETERMINATION = = 1 a2 1 a2 IM IM = 2 a1 2 1 8 @i @i  OF H D2 A2 A1 I 0 @i @i B2 B1 I (A3) In class AB COS’s in which the two current mirrors have transfer gains independent of the input signal but with different values. 2.e. iB 1 = iin . FEBRUARY 1998 (a) (b) Fig. VOL. H D2 and H D3 are given by H D2 where a mirror ratio equal to 1 has been assumed (i. Harmonic distortion due to transconductance–gain mismatches versus the ratio of input current IM to quiescent current IQ for the proposed circuit. NO. and the even ones can be determined . 45. the odd harmonic distortions are zero. Taking the derivative of iout with respect to iin . (a) Second-order harmonic distortion due to threshold–voltage mismatches versus the ratio of input current IM to quiescent current IQ for the proposed circuit. 5. i for iin for i  Q in  0 Q I I (A2) = A2 A1 I @ iA2 @ iA1 I @i @i + + B2 B1 I @ iB 2 @ iB 1 I @i @i 02 0 a1 @i @i A2 A1 I 0 @i @i B2 B1 I (A4) where IQ is the quiescent current of the output branch. (b) Third-order harmonic distortion due to threshold–voltage mismatches versus the ratio of input current IM to quiescent current IQ for the proposed circuit. evaluated at the maximum and minimum input signal (+IM and 0IM ).

Inst. Rao. 1368–1369. [28] . Bruton. vol. Dec. Aug.” in Proc. Lett. J. [7] K. I. 1982. Payne. 1989. 1990. 27. vol. 955–962. “Wide-band integrated receiver with improved dynamic range using a current switch at the input. London. “Operational floating conveyor. 1705–1707. Solid-State Circuits. pp. pp. Lett. vol. pp. vol. Lidgey. Sedra. [21] J. vol. Smith and A. vol. 2. Smith. for < t < T. van den Broeke and A. [27] E. Baumann. Huijsing. Lett. [2] B. M. Pelgrom. 137.. vol.. “High linearity CMOS current output stage. pp. no. [25] W. 132–140. 129–134. Ducan. vol. Apr. Lett. “Characterization and modeling of mismatch in MOS transistors for precision analog design. “Distortion in CMOS operational amplifier circuits. Westgate. this method is much more accurate than the one in Appendix A which has been found to lead to an error of about 4. Dec. pp. Pederson and K. pp. Circuits Syst. London. 115–129. 40. no. [45] D. [33] A. and A. May 1994. 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Budde. “A high-speed CMOS current op amp for very low supply voltage operation. and C. [9] B. 1989.” Proc. Current iA2 and iB 2 can be expressed as iA2 = a1 iA1 = iB2 = b1 iB1 = 0. “Performance analysis of current conveyors. 807–811.” IEEE J. 1984. Crawley and G. 1991. G. Toumazou. vol. “A fast-settling CMOS op amp for SC cir- . Hartung-Gorre Verlag Konstanz.” IEEE J. vol. 131. IEEE ISCAS’94. 1981. Inst. May 1994. F. vol. VOL. pp.. pp. consider a sinusoidal input signal with amplitude IM . Palmisano. Shyu. for 0 < t < for T 2 0a1 iin . 1990. [38] K. vol. “Random error effects in matched MOS capacitors and current sources. assuming a mirror ratio about equal to 1. “Analysis of op-amp power supply current sensing. vol.. 1. Inst. “Indirect current feedback instrumentation amplifier with a common-mode input range that includes the negative rail. 533–536. 789–790.. Temes. . Fong and R. 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i ) 1 p where g(t. This observation not only simplifies the proof of the approximation property.-S. Appendix] is based on Gaussian curves of fixed width translated to predetermined locations (the extrema of the sinusoid). Ferreira Abstract—We point out that an approximation property of Gaussian functions. “The CMOS gain-boosting technique. 119–135. revised April 24. pp. and the results mentioned imply that even very spread-out Gaussian curves can somehow be combined to closely approximate these signals. no. i ) = i 2 e0t =2 : It is not our intention to shift attention from the main results and conclusions presented in [1]. closure of translations. 25. The purpose of the long Appendix in [1] is to prove that any finite-energy signal which vanishes outside a certain interval can be arbitrarily well approximated by linear combinations of Gaussian functions. 0  t  T . the results obtained by Wiener imply that. despite their usefulness and importance. Dec. the methods used by Wiener are not constructive. can be approximated by Gaussian functions. Gaussion functions.pt). ) 2 dt < : 01 f (t) 0 i=1 ai g(t These conclusions generalize those obtained. Unfortunately.” Int. II. TABLE I APPROXIMATING sin(2t). 241–243. He also showed that a similar result holds in L2 if and only if the set of zeros of the Fourier transform of has zero measure. ) clearly belongs to L1 and L2 . Our remarks in no way compromise the main results and conclusions presented in that paper. 1995. We hope that our observations might be of use to researchers interested in nonlinear approximation problems such as this.” IEEE Trans. Lee. 1994. but simply to address this approximation problem in the light of Wiener’s results on the closure of translations which. superpositions. the approximation now being 0 ti . 0 t1 A Comment on the Approximation of Signals by Gaussian Functions Paulo Jorge S. if and only if the Fourier transform of has no zeros. Universidade de Aveiro. a somewhat surprising result: the spaces L1 and L2 contain very rapidly varying functions. VOL. FEBRUARY 1998 cuits with 90-dB DC gain. Much better 1057–7130/98$10. INTRODUCTION The purpose of this note is to comment on certain side aspects of a recent and interesting work [1]. Thus. The approximation property just discussed holds no matter the value of  . 1991. Our aim is to show that similar. and who remain unaware of Wiener’s results. the approximation of sinusoids as discussed in [1. 41. vol. “A CMOS op amp with fully-differential gainenhancement. by linear combinations of the translates of a single function 2 L1: N i=1 ai (t 0 ti ) ai g (t 0 ti . which addresses the approximation of finite-energy signals by linear combinations of Gaussian functions: i Hilbert spaces of functions f such that jf j and jf j2 is Lebesgue integrable over (01. Wiener showed that any function belonging to L1 can be approximated to any prescribed tolerance. vol. pp. 45. Proofs of these results can be found in [3] and [4]. This is done very much in the spirit of Lauricella’s theorem [2]. 3810 Aveiro. nonlinear functions. Circuits Syst. to other functions (not necessarily Gaussian). [48] J. but also renders the result applicable. Portugal c˜ (e-mail: pjf@inesca. for example. do not seem to be as well known as some of the other works. The Gaussian function g(t. and its Fourier transform certainly has no zeros. is a direct corollary to the work of Wiener on the closure of translations in L1 and L2 . independently of  . The author is with the Departamento de Electr´ nica e o Telecomunica¸ oes/INESC. Index Terms— Approximation methods. and indeed more general.” IEEE J. Solid-State Circuits. pp. NO. the Banach and Manuscript received November 16. Lloyd and H. conclusions follow from the approximation results due to Wiener on the closure of translations in L1 and L2 —respectively. at much greater length. derived in a recent work. 1996. in [1]. in the L1 norm. there is an integer N and constants (ai )1iN and (ti )1iN such that 1 01 1 f (t) 0 N i=1 N ai g(t 0 ti . that is. 1990. Publisher Item Identifier S 1057-7130(98)01638-3. and do not offer any hints on how to pick N. signal representations. 2. This paper was recommended by Associate Editor R. J. Analog Integrated [47] Circuits Signal Processing. . in a more general setting. G. for any f 2 L1 and  > 0. Mar. Newcomb. W. ) dt < : A similar result holds for any f in the L2 norm: 2 L2. I.250 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING.00 © 1998 IEEE . nonlinear approximation. (ai )1iN and (ti )1iN . 1379–1384. +1). For example. by showing that any sinusoidal signal sin(2kt=T ). 1.