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Jay Kumar

Jay Kumar Contact Info: Res: (408) 741-5546; Cell: (408) 348-2643 A. Semicoa, Orange County, CA (March 09 Jan 12): V.P of Operations /Engineering :
In charge of ALL manufacturing Operations (Fab, Assembly, Test); Planning/Production Control and support engineeringcompany manufactures and ships products to the Aerospace and Military markets. The facility is DSCC/DLA certified and the total volume of shipment is > $30M /Year. I have > 90 personnel in all areas in the companyproducts designed, debugged, transferred to manufacturing after detailed quals: High Voltage discrete (Diodes, Transistors, Power-MOSFETs)

B. InSilica: Santa Clara (March 05 Mar09): V. P, Operations

In charge of all Production Operations (Fab, Assembly, Test), Test Program Development (Engineering debug and production versions), Product performance, cost structure, yields, production control, customer support, product bring-up, quality & reliability, package development (MCM, BGA, POP, QFP/N) Have excellent contact with all Fab, Assembly, and Test subcontractors; FA labs Have implemented WIP, Sales, PO tracking system through Web-based service Very much involved in hands-on bring-up of new products (Debug, Characterization, Product Mask Revisions, Customer samples) Have; 1. Shipped > 8Mu of Imaging Product to Tier1 customer (Flextronics Sony/Erickson) with optimized, excellent test flow (multi-site probe, multi-site handler) with > 99% on time delivery of ALL line items to ALL sites. 2. Shipped Large volume of complex SOC to key customers in UK, Germany, Japan 3. Several very complex products in preproduction and pilot production mode (from 180nm, 130nm, 90nm, 65nm nodes)

C. Sensechip : V.P , IC Design and Operations (May 03-Mar 05): Self funded start-up with Angel funding to make chips for the Digital Cameras (DSC and Camcorder)did not get Series A funding D. Santel Networks, Fremont, Calif (Nov99-Mar03): V.P, I.C Engineering/Operations:
In charge of all Analog Design, Digital Design, and Operational activities (about 50 engineers). The group was working on OC-192 products for Long haul and metro area applications. Working with leading SiGe and mixed-mode CMOS technologies; advanced package vendors. The product family consisted of an Analog Chip (AFE) and a DSP Digital chip (FFE/DFE architecture). The AFE chip was fabricated in SiGe (Silicon Germanium) technology and the DSP chip was fabricated in 130nM technology (TSMC). The DSP chip processed data at OC192 (10Gbps) data rate (32 bits at 322MHz). The chipset worked at the designed targets. The product family was designed with a team of 5 DSP engineers, 6 Analog Design Engineers, and a team of Digital Design Engineers familiar with 130nM technology. The product objectives were to convert line signals into Digital Stream using AFE chip and use the DSP chip to process the information. Sampled industrys FIRST 10Gbps EDC Product. Santel closed in Mar 03 due to lack of Market in the Long Haul All products worked on First Silicon

E. Alliance Semiconductor, San Jose, Calif (June 95 Oct 99): Vice-President, Engineering:
In charge of Engineering Responsibilities for SRAMs and Embedded ASIC Products (20 engineers in Silicon Valley). The Embedded products include blocks of SRAMs, FLASH, DRAM, and other IP Cores in

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Jay Kumar
various advanced technologies that work in concert with complex Logic Blocks. Responsibilities include product definition, design, and transfer to production. The products are developed using advanced CAD tools and technologies. Interfaced heavily with Fabs on technology issues and all products worked the FIRST TIME and were transferred to production. In 4 years, transferred more than 20 products to production at UMC and CSM fabs. Developed several leading edge products: 10Port Fast Ethernet Chips physical implementation in 0.25u technology for a partner company. Technologies used: 0.18u; 0.25u CMOS

F. Advanced Micro Devices, Sunnyvale, Calif (Dec92-June95): Product Line Director/Business Manager: in charge of Peripheral Products for the PC:
In charge of Engineering Responsibilities for Design, Product / Test, Systems functions on several PCI products (Ethernet and SCSI controllers). The group successfully introduced several products for P5, K5 series of processors. The quarterly revenue at the peak was $20M. The group had engineers at 3 locations: Silicon Valley; Singapore; Austin totaling about 60

G. Chips and Technology, San Jose, Calif (Dec89-Dec92): Director of Engineering, Microprocessor Division:
Led engineering groups as Program Manager to accomplish fully working silicon of a Clean Room x 386 and X386+. The product started shipping and was manufactured at Far East foundries, Assembly, and Test houses and I traveled frequently to the sub-contractors to facilitate on time delivery.

H. Advanced Micro Devices, Sunnyvale, Calif (May84-Dec89): Product Line Director:

In charge of RAM Business Group with Engineering Responsibilities for Design, Product / Test, Systems functions; with business responsibilities for Production Control and Marketing. The Sales of the P & L center grew from $6M / Quarter to > $20M / Quarter under my guidance. The Business Group was ALWAYS profitable. The products were introduced on time and were better than or equal to the best competitive products in the market. .

---------------------------------------------------------------------------------------------------------------------------EDUCATION: MSEE: University of California, Berkeley BSEE: Indian Institute of Science, Bangalore, India,
Personal traits/Management Methods: 1. Ambitious, Goals driven, Results oriented, No-nonsense manager. 2. Lead by example (work hard and smart)high energy, enthusiastic, positive, aggressive, don't-like-to-lose attitude 3. Treat all stake holders (employees, investors, vendors, customers, partners.) with professional respect and courtesy 4. Manage by goals (consensus is required on key goals). Everyone is accountable; those who deliver excellent results get rewarded 5. Motivate by having BHAG (Big Hairy Audacious Goals), track them, get them done, and celebrate!! 6. At every stage, thoroughness, and attention to details is a must. Also, concise but effective checklists will be used as gating items to the next step. 7. Open, tactful, factual (backed by data or simulations or articles) communication is very much encouraged at all levels. 8. Know the individuals in the group. Travel frequently to remote Design Center, understand their requirements and limitations

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Jay Kumar
9. Travel frequently to Fab, Assembly partners--establish very good rapport 10. Involve the right people in negotiating prices (CAD tools, wafer cost, package cost.) 11. Sense of urgency (not sense of panic) is imparted in a constructive way

MAJOR AREAS OF EXPERTISE: A. Design and Development Engineering:

Very familiar and Hands-on with Digital and Analog Designs. In charge of Analog Design (very high speed), Digital Design (very high speed), and Reference Board Design groups at various companies. The teams have worked on: OC 192 products (10Gbps-12Gbps line rate) EDC Product; Digital Wrapper (OC192); 3D Graphics Product with Embedded DRAM; PC Peripheral products such as PCI-SCSI; 32 Bit Microprocessor (Chips x486). Have a success rate > 90% on the Projects. Very Familiar and Hands-on with all CAD tools from Cadence, Synopsys, Mentor and very good in bringing tools when needed, negotiating prices, and getting engineers trained. Also very familiar with Libraries available from Artisan, Virtual Silicon, Virage Logic, and TSMC (standard cell libraries, PLLs, PCI-X, LVDS 622MHz/1244MHz, SerDes etc)

B. Production Engineering and Operation/Management:

Worked with foundries (Far East and USA) to come up with leading edge products in Leading edge technologies (< 130nM) (working at Fabless semiconductor house) Successfully transferred products on various Advanced Technologies from R & D fab to Production Fab. Successfully transferred Products to Offshore Manufacturing areas with streamlined flow for excellent Cost structure, Quality, and Reliability (working at Companies with their own fabs, assembly, and test houses). Have been in charge of Product Engineering and Test Engineering Groups at several companies. Very good in: studying cost structures; implementing optimal flows and optimal hardware solutions (such as multi-site probecards, multi-site handlers etc) at sort, initial/final tests, QA flows and still keep quality levels very high. Experienced in Budget Management; Strong in Profit and Loss analysis; Have run P & L Centers (Business Groups) with an aggressive and likable style of management. Well developed interpersonal and communication skills and have run groups with > 100 engineering staff. Excellent in team building concepts and recruiting & keeping top-notch personnel with very low turnover. Experienced in making and presenting cohesive business plans to Business Community; Key Customers, and Key Vendors. Turned around losing P & L centers after a careful analysis and implementation of improved Cost Structures.

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