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8.

Instruction Set Reference

NII51017-9.0.0

Introduction
This section introduces the Nios® II instruction-word format and provides a detailed reference of the Nios II instruction set. This chapter contains the following sections:
■ ■ ■ ■ ■

“Word Formats” on page 8–1 “Instruction Opcodes” on page 8–2 “Assembler Pseudo-Instructions” on page 8–3 “Assembler Macros” on page 8–4 “Instruction Set Reference” on page 8–4

Word Formats
There are three types of Nios II instruction word format: I-type, R-type, and J-type.

I-Type
The defining characteristic of the I-type instruction-word format is that it contains an immediate value embedded within the instruction word. I-type instructions words contain:
■ ■ ■

A 6-bit opcode field OP Two 5-bit register fields A and B A 16-bit immediate data field IMM16

In most cases, fields A and IMM16 specify the source operands, and field B specifies the destination register. IMM16 is considered signed except for logical operations and unsigned comparisons. I-type instructions include arithmetic and logical operations such as addi and andi; branch operations; load and store operations; and cache management operations. The I-type instruction format is:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A

B

IMM16

OP

R-Type
The defining characteristic of the R-type instruction-word format is that all arguments and results are specified as registers. R-type instructions contain:
■ ■ ■

A 6-bit opcode field OP Three 5-bit register fields A, B, and C An 11-bit opcode-extension field OPX

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Nios II Processor Reference Handbook

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Chapter 8: Instruction Set Reference Instruction Opcodes

In most cases, fields A and B specify the source operands, and field C specifies the destination register. Some R-Type instructions embed a small immediate value in the low-order bits of OPX. R-type instructions include arithmetic and logical operations such as add and nor; comparison operations such as cmpeq and cmplt; the custom instruction; and other operations that need only register operands. The R-type instruction format is:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A

B

C

OPX

OP

J-Type
J-type instructions contain:
■ ■

A 6-bit opcode field A 26-bit immediate data field

J-type instructions, such as call and jmpi, transfer execution anywhere within a 256 MByte range. The J-type instruction format is:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IMMED26

OP

Instruction Opcodes
The OP field in the Nios II instruction word specifies the major class of an opcode as shown in Table 8–1 and Table 8–2. Most values of OP are encodings for I-type instructions. One encoding, OP = 0x00, is the J-type instruction call. Another encoding, OP = 0x3a, is used for all R-type instructions, in which case, the OPX field differentiates the instructions. All undefined encodings of OP and OPX are reserved.
Table 8–1. OP Encodings (Part 1 of 2) OP 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A ldbu addi stb br ldb cmpgei Instruction call jmpi OP 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A initda ori stw blt ldw cmpnei Instruction cmplti OP 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A ldbuio muli stbio beq ldbio cmpgeui Instruction cmpeqi OP 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A R-type custom initd orhi stwio bltu ldwio Instruction cmpltui

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Chapter 8: Instruction Set Reference Assembler Pseudo-Instructions

8–3

Table 8–1. OP Encodings (Part 2 of 2) OP 0x0B 0x0C 0x0D 0x0E 0x0F Instruction ldhu andi sth bge ldh OP 0x1B 0x1C 0x1D 0x1E 0x1F bne Instruction flushda xori OP 0x2B 0x2C 0x2D 0x2E 0x2F Instruction ldhuio andhi sthio bgeu ldhio OP 0x3B 0x3C 0x3D 0x3E 0x3F Instruction flushd xorhi

Table 8–2. OPX Encodings for R-Type Instructions OPX 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F ror flushi jmp and eret roli rol flushp ret nor mulxuu cmpge bret Instruction OPX 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F srli srl nextpc callr xor mulxss or mulxsu cmpne slli sll Instruction cmplt OPX 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F trap wrctl divu div rdctl mul cmpgeu initi Instruction cmpeq OPX 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F sub srai sra sync break Instruction cmpltu add

Assembler Pseudo-Instructions
Table 8–3 lists pseudo-instructions available in Nios II assembly language. Pseudo-instructions are used in assembly source code like regular assembly instructions. Each pseudo-instruction is implemented at the machine level using an equivalent instruction. The movia pseudo-instruction is the only exception, being implemented with two instructions. Most pseudo-instructions do not appear in disassembly views of machine code.
Table 8–3. Assembler Pseudo-Instructions (Part 1 of 2) Pseudo-Instruction bgt rA, rB, label bgtu rA, rB, label ble rA, rB, label bleu rA, rB, label cmpgt rC, rA, rB Equivalent Instruction blt rB, rA, label bltu rB, rA, label bge rB, rA, label bgeu rB, rA, label cmplt rC, rB, rA

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Nios II Processor Reference Handbook

rB. rB cmpgtui rB. rA cmplti rB. IMMED movi rB.16] of immed32 Extract bits [31.. r0. rA. rA. rA. When used with an instruction that requires a 16-bit signed immediate value. rA. these macros return a value ranging from 0 to 65535. IMMED cmpleu rC. rA. Assembler Macros Macro %lo(immed32) %hi(immed32) %hiadj(immed32) %gprel(immed32) Note to Table 8–4: (1) Refer to the Application Binary Interface chapter of the Nios II Processor Reference Handbook for more information about global pointers. r0. %hiadj(label) addi. rA movhi rB. rA. Description Extract bits [15. %lo(label) ori rB. rA... rB. Table 8–4 lists the available macros. r0. r0. (IMMED+1) cmpgeu rC. (-IMMED) Assembler Macros The Nios II assembler provides macros to extract halfwords from labels and from 32-bit immediate values. rB cmplei rB. IMMED nop subi rB. r0 orhi rB. rB. (IMMED+1) add rC. r0 addi rB. (IMMED+1) cmpge rC. rA. r0. rA. r0.8–4 Chapter 8: Instruction Set Reference Assembler Macros Table 8–3.0] of immed32 Extract bits [31. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rB. (IMMED+1) cmpltu rC. These macros return 16-bit signed values or 16-bit unsigned values depending on where they are used. IMMED orhi rB. When used with an instruction that requires a 16-bit unsigned immediate value. IMMED cmpgtu rC. Table 8–4. rA. IMMED movia rB.16] and adds bit 15 of immed32 Replace the immed32 address with an offset from the global pointer (1) Operation immed32 & 0xffff (immed32 >> 16) & 0xffff ((immed32 >> 16) & 0xffff) + ((immed32 >> 15) & 0x1) immed32 –_gp Instruction Set Reference The following pages list all Nios II instruction mnemonics in alphabetical order. rA cmpltui rB. label movui rB. rA. rA cmpgeui rB. Table 8–5 shows the notation conventions used to describe instruction operation. rA. IMMED mov rC. IMMED Equivalent Instruction cmpgei rB. Assembler Pseudo-Instructions (Part 2 of 2) Pseudo-Instruction cmpgti rB. IMMED add r0. rA. rA. IMMED cmple rC. IMMED addi. these macros return a value ranging from –32768 to 32767. rB. rB cmpleui rB.

(0x12 : 0x34) = 0x1234 The value of X after being sign-extended to a full register-sized signed integer The value X after being right-shifted n bit positions The value X after being left-shifted n bit positions Bitwise logical AND Bitwise logical OR Bitwise logical XOR Bitwise logical NOT (one’s complement) The byte located in data memory at byte-address X The halfword located in data memory at byte-address X The word located in data memory at byte-address X An address label specified in the assembly file The value of rX treated as a signed number The value of rX treated as an unsigned number Meaning The following exceptions are not listed for each instruction because they can occur on any instruction fetch: ■ ■ ■ ■ ■ Supervisor-only instruction address Fast TLB miss (instruction) Double TLB miss (instruction) TLB permission violation (execute) MPU region violation (instruction) f For details on these and all Nios II exceptions.m 0xNNMM X:Y σ(X) X >> n X << n X&Y X|Y X^Y ~X Mem8[X] Mem16[X] Mem32[X] label (signed) rX (unsigned) rX X is written with Y The program counter (PC) is written with address X. rB.. refer to the Programming Model chapter of the Nios II Processor Reference Handbook.Chapter 8: Instruction Set Reference Instruction Set Reference 8–5 Table 8–5. the instruction at X will be the next instruction to execute The address of the assembly instruction in question One of the 32-bit general-purpose registers An n-bit immediate value. rC IMMn IMMED Xn Xn. © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . Notation Conventions Notation X ←Y PC ← X PC rA. embedded in the instruction word An immediate value The nth bit of X. where n = 0 is the LSB Consecutive bits n through m of X Hexadecimal notation Bitwise concatenation For example.

a carry out of the MSB can be detected by checking whether the unsigned sum is less than one of the unsigned operands. Combine comparisons . The original add operation . rA. rC. r7. rA. rB Example: Description: add r6. rB cmpltu rD.label . rD. r8 Calculates the sum of rA and rB. Compare signs of sum and rA . Branch if carry was generated Overflow Detection (signed operands): An overflow is detected when two positives are added and the sum is negative. or when two negatives are added and the sum is positive. as shown below. or a conditional branch can be taken based on the carry condition. rA xor rE. r0. Stores the result in rC. add rC. Used for both signed and unsigned addition. rA add rC. The original add operation . Both cases are shown below. Compare signs of sum and rB . rA. rD is written with the carry bit . Usage: Carry Detection (unsigned operands): Following an add operation. rC. The carry bit can be written to a register. rB xor rD. rA. The original add operation . add rC. Branch if overflow occurred Exceptions: None Instruction Type: R Instruction Fields: A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x31 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rC. label . The overflow condition can control a conditional branch. rB bltu rC.8–6 Chapter 8: Instruction Set Reference Instruction Set Reference add Operation: rC ← rA + rB add Assembler Syntax: add rC. rA. rB and rD. rE blt rD.

rA. or when two negatives are added and the sum is positive. rD blt rC. Compare signs of sum and rA . IMM16 cmpltu rD. Branch if overflow occurred Exceptions: Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x04 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . The original add operation .Chapter 8: Instruction Set Reference Instruction Set Reference 8–7 addi Operation: Assembler Syntax: Example: Description: rB ← rA + σ (IMM16) addi rB. Combine comparisons . The carry bit can be written to a register. rA. IMM16 addi r6. Compare signs of sum and IMM16 . r0. label . a carry out of the MSB can be detected by checking whether the unsigned sum is less than one of the unsigned operands. IMM16 xor rC. rD is written with the carry bit . The overflow condition can control a conditional branch. rA. The original add operation . or a conditional branch can be taken based on the carry condition. IMM16 and rC. rA. r7. rA. Branch if carry was generated Overflow Detection (signed operands): An overflow is detected when two positives are added and the sum is negative. -100 add immediate Sign-extends the 16-bit immediate value and adds it to the value of rA. Both cases are shown below.label None . Stores the sum in rB. The original add operation . rB. as shown below. Usage: Carry Detection (unsigned operands): Following an addi operation. rC. rB. addi rB. rB. addi rB. rA xorhi rD. rA addi rB. IMM16 bltu rB.

Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x0e 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rB and r6. rA. r8 bitwise logical and Calculates the bitwise logical AND of rA and rB and stores the result in rC.8–8 Chapter 8: Instruction Set Reference Instruction Set Reference and Operation: Assembler Syntax: Example: Description: rC ← rA & rB and rC. r7.

Chapter 8: Instruction Set Reference Instruction Set Reference 8–9 andhi Operation: Assembler Syntax: Example: Description: bitwise logical and immediate into high halfword rB ← rA & (IMM16 : 0x0000) andhi rB. r7. 100 Calculates the bitwise logical AND of rA and (IMM16 : 0x0000) and stores the result in rB. rA. IMM16 andhi r6. Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x2c © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .

Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x0c Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . 100 bitwise logical and immediate Calculates the bitwise logical AND of rA and (0x0000 : IMM16) and stores the result in rB. rA. r7.8–10 Chapter 8: Instruction Set Reference Instruction Set Reference andi Operation: Assembler Syntax: Example: Description: rB ← rA & (0x0000 : IMM16) andi rB. IMM16 andi r6.

label branch if equal If rA == rB. rB. because instruction addresses must be word-aligned. the offset given by IMM16 is treated as a signed number of bytes relative to the instruction immediately following beq.Chapter 8: Instruction Set Reference Instruction Set Reference 8–11 beq Operation: if (rA == rB) then PC ← PC + 4 + σ (IMM16) else PC ← PC + 4 Assembler Syntax: Example: Description: beq rA. In the instruction encoding. The two least-significant bits of IMM16 are always zero. then beq transfers program control to the instruction at label. r7. label beq r6. Exceptions: Misaligned destination address Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x26 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .

Misaligned destination address Exceptions: Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x0e Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .8–12 Chapter 8: Instruction Set Reference Instruction Set Reference bge Operation: if ((signed) rA >= (signed) rB) then PC ← PC + 4 + σ (IMM16) else PC ← PC + 4 Assembler Syntax: Example: Description: bge rA. then bge transfers program control to the instruction at label. the offset given by IMM16 is treated as a signed number of bytes relative to the instruction immediately following bge. top_of_loop branch if greater than or equal signed If (signed) rA >= (signed) rB. label bge r6. because instruction addresses must be word-aligned. The two least-significant bits of IMM16 are always zero. r7. In the instruction encoding. rB.

top_of_loop branch if greater than or equal unsigned If (unsigned) rA >= (unsigned) rB. rB.Chapter 8: Instruction Set Reference Instruction Set Reference 8–13 bgeu Operation: if ((unsigned) rA >= (unsigned) rB) then PC ← PC + 4 + σ (IMM16) else PC ← PC + 4 Assembler Syntax: Example: Description: bgeu rA. then bgeu transfers program control to the instruction at label. In the instruction encoding. The two least-significant bits of IMM16 are always zero. the offset given by IMM16 is treated as a signed number of bytes relative to the instruction immediately following bgeu. Misaligned destination address Exceptions: Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x2e © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . r7. because instruction addresses must be word-aligned. label bgeu r6.

r7. label bgt r6. then bgt transfers program control to the instruction at label. bgt is implemented with the blt instruction by swapping the register operands. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .8–14 Chapter 8: Instruction Set Reference Instruction Set Reference bgt Operation: if ((signed) rA > (signed) rB) then PC ← label else PC ← PC + 4 Assembler Syntax: Example: Description: Pseudo-instruction: bgt rA. rB. top_of_loop branch if greater than signed If (signed) rA > (signed) rB.

© March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . then bgtu transfers program control to the instruction at label. top_of_loop branch if greater than unsigned If (unsigned) rA > (unsigned) rB.Chapter 8: Instruction Set Reference Instruction Set Reference 8–15 bgtu Operation: if ((unsigned) rA > (unsigned) rB) then PC ← label else PC ← PC + 4 Assembler Syntax: Example: Description: Pseudo-instruction: bgtu rA. label bgtu r6. rB. r7. bgtu is implemented with the bltu instruction by swapping the register operands.

r7. top_of_loop branch if less than or equal signed If (signed) rA <= (signed) rB. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . label ble r6. rB. then ble transfers program control to the instruction at label.8–16 Chapter 8: Instruction Set Reference Instruction Set Reference ble Operation: if ((signed) rA <= (signed) rB) then PC ← label else PC ← PC + 4 Assembler Syntax: Example: Description: Pseudo-instruction: ble rA. ble is implemented with the bge instruction by swapping the register operands.

top_of_loop branch if less than or equal to unsigned If (unsigned) rA <= (unsigned) rB. then bleu transfers program counter to the instruction at label.Chapter 8: Instruction Set Reference Instruction Set Reference 8–17 bleu Operation: if ((unsigned) rA <= (unsigned) rB) then PC ← label else PC ← PC + 4 Assembler Syntax: Example: Description: Pseudo-instruction: bleu rA. © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . rB. r7. label bleu r6. bleu is implemented with the bgeu instruction by swapping the register operands.

rB. In the instruction encoding. Exceptions: Misaligned destination address Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x16 Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . the offset given by IMM16 is treated as a signed number of bytes relative to the instruction immediately following blt. then blt transfers program control to the instruction at label. label branch if less than signed blt r6.8–18 Chapter 8: Instruction Set Reference Instruction Set Reference blt Operation: if ((signed) rA < (signed) rB) then PC ← PC + 4 + σ (IMM16) else PC ← PC + 4 Assembler Syntax: Example: Description: blt rA. r7. The two least-significant bits of IMM16 are always zero. because instruction addresses must be word-aligned. top_of_loop If (signed) rA < (signed) rB.

label bltu r6. Exceptions: Misaligned destination address Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB MM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x36 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . rB. because instruction addresses must be word-aligned. The two least-significant bits of IMM16 are always zero. top_of_loop branch if less than unsigned If (unsigned) rA < (unsigned) rB.Chapter 8: Instruction Set Reference Instruction Set Reference 8–19 bltu Operation: if ((unsigned) rA < (unsigned) rB) then PC ← PC + 4 + σ (IMM16) else PC ← PC + 4 Assembler Syntax: Example: Description: bltu rA. the offset given by IMM16 is treated as a signed number of bytes relative to the instruction immediately following bltu. In the instruction encoding. r7. then bltu transfers program control to the instruction at label.

The two least-significant bits of IMM16 are always zero. Exceptions: Misaligned destination address Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x1e Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . label bne r6. the offset given by IMM16 is treated as a signed number of bytes relative to the instruction immediately following bne. then bne transfers program control to the instruction at label. top_of_loop branch if not equal If rA != rB. because instruction addresses must be word-aligned. rB.8–20 Chapter 8: Instruction Set Reference Instruction Set Reference bne Operation: if (rA != rB) then PC ← PC + 4 + σ (IMM16) else PC ← PC + 4 Assembler Syntax: Example: Description: bne rA. r7. In the instruction encoding.

In the instruction encoding. Exceptions: Misaligned destination address Instruction Type: Instruction Fields: I IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 IMM16 0x06 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . because instruction addresses must be word-aligned. the offset given by IMM16 is treated as a signed number of bytes relative to the instruction immediately following br. The two least-significant bits of IMM16 are always zero.Chapter 8: Instruction Set Reference Instruction Set Reference 8–21 br Operation: Assembler Syntax: Example: Description: PC ← PC + 4 + σ (IMM16) br label br top_of_loop unconditional branch Transfers program control to the instruction at label.

The 5-bit immediate field imm5 is ignored by the processor.8–22 Chapter 8: Instruction Set Reference Instruction Set Reference break Operation: bstatus ← status PIE ← 0 U ←0 ba ← PC + 4 PC ← break handler address Assembler Syntax: Example: Description: break break imm5 break debugging breakpoint Breaks program execution and transfers control to the debugger break-processing routine. Only debuggers should place break in a user program. Saves the address of the next instruction in register ba and saves the contents of the status register in bstatus. Disables interrupts. Usage: break is used by debuggers exclusively. Exceptions: Break Instruction Type: Instruction Fields: R IMM5 = Type of breakpoint 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0x1e 0x34 IMM5 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . Some debuggers support break and break 0 instructions in source code. but it can be used by the debugger. operating system. or exception handler. These debuggers treat the break instruction as a normal breakpoint. break with no argument is the same as break 0. The address of the break handler is specified at system generation time. then transfers execution to the break handler.

Chapter 8: Instruction Set Reference Instruction Set Reference 8–23 bret Operation: Assembler Syntax: Example: Description: status ← bstatus PC ← ba bret bret breakpoint return Copies the value of bstatus to the status register. or exception handlers. then transfers execution to the address in ba. Exceptions: Misaligned destination address Supervisor-only instruction Instruction Type: Instruction Fields: R None 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1e 0 0 0x09 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . Usage: bret is used by debuggers exclusively and should not appear in user programs. operating systems.

8–24 Chapter 8: Instruction Set Reference Instruction Set Reference call Operation: ra ← PC + 4 PC ← (PC31. Exceptions: None Instruction Type: Instruction Fields: J IMM26 = 26-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMM26 0 Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .28 : IMM26 × 4)...28 : IMM26 × 4) Assembler Syntax: Example: Description: call label call write_char call subroutine Saves the address of the next instruction in register ra. The Nios II GNU linker does not automatically handle cases in which the address is out of this range..28. and transfers execution to the instruction at address (PC31. Usage: call can transfer execution anywhere within the 256 MByte range determined by PC31.

and transfers execution to the address contained in register rA. Usage: callr is used to dereference C-language function pointers.Chapter 8: Instruction Set Reference Instruction Set Reference 8–25 callr Operation: Assembler Syntax: Example: Description: ra ← PC + 4 PC ← rA callr rA callr r6 call subroutine in register Saves the address of the next instruction in the return-address register. Exceptions: Misaligned destination address Instruction Type: Instruction Fields: R A = Register index of operand rA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0x1f 0x1d 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .

compare equal Usage: cmpeq performs the == operation of the C programming language. stores 0 to rC. r7. then stores 1 to rC. rA. r8 If rA == rB. cmpeq can be used to implement the C logical-negation operator “!”. Implements rC = !rA Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x20 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rB cmpeq r6. otherwise.8–26 Chapter 8: Instruction Set Reference Instruction Set Reference cmpeq Operation: if (rA == rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmpeq rC. Also. rA. cmpeq rC. r0 .

r7. Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x20 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . otherwise stores 0 to rB. IMM16 cmpeqi r6. cmpeqi stores 1 to rB. 100 compare equal immediate Sign-extends the 16-bit immediate value IMM16 to 32 bits and compares it to the value of rA. rA. If rA == σ (IMM16).Chapter 8: Instruction Set Reference Instruction Set Reference 8–27 cmpeqi Operation: if (rA σ (IMM16)) then rB ← 1 else rB ← 0 Assembler Syntax: Example: Description: cmpeqi rB. Usage: cmpeqi performs the == operation of the C programming language.

8–28 Chapter 8: Instruction Set Reference Instruction Set Reference cmpge Operation: if ((signed) rA >= (signed) rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmpge rC. Usage: cmpge performs the signed >= operation of the C programming language. rA. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x08 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . r8 compare greater than or equal signed If rA >= rB. rB cmpge r6. otherwise stores 0 to rC. then stores 1 to rC. r7.

If rA >= σ(IMM16).Chapter 8: Instruction Set Reference Instruction Set Reference 8–29 cmpgei Operation: then rB ← 1 else rB ← 0 Assembler Syntax: Example: Description: compare greater than or equal signed immediate if ((signed) rA >= (signed) σ (IMM16)) cmpgei rB. r7. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x08 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . rA. IMM16 cmpgei r6. then cmpgei stores 1 to rB. 100 Sign-extends the 16-bit immediate value IMM16 to 32 bits and compares it to the value of rA. otherwise stores 0 to rB. Usage: cmpgei performs the signed >= operation of the C programming language.

Usage: cmpgeu performs the unsigned >= operation of the C programming language. r8 compare greater than or equal unsigned If rA >= rB. then stores 1 to rC.8–30 Chapter 8: Instruction Set Reference Instruction Set Reference cmpgeu Operation: if ((unsigned) rA >= (unsigned) rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmpgeu rC. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x28 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rB cmpgeu r6. r7. rA. otherwise stores 0 to rC.

rA. 100 Zero-extends the 16-bit immediate value IMM16 to 32 bits and compares it to the value of rA. Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x28 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . If rA >= (0x0000 : IMM16).Chapter 8: Instruction Set Reference Instruction Set Reference 8–31 cmpgeui Operation: compare greater than or equal unsigned immediate if ((unsigned) rA >= (unsigned) (0x0000 : IMM16)) then rB ← 1 else rB ← 0 cmpgeui rB. r7. IMM16 cmpgeui r6. otherwise stores 0 to rB. Assembler Syntax: Example: Description: Usage: cmpgeui performs the unsigned >= operation of the C programming language. then cmpgeui stores 1 to rB.

then stores 1 to rC. r8 compare greater than signed If rA > rB.8–32 Chapter 8: Instruction Set Reference Instruction Set Reference cmpgt Operation: if ((signed) rA > (signed) rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmpgt rC. Pseudo-instruction: cmpgt is implemented with the cmplt instruction by swapping its rA and rB operands. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rA. Usage: cmpgt performs the signed > operation of the C programming language. rB cmpgt r6. r7. otherwise stores 0 to rC.

rA. © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . IMMED cmpgti r6. then cmpgti stores 1 to rB. The minimum allowed value is –32769. 100 compare greater than signed immediate Sign-extends the immediate value IMMED to 32 bits and compares it to the value of rA. r7. If rA > σ(IMMED).Chapter 8: Instruction Set Reference Instruction Set Reference 8–33 cmpgti Operation: if ((signed) rA > (signed) IMMED) then rB ← 1 else rB ← 0 Assembler Syntax: Example: Description: cmpgti rB. Pseudo-instruction: cmpgti is implemented using a cmpgei instruction with an IMM16 immediate value of IMMED + 1. otherwise stores 0 to rB. The maximum allowed value of IMMED is 32766. Usage: cmpgti performs the signed > operation of the C programming language.

r7. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . otherwise stores 0 to rC. rB cmpgtu r6.8–34 Chapter 8: Instruction Set Reference Instruction Set Reference cmpgtu Operation: if ((unsigned) rA > (unsigned) rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmpgtu rC. r8 compare greater than unsigned If rA > rB. rA. Pseudo-instruction: cmpgtu is implemented with the cmpltu instruction by swapping its rA and rB operands. Usage: cmpgtu performs the unsigned > operation of the C programming language. then stores 1 to rC.

rA. IMMED cmpgtui r6. Pseudo-instruction: cmpgtui is implemented using a cmpgeui instruction with an IMM16 immediate value of IMMED + 1. The minimum allowed value is 0. Assembler Syntax: Example: Description: Usage: cmpgtui performs the unsigned > operation of the C programming language. If rA > IMMED. 100 Zero-extends the immediate value IMMED to 32 bits and compares it to the value of rA. The maximum allowed value of IMMED is 65534. then cmpgtui stores 1 to rB. r7.Chapter 8: Instruction Set Reference Instruction Set Reference 8–35 cmpgtui Operation: compare greater than unsigned immediate if ((unsigned) rA > (unsigned) IMMED) then rB ← 1 else rB ← 0 cmpgtui rB. © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . otherwise stores 0 to rB.

r8 compare less than or equal signed If rA <= rB. r7. rB cmple r6. Pseudo-instruction: cmple is implemented with the cmpge instruction by swapping its rA and rB operands. then stores 1 to rC.8–36 Chapter 8: Instruction Set Reference Instruction Set Reference cmple Operation: if ((signed) rA <= (signed) rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmple rC. otherwise stores 0 to rC. Usage: cmple performs the signed <= operation of the C programming language. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rA.

rA. then cmplei stores 1 to rB.Chapter 8: Instruction Set Reference Instruction Set Reference 8–37 cmplei Operation: compare less than or equal signed immediate if ((signed) rA < (signed) IMMED) then rB ← 1 else rB ← 0 cmplei rB. r7. 100 Sign-extends the immediate value IMMED to 32 bits and compares it to the value of rA. © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . otherwise stores 0 to rB. The minimum allowed value is –32769. The maximum allowed value of IMMED is 32766. Pseudo-instruction: cmplei is implemented using a cmplti instruction with an IMM16 immediate value of IMMED + 1. Assembler Syntax: Example: Description: Usage: cmplei performs the signed <= operation of the C programming language. If rA <= σ(IMMED). IMMED cmplei r6.

r7. rA. rB cmpleu r6. otherwise stores 0 to rC. then stores 1 to rC. Usage: cmpleu performs the unsigned <= operation of the C programming language. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . r8 compare less than or equal unsigned Description: If rA <= rB. Pseudo-instruction: cmpleu is implemented with the cmpgeu instruction by swapping its rA and rB operands.8–38 Chapter 8: Instruction Set Reference Instruction Set Reference cmpleu Operation: if ((unsigned) rA < (unsigned) rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: cmpleu rC.

Pseudo-instruction: cmpleui is implemented using a cmpltui instruction with an IMM16 immediate value of IMMED + 1. IMMED cmpleui r6. The minimum allowed value is 0. 100 Zero-extends the immediate value IMMED to 32 bits and compares it to the value of rA. then cmpleui stores 1 to rB. r7. © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . The maximum allowed value of IMMED is 65534.Chapter 8: Instruction Set Reference Instruction Set Reference 8–39 cmpleui Operation: compare less than or equal unsigned immediate if ((unsigned) rA <= (unsigned) IMMED) then rB ← 1 else rB ← 0 cmpleui rB. otherwise stores 0 to rB. rA. If rA <= IMMED. Assembler Syntax: Example: Description: Usage: cmpleui performs the unsigned <= operation of the C programming language.

rB cmplt r6.8–40 Chapter 8: Instruction Set Reference Instruction Set Reference cmplt Operation: if ((signed) rA < (signed) rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmplt rC. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x10 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . then stores 1 to rC. compare less than signed Usage: cmplt performs the signed < operation of the C programming language. r8 If rA < rB. otherwise stores 0 to rC. rA. r7.

Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x10 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . r7. rA. Usage: cmplti performs the signed < operation of the C programming language. then cmplti stores 1 to rB. If rA < σ (IMM16).Chapter 8: Instruction Set Reference Instruction Set Reference 8–41 cmplti Operation: if ((signed) rA < (signed) σ (IMM16)) then rB ← 1 else rB ← 0 Assembler Syntax: Example: Description: cmplti rB. IMM16 cmplti r6. 100 compare less than signed immediate Sign-extends the 16-bit immediate value IMM16 to 32 bits and compares it to the value of rA. otherwise stores 0 to rB.

r7. compare less than unsigned Usage: cmpltu performs the unsigned < operation of the C programming language. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x30 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rA. then stores 1 to rC.8–42 Chapter 8: Instruction Set Reference Instruction Set Reference cmpltu Operation: if ((unsigned) rA < (unsigned) rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmpltu rC. r8 If rA < rB. otherwise stores 0 to rC. rB cmpltu r6.

r7.Chapter 8: Instruction Set Reference Instruction Set Reference 8–43 cmpltui Operation: then rB ← 1 else rB ← 0 Assembler Syntax: Example: Description: cmpltui rB. 100 compare less than unsigned immediate if ((unsigned) rA < (unsigned) (0x0000 : IMM16)) Zero-extends the 16-bit immediate value IMM16 to 32 bits and compares it to the value of rA. IMM16 cmpltui r6. Usage: cmpltui performs the unsigned < operation of the C programming language. If rA < (0x0000 : IMM16). rA. then cmpltui stores 1 to rB. otherwise stores 0 to rB. Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x30 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .

then stores 1 to rC. rB cmpne r6. r7. rA. otherwise stores 0 to rC. r8 If rA != rB. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x18 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .8–44 Chapter 8: Instruction Set Reference Instruction Set Reference cmpne Operation: if (rA != rB) then rC ← 1 else rC ← 0 Assembler Syntax: Example: Description: cmpne rC. compare not equal Usage: cmpne performs the != operation of the C programming language.

Usage: cmpnei performs the != operation of the C programming language. IMM16 cmpnei r6. r7.Chapter 8: Instruction Set Reference Instruction Set Reference 8–45 cmpnei Operation: if (rA != σ (IMM16)) then rB ← 1 else rB ← 0 Assembler Syntax: Example: Description: cmpnei rB. Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x18 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . 100 compare not equal immediate Sign-extends the 16-bit immediate value IMM16 to 32 bits and compares it to the value of rA. then cmpnei stores 1 to rB. If rA != σ (IMM16). otherwise stores 0 to rB. rA.

xB custom instruction Where xA means either general purpose register rA. r5. r8 The custom opcode provides access to up to 256 custom instructions allowed by the Nios II architecture. For example. readrb. The function implemented by a custom instruction is user-defined and is specified at system generation time. c3. A. r7. C) Assembler Syntax: Example: Description: custom N. B. and stores the result in custom register 3. or custom register cA. The 8-bit immediate N field specifies which custom instruction to use. xC. 0 otherwise N = 8-bit number that selects instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C ra rb rc N 0x32 Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . the notation cN refers to register N in the custom register file and causes the assembler to clear the c bit of the opcode. r0 performs custom instruction 0. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand A B = Register index of operand B C = Register index of operand C readra = 1 if instruction uses rA. rB. 0 otherwise writerc = 1 if instruction provides result for rC.8–46 Chapter 8: Instruction Set Reference Instruction Set Reference custom Operation: if c == 1 then rC ← fN(rA. 0 otherwise readrb = 1 if instruction uses rB. Custom instructions can use up to two parameters. custom 0. operating on general-purpose registers r5 and r0. C) else Ø ← fN(rA. and can optionally write the result to a register xC. rB. or writerc that corresponds to the register field. xA. Usage: To access a custom register inside the custom instruction logic. clear the bit readra. A. c6. xA and xB. B. In assembler syntax. custom 0.

The original div operation . rA. rA. Usage: Remainder of Division: If the result of the division is defined. After attempted division by zero. Nios II processors that do not implement the div instruction cause an unimplemented-instruction exception. then the remainder can be computed in rD using the following instruction sequence: div rC. r8 divide Treating rA and rB as signed integers.Chapter 8: Instruction Set Reference Instruction Set Reference 8–47 div Operation: Assembler Syntax: Example: Description: rC ← rA ÷ rB div rC. After dividing –2147483648 by –1. rB div r6. rD = remainder Exceptions: Division error Unimplemented instruction Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x25 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . rB mul rD. this instruction divides rA by rB and then stores the integer portion of the resulting quotient to rC. the value of rC is undefined. There is no overflow exception. rA. the value of rC is undefined (the number +2147483648 is not representable in 32 bits). rD . r7. rB sub rD. rC. There is no divide-by-zero exception.

rB divu r6. rD . The original divu operation Exceptions: Division error Unimplemented instruction Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x24 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rA. rC. this instruction divides rA by rB and then stores the integer portion of the resulting quotient to rC.8–48 Chapter 8: Instruction Set Reference Instruction Set Reference divu Operation: Assembler Syntax: Example: Description: rC ← rA ÷ rB divu rC. the value of rC is undefined. r8 divide unsigned Treating rA and rB as unsigned integers. r7. There is no divide-by-zero exception. Nios II processors that do not implement the divu instruction cause an unimplemented-instruction exception. rA. Usage: Remainder of Division: If the result of the division is defined. After attempted division by zero. rD = remainder . rB mul rD. rB sub rD. rA. then the remainder can be computed in rD using the following instruction sequence: divu rC.

Chapter 8: Instruction Set Reference Instruction Set Reference 8–49 eret Operation: Assembler Syntax: Example: Description: status ← estatus PC ← ea eret eret exception return Copies the value of estatus into the status register. and other exception-handling routines. external interrupts. and transfers execution to the address in ea. Note that before returning from hardware interrupt exceptions. Usage: Use eret to return from traps. the exception handler must adjust the ea register. Exceptions: Misaligned destination address Supervisor-only instruction Instruction Type: Instruction Fields: R None 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1d 0x1e 0 0x01 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .

flushd writes the data cache line that is mapped to the specified address back to memory if the line is dirty. the flushd instruction performs no operation. A cache line is dirty when one or more words of the cache line have been modified by the processor. write the line back to memory. Identify the data cache line associated with the computed effective address. If the data cache line is dirty. Each data cache effective address comprises a tag field and a line field. flushd writes the dirty data back to memory even when the addressed data is not currently in the cache. Usage: Use flushd to write dirty lines back to memory even if the addressed memory location is not in the cache. By contrast. flushd flushes the cache line regardless of whether the specified data location is currently cached. but have not yet been written to memory. This process comprises the following steps: ■ Compute the effective address specified by the sum of rA and the signed 16-bit immediate value. Clear the valid bit for the line. and “initda initialize data cache address” on page 8–55 for other cache-clearing options. ■ ■ ■ ■ If the Nios II processor core does not have a data cache. Unlike flushda.8–50 Chapter 8: Instruction Set Reference Instruction Set Reference flushd Operation: Assembler Syntax: Example: Description: flush data cache line Flushes the data cache line associated with address rA + σ (IMM16). flushd ignores the tag field and only uses the line field to select the data cache line to clear. Skip comparing the cache line tag with the effective address to determine if the addressed data is currently cached. and then flush the cache line. Because flushd ignores the cache line tag. When identifying the data cache line. flushd IMM16(rA) flushd -100(r6) If the Nios II processor implements a direct mapped data cache. For more information on data cache. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. and then clears the data cache line. Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 IMM16 0x3b Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . “initd initialize data cache line” on page 8–54. refer to “flushda flush data cache address” on page 8–51.

Each data cache effective address comprises a tag field and a line field. “initd initialize data cache line” on page 8–54. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. flushda writes the dirty data back to memory only when the addressed data is currently in the cache. refer to “flushd flush data cache line” on page 8–50. and then flush the cache line. When identifying the line. A cache line is dirty when one or more words of the cache line have been modified by the processor. flushda uses both the tag field and the line field. and “initda initialize data cache address” on page 8–55 for other cache-clearing options. For more information on the Nios II data cache. Clear the valid bit for the line. but are not yet written to memory. Exceptions: Supervisor-only data address Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 IMM16 0x1b © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . and then clears the data cache line. the effective address is not currently cached.Chapter 8: Instruction Set Reference Instruction Set Reference 8–51 flushda Operation: Assembler Syntax: Example: Description: flush data cache address Flushes the data cache line currently caching address rA + σ (IMM16) flushda IMM16(rA) flushda -100(r6) If the Nios II processor implements a direct mapped data cache. write the dirty cache line back to memory. By contrast. Usage: Use flushda to write dirty lines back to memory only if the addressed memory location is currently in the cache. Unlike flushd. flushda writes the data cache line that is mapped to the specified address back to memory if the line is dirty. Compare the cache line tag with the effective address to determine if the addressed data is currently cached. If the tag fields do not match. Identify the data cache line associated with the computed effective address. ■ ■ ■ ■ If the Nios II processor core does not have a data cache. so the instruction does nothing. the flushda instruction performs no operation. This process comprises the following steps: ■ Compute the effective address specified by the sum of rA and the signed 16-bit immediate value. If the data cache line is dirty and the tag fields match.

For more information about the data cache. flushi rA flushi r6 Ignoring the tag.8–52 Chapter 8: Instruction Set Reference Instruction Set Reference flushi Operation: Assembler Syntax: Example: Description: flush instruction cache line Flushes the instruction-cache line associated with address rA. flushi identifies the instruction-cache line associated with the byte address in rA. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0x0c 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . If the Nios II processor core does not have an instruction cache. and invalidates that line. the flushi instruction performs no operation. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook.

Usage: Use flushp before transferring control to newly updated instruction memory.Chapter 8: Instruction Set Reference Instruction Set Reference 8–53 flushp Operation: Assembler Syntax: Example: Description: Flushes the processor pipeline of any pre-fetched instructions. flushp flushp flush pipeline Ensures that any instructions pre-fetched after the flushp instruction are removed from the pipeline. Exceptions: None Instruction Type: Instruction Fields: R None 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0x04 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .

Skip comparing the cache line tag with the effective address to determine if the addressed data is currently cached. This process comprises the following steps: ■ Compute the effective address specified by the sum of rA and the signed 16-bit immediate value. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. data that has been modified by the processor. the initd instruction performs no operation.8–54 Chapter 8: Instruction Set Reference Instruction Set Reference initd Operation: Assembler Syntax: Example: Description: initialize data cache line Initializes the data cache line associated with address rA + σ (IMM16). Usage: Use initd after processor reset and before accessing data memory to initialize the processor’s data cache. initd flushes the cache line regardless of whether the specified data location is currently cached. Skip checking if the data cache line is dirty. Each data cache effective address comprises a tag field and a line field. Because initd skips the dirty cache line check. ■ ■ ■ ■ If the Nios II processor core does not have a data cache. initd ignores the tag field and only uses the line field to select the data cache line to clear. For more information on data cache. “flushda flush data cache address” on page 8–51. Unlike initda. Altera recommends using initd only when the processor comes out of reset. refer to “flushd flush data cache line” on page 8–50. but not yet written to memory is lost. Clear the valid bit for the line. initd IMM16(rA) initd 0(r6) If the Nios II processor implements a direct mapped data cache. Use initd with caution because it does not write back dirty data. Because initd ignores the cache line tag. initd clears the cache line regardless of whether the addressed data is currently cached. Identify the data cache line associated with the computed effective address. Exceptions: Supervisor-only instruction Instruction Type: Instruction Fields: I A = Register index of operand rA IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 IMM16 0x33 Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . By contrast. initd clears the data cache line without checking for (or writing) a dirty data cache line that is mapped to the specified address back to memory. and “initda initialize data cache address” on page 8–55 for other cache-clearing options. When identifying the line.

the initda instruction performs no operation. so the instruction does nothing. When identifying the line. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. initda clears the cache line only when the addressed data is currently cached. Skip checking if the data cache line is dirty.Chapter 8: Instruction Set Reference Instruction Set Reference 8–55 initda Operation: Assembler Syntax: Example: Description: initialize data cache address Initializes the data cache line currently caching address rA + σ (IMM16) initda IMM16(rA) initda -100(r6) If the Nios II processor implements a direct mapped data cache. and “initd initialize data cache line” on page 8–54 for other cache-clearing options. Unlike initd. the effective address is not currently cached. Exceptions: Supervisor-only data address Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Unimplemented instruction Instruction Type: Instruction Fields: I A = Register index of operand rA IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 IMM16 0x13 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . ■ ■ ■ ■ If the Nios II processor core does not have a data cache. Each data cache effective address comprises a tag field and a line field. Because initd skips the dirty cache line check. initda uses both the tag field and the line field. For more information on the Nios II data cache. Use initda with caution because it does not write back dirty data. By contrast. refer to “flushd flush data cache line” on page 8–50. but not yet written to memory is lost. Clear the valid bit for the line. initda clears the data cache line without checking for (or writing) a dirty data cache line that is mapped to the specified address back to memory. data that has been modified by the processor. This process comprises the following steps: ■ Compute the effective address specified by the sum of rA and the signed 16-bit immediate value. If the tag fields do not match. “flushda flush data cache address” on page 8–51. Usage: Use initda to skip writing dirty lines back to memory and to flush the cache line only if the addressed memory location is currently in the cache. Compare the cache line tag with the effective address to determine if the addressed data is currently cached. Identify the data cache line associated with the computed effective address.

refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. and initi invalidates that line. Exceptions: Supervisor-only instruction Instruction Type: Instruction Fields: R A = Register index of operand rA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0x29 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . If the Nios II processor core does not have an instruction cache. For more information on instruction cache. use initi to invalidate each line of the instruction cache. initi identifies the instruction-cache line associated with the byte address in ra. Usage: This instruction is used to initialize the processor’s instruction cache. Immediately after processor reset. the initi instruction performs no operation. initi rA initi r6 Ignoring the tag.8–56 Chapter 8: Instruction Set Reference Instruction Set Reference initi Operation: Assembler Syntax: Example: Description: initialize instruction cache line Initializes the instruction-cache line associated with address rA.

use ret instead of jmp. To return from subroutines called by call or callr.Chapter 8: Instruction Set Reference Instruction Set Reference 8–57 jmp Operation: Assembler Syntax: Example: Description: PC ← rA jmp rA jmp r12 Transfers execution to the address contained in register rA. Exceptions: Misaligned destination address Instruction Type: Instruction Fields: R A = Register index of operand rA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0x0d 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . computed jump Usage: It is illegal to jump to the address contained in register r31.

. Exceptions: None Instruction Type: Instruction Fields: J IMM26 = 26-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMM26 0x01 Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . jump immediate Usage: jmpi is a low-overhead local jump.8–58 Chapter 8: Instruction Set Reference Instruction Set Reference jmpi Operation: Assembler Syntax: Example: Description: PC ← (PC31..28 : IMM26 × 4).28. The Nios II GNU linker does not automatically handle cases in which the address is out of this range. jmpi can transfer execution anywhere within the 256 MByte range determined by PC31.28 : IMM26 × 4) jmpi label jmpi write_char Transfers execution to the instruction at address (PC31..

In Nios II processor cores with a data cache. ldbio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. byte_offset(rA) ldbio rB. byte_offset(rA) Example: Description: ldb r6. In processors without a data cache. Exceptions: Supervisor-only data address Misaligned data address TLB permission violation (read) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldb 0x07 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldbio 0x27 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . ldbio acts like ldb. Loads register rB with the desired memory byte. this instruction may retrieve the desired data from the cache instead of from memory. Usage: Use the ldbio instruction for peripheral I/O. In processors with a data cache.Chapter 8: Instruction Set Reference Instruction Set Reference 8–59 ldb / ldbio Operation: Assembler Syntax: rB ← σ (Mem8[rA + σ (IMM16)]) ldb rB. 100(r5) load byte from memory or I/O peripheral Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value. sign extending the 8-bit value to 32 bits. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. For more information on data cache.

ldbuio acts like ldbu. this instruction may retrieve the desired data from the cache instead of from memory. zero extending the 8-bit value to 32 bits. ldbuio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. In processors without a data cache. Usage: In processors with a data cache. Use the ldbuio instruction for peripheral I/O. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. In processors with a data cache. Exceptions: ■ ■ ■ ■ ■ ■ Supervisor-only data address Misaligned data address TLB permission violation (read) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldbu 0x03 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldbuio 0x23 Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . Loads register rB with the desired memory byte. For more information on data cache. 100(r5) Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value.8–60 Chapter 8: Instruction Set Reference Instruction Set Reference ldbu / ldbuio Operation: Assembler Syntax: Example: Description: load unsigned byte from memory or I/O peripheral rB ← 0x000000 : Mem8[rA + σ (IMM16)] ldbu rB. byte_offset(rA) ldbuio rB. byte_offset(rA) ldbu r6.

For more information on data cache. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. sign extending the 16-bit value to 32 bits. ldhio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. ldhio acts like ldh. If the byte address is not a multiple of 2. The effective byte address must be halfword aligned. Loads register rB with the memory halfword located at the effective byte address. In processors without a data cache. Use the ldhio instruction for peripheral I/O. 100(r5) Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value. Exceptions: ■ ■ ■ ■ ■ ■ Supervisor-only data address Misaligned data address TLB permission violation (read) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldh 0x0f 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldhio 0x2f © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . byte_offset(rA) ldhio rB. the operation is undefined. this instruction may retrieve the desired data from the cache instead of from memory. Usage: In processors with a data cache.Chapter 8: Instruction Set Reference Instruction Set Reference 8–61 ldh / ldhio Operation: Assembler Syntax: Example: Description: load halfword from memory or I/O peripheral rB ← σ (Mem16[rA + σ (IMM16)]) ldh rB. byte_offset(rA) ldh r6. In processors with a data cache.

Usage: In processors with a data cache.8–62 Chapter 8: Instruction Set Reference Instruction Set Reference ldhu / ldhuio Operation: Assembler Syntax: Example: Description: load unsigned halfword from memory or I/O peripheral rB ← 0x0000 : Mem16[rA + σ (IMM16)] ldhu rB. Exceptions: Supervisor-only data address Misaligned data address TLB permission violation (read) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldhu 0x0b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldhuio 0x2b Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . The effective byte address must be halfword aligned. If the byte address is not a multiple of 2. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. In processors with a data cache. Loads register rB with the memory halfword located at the effective byte address. ldhuio acts like ldhu. byte_offset(rA) ldhu r6. the operation is undefined. 100(r5) Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value. For more information on data cache. byte_offset(rA) ldhuio rB. this instruction may retrieve the desired data from the cache instead of from memory. Use the ldhuio instruction for peripheral I/O. In processors without a data cache. ldhuio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. zero extending the 16-bit value to 32 bits.

The effective byte address must be word aligned. byte_offset(rA) ldw r6. this instruction may retrieve the desired data from the cache instead of from memory. byte_offset(rA) ldwio rB. Use the ldwio instruction for peripheral I/O. Use the ldwio instruction for peripheral I/O. ldwio bypasses the cache and memory. Usage: In processors with a data cache. In processors with a data cache. refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. In processors with a data cache. If the byte address is not a multiple of 4. In processors without a data cache. For more information on data cache.Chapter 8: Instruction Set Reference Instruction Set Reference 8–63 ldw / ldwio Operation: Assembler Syntax: Example: Description: load 32-bit word from memory or I/O peripheral rB ← Mem32[rA + σ (IMM14)] ldw rB. Exceptions: Supervisor-only data address Misaligned data address TLB permission violation (read) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldw 0x17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for ldwio 0x37 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . ldwio acts like ldw. the operation is undefined. ldwio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. Loads register rB with the memory word located at the effective byte address. 100(r5) Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value.

rA. r0. rA mov r6. mov is implemented as add rC. move register to register Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . r7 Moves the contents of rA to rC.8–64 Chapter 8: Instruction Set Reference Instruction Set Reference mov Operation: Assembler Syntax: Example: Description: Pseudo-instruction: rC ← rA mov rC.

The %hi() macro can be used to extract the upper 16 bits of a constant or a label. %hi(value) ori rB. IMMED movhi r6. movhi rB. 0x8000 move immediate into high halfword Writes the immediate value IMMED into the high halfword of rB. load the lower 16 bits with an ori instruction.Chapter 8: Instruction Set Reference Instruction Set Reference 8–65 movhi Operation: Assembler Syntax: Example: Description: rB ← (IMMED : 0x0000) movhi rB. movhi rB. Usage: The maximum allowed value of IMMED is 65535. %lo(value) An alternative method to load a 32-bit constant into a register uses the %hiadj() macro and the addi instruction as shown below. Then. r0. The minimum allowed value is 0. rB. The %lo() macro can be used to extract the lower 16 bits of a constant or label as shown below. rB. IMMED. %hiadj(value) addi rB. © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . To load a 32-bit constant into a register. %lo(value) Pseudo-instruction: movhi is implemented as orhi rB. first load the upper 16 bits using a movhi pseudo-instruction. and clears the lower halfword of rB to 0x0000.

The minimum allowed value is –32768. Pseudo-instruction: movi is implemented as addi rB. -30 move signed immediate into word Sign-extends the immediate value IMMED to 32 bits and writes it to rB. To load a 32-bit constant into a register.8–66 Chapter 8: Instruction Set Reference Instruction Set Reference movi Operation: Assembler Syntax: Example: Description: rB ← σ (IMMED) movi rB. IMMED movi r6. Usage: The maximum allowed value of IMMED is 32767. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . IMMED. r0. refer to the movhi instruction.

function_address Writes the address of label to rB. %hiadj(label) addi rB. r0. label movia r6. movia is implemented as: orhi rB. rB.Chapter 8: Instruction Set Reference Instruction Set Reference 8–67 movia Operation: Assembler Syntax: Example: Description: Pseudo-instruction: rB ← label movia rB. %lo(label) move immediate address into word © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .

Usage: The maximum allowed value of IMMED is 65535. r0. refer to the movhi instruction. Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . To load a 32-bit constant into a register. IMMED movui r6. The minimum allowed value is 0. 100 move unsigned immediate into word Zero-extends the immediate value IMMED to 32 bits and writes it to rB. IMMED. Pseudo-instruction: movui is implemented as ori rB.8–68 Chapter 8: Instruction Set Reference Instruction Set Reference movui Operation: Assembler Syntax: Example: Description: rB ← (0x0000 : IMMED) movui rB.

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mul
Operation: Assembler Syntax: Example: Description: rC ← (rA × rB) 31..0 mul rC, rA, rB mul r6, r7, r8

multiply

Multiplies rA times rB and stores the 32 low-order bits of the product to rC. The result is the same whether the operands are treated as signed or unsigned integers. Nios II processors that do not implement the mul instruction cause an unimplemented-instruction exception.

Usage:

Carry Detection (unsigned operands): Before or after the multiply operation, the carry out of the MSB of rC can be detected using the following instruction sequence: mul rC, rA, rB mulxuu rD, rA, rB cmpne rD, rD, r0 ; The mul operation (optional) ; rD is non-zero if carry occurred ; rD is 1 if carry occurred, 0 if not

The mulxuu instruction writes a non-zero value into rD if the multiplication of unsigned numbers will generate a carry (unsigned overflow). If a 0/1 result is desired, follow the mulxuu with the cmpne instruction. Overflow Detection (signed operands): After the multiply operation, overflow can be detected using the following instruction sequence: mul rC, rA, rB cmplt rD, rC, r0 mulxss rE, rA, rB add rD, rD, rE cmpne rD, rD, r0 ; rD is non-zero if overflow ; rD is 1 if overflow, 0 if not ; The original mul operation

The cmplt–mulxss–add instruction sequence writes a non-zero value into rD if the product in rC cannot be represented in 32 bits (signed overflow). If a 0/1 result is desired, follow the instruction sequence with the cmpne instruction.

Exceptions:

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muli
Operation: Assembler Syntax: Example: Description: rB ← (rA × σ(IMM16)) 31..0 muli rB, rA, IMM16 muli r6, r7, -100

multiply immediate

Sign-extends the 16-bit immediate value IMM16 to 32 bits and multiplies it by the value of rA. Stores the 32 low-order bits of the product to rB. The result is independent of whether rA is treated as a signed or unsigned number.

Nios II processors that do not implement the muli instruction cause an unimplemented-instruction exception.

Carry Detection and Overflow Detection: For a discussion of carry and overflow detection, refer to the mul instruction.

Exceptions:

Unimplemented instruction

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I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value

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mulxss
Operation: Assembler Syntax: Example: Description: rC ← ((signed) rA) × ((signed) rB)) 63..32 mulxss rC, rA, rB mulxss r6, r7, r8

multiply extended signed/signed

Treating rA and rB as signed integers, mulxss multiplies rA times rB, and stores the 32 high-order bits of the product to rC.

Nios II processors that do not implement the mulxss instruction cause an unimplemented-instruction exception.

Usage:

Use mulxss and mul to compute the full 64-bit product of two 32-bit signed integers. Furthermore, mulxss can be used as part of the calculation of a 128-bit product of two 64-bit signed integers. Given two 64-bit integers, each contained in a pair of 32-bit registers, (S1 : U1) and (S2 : U2), their 128-bit product is (U1 × U2) + ((S1 × U2) << 32) + ((U1 × S2) << 32) + ((S1 × S2) << 64). The mulxss and mul instructions are used to calculate the 64-bit product S1 × S2.

Exceptions:

Unimplemented instruction

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R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC

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rA. Usage: mulxsu can be used as part of the calculation of a 128-bit product of two 64-bit signed integers. r7. Nios II processors that do not implement the mulxsu instruction cause an unimplemented-instruction exception. Exceptions: Unimplemented instruction Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x17 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .8–72 Chapter 8: Instruction Set Reference Instruction Set Reference mulxsu Operation: Assembler Syntax: Example: Description: rC ← ((signed) rA) × ((unsigned) rB)) 63. mulxsu multiplies rA times rB. each contained in a pair of 32-bit registers. rB mulxsu r6.. their 128-bit product is: (U1 × U2) + ((S1 × U2) << 32) + ((U1 × S2) << 32) + ((S1 × S2) << 64). (S1 : U1) and (S2 : U2). Given two 64-bit integers. and stores the 32 high-order bits of the product to rC. The mulxsu and mul instructions are used to calculate the two 64-bit products S1 × U2 and U1 × S2.32 mulxsu rC. r8 multiply extended signed/unsigned Treating rA as a signed integer and rB as an unsigned integer.

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mulxuu
Operation: Assembler Syntax: Example: Description:

multiply extended unsigned/unsigned
rC ← ((unsigned) rA) × ((unsigned) rB)) 63..32 mulxuu rC, rA, rB mulxuu r6, r7, r8 Treating rA and rB as unsigned integers, mulxuu multiplies rA times rB and stores the 32 high-order bits of the product to rC.

Nios II processors that do not implement the mulxuu instruction cause an unimplemented-instruction exception.

Usage:

Use mulxuu and mul to compute the 64-bit product of two 32-bit unsigned integers. Furthermore, mulxuu can be used as part of the calculation of a 128-bit product of two 64-bit signed integers. Given two 64-bit signed integers, each contained in a pair of 32-bit registers, (S1 : U1) and (S2 : U2), their 128-bit product is (U1 × U2) + ((S1 × U2) << 32) + ((U1 × S2) << 32) + ((S1 × S2) << 64). The mulxuu and mul instructions are used to calculate the 64-bit product U1 × U2. mulxuu also can be used as part of the calculation of a 128-bit product of two 64-bit unsigned integers. Given two 64-bit unsigned integers, each contained in a pair of 32-bit registers, (T1 : U1) and (T2 : U2), their 128-bit product is (U1 × U2) + ((U1 × T2) << 32) + ((T1 × U2) << 32) + ((T1 × T2) << 64). The mulxuu and mul instructions are used to calculate the four 64-bit products U1 × U2, U1 × T2, T1 × U2, and T1 × T2.

Exceptions:

Unimplemented instruction

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R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC

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nextpc
Operation: Assembler Syntax: Example: Description: rC ← PC + 4 nextpc rC nextpc r6

get address of following instruction

Stores the address of the next instruction to register rC.

Usage:

A relocatable code fragment can use nextpc to calculate the address of its data segment. nextpc is the only way to access the PC directly.

Exceptions:

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R C = Register index of operand rC

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Operation: Assembler Syntax: Example: Description: Pseudo-instruction: None nop nop nop does nothing. nop is implemented as add r0, r0, r0.

no operation

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8–76 Chapter 8: Instruction Set Reference Instruction Set Reference nor Operation: Assembler Syntax: Example: Description: rC ← ~(rA | rB) nor rC. r8 bitwise logical nor Calculates the bitwise logical NOR of rA and rB and stores the result in rC. rA. rB nor r6. r7. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x06 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .

rA. bitwise logical or Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x16 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .Chapter 8: Instruction Set Reference Instruction Set Reference 8–77 or Operation: Assembler Syntax: Example: Description: rC ← rA | rB or rC. r8 Calculates the bitwise logical OR of rA and rB and stores the result in rC. rB or r6. r7.

IMM16 orhi r6. 100 Calculates the bitwise logical OR of rA and (IMM16 : 0x0000) and stores the result in rB.8–78 Chapter 8: Instruction Set Reference Instruction Set Reference orhi Operation: Assembler Syntax: Example: Description: bitwise logical or immediate into high halfword rB ← rA | (IMM16 : 0x0000) orhi rB. rA. r7. Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x34 Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .

rA. Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x14 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . r7.Chapter 8: Instruction Set Reference Instruction Set Reference 8–79 ori Operation: Assembler Syntax: Example: Description: rB ← rA | (0x0000 : IMM16) ori rB. IMM16 ori r6. 100 bitwise logical or immediate Calculates the bitwise logical OR of rA and (0x0000 : IMM16) and stores the result in rB.

8–80 Chapter 8: Instruction Set Reference Instruction Set Reference rdctl Operation: Assembler Syntax: Example: Description: rC ← ctlN rdctl rC. ctl31 read from control register Reads the value contained in control register ctlN and writes it to register rC. Exceptions: Supervisor-only instruction Instruction Type: Instruction Fields: R C = Register index of operand rC N = Control register index of operand ctlN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 C 0x26 N 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . ctlN rdctl r3.

Exceptions: Misaligned destination address Instruction Type: Instruction Fields: R None 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1f 0 0 0x05 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .Chapter 8: Instruction Set Reference Instruction Set Reference 8–81 ret Operation: Assembler Syntax: Example: Description: PC ← ra ret ret Transfers execution to the address in ra. return from subroutine Usage: Any subroutine called by call or callr must use ret to return.

The bits that shift out of the register rotate into the least-significant bit positions.0 and stores the result in rC...0 bit positions rol rC. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x03 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .8–82 Chapter 8: Instruction Set Reference Instruction Set Reference rol Operation: Assembler Syntax: Example: Description: rC ← rA rotated left rB4. r7. Bits 31–5 of rB are ignored. rB rol r6. rA. r8 rotate left Rotates rA left by the number of bits specified in rB4.

Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA C = Register index of operand rC IMM5 = 5-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 C 0x02 IMM5 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .Chapter 8: Instruction Set Reference Instruction Set Reference 8–83 roli Operation: Assembler Syntax: Example: Description: rC ← rA rotated left IMM5 bit positions roli rC. 3 rotate left immediate Rotates rA left by the number of bits specified in IMM5 and stores the result in rC. Usage: In addition to the rotate-left operation. rA. Rotating left by (32 – IMM5) bits is the equivalent of rotating right by IMM5 bits. r7. roli can be used to implement a rotate-right operation. The bits that shift out of the register rotate into the least-significant bit positions. IMM5 roli r6.

8–84 Chapter 8: Instruction Set Reference Instruction Set Reference ror Operation: Assembler Syntax: Example: Description: rC ← rA rotated right rB4. Bits 31– 5 of rB are ignored. rB ror r6. The bits that shift out of the register rotate into the most-significant bit positions. r7. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x0b 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation ..0 bit positions ror rC. r8 rotate right Rotates rA right by the number of bits specified in rB4. rA.0 and stores the result in rC..

. sll performs the << operation of the C programming language. r8 shift left logical Shifts rA left by the number of bits specified in rB4. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x13 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . r7..0) sll rC. rB sll r6.Chapter 8: Instruction Set Reference Instruction Set Reference 8–85 sll Operation: Assembler Syntax: Example: Description: rC ← rA << (rB4. rA. and then stores the result in rC.0 (inserting zeroes).

Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA C = Register index of operand rC IMM5 = 5-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 C 0x12 IMM5 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . IMM5 slli r6.8–86 Chapter 8: Instruction Set Reference Instruction Set Reference slli Operation: Assembler Syntax: Example: Description: rC ← rA << IMM5 slli rC. Usage: slli performs the << operation of the C programming language. and then stores the result in rC. rA. r7. 3 shift left logical immediate Shifts rA left by the number of bits specified in IMM5 (inserting zeroes).

r7. Bits 31–5 are ignored... rA. rB sra r6. Usage: sra performs the signed >> operation of the C programming language.Chapter 8: Instruction Set Reference Instruction Set Reference 8–87 sra Operation: Assembler Syntax: Example: Description: rC ← (signed) rA >> ((unsigned) rB4. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x3b 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . and then stores the result in rC.0) sra rC.0 (duplicating the sign bit). r8 shift right arithmetic Shifts rA right by the number of bits specified in rB4.

8–88 Chapter 8: Instruction Set Reference Instruction Set Reference srai Operation: Assembler Syntax: Example: Description: rC ← (signed) rA >> ((unsigned) IMM5) srai rC. and then stores the result in rC. IMM5 srai r6. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA C = Register index of operand rC IMM5 = 5-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 C 0x3a IMM5 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . Usage: srai performs the signed >> operation of the C programming language. r7. 3 shift right arithmetic immediate Shifts rA right by the number of bits specified in IMM5 (duplicating the sign bit). rA.

r8 shift right logical Shifts rA right by the number of bits specified in rB4.. and then stores the result in rC. rA..0 (inserting zeroes). Bits 31–5 are ignored.Chapter 8: Instruction Set Reference Instruction Set Reference 8–89 srl Operation: Assembler Syntax: Example: Description: rC ← (unsigned) rA >> ((unsigned) rB4. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x1b 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . rB srl r6. r7. Usage: srl performs the unsigned >> operation of the C programming language.0) srl rC.

and then stores the result in rC. r7. Usage: srli performs the unsigned >> operation of the C programming language. rA. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA C = Register index of operand rC IMM5 = 5-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 C 0x1a IMM5 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . IMM5 srli r6.8–90 Chapter 8: Instruction Set Reference Instruction Set Reference srli Operation: Assembler Syntax: Example: Description: rC ← (unsigned) rA >> ((unsigned) IMM5) srli rC. 3 shift right logical immediate Shifts rA right by the number of bits specified in IMM5 (inserting zeroes).

Exceptions: Supervisor-only data address Misaligned data address TLB permission violation (write) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for stb 0x05 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for stbio 0x25 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .Chapter 8: Instruction Set Reference Instruction Set Reference 8–91 stb / stbio Operation: Assembler Syntax: Example: Description: Mem8[rA + σ (IMM16)] ← rB7. byte_offset(rA) stb r6. Use the stbio instruction for peripheral I/O. Stores the low byte of rB to the memory byte specified by the effective address. In processors without a data cache. 100(r5) store byte to memory or I/O peripheral Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value.0 stb rB. In processors with a data cache. stbio acts like stb. byte_offset(rA) stbio rB.. this instruction may not generate an Avalon-MM bus cycle to non-cache data memory immediately. stbio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. Usage: In processors with a data cache.

the operation is undefined. Use the sthio instruction for peripheral I/O. Exceptions: Supervisor-only data address Misaligned data address TLB permission violation (write) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for sth 0x0d 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for sthio 0x2d Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . Usage: In processors with a data cache.8–92 Chapter 8: Instruction Set Reference Instruction Set Reference sth / sthio Operation: Assembler Syntax: Example: Description: Mem16[rA + σ (IMM16)] ← rB15. In processors with a data cache. In processors without a data cache.. Stores the low halfword of rB to the memory location specified by the effective byte address. this instruction may not generate an Avalon-MM data transfer immediately. If the byte address is not a multiple of 2.0 store halfword to memory or I/O peripheral sth rB. The effective byte address must be halfword aligned. sthio acts like sth. sthio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. byte_offset(rA) sthio rB. byte_offset(rA) sth r6. 100(r5) Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value.

stwio acts like stw. 100(r5) store word to memory or I/O peripheral Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value. the operation is undefined. Exceptions: Supervisor-only data address Misaligned data address TLB permission violation (write) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit signed immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for stw 0x15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 Instruction format for stwio 0x35 © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . In processors without a data cache. In processors with a data cache. Usage: In processors with a data cache.Chapter 8: Instruction Set Reference Instruction Set Reference 8–93 stw / stwio Operation: Assembler Syntax: Example: Description: Mem32[rA + σ (IMM16)] ← rB stw rB. If the byte address is not a multiple of 4. byte_offset(rA) stw r6. byte_offset(rA) stwio rB. this instruction may not generate an Avalon-MM data transfer immediately. Stores rB to the memory location specified by the effective byte address. stwio bypasses the cache and is guaranteed to generate an Avalon-MM bus cycle. Use the stwio instruction for peripheral I/O. The effective byte address must be word aligned.

rA. rA. sub rC. The original sub operation (optional) . rA. rD is written with the carry bit . label . The overflow condition can control a conditional branch. Combine comparisons . If rA and rB have different signs. Compare signs of rA and rB . rD. rB sub r6. rB. rA. The carry bit can be written to a register. as shown below. Both cases are shown below. Branch if carry was generated Overflow Detection (signed operands): Detect overflow of signed subtraction by comparing the sign of the difference that is written to rC with the signs of the operands. subtract Usage: Carry Detection (unsigned operands): The carry bit indicates an unsigned overflow. label . rB bltu rA. The original sub operation (optional) . rB xor rE. a carry out of the MSB can be detected by checking whether the first operand is less than the second operand. rB cmpltu rD.8–94 Chapter 8: Instruction Set Reference Instruction Set Reference sub Operation: Assembler Syntax: Example: Description: rC ← rA – rB sub rC. and the sign of rC is different than the sign of rA. an overflow occurred. rB xor rD. Compare signs of rA and rC . The original sub operation . Before or after a sub operation. rA. r0. rA. rC and rD. rE blt rD. r7. sub rC. r8 Subtract rB from rA and store the result in rC. or a conditional branch can be taken based on the carry condition. Branch if overflow occurred Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x39 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rB sub rC. rA.

IMMED subi r8. r8.Chapter 8: Instruction Set Reference Instruction Set Reference 8–95 subi Operation: Assembler Syntax: Example: Description: rB ← rA – σ (IMMED) subi rB. 4 subtract immediate Sign-extends the immediate value IMMED to 32 bits. The minimum allowed value is –32767. subtracts it from the value of rA and then stores the result in rB. Usage: The maximum allowed value of IMMED is 32768. rA. Pseudo-instruction: subi is implemented as addi rB. rA. -IMMED © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook .

8–96 Chapter 8: Instruction Set Reference Instruction Set Reference sync Operation: Assembler Syntax: Example: Description: None sync sync memory synchronization Forces all pending memory accesses to complete before allowing execution of subsequent instructions. In processor cores that support in-order memory accesses only. Exceptions: None Instruction Type: Instruction Fields: R None 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0x36 0 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . this instruction performs no operation.

and transfers execution to the exception handler. but it can be used by the debugger. execute an eret instruction. saves the contents of the status register in estatus. trap with no argument is the same as trap 0.Chapter 8: Instruction Set Reference Instruction Set Reference 8–97 trap Operation: estatus ← status PIE ← 0 U ←0 ea ← PC + 4 PC ← exception handler address Assembler Syntax: Example: Description: trap trap imm5 trap trap Saves the address of the next instruction in register ea. Exceptions: Trap Instruction Type: Instruction Fields: R IMM5 = Type of breakpoint 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0x1d 0x2d IMM5 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . Usage: To return from the exception handler. The address of the exception handler is specified at system generation time. The 5-bit immediate field imm5 is ignored by the processor. disables interrupts.

8–98 Chapter 8: Instruction Set Reference Instruction Set Reference wrctl Operation: Assembler Syntax: Example: Description: ctlN ← rA wrctl ctlN. rA wrctl ctl6. Exceptions: Supervisor-only instruction Instruction Type: Instruction Fields: R A = Register index of operand rA N = Control register index of operand ctlN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0x2e N 0x3a Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . r3 write to control register Writes the value contained in register rA to the control register ctlN.

r7. rA. r8 bitwise logical exclusive or Calculates the bitwise logical exclusive XOR of rA and rB and stores the result in rC.Chapter 8: Instruction Set Reference Instruction Set Reference 8–99 xor Operation: Assembler Syntax: Example: Description: rC ← rA ^ rB xor rC. Exceptions: None Instruction Type: Instruction Fields: R A = Register index of operand rA B = Register index of operand rB C = Register index of operand rC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C 0x1e 0 0x3a © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . rB xor r6.

Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x3c Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . rA. IMM16 xorhi r6. 100 Calculates the bitwise logical exclusive XOR of rA and (IMM16 : 0x0000) and stores the result in rB. r7.8–100 Chapter 8: Instruction Set Reference Instruction Set Reference xorhi Operation: Assembler Syntax: Example: Description: bitwise logical exclusive or immediate into high halfword rB ← rA ^ (IMM16 : 0x0000) xorhi rB.

Exceptions: None Instruction Type: Instruction Fields: I A = Register index of operand rA B = Register index of operand rB IMM16 = 16-bit unsigned immediate value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B IMM16 0x1c © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . 100 bitwise logical exclusive or immediate Calculates the bitwise logical exclusive OR of rA and (0x0000 : IMM16) and stores the result in rB. rA. IMM16 xori r6. r7.Chapter 8: Instruction Set Reference Instruction Set Reference 8–101 xori Operation: Assembler Syntax: Example: Description: rB ← rA ^ (0x0000 : IMM16) xori rB.

srli instruction correction.0.8–102 Chapter 8: Instruction Set Reference Referenced Documents Referenced Documents This chapter references the following documents: ■ ■ ■ Programming Model chapter of the Nios II Processor Reference Handbook Application Binary Interface chapter of the Nios II Processor Reference Handbook Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook Document Revision History Table 8–6 shows the revision history for this document.2 ■ ■ ■ ■ ■ ■ ■ ■ ■ Changes Made Backward-compatible change to the eret instruction B field encoding.2.0 October 2005 v5.1.1. Maintenance release.0. Added jmpi instruction.1.0 October 2007 v7. Added an Exceptions section to all instructions.0 December 2004 v1. Added U bit operation for break and trap instructions. — — — — — — — Maintenance release. Added new flushda instruction.0. Updated flushd instruction.0 November 2008 v8.0 May 2006 v6. Maintenance release.1 May 2005 v5.0. Table 8–6. Maintenance release.0 May 2008 v8. Added table of contents to Introduction section.1.0.0 November 2006 v6. Added Referenced Documents section. Document Revision History (Part 1 of 2) Date & Document Version March 2009 v9. Summary of Changes — — Added MMU. — — Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation . break instruction update.0 May 2007 v7.0 July 2005 v5. Maintenance release.0. Instruction Opcode table updated with flushda instruction. Correction to the blt instruction.0 March 2007 v7.

1 May 2004 v1. Summary of Changes — © March 2009 Altera Corporation Preliminary Nios II Processor Reference Handbook . — Changes Made Updates for Nios II 1.Chapter 8: Instruction Set Reference Document Revision History 8–103 Table 8–6.01 release.0 Initial release. Document Revision History (Part 2 of 2) Date & Document Version September 2004 v1.

8–104 Chapter 8: Instruction Set Reference Document Revision History Nios II Processor Reference Handbook Preliminary © March 2009 Altera Corporation .