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Center for Experimental Research in Computer Systems

Georgia Institute of Technology, Karsten Schwan, Director, 404.894.2589,
Georgia Institute of Technology, Calton Pu, 404.385.1106,
Georgia Institute of Technology, Doug Blough, 404.385.1271,
Georgia Institute of Technology, Sudhakar Yalamanchili, 404.894.2940,
Ohio State University, Jay Ramanathan, 614.565.4187,
Center website:

Power-Efficient and Tamper-Proof Embedded Architectures
This research focuses on novel embedded processor architectures that provide power/thermal efficiency
and tamper-proofness while without compromising the performance objective. As process technology
shrinks, power and heat dissipation has become the main debacle in embedded processor design that lim-
its their usability. On the other hand, the increasing number of physical tampering on such platforms fur-
ther jeopardizes the security and privacy of their usage.

To combat the power/thermal issues, two
thrusts examine low-power techniques for
cache architecture. The first analyzes the
memory access stream based on semantic
distribution defined by programming lan-
guage and isolates the higher frequency,
higher locality accesses into a more power-
efficient memory structure for less power
consumption. The second thrust exploits
bloom filters for cache hierarchies that gen-
erate the signature of observed memory
addresses. Such information is used to elimi-
nate unnecessary cache lookup's to reduce
power. This work has demonstrated that the
effectiveness of these CERCS techniques in
power reduction. CERCS researchers are
working with ARM Ltd. to evaluate how these techniques can be integrated into their embedded proces-
sors. To prevent physical tampering and compromised digital rights, researchers first devised and evalu-
ated potential side-channel attacks via tapping on the bus interface and differential power measurement
to reveal the vulnerability of current embedded platforms. For addressing these issues, researchers pro-
posed several low-overhead integrations at the micro-architectural level to enable data protection on
these devices. Hardware schemes increase the randomness of the information flow, making these embed-
ded systems more secure. For more information, contact Matthew Wolf, 404.385.1278, or Karsten Schwan, 404.894.2589,

Power-Efficient and Tamper-Proof Embedded Architectures 43
Center for Experimental Research in Computer Systems (CERCS)

Insights from High Performance Computing Service
Service augmentation is a new concept developed by researchers at the Georgia Tech Center for Experi-
mental Research in Computer Systems (CERCS) to benefit high performance, I/O intensive applications.
Receiving the “Best Paper” award at the 2006 Conference on Cluster Computing, service augmentation
uses runtime binary code generation to augment complex codes with new functionality, as and when
needed by these applications. Originally intended for and applied to enable the online visualization of high
performance simulations running on supercomputers, this concept is now showing promise for commer-
cial applications. For retail forecasting, for instance, the concept can be used to efficiently extract data from
the complex internal structures used by these codes to make it useful for display to managers and plan-
ners. Ongoing work with a startup company is exploring this use of the idea.
For more information, contact Matthew Wolf, 404.385.1278, or Karsten Schwan,

Automated Performance Characterization (APC) During Staging
As the complexity of large-scale enterprise applications increases, providing performance verification
through iterative staging becomes an important part of reducing business risks associated with violating
sophisticated service-level agreements. Staging is the deployment and validation of the entire application
in a controlled testing environment. Currently, performance verification during the staging process is
accomplished through either an expensive, cumbersome manual approach or ad hoc automation.
Researchers at the Center for Experimental Research in Computer Systems (CERCS) have developed an
automated approach for supporting the monitoring and performance analysis of distributed multi-tiered
applications. The process uses code generation and machine learning to automatically determine service
level agreement satisfaction and to locate bottlenecks in candidate application deployment scenarios. The
intent is to detect bottlenecks and enable the system to self-tune by addressing the detected bottlenecks
through redesign; thus using iterative staging until a satisfactory system is designed. Evaluation tools are
used to examine and illustrate the effectiveness of the APC monitoring and analysis process in successfully
locating performance limitations as part of automated iterative staging. For more information, contact
Karsten Schwan, 404.894.2589,

44 Insights from High Performance Computing Service Augmentation