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Modeling On-Chip Variations in Digital Circuits Using Statistical Timing Analysis

Gor Petrosyan

Synopsys Armenia CJSC

gor@synopsys.com

Sargis Abovyan

Synopsys Armenia CJSC

asargis@synopsys.com

Tigran Harutyunyan

Synopsys Armenia CJSC

htigran@synopsys.com

Abstract

The purpose

of this

paper is to model timing

of

digital circuits by determining dependencies between the logical depth of standard cells in digital circuit and variation margins applied during timing analysis. The simulation results for the cells used in clock tree are presented.

  • 1. Introduction

With process technologies scaling down process variation is becoming more important. It is enough to say that MOS transistor threshold voltage percentage variation has almost doubled in scaling from 90nm to 45nm [1]. Among them delay variations that impact the circuit performance also increased and affect the design timing yield. In traditional timing analysis, better known as static timing analysis (STA), gate and interconnect timing modeling is performed [2]. For 90nm and below technologies for consideration of on- chip variations (OCV) in timing analysis the flat global margins are applied across the entire digital circuit. But with process, voltage, temperature variations increasing it becomes very difficult to have a single flat margin for the entire circuit. Taking into account that with every step of technology scaling more corners need to be considered and analyzed to satisfy design parameters with variations, this approach requires a big number of timing closure iterations and causes design performance reduction as well as power and area increase. Thus for better and more accurate timing analysis it is better to apply a variation-related margin to the design.

  • 2. Statistical static timing analysis

Statistical static timing analysis (SSTA) is used in practice as an extension to STA to analyze the impact of process variations on timing. SSTA handles the

random parts of the process variations as probability distributions to calculate the delay statistically [2]. This allows having more realistic results during timing analysis of digital circuits. There are several approaches to perform SSTA [3, 4] and some of them are embedded into STA tools.

3. Advanced OCV technology

A few timing signoff tools [5] support the advanced OCV (AOCV) technology [6] which enables to run STA with the specific variation-related margins for different cells in the design. That reduces the pessimism during STA analysis and provides more accurate results compared with the flat margin. In Figure 1 timing signoff flow with combined AOCV and global OCV technologies is shown.

Modeling On-Chip Variatio ns in Digital Circuits Using Statistical Timing Analysis Gor Petrosyan Synopsys Armenia CJSC

Figure 1. Timing signoff flow with AOCV

This method determines the derating factors as a function of logic depth of cells. Figure 1 shows an example of how path depths for launch and capture paths are determined.

978-1-4244-9556-6/10/$26.00 ©2010 IEEE

Figure 2. Depth-based AOCV During this analysis the clock re-convergence pessimism removal should be set to

Figure 2. Depth-based AOCV

During this analysis the clock re-convergence pessimism removal should be set to true to avoid discrepancy of derating factors for setup and hold timing analysis. In general, AOCV technology supports two types of methodologies – depth-based and location based. But they model different types of variations. The variations can be classified as random and systematic [7]. While the random variations can be modeled by statistical Spice analysis, systematic variation modeling requires measurements from the real silicon. So this work focuses on the implementation of STA flow for random variations- aware derating values only.

4. Experimental work and results

While using advanced OCV technology in STA signoff flow the most important thing is to determine the optimal value for derate margin of each separate cell. In this paper the dependencies between logical depth and derating values for the standard cells built with predictable 45nm HSPICE statistical models have been obtained.

Figure 2. Depth-based AOCV During this analysis the clock re-convergence pessimism removal should be set to

Figure 3. Monte-Carlo simulation results for inverter with 0 driving strength and 6 stages

These models do not guarantee 100% accuracy but give enough bandwidth to have results close to real. To get the dependence of cell delay from the cell depth, 35000 HSPICE Monte-Carlo simulations [8] are run. As the data path logic derating separation is more complicated and requires more runtime and analysis, in this paper only inverters are modeled assuming that variation-related margins should be applied only to clock tree cells which are usually inverters and buffers. The simulations have been run for the inverters having 0, 4, 8, 12 and 16 driving strengths and with the chains having 4-10 stages for each. In Figures 3-5 the simulation results for the inverter with 0 driving strength for 4, 6, 8 and 10 stages are shown.

Figure 2. Depth-based AOCV During this analysis the clock re-convergence pessimism removal should be set to

Figure 4. Monte-Carlo simulation results for inverter with 0 driving strength and 8 stages

Figure 2. Depth-based AOCV During this analysis the clock re-convergence pessimism removal should be set to

Figure 5. Monte-Carlo simulation results for inverter with 0 driving strength and 10 stages

Similar dependencies have been obtained for all the mentioned inverters and stages. As seen from the mean and standard deviation values in Figures 3-5, the delay variation increases with the increase of logic stages. Therefore, the derating values should also increase for proper modeling of delay variations. After having delay values and standard deviations for each cell, derating table is created using the special utility and the obtained dependencies of derating values from the driving strength and logical depth of clock tree inverters. Figure 6 illustrates the mentioned dependency for the early derate.

Similar dependencies have been obtained for all the mentioned inverters and stages. As seen from the

Figure 6. Dependence of derate margins from the number of stages for different driving strengths

As seen from the dependencies shown in Figure 6, derating values increase with the number of stages almost exponentially. Also, the derating values are smaller for the cells having higher driving strengths as the process variation influence on the transistors having larger width is less. The obtained dependencies of derating values are used for STA of OPENSPARC T1 processor [9] and compared to the STA results with global derating margin. Table 1 shows the comparison results for both setup and hold analysis.

Table 1. STA results comparison for OPENSPARC T1 processor

 

Worst

Total

Number

Negative

Negative

of

Slack

Slack

Violations

Global

     

derating

-78.45ps

-125870ps

8746

AOCV

-54.16ps

-46517ps

3119

  • 5. Conclusion

The AOCV technology can be used to reduce the overall pessimism during STA analysis. In this paper the dependence of derate margins for the standard cells have been obtained. These dependences can be used as a reference for different technologies to specify optimal OCV margins. A limitation of the current capability is that analysis times for AOCV require the user to apply this capability when the number of timing violations is relatively small. This means that it can only be applied in the final stages of signoff analysis and cannot be used as a replacement for all timing analysis runs.

  • 6. References

[1] C. Chiang, J. Kawa “Design for Manufacturability and Yield for Nano-Scale CMOS”, Springer, Dordrecht, The Netherlands, 2007 [2] D. Blaauw, K. Chopra, A. Srivastava, and L. Scheffer, “Statistical Timing Analysis: From Basic Principles to State of the Art”, IEEE transactions on computer-aided design of integrated circuits and systems, vol. 27, pp. 589-607, 2009 [3] K. Homma, I. Nitta, T. Shibuya, “Non-Gaussian Statistical Timing Models of Die-to-Die and Within-die Parameter Variations for Full Chip Analysis”, IEEE transactions on VLSI Systems, vol. 4, pp. 292-297 , 2008 4] J.H. Liu, J.K Zeng, A.S. Hong, L. Chen and C. Chung Ping Chen, “Process Variation Statistical Modeling for VLSI Timing Analysis”, 9th International Synposium on Quality Electronic Design, pp.730-733, 2008. [5] Synopsys PrimeTime User Guide, 2009 [6] PrimeTime Advanced OCV Technology White Paper, Synopsys, April 2009 [7] M.G. Karen, V. Gettings and D. S. Boning, “Study of CMOS Process Variation by Multiplexing Analog Characteristics” IEEE transactions on Semiconductor Manufacturing, vol. 21, pp.513-525, 2008 [8] V. Veetil, D. Sylvester, D. Blaauw, “Efficient Monte Carlo based Incremental Statistical Timing Analysis”, DAC, Anaheim, California, pp. 676-681, 2008 [9] http://www.opensparc.net/opensparc-t1/index.html