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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 2, APRIL 2005

A Voltage-Sensorless Control Method to Balance the Input Currents of a Three-Wire Boost Rectiﬁer Under Unbalanced Input Voltages Condition

Souvik Chattopadhyay and V. Ramanarayanan, Member, IEEE

Abstract—This paper proposes a control method that can balance the input currents of the three-phase three-wire boost rectiﬁer under unbalanced input voltage condition. The control objective is to operate the rectiﬁer in the high-power-factor mode under balanced input voltage condition but to give overriding priority to the current balance function in case of unbalance in the input voltage. The control structure has been divided into two major functional blocks. The inner loop current-mode controller implements resistor emulation to achieve high-power-factor operation on each of the two orthogonal axes of the stationary reference frame. The outer control loop performs magnitude scaling and phase-shifting operations on current of one of the axes to make it balanced with the current on the other axis. The coefﬁcients of scaling and shifting functions are determined by two closed-loop prportional–integral (PI) controllers that impose the conditions of input current balance as PI references. The control algorithm is simple and high performing. It does not require input voltage sensing and transformation of the control variables into a rotating reference frame. The simulation results on a MATLAB-SIMULINK platform validate the proposed control strategy. In implementation Texas Instrument’s digital signal processor TMS320F240F is used as the digital controller. The control algorithm for high-power-factor operation is tested on a prototype boost rectiﬁer under nominal and unbalanced input voltage conditions. Index Terms—Boost rectiﬁer, current-mode control, highpower-factor rectiﬁers, input current unbalance, input voltage unbalance, power-factor correction.

I. INTRODUCTION OR three-phase high-power-factor rectiﬁcation, boost-type pulsewidth-modulation (PWM) converters are very widely used. The methods normally used for controlled rectiﬁcation are based either on regulation of active and reactive current components in the synchronously rotating reference frame or on direct control of active and reactive power components by hysteresis type of controllers [1], [2]. Some of the proposed power-factor-correction methods are input voltage sensorless [3], [4]. Using these methods the output dc voltage of the rectiﬁer can be regulated and unity-power-factor operation with near-sinusoidal input current can be achieved. However, it is assumed in these methods that the input voltages both in terms of

Manuscript received December 30, 2003; revised February 13, 2004. Abstract published on the Internet January 13, 2005. S. Chattopadhyay is with the Department of Electrical Engineering, Indian Institute of Technology, Chennai 600036, India (e-mail: souvikc@ee.iitm.ernet.in. V. Ramanarayanan is with the Department of Electrical Engineering, Indian Institute of Science, Bangalore 560012, India (e-mail: vram@ee.iisc.ernet.in). Digital Object Identiﬁer 10.1109/TIE.2005.843917

F

Thevenin equivalent voltages and output impedances are balanced. If the input voltages of such a three-phase three-wire system, as shown in Fig. 1, are not balanced then they cause abnormal even harmonics in the output dc voltage and odd harmonics in the input line currents [5]. A few methods have been proposed [6]–[8] to solve the problem of harmonics under unbalanced input voltage condition. The objective of the method proposed in [6] is to balance the input currents. For that the input voltages are decomposed into symmetrical components so that the detected negative-sequence components can be added to the positive-sequence control voltages for balancing the currents. This method performs well, however, it requires input voltage sensing and the current balance function is basically executed in the open loop. Another method proposed in [7] computes the second-order harmonics in the dc bus and generates three independent current references that will cancel the even harmonics. In this method the input currents need not be balanced. It also needs input voltage sensing and the implementation is based on variable-switching-frequency operation. The method proposed in [8] is complex and achieves reduction instead of elimination of harmonics in the input current. In this paper a closed-loop input current balance control method for a three-phase three-wire boost rectiﬁer is proposed. The control objective is to operate the rectiﬁer in the high-power-factor mode under normal operating condition but to give overriding priority to the current balance function in case of unbalance in the input voltages. This control algorithm provides high performance with a much simpler control structure than the methods mentioned above. It does not require sensing of input voltages and is based on operation at ﬁxed switching frequency. It is suitable for digital implementation with the sampling frequency of the currents being equal to the switching frequency of the converter. The input impedances of the boost rectiﬁer need not be balanced as two independent closed-loop proportional–integral (PI) controllers are used to balance the phase currents both in magnitude and in phase. The conditions for high-power-factor operation under unbalanced input voltage condition are given in Section II. The proposed digital control algorithm for balancing the input currents of a three-phase boost rectiﬁer is derived in Section III. The method for determination of scaling and phase shifting constants is given in Section IV. The simulation results are presented in Section V. Implementation of the algorithm in digital signal processor (DSP) TMS320F240 is described in Section VI. The experimental results of the three-phase boost

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Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. Downloaded on April 23,2010 at 07:40:50 UTC from IEEE Xplore. Restrictions apply.

The phase voltages and the corresponding phase currents are indicated in the same ﬁgure as and . However. Restrictions apply. Input voltages are not sensed. rectiﬁer are available in Sections VII and VIII is used for conclusion. and is the phasor of the input phase currents. respectively. Downloaded on April 23. 1. in and components case of unbalance. i ) and unbalanced (v voltage conditions. reference frame implementation of (4) and (5) In the and are by a current controller ensures that the currents Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. 2. Two input currents and the output dc voltage are sensed for current balance control. We can use these variables to recast the control objective of (1) by two scalar equations (4) (5) It may be noted that if the phase voltages . High-power-factor operation in balanced (v . Mathematically. Fig. II. 1 Circuit schematic of the digitally controlled three-phase high-power-factor boost rectiﬁer. For high-power-factor operation phase currents should be made proportional to the phase voltages. phasor of the input phase voltages.CHATTOPADHYAY AND RAMANARAYANAN: CONTROL METHOD TO BALANCE THE INPUT CURRENTS OF A THREE-WIRE BOOST RECTIFIER 387 Fig. These quantities can be expressed as (2) (3) The components of input voltage and input current on the stareference frame are tionary and orthogonal and . and are and are phase shifted balanced then the components by 90 and their peak magnitudes are also equal.i and ) (chosen arbitrarily) input . The power-factor-correction objective in terms of space phasor quantities is deﬁned as (1) where is the constant of proportionality representing the is the emulated resistance of the rectiﬁer. HIGH-POWER-FACTOR OPERATION AND VOLTAGE UNBALANCE The schematic of a three-phase three-wire boost rectiﬁer is shown in Fig. .2010 at 07:40:50 UTC from IEEE Xplore. the corresponding will not retain the magnitude and phase relationship mentioned above.

It can be noted that . 2. -axes variables under and irrespective of the naproportional to the voltages ture of unbalance in the input voltages.and -axes variables under balanced and unbalanced (chosen arbitrarily) input voltage conditions are shown in the space phasor diagram of Fig. Since for a three-phase three-wire system the input currents are given by (6) (7) (8) . The high-power-factor operation in .

4. . 2. Voltage vectors produced by the PWM converter of Fig. Restrictions apply. Downloaded on April 23.388 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. 52. 3. APRIL 2005 Fig. The current balance function in the controller Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. 5. Fig. The right-hand sides of (6)–(8) show that the implementation of pro(4) and (5) will not make the phase currents because in general portional to the phase voltages . 1 and the corresponding deﬁnition of Sector’s. VOL. This paper proposes a modiﬁcation of the current control structure and adds the function of input current balance in the outer control loop. NO. TABLE I GENERATION OF RECTIFIED CURRENT VARIABLES Fig. Block diagram of the input current balance controller.2010 at 07:40:50 UTC from IEEE Xplore. Functional block diagram of the three-phase high-power-factor boost rectiﬁer represented by two independent single-phase rectiﬁers in current-mode-control structure.

DIGITAL CONTROL ALGORITHM FOR BALANCING THE INPUT CURRENTS The objective of this section is to describe a voltage-sensorless digital current-mode control technique that would balance the input currents of a three-phase three-wire boost rectiﬁer under unbalanced phase voltage condition. It can simultaneously achieve unity-power-factor operation if the unbalanced phase voltages are at least balanced in phases. The derivation of the control method is given below. R. 4. and . in all other cases of unbalance unity-power-factor operation is not possible. i. irrespective of the kind of unbalance present in the phase voltages. a scaled and phase-shifted current is of . The digital current-mode control technique used here is input voltage sensorless and has been discussed in detail in [9]. 3. phase shifted by 120 . The control method will be discussed in more detail in subsequent sections. The phase voltages are unbalanced. 6. The objective of the inner such that they become loop is to shape the currents and then generate switching pulses proportional to by space-vector-modulation strategy. TABLE II ACTIVE VECTOR SELECTION CHART IN SECTORS 1. in general. quence. respectively. Q. The control objective of the input current balance controller is to satisfy (11) and (12) simultaneously (11) (12) In order to balance the input phase currents and still retain the basic function of power-factor correction the controller makes and a new variable .2010 at 07:40:50 UTC from IEEE Xplore. = V and A = V for gets priority over the inner loop control objective of powerfactor correction. It can be seen that the structure of the conproportional to troller is such that under unbalanced condition the task of balancing the input currents gets priority over the default function where (10) where is the phase difference between and . 3. (9) III. Downloaded on April 23. The difference is that instead . as in [9]. therefore. The input voltages are assumed to be sinusoidal but unbalanced. produce two constants These constants are used to generate the current reference that is to be given as an input to the inner loop for making it .e. Restrictions apply. With the implementation of current balance function the peak values of the phase currents will be equal in magnitude and their zero crossings will have 120 phase shift. instead of . The block diagram of the closed-loop controller in shown in Fig. Two closed-loop PI controllers impose the conditions for input current balance and.. For example: A vector Q. The function of the outer loop of this controller is to make sure that the input currents are equal in magnitude and also phase shifted by 120 . The block diagram of the controller is shown in Fig. as in (13) is then given by (14) can be expressed as a linear combination of the currents and (15) Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. as a conseand under steady state. S vectors into M in Sector 1 of positive alpha–beta axis for solution of T1 and T2. This is done in order to balance made proportional to the input currents. proportional to and . Therefore. . 6 of power-factor correction. . 3. Mapping of P .CHATTOPADHYAY AND RAMANARAYANAN: CONTROL METHOD TO BALANCE THE INPUT CURRENTS OF A THREE-WIRE BOOST RECTIFIER 389 Fig. It is inherently a current controller for high-power-factor operation.

D vectors into N in Sector 2A of positive alpha–beta axis for solution of T1 and T2. It may be noted that under and . 5A. B. i ). NO. 52. Mapping of A. and are constants under steady state. it follows from (13) that the closed-loop PI controllers will output and under balanced input voltage condition and will result in high-power-factor operation. 1: Balanced input voltage (i . Time phasor diagram of the control variables under three different . C . therefore. .i ). Downloaded on April 23. means that we can functionally represent a three-phase boost rectiﬁer by two independent single-phase boost rectiﬁers as shown in Fig. 2: unbalanced operating conditions. 5B Fig. balanced input voltage condition . VOL. APRIL 2005 Fig. i . This implies that Therefore. The digital controller proposed in this paper calculates from the currents and using (15). 4. and 5A will not produce acceptable solution but the modulator will lock at sector 5B (A-B-C). = V and A = V for where (16) (17) and are obtained from the outputs of the two PI controllers that impose the conditions of current balance. 2. Using continuous-conduction-mode voltage conversion relationships of the boost Fig. 2B.2010 at 07:40:50 UTC from IEEE Xplore.390 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. 7. 9. be expressed as period (18) where currents and and can be calculated from the sensed phase TABLE III ACTIVE VECTOR SELECTION CHART IN SECTORS 2A. Restrictions apply. input voltage but without current balance function activated (i and 3: unbalanced input voltage but with current balance function activated (i . For the th switching can.i ). converters and in (21) and (22). (19) (20) The control objective for the input current balance controller can be expressed in the sampled form as (21) (22) This. For example: A vector A whereas A = V and A = V for Vector B mode controller. Sequence of sector change to be followed to eventually synchronize with the location of voltage vector: for example if the voltage vector is in sector 5B and the initial assumption of sector is 3 then 3. in essence. 4. 8. the control law can be made input voltage Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE.

4.CHATTOPADHYAY AND RAMANARAYANAN: CONTROL METHOD TO BALANCE THE INPUT CURRENTS OF A THREE-WIRE BOOST RECTIFIER 391 Fig. From Fig. and . and 6 are identiﬁed as in tors and . The reof the period should be used for the null maining time . Flowchart of the control algorithm implemented in TMS320F240 DSP for current balance control on the outer loop of a resistor emulator-type input current-shaping controller. or ) with an angle with respect to the axis of the segment. can be obtained by solving the following simultaneous equations: (25) (26) Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. We generate and based on the sector information. 6. 5. 4. . For that purpose the voltage vectors and the corresponding sectors are deﬁned as in Fig. sensorless. It is well known that symmetric space-vector PWM technique is one of the convenient ways of producing switching signals for a three-phase PWM converter. Therefore. The duty ratios and converter switches and of the two boost are given by (23) (24) where is the output of the voltage error amis the current sense resistance as shown in Fig. 10. pliﬁer and It may be noted that and are positive quantities and obtained after rectiﬁcation of the control variables . then the corresponding time for synthesis of any vector ( . for the two active vectors and tions to effectively produce the same volt-seconds on each axis as demanded by the independent boost rectiﬁer controllers. Restrictions apply. Downloaded on April 23. needed Table II. we have to convert the duty ratio information given by (23) and (24) to the space-vector PWM signals of individual switches. we have to ﬁnd out the time duraFrom and .2010 at 07:40:50 UTC from IEEE Xplore. as shown in Table I. 3. it can be noted that if the active vecvector and for Sectors 1.

and we need to compute the time durations From .i . Table III gives the selection of vectors.. as shown in Fig. for Sectors . as shown in Fig. The following simultaand : neous equations can be used to solve for (27) (28) and .2010 at 07:40:50 UTC from IEEE Xplore.i . and by using (29)–(33) of (29) It can be seen that the input voltages need not be sensed for and . VOL.1) v (b) Scaled (0. the next sector in sequence is chosen. APRIL 2005 Fig. i. and . NO. Similarly. When any one of these conditions is not satisﬁed. 2. the sector information computation of should be known for appropriate selection of active vectors. (30) (31) (32) (33) Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. i .e. .v and i .v . The input current balance controller is active. (a) Scaled (0. (c) K . the . for the modulator to operate in the unsaturated region. 52.and -axes modulators will produce duty ratios less than 1.392 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. This controller implements self-synchronization of the converter switching with respect to line voltage based on the following logic: as long as the sector selection is correct. However. 11. v and i . 8. Similarly. Downloaded on April 23. Restrictions apply. Simulation results under balanced input voltage condition. K .1) v . . 7.

This closed-loop controllers in order to determine (37) is shown in the block diagram of Fig.1) . This will be discussed in Section VI. .1) v .v . If due to some reason is positive in a increases as the integrator increments with a if Sw is ON and line cycle then if Sw is OFF (43) has to move positive slope.v and We will need the timing values computed above for DSP TMS320F240–based implementation of the algorithm. 1 is based on the following equations: (34) (35) It can be seen from (18) that the constants and should be known for the computation of . Under balanced condiif Sw is ON and if Sw is OFF (42) should be zero. has to be equal to the peak value of the –axis .i Simulation results under unbalanced input voltage condition. 10. as a result of which the phase of toward 0 in subsequent cycles in order to satisfy (18). (b) Scaled (0. The nominal operating condition of the simulation model is Fig.2010 at 07:40:50 UTC from IEEE Xplore. Under balanced con. (38) . It is deﬁned as the -axis The input to this PI controller is (41) current sampled at the instant when the -axis current attains its positive peak value in a line cycle. Downloaded on April 23. The simulation model of the digital controller is based on (18)–(33) described in Section III of this paper. DETERMINATION OF AND The mathematical model of the three-phase converter circuit shown in Fig. Restrictions apply. The conditions neces(36) and are imposed on two independent sary for balancing and . and to given below illustrate the action of the phase current balance controller. 12. 3. over a line cycle. V(rms) V.CHATTOPADHYAY AND RAMANARAYANAN: CONTROL METHOD TO BALANCE THE INPUT CURRENTS OF A THREE-WIRE BOOST RECTIFIER 393 Fig. trollers in order to determine (39) is obtained in a similar manner from the output of another (40) PI controller that basically imposes the phase balance condition. V(dc-regulated) mH s It can be noted that the control function to balance the input currents of the rectiﬁer remains active all the time in the outer Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE.3) platform. v . where dition peak value of the -axis current. SIMULATION RESULTS The proposed input current balance controller for a threephase three-wire boost rectiﬁer is simulated on a MATLABSIMULINK (Version 5. i . . The ﬂowchart of the digital controller is shown in Fig. The input current balance controller is not active. IV. This condition is imposed on one of the PI concurrent. 9 shows the time phasor diagram of . i .i . . (a) Scaled (0. and this is deﬁned as the zero-phase tion condition for . v and i .

i . Downloaded on April 23.2010 at 07:40:50 UTC from IEEE Xplore. the constants that are the from Fig. achieve steady-state values that are nearly equal to 0 and 1. 11(c) that outputs of two independent PI controllers. 2. that Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. . NO. VOL. i (c) K . 13. 52. implying . loop of the control structure. It does not interfere with the power-factor-correction objective of the inner control loop if the input voltages are balanced. APRIL 2005 Fig. This is shown in Fig. 14. Restrictions apply.i . and in Fig. K . 11(a) and and in and (b). It can be seen and . respectively.1) v (b) Scaled (0. (a) Scaled (0. Simulations result under unbalanced input voltage condition.1) v . . TABLE IV TMS320F240 CMP REGISTER TIMING CHART Fig.v . The input current balance controller is active.v and i . as Fig. 11(a) . v and i . 11(b) are balanced in magnitude and phase.394 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. Generation of symmetric PWM pulses in the Event Manager Module of DSP TMS320F240.

The Event Manager Module (EVM) in the peripheral library of TMS320F240 provides necessary hardware support for the generation of PWM pulses for the switching devices of the three-phase boost rectiﬁer. (c) v (Ch1: 300 V/div) and K . The magnitude of the phase-shifted current is determined by the dc voltage error ampliﬁer. i (Ch1. 13(a) and (b) are obtained with the current balance controller activated. This is shown in Fig. i (Ch1. IMPLEMENTATION IN DSP TMS320F240 The calculated timing values of (29)–(33) are required for loading the compare registers of TMS320F240—a DSP controller that is for implementation of the current balance control algorithm as described above. i . the input phases currents are not proportional to the input voltages. (d) i . Ch3: 1/div). and Fig.2010 at 07:40:50 UTC from IEEE Xplore. 13(c). (a) v (Ch4: 300 V/div) and i . Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. (b) v (Ch4: 300 V/div). The simulation results shown in Fig. and ) are balanced. produce values of respectively.2 A/div). Ch2. 12(b) shows the waveforms of scaled -axes voltages and the currents . 15. Ch2: 8 A/div) and V (Ch3: 270 V/div). It can be seen that although the voltages are unbalanced the phase currents ( . 12(a) shows the waveforms of scaled input voltages and input currents . Experimental results with the current balance controller under normal input voltage condition. K (Ch2. i . In this simulation the unbalanced input voltages are chosen arbitrarily as . Downloaded on April 23. Ch2: 8 A/div) and ‘Sector’ (Ch3: 4/div). The PI controllers and that are different from 0 and 1. Ch3: 3. i (Ch1. Under such a condition if the current balance control is not used then Fig. Restrictions apply. It can be seen that although unbalanced -axes voltages and currents satisfy high-power-factor operation. VI.CHATTOPADHYAY AND RAMANARAYANAN: CONTROL METHOD TO BALANCE THE INPUT CURRENTS OF A THREE-WIRE BOOST RECTIFIER 395 Fig. .

396 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. At ﬁrst. Under such condition Fig. VOL. The execution of the control loop is initiated by the GP timer 1 underﬂow interrupt while counting down. the constants are 0 and 1.i (Ch1. Experimental results without the current balance controller under unbalanced input voltage condition. 16. 2. the timer 1 period register T1PR is loaded with a constant . The timer 1 in the up–down counting mode generates a triangle waveform of frequency 10 kHz. CMP2. These results demonstrate that the current balance controller does not interfere with the power-factor-correction objective under balanced input voltage condition. Fig.2 A/div). anced. i (Ch1. i. As the constants expected. 52. VII. (Ch4: 300 V/div) and i . In this experimental unit we have added and mH in sean impedance made of ries with the phase. We expect that high-power-factor operation should be possible under balanced input voltage condition and and waveforms shown in Fig.. The values that need to be loaded to the three compare registers CMP1. 15(a) this is proved by the that are in phase. Downloaded on April 23. The six output signals are available on dedicated PWM output pins PWM1–PWM6. Ch3: 3. NO. Necessary adjustments to the basic ON and OFF times of each switch are performed in the Dead Band units. Ch2: 8 A/div) and V (Ch3: 270 V/div). (b) v (Ch4: 300 V/div). (a) v Ch2.e. 15(d) shows the steady-state values of and the sequence of “Sector” change. . respectively.supply line of the rectiﬁer. 15(a) shows that the phase currents -axes currents in Fig. If an odd-numbered pin is used for driving the top device then the corresponding even-numbered pin should be used for the bottom device. In order to verify the effectiveness of the current balance controller we create an unbalance in the input phase voltages by changing the equivalent Thevenin impedance of one of the input source voltages. of each PWM output. The outer loop consisting of two PI controllers for the determination of and another PI controller for regulation of are executed in the ratio of 1 : 10 to the inner control loop. are balFig. corresponding to 50 s. The experimental results of the rectiﬁer under balanced input voltage condition are shown in Fig.i . 15(c) shows that the output dc voltage at reference value. The switch dead time is controlled by dead-time control register DBTCON. and CMP3 for the entire line cycle of the input voltage waveform are given in Table IV. In this implementation the timer 1 is clocked by CPU clock CPUCLK at 20 MHz. thus requiring a total conversion time of s. Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. and each step of the sector change waveform is equal indicating that the phase voltages are balanced. In each underﬂow interrupt the dual 10-bit analog-to-digital converter module (ADC) of the TMS320F240 measures two phase currents. The generation of switching signals for individual devices is shown as an example in Fig. we do not activate the current balance controller. active high or active low. It corresponds to the Sector 1 of the space-vector modulation. APRIL 2005 Fig. when the timer counter reaches 0000H. 15. and so are is well regulated Fig. 14. The Output Logic units of the Event Manager Module determine the logic level. For that.e. The output PWM pulses are obtained by comparison of values in timer 1 counter register T1CNT and the compare registers CMPR1-2-3. Restrictions apply. The general-purpose (GP) timer 1 of the Event Manager Module [10] is conﬁgured in the initialization part of the program to work in the continuous up–down counting mode for the generation of symmetric PWM waveforms. i. i . 16(a) and (b) shows that the currents and are unbalanced. EXPERIMENTAL RESULTS The nominal operating point of the experimental boost rectiﬁer when the phase voltages are very nearly balanced is as follows: phase V rms star V dc regulated mH s It may also be assumed that the per-phase boost inductances are very nearly equal. 15(b). By observing and we can infer that the power factor is not unity.. The current conversions are simultaneous in the two ADCs.2010 at 07:40:50 UTC from IEEE Xplore.

. (c) v (Ch1: 300 V/div) and K .2010 at 07:40:50 UTC from IEEE Xplore. i . Ch2. K (Ch2. and i (Ch1. Ch2. Downloaded on April 23. (b) v (Ch4: 300 V/div).2 A/div). Experimental results with the current balance controller under unbalanced input voltage condition. i (Ch1. i . Ch3: 8 A/div). (a) v (Ch4: 300 V/div) and i . (d) i . Ch2: 8 A/div) and V (Ch3: 270 V/div).CHATTOPADHYAY AND RAMANARAYANAN: CONTROL METHOD TO BALANCE THE INPUT CURRENTS OF A THREE-WIRE BOOST RECTIFIER 397 Fig. Ch3: 3. (e) i . i . Ch2: 8 A/div) and “Sector” (Ch3: 4/div). Restrictions apply. Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. 17. Ch3: 1/div). i (Ch1. i (Ch1.

1992. Ind. vol. Power Electron. being a closed-loop current balance method. A. S. India. H. Madras. Bangalore. [5] L. Texas Instruments. IEEE PESC’93. 2175–2180. “A novel control method for input output harmonic elimination of the PWM boost type rectiﬁer under unbalanced operating conditions. [10] TMS320C24x DSP Controllers Peripheral Library and Speciﬁc Devices—Reference Set—Volume 2. 2. Ind. Delhi. G. in 1986. Souvik Chattopadhyay received the B. 3. the M. pp.Sc. D. 17(b) shows that and is regulated. 17(c) shows that the constants have changed due to the actions of the PI controllers in order to balance the input currents. Nov. “Virtual-ﬂux-based direct power control of three-phase PWM rectiﬁers. Fig. The inner loop implements resistor emulator-type current-shaping strategy on .” IEEE Trans. and S. and J. and power quality issues. Authorized licensed use limited to: INDIAN INSTITUTE OF SCIENCE. [4] I. and the M. 28. 2001..” IEEE Trans. switched-mode power conversion. 603–611. In conclusion.(Eng. S.E. using the coefﬁcients scaling and phase-shifting coefﬁcients are determined by two closed-loop PI controllers that impose the conditions of input current balance as PI references. 503–509. [6] H. Bangalore. 16. Jamshedpur. if the input voltages are unbalanced then priority is given to the implementation of the current balance function. industrial drives. 927–933. 2001. Restrictions apply. IEEE PESC’98. Blasko. it can be said that the method proposed in this paper for balancing the input currents of a three-phase three-wire boost rectiﬁer is simpler in implementation compared to other input current balance methods but provides equal or better performance. Kim. Ramanarayanan (M’05) received the B. “Design aspects of synchronous PWM rectiﬁer-inverter system under unbalanced input voltage conditions. IEEE-IAS Annu. no.” in Proc.” in Proc. Agirman and V.. V. The rent-shaping controller. Ramanarayanan. Meeting. H. India.E. These results validate the analysis of unbalance..E.2 s.” IEEE Trans. India. Pouliquen. Marques. degree from Bengal Engineering College. [8] P.398 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. in 1988. pp. pp. “Regulation of a PWM rectiﬁer in the unbalanced network state. in 1975. show that the phase currents but. He is currently an Assistant Professor in the Department of Electrical Engineering. Stankovic and T. Appl.. pp. The controller performs high-power-factor rectiﬁcation under balanced input voltage condition. vol. Y. Downloaded on April 23. is insensitive to the unbalance in the circuit component values—like boost inductance in each phase. “Design of current controller for 3-phase PWM converter with unbalanced input voltage. as shown by the waveforms of be equal in magnitude to Fig. . VIII. V. D. P. Chattopadhyay and V. the power factor is not unity in phase . Ind. The outer loop scales and phase shifts the -axis current in order to . (1979–1982). TX. as a Research and Development Engineer in the Power Electronics Group of R&D (Electricals). IEEE APEC’01. 52. D. VOL. P. He is a Professor and Chairman of the Department of Electrical Engineering. In the same ﬁgure it can be noted that “Sector” change steps are not equal. degree from California Institute of Technology. 592–600. Pasadena. he was with M/s Cegelec India Ltd. “Digital implementation of a line current shaping algorithm for three phase high power factor boost rectiﬁer without input voltage sensing. 1. Nabae. as a Project Engineer—Industrial Drives. and modeling of power converters for PFC circuits and active ﬁlter systems. vol. pt. India. REFERENCES [1] S. -axes currents are also balanced Fig. [9] S. Tsukamoto. supplied as a reference to the inner loop curproduce and . Rioual. Choe. He is a Consultant to several industries in related areas. S. 2. Akagi. 17(e) shows the currents together for easy comparison of magnitudes. pp.. respectively. 6. and G. 1998. Jan. Bombay. (1970–1979) and NGEF Ltd. no./Dec. 93–98. The control technique is input voltage sensorless and suitable for ﬁxed-switching-frequency digital implementation. and the Ph. 2001. F. pp. Howrah. 4. Indian Institute of Technology. The controller has two basic functional loops. P.) and Ph. India.D. IEEE APEC’94. India. 17(d). May/Jun. 1. Malinowski. Rec. no.D. “Control of front-end three-phase boost rectiﬁer. Bangalore. he was with M/s Crompton Greaves Ltd. It is computationally simple—the execution time of the control loop is less than 40 s on a TMS320F240 that is clocked at 20 MHz and this 40 s includes the ADC conversion time of 13. Kazmeirkowski. Moran.2010 at 07:40:50 UTC from IEEE Xplore. 641–647. Ziogas. and G. Between 1996–1998. pp. 17(a) are now balanced. Lipo. Dec. Appl. 1994. India. His areas of interest are power electronics. Hyun. 26. Mok. [7] A.. [2] H. no.” in Proc. 1997. pp. Chennai. 1286–1293. H. Choe. Louis. 428–436. 2001. M. Appl. Sep. [3] M. vol. Y. CONCLUSION This paper has proposed a simple control method that can balance the input currents of a three-phase three-wire boost rectiﬁer under unbalanced input voltage condition.” in Proc. indicating that the input voltages are unbalanced.” in Conf. Boroyevich. The experimental results of Fig. The proposed control method. as expected. Hansen. vol. India. 37. NO. Dallas. degree from the Indian Institute of Science. However. “Analysis and design of an active power ﬁlter using quad-series voltage source PWM converters. Hiti and D. S. Joos.” IEEE Trans. India. control. 1993. 5. degree from the University of Madras. He was a part of the commissioning team for phase IV modernization of the TISCO Hot Strip Mill. Blaabjerg. pp. Fig. APRIL 2005 We then activate the current balance controller in the outer loop of the control structure. He has held positions in industry as a Senior Design Engineer and Chief of R&D with M/s Larsen and Toubro Ltd. vol. and A. and on the scaled and phase-shifted current . analysis. in 1990 and 2002. His research interests include design. “A novel control method of a VSC without AC line voltage sensors. in 1970. degrees from the Indian Institute of Science. We expect that the internal current but it should not should be in phase with variable . 1990./Feb. Between 1991–1995. Indian Institute of Science.

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