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Power MOS FET
Application Note

Rev.2.00 2004.08

Keep safety first in your circuit designs!
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Index

1. Electrical Characteristics Definition and Usage Explanation ............................................................ 1 1.1 Absolute Maximum Ratings and Electrical Characteristics .............................................................. 1 1.1.1 Absolute Maximum Ratings........................................................................................................ 1 1.1.2 Electrical Characteristics ............................................................................................................ 2 1.2 Relationship between On-Resistance RDS(on) and Withstand Voltage VDSS ...................................... 3 1.3 Saturation Voltage VDS(on)(= Id × RDS(on)) Gate Drive Voltage Dependence...................................... 4 1.3.1 On-Resistance RDS(on) Temperature Dependence...................................................................... 4 1.4 Gate Charge Amounts Qg, Qgs, Qgd............................................................................................... 5 1.4.1 Characteristics of Internal Diode between Source and Drain .................................................... 6 1.5 Internal Diode Reverse Recovery Time trr Current IDR Characteristic.............................................. 6 1.6 Transient Thermal Resistance Characteristic θch-c(t) – Pulse Width PW Characteristic ................ 7 1.7 Area of Safe Operation (ASO) .......................................................................................................... 9 1.7.1 Area of Safe Operation (ASO) Diagram ..................................................................................... 9 1.7.2 Notes on ASO in Circuit Control System.................................................................................. 10 2. Power MOS FET Destruction Mechanisms and Countermeasures ............................................... 11 2.1 Relationship between Power MOS FET Application Areas and Destruction Modes...................... 11 2.1.1 Relationship between Main Power MOS FET Application Areas and Destruction Modes....... 11 2.1.2 Power MOS FET Applications and Operating Range .............................................................. 13 2.1.3 Power MOS FET Structure....................................................................................................... 14 2.2 Avalanche Destruction .................................................................................................................... 16 2.2.1 Explanation of Avalanche Destruction...................................................................................... 16 2.2.2 Avalanche Destruction Resistance Test Circuit and Waveform............................................... 16 2.2.3 Avalanche Energy Calculation Method .................................................................................... 17 2.2.4 Classification of Avalanche Destruction Factors ...................................................................... 18 2.2.5 Avalanche Destruction Current and Energy Value................................................................... 19 2.2.6 Avalanche Destruction Current and dV/dt Resistance ............................................................. 20 2.2.7 Simple Determination Method for Avalanche Resistance Guaranteed Products..................... 20 2.2.8 Avalanche Destruction Countermeasures................................................................................ 22 2.3 ASO Destruction (Heat Radiation Design)...................................................................................... 22 2.3.1 Explanation of ASO Destruction ............................................................................................... 22 2.3.2 ASO Destruction Countermeasures ......................................................................................... 22 2.3.3 Forward Bias ASO (Area of Safe Operation) ........................................................................... 23 2.3.4 Load Shorting Resistance and Countermeasures.................................................................... 24 2.3.5 Heat Radiation Design.............................................................................................................. 24 2.4 Internal Diode Destruction .............................................................................................................. 29 2.4.1 Explanation of Internal Diode Destruction ................................................................................ 29 2.4.2 Example of Internal Diode Destruction Circuit Countermeasures............................................ 31 2.5 Destruction Due to Parasitic Oscillation.......................................................................................... 32 2.5.1 Explanation of Destruction Due to Parasitic Oscillation ........................................................... 32 2.5.2 Power MOS FET Parasitic Oscillation Mechanism .................................................................. 33 2.6 Notes on Parallel Connection ......................................................................................................... 34 2.6.1 Notes on Mounting ................................................................................................................... 34 2.6.2 Advice on Selection and Use of Power MOS FETs ................................................................. 34 2.7 Electrostatic Destruction ................................................................................................................. 35 2.7.1 Explanation of Electrostatic Destruction................................................................................... 35

.... Power MOS FET Applications .................................................................... 49 .................. 44 3....................... 38 2.............................. 40 3............................................................................................2 Sample Automobile ABS Application ..................................................1 Technological Trends in Automotive Electrical Equipment ................. 44 3........................... 43 3..7............................................ 47 3........................8...................1 Power MOS FET Main Loss Frequency Dependence and Relationship to Main Characteristics .............................................................................. 38 2...................................1 Switching Power Supplies ....................................................................................4 Motor Drive Applications ......7.............................................1 Small Motor Drive ...2...............................................................3............3 Non-Isolated Synchronous Rectification Converter Low-Side Self-Turn-On Phenomenon ...............3....2........2 Automotive Applications........ 35 2.....2........ 49 3........2 Electrostatic Destruction Countermeasures ...................3............ 45 3.........7................................. 36 2....2.....................................3 Power Supply Applications ........................... 46 3..3 Sample Automobile Power Steering Application ............................2.....................8 Usage Notes ..............................................................1 Application Map ..................................2 DC/DC Converters...... 43 3................................ 38 2....... 41 3...............................................................3..................................................................................5 Communication Equipment DC/DC Converter .....................4.............................. 48 3...........................................2 Malfunction (Arm Shorting) Countermeasures in Motor Application ............................................................................................... 42 3...............8......4 Base Station SMPS (Switch-Mode Power Supply) ........................................................................... 37 2........................................ 42 3......................................... 41 3....4 Sample Automobile HID Headlamp Control Application ..3...............................8..................... 42 3....4 Mechanism whereby Gate Destruction Product B Come to ASO Destruction..................................3 Destruction Progression Modes after Electrostatic Destruction ........3 VRM (Voltage Regulator Module) ......................

1. duty ≤ 1% 2. Allowable value at Tc = 25°C Pch temperature derating: Tchmax – Tc Pch(Tx) = Pch(25°C) × Tchmax – 25 Tchmax – Tc θch-c = Pch (Determined by package and chip size) Figure 1 Power MOS FET Absolute Maximum Ratings Rev.1 shows the meaning of power MOSFET absolute maximum ratings.Power MOS FET Application Note 1.14 Unit V V A A A A mJ W °C °C/W VDSS has correlation to on-resistance Lower for low-voltage drive component Theoretical equation for drain current ID: ID = Tchmax – Tc RDS(on)max × α × θch – c Drain peak current Body-drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Thermal resistance ID(pulse) uses transient thermal resistance 150°C RDS(on) α= 25°C RDS(on) Rated current of source to drain diode EAR = V(BR)DSS 1 L • IAP2 V(BR)DSS – VDSS 2 EAR *2 Pch *3 Tch θch-c Notes: 1. Allowable value at Tch = 25°C.00 Aug.2.23.1.1 1.1 Electrical Characteristics Definition and Usage Explanation Absolute Maximum Ratings and Electrical Characteristics Absolute Maximum Ratings Figure 1. Allowable value at PW ≤ 10µs.2004 Page 1 of 49 REJ05G0001-0200 . Example of 2SK3418 Item Drain to source voltage Gate to source voltage Drain current Symbol VDSS VGSS ID ID(pulse) *1 IDR IAP * 2 (Ta = 25°C) Rating 60 ±20 85 340 85 60 308 110 150 1. Rg ≥ 50Ω 3.

tf Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance 1 Static drain to source on state resistance 2 Input capacitance Output capacitance Reverse transfer capacitance Total gate charge VGS(off) |Yfs| RDS(on)1 1. di/dt = 50µA/µs V trr — 70 — ns Note: : Has positive temperature coefficient.0 — — — — — VGS = 10V. ID = 1mA ID = 45A. and gate drive voltage.3 2. tf. Influences switching time tr. VGS = 10V ID = 45A. VGS = 0. Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time td(on) tr td(off) tf VDF — — — — — 53 320 700 380 1. VGS = 4V VDS = 10V.1 shows the meaning of power MOSFET electrical characteristics. Ciss Coss Crss Qg — — — — 9770 1340 470 180 — — — — pF pF pF — — — — VDS dependent. Drive loss indicator in analog operation VDS dependent. Influence surge voltage (noise) when switching off.2004 Page 2 of 49 REJ05G0001-0200 . Qgd.1.0 9. Influence diode onloss in inverter use. VDS = 10V ID = 45A. Qgd.Power MOS FET 1. : Has negative temperature coefficient Rev.0 55 — — 90 4. RL = 0.5 — 5.5 VDS = 10V. and Vth. VGS = 0 VDS = 60V. but low in terms of loss — For products with on-chip protective diode.2.23. VDS dependent.00 Aug.1 1. guaranteed value of ±10 µA Affects switching operation noise and switching time tr. VDS = 0 Temperature Dependence Table 1. ID = 85A nC Gate to source charge Gate to drain charge Qgs Qgd — — 32 36 — — nC nC — — Characteristic that determines switching time tr. VGS = 10V. Dependent on power supply voltage VDD (increases when VDD rises). several tens of nA to several µA.67Ω. Rg = 50Ω ns ns ns ns — — — — IF = 85A. ID = 45A. Greatly dependent on gate drive voltage. Affects fall time tf under light load.2 Table 1. Electrical Characteristics Definition and Usage Explanation Electrical Characteristics Power MOS FET Electrical Characteristics (Ta = 25°C) Ratings Test Conditions ID = 10mA. VGS = 0 VGS = ±20V. Item Drain to source breakdown voltage Zero gate voltage drain current Gate to source leakage current Symbol V(BR)DSS IDSS IGSS Min 60 — — Typ — — — Max — 10 ±0.0 mΩ Most important parameters in determining on-loss. f = 1MHz V s mΩ RDS(on)2 — 6. Characteristic that determines drive loss. Becomes same characteristic as on-resistance when positive bias is applied to VGS. Note that these rise together with temperature. Determined by Rg. Determined by Rg.1 Unit V µA µA Design Notes Correlation to on-resistance Thermal dependence is high. VDD = 50V. Short-circuit current: lowers di/dt to suppress noise. VGS = 0 IF = 85A. tf. VGS = 0.

3 V(BR)DSS – Tc Characteristics (2SK3418) Rev.2 RDS(on) – VDSS Relationship Figure 1. the minimum temperature environment conditions for use of the component must be taken into consideration. Recently.00 Aug. a margin should be left in the settings with respect to circuit operation conditions power supply voltage VDD and surge voltage VDS(peak) generated when switching off.2 1. Electrical Characteristics Definition and Usage Explanation Relationship between On-Resistance RDS(on) and Withstand Voltage VDSS Figure 1.3 shows the V(BR)DSS temperature characteristic (taking the example of the 2SK3418).Power MOS FET 1. making the withstand voltage margin larger than necessary is inadvisable as it will result in higher on-resistance and greater steadystate loss.2 shows the relationship between a withstand voltage VDSS = 20 to 100 V rated component and on-resistance RDS(on). components have appeared that can handle guaranteed avalanche resistance in order to reduce this margin as much as possible and provide the benefit of lower loss. As VDSS has a positive temperature characteristic with respect to temperature. 20 D6 (SOP-8) D7 (SOP-8) On-Resistance RDS(on) (mΩ) 10 D6 (LFPAK) D7 (LFPAK) 5 2 VGS = 10 V 1 10 20 50 100 Drain to Source Voltage VDSS (V) 200 Figure 1.2004 Page 3 of 49 REJ05G0001-0200 .2. Withstand Voltage V(BR)DSS (V) 90 80 70 60 –50 0 50 100 150 200 Case Temperature Tc (°C) Figure 1.23. When selecting the withstand voltage of an component. In this case.

but rises above that temperature. When selecting the type of component in terms of drive voltage. What this means is that. the value is approximately 1. as shown in the figure. Tch does not simply rise by 20°C to become 150°C. this temperature characteristic must be carefully considered in heat radiation design. when an component is used in a high-temperature environment such as automotive electrical equipment.00 Aug. a distinction may be made between the use of 4 V drive components and 10 V drive components according to the conditions of use and application even in automotive electrical equipment.2. when ambient temperature Ta = 100°C. 4 V drive components. therefore.8 times for an component with a withstand voltage of 100 V or less. Gate to Source Voltage Drain to Source Saturation VDS(on) (V) 0.7 to 1.Power MOS FET 1. 10 V drive components.1 10 A 0 4 8 12 20 A 0 16 20 Gate to Source Voltage VGS (V) Figure 1.5 shows temperature dependence of on-resistance RDS(on). refer to the power MOS FET heat radiation design example.3 1.5 times for an component with a withstand voltage of 500 V.23. for example.2004 Page 4 of 49 REJ05G0001-0200 . Rev. 4 V drive (or lower) components are produced according to the gate drive operating current. Recently.4 VDS(on) – VGS Characteristics (2SK3418) 1.3 ID = 50 A 0. Electrical Characteristics Definition and Usage Explanation Saturation Voltage VDS(on)(= Id × RDS(on)) Gate Drive Voltage Dependence This characteristic is a characteristic curve for designing at what gate drive voltage the VDS(on) area (on-resistance area) is effected in the case of a predetermined operating current Id.5 V with a 100°C rise).3. if the channel temperature calculation result is that Tch = 130°C. and Ta is made 120°C (a 20°C rise). The means of achieving low-voltage drive is generally to use a thin gate oxide film (whereby the gate-source withstand voltage VGSS rating is reduced) to attain a lower VGS(off) value.1 On-Resistance RDS(on) Temperature Dependence Figure 1. selection of a 10 V drive component with a high VGS(off) value to cope with noise in switching power supply or motor drive applications) and the specifications of the gate drive IC or LSI to be used (such as a low-level voltage that keeps the MOS FET off). It should also be noted that.4 0. Therefore. If the ratio between channel temperature rating Tch(max. Drain to Source Saturation Voltage vs. Power MOS FET on-resistance RDS(on) has a positive temperature characteristic.5 Pulse Test 0. but increases in a curvilinear shape. VGS(off) has an approximately –5 mV/°C negative temperature coefficient (characteristic that falls approximately 0. RDS(on) does not rise linearly with a rise in temperature. and approximately 2.) of 150°C and room temperature of 25°C (150°CRon/25°CRon) is designated α. In the case of power MOS FETs. it is necessary to consider the application (for example. For details.4 to 2.2 0.

5 RDS(on) – Tc Characteristics (2SK3418) 1. 20 A Static Drain to Source on State Resistance RDS(on) (mΩ) 12 8 4V 4 VGS = 10 V 10. Dynamic Input Characteristics 100 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) ID = 85 A VGS 20 XV VGS (V) Qg (VGS = X V) Qgs Qth Qgd VDS VGS(on) Vth Gate Charge VDS (V) 80 16 VGS 60 40 VDS = 50 V 25 V 10 V VDS VDS = 50 V 25 V 10 V 0 80 160 240 320 Gate Charge Qg (nc) (b) 12 8 20 4 0 0 400 (a) Figure 1.2. it can be said that the smaller the Ron·Qg or Ron·Qgd product. 50 A 0 –50 0 50 100 150 200 Case Temperature Tc (°C) Figure 1. Temperature 20 Pulse Test 16 ID = 50 A 10. Qgs. In high-frequency (f = 100 kHz or above) applications. and depends on power supply voltage VDS. Qgd In figure 1. It is also a parameter that influences switching characteristics.Power MOS FET 1.6(a). the higher is the performance of the component. tf ≅ (Rs + rg) ⋅ Qgd Vgs(on) ………(3) log Vgs(on) – Vth Vth Fall time tf that controls L load switching loss is expressed by equation (3).2004 Page 5 of 49 REJ05G0001-0200 . This is the characteristic parameter that determines gate peak current ig(peak) for driving the gate and drive loss P(drive loss). 20. the point up to prescribed drive voltage VGS (=XV) is total charge amount Qg.6 Input Dynamic Characteristics (2SK3418) Rev.4 Gate Charge Amounts Qg.00 Aug. Electrical Characteristics Definition and Usage Explanation Static Drain to Source on State Resistance vs. Ig(peak) = Qg/t …………………………(1) ……………(2) P(drive loss) = f ⋅ Qg ⋅ VGS Qgd corresponds to mirror capacitance Crss. Qg and Qgd are important items in designing high-frequency operation loss.23.

1. In these applications.2004 Page 6 of 49 REJ05G0001-0200 .2 1. starter generators. Generally. in the case of electrical equipment) and switching power supply synchronous rectification applications that make positive use of a power MOSFET internal diode. Electrical Characteristics Definition and Usage Explanation Characteristics of Internal Diode between Source and Drain In a power MOSFET. operationally upper arm/lower arm shorting and excess turn-on loss occur in this trr period. • • • • Load switches for preventing battery reverse connection Switching power supply (n+1) redundant-type hot swap circuits Motor drive circuit external diode replacement Switching power supply secondary-side drive rectification circuits. Source to Drain Voltage 100 Reverse Drain Current IDR (A) 80 10 V 5V 60 VGS = 0. a dead time (longer than trr) is provided that turns off the gate signal at the time of upper/lower component switching. there is a requirement for this reverse recovery time trr to be fast. The characteristics of this diode show the same forward voltage characteristics as an ordinary diode in the case of zero bias of the gate drive voltage (VGS = 0).1 1.6 2. trr ta tb 0 irr Turn-on loss particularly large in this period 0. Reverse Drain Current vs.4 0. –5 V 40 20 Pulse Test 0 0.00 Aug.8 1.7 there is a voltage drop determined by on-resistance RDS(on) (VSD = Id × RDS(on)) that is the same as in the forward direction. Rated current IDR of this diode is the same value as forward drain current rating ID. as shown in Figure 1.23.4.2. in the control circuitry.Power MOS FET 1.7 IDR – VSD Characteristics (2SK3418) The benefits of such reverse-direction characteristics are actively applied in the following kinds of uses.5 Internal Diode Reverse Recovery Time trr Current IDR Characteristic In motor drive (power steering. etc. a parasitic diode is provided between the source and drain. If the gate drive voltage is given positive bias (in the Nch case). etc.8 Reverse Recovery Time trr Waveform Rev.0 Source to Drain Voltage VSD (V) 0 Figure 1.1irr Soft recovery characteristic desired (Assuming circuit floating inductance is made small) Figure 1. and a much lower forward voltage can be obtained even than with an SBD (Schottky barrier diode). therefore.

2) θch-c(t) = γs (t) • θch – c θch-c = 1. the following equation may be used.00 Aug.2).10 θch-c(t) – Pulse Width PW Characteristics (2SK3418) Rev. Also.14 = 13. Pulse Width 3 Noamalized Transient Thermal Impedance γs (t) Tc = 25°C 1 D=1 0. This is a characteristic for calculating channel temperature Tch in the component operating state.1 0.5 0. PW = 1 ms. Tch = Pd × θch-c(t) = 60 × 0. Generally.3 1 3 10 30 100 Reverse Drain Current IDR (A) Figure 1.05 t1 t2(D=0.2°C Noamalized Transient Thermal Impedance vs. it is comparatively fast at a value of 40 to 60 ns. Body-Drain Diode Reverse Recovery Time 1000 Reverse Recovery Time trr (ns) 500 di / dt = 50 A / µs VGS = 0. and therefore a soft recovery characteristic is desirable.23. Electrical Characteristics Definition and Usage Explanation This reverse recovery time trr shows a tendency to increase as the temperature rises. PW = 10 ms. in the high-withstandvoltage class of 250 V and above. Pulse width PW on the horizontal axis is the operating time.Power MOS FET 1. the more likely is the occurrence of noise.2 0. Ta = 25°C 200 100 50 20 10 0.2 × Pd) × θch-c = (0.03 1 0. the transient thermal resistance characteristic should be used.01 10 µ 0.6 Transient Thermal Resistance Characteristic θch-c(t) – Pulse Width PW Characteristic Figure 1.9).02 1 0.1 0. but since error arises as shown below.10 shows the θch-c(t)—pulse width PW characteristic.2004 Page 7 of 49 REJ05G0001-0200 .7°C When the transient thermal resistance characteristic is used. the steeper di/dt at the time of recovery (area tb in figure 1.44 × 1.2 (duty cycle = 20%) means that the repetition frequency is 200 Hz (repetition cycle T = 5 ms).0 se ul tp o sh D= PW T t3 1m 10 m 100 m T 100 µ 1 10 Pulse Width PW (S) Figure 1.3 0.5ºC error arises as shown below. Tch = (0. In the case of a withstand voltage of 60 V or less.2 × 60) × 1. when channel temperature rise ∆Tch is calculated with duty cycle = 20% (D = 0.14 = 30.9 trr – IDR Characteristics (2SK3418) 1. products have been developed that have been speeded up to around 100 ns by means of lifetime control technology. 16. and 1 Shot Single Pulse repeat operation conditions are shown. It is around 100 ns in the 100 V class. Tc = 25°C PDM PW 0. Therefore. D = 0. For example. and current dissipation Pd = 60 W.14°C/W.2.1 0. and around 300 to 600 ns in the 250 to 500 V high-withstand-voltage class. Reverse recovery time trr differs greatly according to the withstand voltage of the component.

repeat operation with duty cycle = 20%.14) = 85 + 12.Power MOS FET 1.2. • Example 1 To calculate channel temperature Tch under the following conditions: when case temperature Tc = 85°C. repetition cycle T = 500 µs. operating frequency f = 2 kHz. applied power Pd(peak)2 = 50 W From the above operation. 1 shot single pulse Tch1 = Tc + (Pd(peak)1) × θch-c(t1) = 85 + (50 × 0.54°C • Example 3 To calculate peak channel temperature Tch(peak) when peak power Pd(peak)3 = 500 W is further applied for a period of t3 = 60 µs by another circuit control system during the operation in Example 2 Tch2 = Tc + (Pd(peak)2) × θch-c(t2/T) + {(Pd(peak)3 – Pd(peak)2 × t2/T)} × θch-c(t3) = 85 + (50 × 0. and D = t2/T = 0.14) = 97.32 = 114.14) = 102.2004 Page 8 of 49 REJ05G0001-0200 . Therefore: Tch2 = Tc + (Pd(peak)2) × θch-c(t2/T) = 85 + (50 × 0.22 × 1. Electrical Characteristics Definition and Usage Explanation Examples of channel temperature Tch calculation (2SK3418) using transient thermal resistance are shown below.3 × 1.031 × 1.22 × 1.86°C t3 Pd(peak)3 t2 Pd(peak)2 T Rev. peak power Pd(peak)1 = 50 W.1°C • Example 2 To calculate channel temperature Tch under the following conditions: when case temperature Tc = 85°C.2) × 0. application time t2 = 100 µs. application time ts = 10 ms.2.00 Aug.54 + 17.23.14) + (500 – 50 × 0.

When the area becomes a large current area that entails a change to a positive temperature characteristic.7. this area is divided separately from the ASO area. but in this small current area the output transfer characteristic (Vgs-Id characteristic) is a negative temperature characteristic. Area (3) is an area limited by channel loss. Area (1) is an area limited by maximum rated currents IDC.1 1.3 Ta = 25°C 0. and this can be guaranteed with a so-called constant power line with no secondary breakdown.7 1. Maximum Safe Operation Area 1000 300 Drain Current ID (A) 10 µs 1 100 2 0µ = 3 1 s m DC 10 m s Op s (1 30 e (T rati sho c = on t) 10 25 Operation in this °C ) 4 3 area is limited by RDS(on) PW 10 1 0.2. Generally.Power MOS FET 1. Area (2) is an area limited by on-resistance RDS(on)max [ID = VDS/RDS(on)]. The ASO limited area is divided into the following 5 areas. Area (5) is an area limited by withstand voltage VDSSmax.3 1 3 10 30 5 100 Drain to Source Voltage VDS (V) Figure 1. when the operating voltage increases in the same applied power line. Area (4) is the same kind of secondary breakdown area as in a bipolar transistor that appears under conditions of continuous operation or opened with a comparatively long pulse width (several ms or more).2004 Page 9 of 49 REJ05G0001-0200 .11 ASO Diagram (2SK3418) Rev. the operating current naturally decreases.23.11 shows an area of safe operation (ASO) diagram for the 2SK3418. this phenomenon disappears. This is because.1 0.1 0.00 Aug. ID(pulse)max. Electrical Characteristics Definition and Usage Explanation Area of Safe Operation (ASO) Area of Safe Operation (ASO) Diagram Figure 1. The current value at which the temperature characteristic changes from negative to positive differs from product to product. and with products of several amperes or less this phenomenon is unlikely to occur.

Figure 1. in normal operation they are usually used in limited area (2). making it necessary to confirm whether it is in an area of safe operation. VGS is in an underdrive state in period t1 in the figure. System power supply down Gate drive voltage fall control time controlled to be slower than that of power supply voltage Power supply voltage VDD 0 Gate drive voltage VGS 0 t1 Vth D-S operating voltage VDS 0 Enters ASO area (4) or (5) Drain operating voltage ID 0 t Figure 12 Example of Terminal Electronic Device System Power Supply Voltage and Gate Drive Voltage Sequence Rev.00 Aug.2 1. A point requiring attention in circuit design is the control system sequence. An effective means of avoiding such an operation area is to perform sequence control so that the fall time of gate drive voltage VGS is delayed beyond supply voltage VDD as shown by the dotted lines. and enters ASO limited area (4) or (5). As shown by the solid lines in the figure.Power MOS FET 1.23.7. Electrical Characteristics Definition and Usage Explanation Notes on ASO in Circuit Control System As power MOS FETs are generally used in switching applications. if the fall time until power supply voltage VDD is turned off is longer than that for gate drive voltage VGS.12 shows an example of the power supply voltage and gate drive voltage sequence for a terminal electronic device when the system’s source power supply is cut.2.2004 Page 10 of 49 REJ05G0001-0200 .

The purpose of this section is to carry out electronic circuit design with a good understanding of the mechanisms behind such destruction. destruction. circuit designers frequently have to confront the problem of unexpected component destruction.23. and against external surges that reach to the circuit.gas injection HDD) (servo) ge) tor — — — — — — — — Destruction Mode 1 Avalanche destruction 2 ASO Forward-bias ASO destructi. Table 2. in order to use power MOS FETs effectively.nance Bridge connec.1 Relationship between Power MOS FET Application Areas and Destruction Modes Relationship between Main Power MOS FET Application Areas and Destruction Modes Table 2. Low Machine Motor solenoid voltage voltage tool ABS (electro. — — — — — — — — — — — — — — — — — — — — — — — Guard against static electricity during handling (including electrostatic charges on the mounting equipment). Power MOS FET destruction modes can be broadly be divided into the five modes shown below.1. and produce as far as possible problems involving heat radiation.1 Relationship between Power MOSFET Application Areas and Destruction Modes Application Field Switching Power Supply AC/DC(OA. Rev.00 Aug.conver. and are used under a wide range of conditions. Power MOS FET Destruction Mechanisms and Countermeasures Introduction As power MOS FETs are often used in the final output circuitry of electronic device application circuits.genera.1 shows the relationship between main power MOSFET application areas and destruction modes.rectifiter method circuit tion ter cation — — — — — — — — — Automobile (electronic components) Motor Drive High Valve. and so forth.EPS OA static start-up direct (PPC.2. in mass production and in the market after design is completed.Loss ASO with short-circuit ↓ of load (Short-circuit on Heat between upper and lower sides) RDS(on) Switching Built-in Di trr 3 Built-in diode destruction 4 Destruction by parasitic oscillation when operating with MOS FETs connected in parallel 5 Gate surge or electrostatic destruction UPS (DCAC) — Audio amp.1 2. 2. Server) Application Largepower SynchForward Resoparallel DC-DC ronous conver. FA dischar.Power MOS FET Application Note 2.2004 Page 11 of 49 REJ05G0001-0200 .

Power MOS FET Destruction Mechanisms and Countermeasures (1) Avalanche destruction mode A phenomenon whereby destruction occurs if a surge voltage exceeding the rated VDSS of the component is applied between the drain and source. From this standpoint.00 Aug.2004 Page 12 of 49 REJ05G0001-0200 . Table 2. Transient factors : Pulse ASO (1 shot pulse application) : Load shorting ASO : Switching loss (turn-on. see section 2. Notes on Parallel Connection. and a certain energy level or higher is attained. turn-off)* : Internal diode trr loss (Upper/lower arm shorting loss)* All are temperature-dependent. electrostatic destruction Main types are gate overvoltage destruction caused by surge application between the gate and source from external circuitry.5. Destruction Due to Parasitic Oscillation. when a parasitic diode configured between the source and drain operates. Main causes of heat radiation are classified as a continuous or transient factors.23. This destruction energy differs according to the individual product and operating conditions. and gate destruction ESD (electrostatic discharge) caused by static electricity due to handling (including a charge from mounting or measuring equipment).1 shows the importance of the above five modes in various devices and applications. (2) ASO (Area of Safe Operation) destruction Mostly caused by heat caused by exceeding the so-called Area of Safe Operation. in which component maximum rating drain current Id. and taking these points into account when designing circuits and selecting components is an effective means of preventing various problems.6. (For details.4. Asterisked items also depend on operating frequency f.) (5) Gate surge. or allowable channel dissipation Pth(W) is exceeded. and section 2. Continuous factors : Heat radiation due to DCASO (loss caused by DC power application) : On-resistance RDS(on) loss (RDS(on) increases at high temperatures) : Loss due to leakage current IDSS (extremely small compared with other loss) 2. see section 2. 1. the following considerations are important. drain-source voltage VDSS.) (4) Destruction due to parasitic oscillation This destruction mode is prone to occur in the case of parallel connection. (3) Internal diode destruction This is a mode in which. destruction voltage V(BR)DSS (whose value differs according to the destruction current) is reached. Rev. (For details. Internal Diode Destruction. a power MOSFET parasitic bipolar transistor operates and breaks down in reverse recovery of that diode.2.Power MOS FET 2.

a demand has recently arisen for products specific to particular applications. the most important characteristics and specifications naturally differ according to the field and application concerned. ) Low loss.Power MOS FET 2. with load inductance and operating frequency as parameters. laser) Power supply for machine processing High-speed. Consequently. printer) 10k Improving start-up performance. high-accuracy Graphic processing High-density.00 Aug. low loss DC-DC converter (VRM.2 2. loss. PC) (Telecommunications) AC-DC switching power supply (Network OA. Rev. Power MOS FET Destruction Mechanisms and Countermeasures Power MOS FET Applications and Operating Range Figure 2.1 Power MOS FET Applications Market requirements are (1) improved energy saving. reducing loss and size f(h igh L( sp sm ee all d). highaccuracy control Motor drive for industry (FA inverter) Small motor drive (HDD. (3) smaller. high reliability 1k 1µ 10µ 100µ Load Inductance L (H) 1m 10m Figure 2. Base station) w L( spe lar e g e d).23. thinner design. 10M Ultrasonic medical appliance MD 1M Machine tool (electrostatic discharge. high-speed processing Reducing voltage.2. (2) lower noise (environmental considerations).1. ) Automobile electronic components (ABS.1 shows the kind of operating conditions in which power MOS FET applications are used. and noise Common Needs •Saving energy •Low noise •Small and slim package f(lo Operating Frequency f (Hz) 100k High-speed processing. With regard to the characteristics demanded of power MOS FETs.2004 Page 13 of 49 REJ05G0001-0200 . injection. solenoid) Actuator for industry Low loss.

4 shows the output static characteristics and diode characteristics of a high-withstand-voltage power MOS FET (2SK1522). so as not to affect the MOS FET destruction tolerance. UPS (uninterruptible power supply).2 N-Channel Power MOS FET Chip and Internal Structure Figure 2. D Partially enlarged view Gate Source Active region G Gate bus lines S Drain (bottom) Figure 2. and are designed so that Rb is made small. together with an equivalent circuit diagram.3 shows the cross-sectional structure of an N-channel power MOS FET (with gate protection diodes).23. the internal diode characteristics can be used effectively. Rev. Power MOS FET Destruction Mechanisms and Countermeasures Power MOS FET Structure Figure 2.1. or similar application.3 Cross-Sectional Structure of N-Channel Power MOS FET (with Gate Protection Diodes) Figure 2. Layer n+ p– n+ p– p– n+ p– n+ Cell Built-in diode Drain current Gate Gate protection diode Operating region of power MOS FET Regions peripheral to gate pads Drain Source Gate protection diode Symbol of MOS FET (Nch) Figure 2. When a power MOS FET is used in a monitor drive. for example. As shown in the figure.00 Aug. A power MOS FET has a structure in which bipolar transistors are connected in parallel between drain and source. S Gate bus lines Active region N+ G P N– N++ D MOS FET cells are connected in parallel in the active region. The cell cross-sectional structure of a general power MOS FET plate structure is shown. As shown in the enlarged cell diagram.3 2.2.2004 Page 14 of 49 REJ05G0001-0200 .Power MOS FET 2. Gate Gate Wire Protection Layer (Polyimide-resins) Poly-Si Source Built-in diode Drain SiO2 P Type Layer n+ N Type Si Epi. the internal structure of an N-channel power MOS FET chip comprises a large number of cells connected in parallel. current flows in the source → drain direction (the reverse is true in a P-channel type). These transistors operate at the time of transitions.2 shows an N-channel power MOS FET chip and its internal structure.

4 Output Static Characteristics and Diode Characteristics (High Withstand Voltage) Figure 2.0 –0. Drain Current ID (A) G S 25 20 15 10 5 10V 4.6 VGS=0V Due to VGS positive bias = RDS(on) Body Diode –0.4 2.6 0.5V N+ P N– N++ Source-Drain Voltage VSD (V) Diode Forward Voltage VF (V) –2.Power MOS FET 2.5 Output Static Characteristics and Diode Characteristics (Low Withstand Voltage) Rev.0 –1.2 Cell Structure (Trench) D RDS(on) Cgd rg G Cgs Rb Parasitic Bipolar Transistor Cds O 0 –5 –10 –15 0. and are therefore much smaller than a rectification Schottky barrier diode (SBD) low-VF component (VF = 0.5 2.4 –0.0V N– IDR N++ Source-Drain Voltage VSD (V) Diode Forward Voltage VF (V) D –1.0 Drain-Source Voltage VDS (V) Reverse Current IDR (A) Body Diode Current IF (A) Body Diode –20 VGS=4. Power MOS FET Destruction Mechanisms and Countermeasures Drain Current ID (A) Source Gate 25 20 15 10 5 VGS=4V 0 VGS=0V 10V Body Diode Cds Rb –5 –10 –15 Body Diode –20 –25 0.23.2. and are widely used as MOS synchronous rectification components for the purpose of achieving higher efficiency of low-voltage power supplies (Vout = 3.5 10V 4.5 –2.5 –1.0 1.5V VGS=0V 0.5 1.5V 10V –25 S Equivalent Circuit Typical Output Characteristics (Example of HAT2064R) Figure 2.0 –0.5V 3.5 V).5 Drain Cell Structure (Planar) D RDS(on) Cgd rg G Cgs Drain-Source Voltage VDS (V) Parasitic Bipolar Transistor S Equivalent Circuit Typical Output Characteristics (Example of 2SK1522) Figure 2.2 0.2004 Page 15 of 49 REJ05G0001-0200 .5V N+ P ID Reverse Current IDR (A) Body Diode Current IF (A) 3.8 –0.5 shows the output static characteristics and diode characteristics of a low-withstand-voltage power MOS FET (HAT2064R) in the same way as in the previous section.4 to 0.8 1. Low-withstand-voltage power MOS FETs attain an ultra-low on-resistance characteristic on the order of several mΩ or less.00 Aug.0 2.3 V or less).

the avalanche area may or may not actually be entered depending on actual withstand voltage V(BR)DSS of the component.6 Avalanche Destruction Resistance Test Circuit and Waveform Period ta in the waveform in (b) is defined as the avalanche time.G (pulse generator) RGS Rg = Rgs = 50Ω Standard Test Circuit Figure 2.2 2. but it is advisable to select a product with guaranteed avalanche resistance.2.2. The range in which drain-source peak voltage Vds(p) satisfies the condition Vdss ≤ Vds(p) < V(BR)DSS is an area in which the so-called rated voltage is exceeded but avalanche destruction has not been reached. In this kind of operation area. use within rating channel temperature Tch ≤ 150°C is necessary.1 2.23. avalanche current rated value IAP(A) and avalanche energy value EAR(J) are stipulated. or a spike voltage due to leakage inductance.2 Avalanche Destruction Resistance Test Circuit and Waveform Figure 2.2. For avalanche resistance guaranteed products.6 shows an avalanche destruction resistance standard test circuit (a) and its operational waveform (b). 2. Avalanche resistance guaranteed products are all subjected to final screening by the standard circuit shown in (a). Rev. EAR is expressed by equation (1). and destruction occurs.00 Aug. with regard to peak channel temperature Tch(peak) in the avalanche operation state. Power MOS FET Destruction Mechanisms and Countermeasures Avalanche Destruction Explanation of Avalanche Destruction Avalanche destruction is a mode in which a flyback voltage generated when dielectric load switching operation is turned off. IAP is variable depending on pulse width Rg IAP VDS Test sample ID P. entered in a destruction area. exceeds the power MOS FET drain rated withstand voltage. An example of calculation of this channel temperature is given in another section.Power MOS FET 2. EAR = Pd ⋅ t = 1 1 V(BR)DSS ⋅ L ⋅ IAP2 ⋅ V ⋅ I ⋅ ta = 2 (BR)DSS AP 2 V(BR)DSS – VDD (J) ………(1) Also. (a) L (b) ta dV/dt Vdss Avalanche time IAP (Avalanche Current) V(BR)DSS VDD VDD 0 VDS(on) VDS(on) = ID · RDS(on) Voltage VDS • Current ID Waveform [Equation for calculating avalanche energy] 1 V(BR)DSS · L · IAP2 · EAR = 2 V(BR)DSS – VDD VGS = 10 to 15V.2004 Page 16 of 49 REJ05G0001-0200 .

Power MOS FET 2.7 Avalanche Test Equivalent Circuit Avalanche energy value EAR in the equivalent circuit is expressed by equation (1).2004 Page 17 of 49 REJ05G0001-0200 .3 2. Power MOS FET Destruction Mechanisms and Countermeasures Avalanche Energy Calculation Method Figure 2.2.00 Aug.7 shows an avalanche test equivalent circuit.23. EAR = ∫ 0 Vds(t) ⋅ Id(t) dt ta ……………………(1) Vds(t) and Id(t) are as follows: Vds(t) = V(BR)DSS Id(t) = IAP – ……………………………(2) IAP t ……………………………(3) ta L ⋅ IAP ………………………(4) ta = V(BR)DSS – VDD Substituting (2) and (3) in equation (1): EAR = ∫ 0 V(BR)DSS IAP – = V(BR)DSS ⋅ IAP ⋅ t – ta ( IAP ta V ⋅I ⋅t t dt = ∫ 0 V(BR)DSS ⋅ IAP – (BR)DSS AP dt ta ta ) ( ) [ V(BR)DSS ⋅ IAP ⋅ t 2ta 2 ta ] = 0 1 ⋅ V(BR)DSS ⋅ IAP ⋅ ta 2 Substituting ta of equation (4) in the above equation: ∴ EAR = 1 V(BR)DSS ⋅ L ⋅ IAP2 ⋅ 2 V(BR)DSS – VDD Rev. Ids(t) IAP L VDD V(BR)DSS D VDD V(BR)DSS L e IAP Ids(t) G S Figure 2.2.

Power MOS FET Destruction Mechanisms and Countermeasures Classification of Avalanche Destruction Factors The following three factors.00 Aug.4 2. affect the avalanche destruction resistance value.2.1 1 Inductance L (mH) 10 100 Figure 2. illustrated in figure 2.Power MOS FET 2.2004 Page 18 of 49 REJ05G0001-0200 .8 Classification of Avalanche Destruction Factors Rev. (1) Limitation due to drain current Id rating (2) Limitation due to excessive channel temperature in avalanche (3) Decline of destruction resistance due to dV/dt (figure 2.23.2.6(b)) 100 Avalanche Destruction Current IAP (A) •ID rating limit •Destruction caused by dv/dt Des t tem ruction p (the eratur caused e rma l AS s in the by ove rO) cha nne l 10 1 0.8.01 0.

9 Avalanche Destruction Current and Energy Value (High Withstand Voltage) Test conditions: VGS = 15V.5 2.23. Ta = 25°C Target device: 2SK2869 (60V / 20A / 45mΩ↓ / DPAK) 100 1000 Destruction Current IAP Avalanche Destruction Current IAP (A) 50 500 Destruction energy EAR 200 ID rating 20 Guar antee 10 d reg ion(T ch≤1 100 50°C ) 5 50 2 20 1 10µ 100µ Inductance L (H) 1m 10 10m Figure 2. Test conditions: VGS = 15V. but the destruction energy EAR value tends to increase.9 and 2. Therefore.2.Power MOS FET 2. VDD = 25V.00 Aug. it can probably be stated that an component with a small inductance value L and large destruction energy value EAR has good avalanche resistance. In general.10 show actual data show how avalanche destruction current IAP and avalanche destruction energy EAR vary with the inductance L value for a high-withstand-voltage 500 V class component and low-withstand-voltage 60 V class component.2004 Page 19 of 49 REJ05G0001-0200 Avalanche Energy EAR (mJ) Avalanche Energy EAR (mJ) . it is necessary to consider both destruction current IAP and energy value EAR. 140°C Target device: 2SK1168 (500V / 15A / 0. Power MOS FET Destruction Mechanisms and Countermeasures Avalanche Destruction Current and Energy Value Figures 2.10 Avalanche Destruction Current and Energy Value (Low Withstand Voltage) Rev.2. Ta = 25. respectively. VDD = 250V. destruction current IAP tends to fall. to see the variations in avalanche resistance. The graphs show that as the inductance L value increases.4Ω↓ / TO-3P) 1000 10000 Avalanche Destruction Current IAP (A) 300 Destruction Current IAP 100 Destruction energy EAR 3000 1000 30 ID current rating 300 10 Item Symbol Tc (°C) IAP 25 140 25 EAR 140 30µ 100µ Guara 100 nteed region (Tch≤ 3 150°C ) 30 1 10µ 300µ Inductance L (H) 1m 3m 10 10m Figure 2.

leading to a drop in destruction resistance. 0.6 2. Ch2 Ch3 10.3336 = 113. Ta = 25°C Rg: dv/dt is variable 15V Rg Pre Drive P. L = 5mH. Tch ≤ Rated 150°C Figure 2.0 V M 200µs Ch1 11.4.12. ID ≤ Rated IAP max 2. VDD = 25V.12 Avalanche Time and Drain-Source Voltage (Drain Current) Rev. This value differs according to the particular component.23.Power MOS FET 2.11 shows measured values for avalanche destruction current IAP dependence on dV/dt resistance. The description is based on the avalanche operation waveform (1 shot period) in figure 2. L = 100µH VGS = 15V. 1 shot •Channel temperature during avalanche: Tch Tch = T(S)ch + Pch × θch-c(t) = 60 + 160 × 0.4°C T(S)ch: Initial channel temperature (assumed to be 60°C) 1 Pch = × IAP × V(BR)DSS 2 1 = × 4 × 80 = 160W 2 θch-c(t): ta = 400ms. Tc = 25°C.2004 Page 20 of 49 REJ05G0001-0200 .2.11. Target device: 2SK1170 (500V / 20A / 0. Figure 2. will now be considered. a parasitic bipolar transistor is formed between the drain and source in the structure shown in figure 2. As dV/dt is made steeper. and this transistor is turned on. taking the example of a 2SK2869 (60 V/20 A.00 Aug. a transient current flows through capacitance Cds.2. DPAK package) avalanche guaranteed product as the tested device. Power MOS FET Destruction Mechanisms and Countermeasures Avalanche Destruction Current and dV/dt Resistance The third factor. as explained before. the relationship between avalanche destruction resistance and dV/dt.5 V Drain to Source Voltage: 20V/DIV Drain Current: 1A/DIV Avalanche time ta Time t : 200µs/DIV Note: 1.7 Simple Determination Method for Avalanche Resistance Guaranteed Products A simple determination method for avalanche resistance guaranteed products is described here.27Ω↓ / TO-3P) 1000 Measured values for destruction Parasitic Bip TRS operates 300 Avalanche Current IAP (A) 100 VDD = 250V. Target device: 2SK2869 (60V / 20A / 45mΩ↓ / DPAK) Test conditions VGS = 15V.2.0mV 20.11 Avalanche Destruction Current and dV/dt Resistance 2.G L DUT 30 ID current rating 10 Area of safe operation (Reference) VDD 3 1 Test Circuit and Conditions 1 3 10 dV/dt (V/ns) 30 100 Figure 2. In a power MOS FET. the area in which dV/dt ≤ 10 V/µs can be called a safe area. In the example in figure 2. 2SK2869 From the transient thermal resistance characteristics. 45 mΩ↓ .3336°C/W is obtained.

3 0.17 = 0.1 0. For dV/dt. it is determined that the value is within the avalanche guarantee range.3336 2 ) = 113.3336°C/W Therefore.5 Transient thermal resistance during avalanche time ta (ta = 400µs) θch-c(t) = γs(t) · θch-c = 0.1 0.08 θch-c(t) = γs(t) · θch-c θch-c = 4.2.05 0.08 × 4. a range of safe operation was assumed. Tc = 25°C pu PDM PW T 0. When more complex conditions or components are involved.17°C/W.2 0. it can be confirmed that it is within avalanche rated current + IAPmax ≤ 6. θch-c(t) is transient thermal resistance.Power MOS FET 3 2. individual measures should be taken. Therefore. substituting numeric values in equation (1) gives: Tch = T(s)ch + = 60 + ( 1 × IAP × V(BR)DSS × θch – c(t) 2 ) ( 1 × 4 × 80 × 0.02 lse 0.00 Aug. θch-c(t = 400 µs) when avalanche opened time ta = 400 µs can be calculated from the graph as shown below. (1) Whether avalanche current IAP is within avalanche guarantee value current rating IAPmax (For 2SK2869 avalanche guaranteed current IAP.13.08 × 4.10)) (2) Whether channel temperature Tch in avalanche operation is within the range Tchmax ≤ 150°C First. Thus. Next. Power MOS FET Destruction Mechanisms and Countermeasures Tc = 25°C Transient Thermal Resistance γs (t) 1 D=1 0.17 = 0.2004 Page 21 of 49 REJ05G0001-0200 . θch – c(t = 400µs) = γ(t) × θch – c = 0. the following two checkpoints should be confirmed. IAPmax = 6. and is calculated from the 2SK2869 data sheet transient thermal resistance characteristics in figure 2.4°C and it can be confirmed that Tch is within the Tchmax ≤ 150°C rating. when L = 5 mH.03 1 0.13 2SK2869 Transient Thermal Resistance Characteristics (Data Sheet) Trial calculations have been carried out assuming that start channel temperature T(s)ch = 60°C before avalanche operation (due to the channel temperature rise caused by on-resistance RDS(on) and switching loss).23.2 A (figure 2. Rev. channel temperature Tch in avalanche operation in (2) is expressed by equation (1). as avalanche current IAP in (1) is 4 A from the waveform.01 10µ 100µ 400µ 1m 10m Pulse Width PW (S) 100m 1 10 Figure 2. Tch = T(s)ch + Pch × θch – c(t) = T(s)ch + ( 1 × IAP × V(BR)DSS × θch – c(t) 2 ) …………(1) Here.3336°C/W 0.2 A.0 1s t ho D= PW T 0.

.2004 Page 22 of 49 REJ05G0001-0200 . thermal runaway occurs.00 Aug. when an overcurrent and the used voltage are applied simultaneously due to load shorting. is inserted. (1) Make large-current path wiring as short and thick as possible to reduce floating inductance.23. As a surge voltage occurs when switching off. Vin(DC) Vd Driving circuit Action 2 Over-current protection circuit Vin R2>>(R1+R3) IC1 R2 Rg Q1 10k Rs Heat sink Load VGS R1 R3 0 VDS (V) Vout Vds ID (A) Action 1 ASO guarantee ID(Pulse) Id Action 3 IDC Operating area Q1 : 2SK2569. Action 1 Thicken wiring Vin(DC) Action 3 VGS(in) Action 2 Control system Driving circuit Gate resistance Twisted-pair wires Vout CR Zener snubber diode Figure 2. destruction is caused by a counter voltage due to floating inductance (inductance load). switching loss will increase.. 2.8 2.2. when chip heat radiation is not performed properly due to thermal mismatching or a high repetition frequency.15 illustrates ASO destruction and countermeasures. 2. etc. as follows.14 shows avalanche destruction countermeasures (methods of suppressing surge voltages).3. and suppress dV/dt. etc.3. and connection should be made directly to the power MOS FET drain and source terminals. It also refers to a mode in which the channel temperature rises excessively due to continuous heat radiation. Power MOS FET Destruction Mechanisms and Countermeasures Avalanche Destruction Countermeasures Figure 2. There are three countermeasures for avalanche destruction. (3) Insertion of CR snubber and Zener diode When a surge absorption snubber. This should be considered when deciding on the circuit constant.14 Avalanche Destruction Countermeasures In avalanche destruction. and destruction results. As a characteristic after destruction. that does not occur in normal operation.3 2. (2) Insert a gate series resistance Rg.Power MOS FET 2. but if the value is made too large. 2SK2980 IC1 : HA17358 Figure 2. surge voltages are suppressed by making the value of turn-off constant Rg large.2.1 ASO Destruction (Heat Radiation Design) Explanation of ASO Destruction ASO destruction refers to a mode in which heat radiation is caused instantaneously and locally. the wiring should be made short and thick. and destruction occurs.2 ASO Destruction Countermeasures Figure 2. electrodes are shorted.15 ASO Destruction (Heat Radiation Design) and Countermeasures Rev.

Gate retention voltage VGS(cut) at the time of overcurrent cutoff is expressed by equation (2). Tc = 75°C 1) Guaranteed value at Tc = 25°C: Pd(25) = 1500W 2) ∴Pd(75) = Pd(25) × 0. and it is turned off. The VGS(off) temperature characteristic (α = –5 mV to –7 mV/°C) is also taken into consideration.2.3. VGS(cut) = Vin × R3 R1 + R2 + R3 ……………………………(2) VGS(cut) must be set to a value smaller than power MOS FET gate-source cutoff voltage VGS(off). (3) Carry out radiation design allowing a sufficient margin.Power MOS FET 2.6 = 900W In the ASO diagram. and is made a constant that prevents the occurrence of surge at the time of overcurrent (cutoff) protection. VGS = Vin × R3 + 10kΩ ……………………(1) (R3 + 10kΩ) + (R1 + R2) VGS is set to a value (VGS = approx. 2. 10 V) at which a power MOS FET operates fully in the on-resistance region. 0. MOS FET Q1 is turned on. it is possible to perform cutoff control of speed at the time of cutoff in a list by means of Q1 gate resistance Rg.3 Forward Bias ASO (Area of Safe Operation) Figure 2.16. Then. refer to the description of the use of power MOS FET characteristics described earlier. as Tc = 75°C derating ratio D = 60%.1 0.) ASO Temperature Derating 1000 Example: 2SK3082(60V/10A. regarding PW = 10 µs and Tc = 25°C guarantee values. and that the temperature derating is adequate. the voltage arose on Rs is detected. Power MOS FET Destruction Mechanisms and Countermeasures There are three countermeasures. (For information on an Area of Safe Operation (ASO). as follows. this is the area indicated by the PW = 10 µs.00 Aug. Rev. LDPAK) Guaranteed line for PW = 10µs.16 shows a forward bias ASO graph (2SK3082) and the corresponding temperature derating method. This is covered in the practical example of radiation design. 75°C D= Derating Ratio D (%) : Destruction point 100 ID(pulse) rating Drain Current ID (A) Tch(max) – Tc 150 – Tc = × 100 Tch(max) – 25 125 100 80 60 40 20 10 µs 10 0µ 10 IDC rating DC s PW Op er 1m = 10 ms s sh o 25 at 1 Region limited by on-resistance RDS(on) ion (1 = (Tc t) ) 0 50 75 100 150 200 °C Case Temperature Tc (°C) Example: •Derating for PW = 10µs. Alternatively. If the designed drain load current is exceeded.6 = 900W Tc = 25°C 0.16 Forward Bias ASO Diagram (Area of Safe Operation) With regard to the ASO temperature derating method. this ASO diagram gives a Pd(25) = 1500 W (= Vds × ID = 50 V × 30 A) power line. Pd(75) = Pd(25) × 0.1 1 10 100 Drain to Source Voltage VDS (V) Figure 2. Tc = 75°C line in figure 2.075Ω↓. insert an overcurrent protection circuit. shorting occurs between G-S of the main power MOS FET via R3. (2) If load shorting is predicted.6 = 1500 × 0.23. PW = 10 µs.2004 Page 23 of 49 REJ05G0001-0200 . (1) Check inclusion within the forward bias ASO (Area of Safe Operation) guarantee. First. Tc = 75°C derating will be described as an example. In this case the value of R3 is made larger than R1 determined as a normal switching off time constant. MOS FET gate-source drive voltage VGS in normal operation is expressed by equation (1).

this load shorting resistance is dependent on the power supply voltage VDD (≈ VDS) used.5 Heat Radiation Design When carrying out mounting design for power devices.2. with destruction occurring in a shorter time the greater the value of VDS (as the power applied due to load shorting increases).17 Power MOS FET Load Shorting Resistance and Countermeasures 2.23. 10A (2 conditions)  PW = 10 µs.3.00 Aug. When a power MOS FET is used in a motor drive application. This destruction time differs from product to product. if the load should short. how heat is to be radiated efficiently under various environmental conditions — is an important consideration. 1. it is necessary to set a cutoff turn-on time slower than the steady state on/off speed.27Ω↓. it goes without saying that cooling technology — that is. As a current considerably larger than the steady state current flows. as the short-circuit current an overcurrent of around 5 to 10 times the normal operation current flows. tf period = 0.17. TO-3P) 2SK1522(500V/50A. and this is cut off.4 2. a setting of between 10 µs and 15 µs or less can be said to be safe.17 shows power MOS FET load shorting resistance (examples of the 2SK1518 and 2SK1522). As shown in figure 2. Examples are given here of practical heat radiation design in which the operating channel temperature of a power MOS FET can be calculated theoretically. 1000 PW: Variable VGS = 10V VDD PG Test sample Test Circuit Drain to Source Voltage VDS (V) Target device: 2SK1518(500V/20A.11Ω↓. Pulse Width PW (µs) Figure 2. it is necessary to be able to withstand the conditions without breaking down until the overcurrent protection circuit operates.3. duty = 50% max (f = 50 kHz operation)  Switching loss P(tf) = 500 W. (1) Operating conditions  Ambient temperature Ta = 50°C  Operating current Id = 8A. Next.17. and suppress the cutoff surge voltage to the component’s rated voltage VDSS or less. TO-3PL) : 2SK1522 : 2SK1518 Test conditions VGS = 10V Ta = 25°C 500 Measured values for destruction Check that VDSS is not exceeded by over-voltages generated by shutdown when shortcircuit occurs ID Short circuit current shutdown VBR(DSS) 200 Example of operating voltage range Short-circuit current 2SK1522: About 200 to 280A 2SK1518: About 80 to 120A VDD 100 10 20 50 100 200 500 1000 Over-currents generated by short-circuit loads must be detected in less than 1/2 to 1/3 of the destruction time PW. 0. but the overcurrent protection detection time in the event of load shorting should be set to between 1/2 and 1/3 or less of the destruction time.Power MOS FET 2. 2. In the case of a power MOS FET. 0. Preconditions when using a 2SK1170 (500 V/20 A. when load shorting occurs. 1. 0.27 Ω. but how to perform theoretical heat calculations efficiently is also important. Power MOS FET Destruction Mechanisms and Countermeasures Load Shorting Resistance and Countermeasures Figure 2. This is showed as the waveform in figure 2. TO-3P) are shown below. A point to be noted here is the surge voltage that is generated when this overcurrent is cut off.2004 Page 24 of 49 REJ05G0001-0200 .2 µs (ton loss is omitted here) Design target: Tch ≤ 120°C Rev.

3 to 0.2 0.8 + 0.5 = 2. θ(f) = 0.4 to 0. In this method.5°C/W.Power MOS FET 2. Results calculated on the basis of the above operating and environmental usage conditions are shown in figure 2.9 0.2.2 0. a design target channel temperature of Tch ≤ 120°C is set.2 to 1. 1.5 0. θ(f) = 1°C/W (III).3 to 0.5 1.1 to 0. silicon grease used (θ(i) + θ(c)) = 0.4 to 0.18 Channel Temperature Tch and Power Dissipation PD Rev.5 — — 45 0.3 to 0.5 to 2.5 1.5 to 0.5°C/W Power dissipation PD(M) characteristic of power MOS FET PD(M) = on-resistance loss + switching loss 42. (II).5 Based on these preconditions.0°C/W.5 to 2.6 1. and the point of intersection at which functions (1) and (2) overlap is taken as the channel temperature in the saturation state to be found.3 0. 2.6 2.0 to 6.2004 Page 25 of 49 REJ05G0001-0200 . Reference value With silicon grease No silicon grease With silicon grease No silicon grease DPAK TO-220AB LDPAK Package TO-220FM TO-3P TO-3PFM TO-3PL Tj max – Tc Rth(ch-c) = Pch 178 80 0.0 to 2. (III).5°C/W (3) Mounting method: Insulating mica used.3 to 0.8°C/W where θ(i): Insulating mica thermal resistance θ(c): Contact thermal resistance Table 2.7 1.18.0 (See individual catalog for Pch(W)) 83.4 D B (III) 30 E 20 A I D = 10 C 2 10 I D = 8A A 0 10 1 for three types of heat PD(f) = θ(ch-a) sink θ(f) at Ta = 50°C 50 100 (120) 150 Channel Temperature Tch (°C) Allowable dissipation characteristic PD(f) Tch – Ta Figure 2.5 to 0.23.5 0. Power MOS FET Destruction Mechanisms and Countermeasures (2) Heat sink thermal resistance θf-a: 3 kinds: (I).0 — — 55 0.34°C/W Power Dissipation PD (W) (I).0 — — 62. 1. 50 θ(ch-a) = θ(ch-c) + θ(i) + θ(c) + θ(f) = 1.5 to 2.5 1.04 + 0.0 42 0.0 to 1.8 2.0 to 2.5°C/W (II).2 Thermal Resistance of Various Transistor Packages Thermal Resistance Rth(ch-c) (°C/W) Rth(c-a) (Rth(i) + Rth(c)) (°C/W) *1 (°C/W) No insulation plate Mica insertion (t = 50 to 100µm) Note: 1.0 2.7 (I) (II) 40 The target is a design for Tch ≤ 120°C 21.00 Aug.5 to 0.0 to 3. allowable power dissipation characteristics under various heat radiation conditions (1) and the power dissipation PD characteristic according to a rise in the power MOS FET channel temperature (2) are calculated.5 4.5 — — 0.1 to 0. 0. θ(f) = 1.

34) Calculation can be performed for the 2 conditions (II) and (III) in the same way.0 22.Power MOS FET 2.4 14. PD(f) = Tch – Ta ………………………………………(2) θ(ch-a) Under condition (I). 150°C gives 0W. 100.6 30. (III) = 3.0 17.09 9.5 = 2. plot allowable loss characteristic (1) under each heat radiation condition. First. power MOS FET on-resistance temperature coefficient α (coefficient when Tch = 25°C is taken as 1.18 is created. power MOS FET power dissipation (at Id = 8 A. the graph of channel temperature Tch vs power dissipation PD in figure 2.7 W respectively (≈ (150 – 50)/2.8 37.8 + 0. L load Ron loss.73 14. there is a curvilinear rise (as shown in individual catalogs) as Tch rises.0 25.3 5 18. 10 A) calculated in table 4 is drawn. As ambient temperature Ta = 50°C has been assumed.1 5 16.5 5 ID = 8A ID = 10A 13. taking this point into consideration.7 5 14. assuming Tch = 50.34°C/W) Allowable power dissipation PD(f) is expressed by equation (2).9 28.6 5 24. With reference to the contents of the box below.6 35.4 W.3 27 5 22.6 150 2. Rev.2004 Page 26 of 49 REJ05G0001-0200 . 10A is found. Table 2. θ(ch-a) when using (I) heat sink is as follows: θ(ch-a) = 1.0) can be read beforehand from the Ron-Tc characteristic of the individual data sheet.7 60 1. 4. When power MOS FET total power dissipation PD(M) accompanying the temperature rise when ID = 8A. and that value entered on the horizontal axis as in table 2. Three points can be used for the allowable loss curve. That is to say.5 40 1.23.1 80 1.64 13. Power MOS FET Destruction Mechanisms and Countermeasures The procedure to reach figure 2.2.0 ID = 8A ID = 10A 8.3. 21. and individual allowable loss characteristics can be drawn for the use of 3 kinds of heat sinks.0 17.4 19.34°C/W (Similarly for (II) = 2.0 20.5 100 1.3 shows the calculation results.27 11. θ(ch-a) = θ(ch-c) + (θ(i) + θ(c)) + θ(f) ………………(1) From equation (1).0 140 2.9 23.00 Aug. • Calculate and plot allowable power dissipation straight line PD(f) under each heat radiation condition ((1) in figure) First. SW loss Notes See Ron-Tc characteristic in individual data sheet Note RDS(on) temperature dependence Switching loss *1 PS = tf · P(tf) T Total power dissipation PD(M) PD(M) = PON + PS Note: 1. In the calculation of power MOS FET power dissipation PD. • Calculate and plot power MOS FET power dissipation curve PD(M) ((2) in figure) Power MOS FET on-resistance RDS(on) has a positive temperature characteristic.18 is described below.27 19. In this way. find total thermal resistance θ(ch-a) under each heat radiation condition. Table 2. the same PS value is used for both ID = 8 A and 10 A.4 120 2. Next. and 3 straight lines plotted.5 5 25. allowable power dissipation characteristics under the aforementioned various heat radiation conditions (1) and the power MOS FET power dissipation characteristic (2) are calculated.5 13.4 5 19.04 + 0. 42. 2 curves can be drawn. taking Tch = 50°C as the zero point (as Tch = 50°C is 0 W).84°C/W.6 18. completing the process.3 Item RDS(on) temperature coefficient α for Tch = 25°C MOS On-resistance loss power PON = ID2 · RDS(on)max dissipation × α · tON T Calculation of Power MOS FET Power Dissipation PD(M) (Example of 2SK1170) Tch(°C) 25 1.8 32.3 32. For the sake of simplicity.41 20.5 Note operating frequency dependence See separate section for detailed calculation of R. 3.

use the transient thermal resistance θch-(t) to calculate the line indicating allowable power dissipation PD(f)(t) Under transient conditions.19 gives further information on the method of use and points for attention concerning figure 2. the following points (combinations). (c) Also.4 and 2.(K). with high-speed operation (f = 100 kHz or higher).2004 Page 27 of 49 REJ05G0001-0200 . When the applied voltage is transient. Note: 1.18. (Points (C) and (D)) (b) When point-of-intersection channel temperature Tch is 150°C or above.5 show power MOS FET loss calculation equations and calculation methods. (Design target Tch is satisfied by (C) and (D). as with the heat sink (III) condition. 6. Power MOS FET Destruction Mechanisms and Countermeasures 5.19 Relationship between Channel Temperature Tch and Power Dissipation PD Rev. move dissipation line (2) horizontally so that point (A) is at Tc and Tch(x) of (F) and (G) at Tc(x) can then be obtained. 10 A 0 10 Thermal equilibrium(with heat sink) Allowable dissipation characteristic PD(f) Tch – Ta for three types of heat PD(f) = θ(ch-a) sink θ(f) at Ta = 50°C 50 100 (120) 150 Channel Temperature Tch (°C) Figure 2. However.2.and (L) are all under 60°C while PW≤10ms even at ID = 10A. the maximum rating is exceeded. Tch rise Ron increase Loss increase Tch rise and thermal destruction • Provision for design value Tch ≤ 120°C (a) Operating current ID is made 8 A max and heat radiation condition (I) or (II) is applied. • Considering Tch-PD graph results (a) Points of intersection (B). Example: TO-3P/2SK1170 → TO-3PL/2SK1629 3) Change MOS FET to a one class higher low-on-resistance component. Tables 2. •Check that there are no metallic particles between the insulating plate and the heat sink (prevent short-circuits between the device and heat sink fins after heating). Figure 2.) (b) In case of use up to operating current ID = 10 A max. 1) Use a heat sink with smaller thermal resistance than (I). the only conditions that satisfy target design Tch ≤ 120°C are ID = 8 A heat radiation conditions (I) and (II). crossing-points (H). The way of interpreting figure 2. etc.) 2) Lower θ(ch-c) by changing the component package. this means that thermal runaway*1 occurs and destruction results. switching loss P(tf) must also be considered (as there is generally a trade-off between on-resistance Ron and switching time tf).23.20 show the calculation method for peak channel temperature Tch(peak) and thermal resistance θchc(PW/T) in repeat operation. use the following equation: Tch = Tc + θch-c · PD(M) Measure the temperature at thermal equilibrium. In the diagram. 50 Power Dissipation PD (W) PW = 10ms PW = 1ms 3 thermal status PD(f)(t) = Tch – Ta θch-c(t) Transient 40 Thermal equilibrium (infinity heat sink) Tch – Ta PD(f) = θch-c The target is design for Tch≤120°C 2 (I) (II) (III) B When calculating channel temperature Tch from a directly measured temperature Tc of the casing of the MOS FET.18 (considering the calculation results) and appropriate measures are described below. (D). 30 Total power dissipation PD(M) of power MOS FET G L K J H F D C E 20 A I D = 10 8A ID = 1 •Check that the surface of the casing of the device is in contact completely with the surface of the heat sink (minimize contact thermal resistance). Figure 2. (C).(J).Power MOS FET 2. when both loss characteristic points of intersection are absent. •Check that there are no heat sources around the device (prevent a rise in Ta).. and (E) represent channel temperature Tch in a state of thermal equilibrium under the respective conditions.00 Aug. (Improve heat radiation conditions and lower θ(cha). That is to say. should be considered and a review conducted.

2. Power MOS FET Destruction Mechanisms and Countermeasures (4) Power MOS FET loss calculation Table 2. Inductance L load Vds Ia tr ton tf Vds(p) 1 2 tr period Ptr ton period Pton Solid line Dashed line [Much smaller than item 2 or 3 and can be ignored.4 Power MOS FET Loss Calculation Category Resistance R load Operating Waveform tr Vds Id ton tf No. Pton = Pton = Ptf = 1 ton (Ia2 + Ia ⋅ Ib + Ib2) Ron ⋅ α 3 T 1 2 ton Ib ⋅ Ron ⋅ α ⋅ 3 T Ib Id 0 t T 3 tf period Ptf 1 tf Vds(p) ⋅ Ib ⋅ 2 T Note: 1. α: Ron thermal coefficient (= T(×°C)/T (25°C)) (5) Examples of power MOS FET loss calculation (for reference) Table 2. 1 Operation Period tr period Ptr Average Loss Calculation Ptr = 1 tr (Vds ⋅ Id + 2Id2 ⋅ Ron ⋅ α) 6 T Smaller than term 1 and can be ignored. 2 0 t T ton period Pton tf period Ptf Pton = Id2 ⋅ Ron ⋅ α ⋅ ton T 3 Ptf = 1 tf (Vds ⋅ Id + 2Id2 ⋅ Ron ⋅ α) 6 T Smaller than term 1 and can be ignored.5 Examples of Power MOS FET Loss Calculation (for Reference) Category Resistance R load Ptf loss during tf period Operating Waveform tr Vds Id ton tf Loss Calculation (Ron thermal coefficient α omitted) Ptf = = = 1 tf ∫ Vds(t) ⋅ Id(t) dt T 0 1 tf ∫ T 0 1 tf ∫ T 0 1 T {( {( Vds – Id ⋅ Ron tf ) t + Id ⋅ Ron }( – Id t + Id dt tf ) Id2 ⋅ Ron – Id ⋅ Vds 2 Id ⋅ Vds – 2Id2 ⋅ Ron t + t + Id2 ⋅ Ron dt tf2 tf 0 t T = [( Id ⋅ Vds – 2Id ⋅ Ron 2 Id ⋅ Ron – Id ⋅ Vds 3 t + Id2 ⋅ Ron ⋅ t t + 3tf2 2tf 2 ) ( ) ( ) 2 ) } ] tf 0 1 1 tf ∴ Ptf = tf(Vds ⋅ Id + 2Id2 ⋅ Ron) ≈ Vds ⋅ Id 6T 6 T Inductance L load Pton loss during ton period (Current is indicated by solid line) tr ton tf Vds(p) Pton = = = = 1 ton 2 ∫ Id (t) ⋅ Ron dt T 0 1 ton Ib – Ia ∫ t + Ia T 0 ton 1 ton ∫ T 0 1 T Vds Ia Id 0 Ib ( {( ) 2 ⋅ Ron dt Ib – Ia Ia2 – 2Ia ⋅ Ib + Ib2 2 t +2 t ⋅ Ia + Ia2 Ron dt ton ton2 ) ( t T [{( Ia ⋅ Ib – Ia Id ⋅ Ron – Id ⋅ Vds 3 t + 3tf2 ton 2 ) ( 2 ) } ) } ] t2 + Ia2 ⋅ t Ron ton 0 1 ton ∴ Pton = (Ia2 + Ia ⋅ Ib + Ib2) Ron 3 T Rev.00 Aug.Power MOS FET 2.23.2004 Page 28 of 49 REJ05G0001-0200 .

AP3-HF (internal high-speed diode). this destruction problem almost never occurs as the voltage used is also low. Power MOS FET Destruction Mechanisms and Countermeasures (6) Repetition frequency Tch(peak).2.20 Repetition Frequency Tch(peak).4. It is limited to use in DC/AC inverters utilized in motor control. but in recent years the destruction mechanism has been clarified.23. From an application standpoint. θch-c is a dc thermal resistance. uninterruptible power supply (UPS). and component diode destruction resistance has been improved. With most 250 to 600 V high-withstand-voltage AP3-H. Internal diode destruction occurs only in the above uses. Rev.00 Aug. and similar H bridge circuits. thermal resistance θch-c(PW/T) for a pulse of width t = PW and perioed of one repetition T is given by equation (6): n n + 1– γs(PW) …………………………………………(6) 100 100 Here.4 2. and applies especially to components with a withstand voltage of 250 V or above used at high voltages. Thermal Resistance θch-c(PW/T) Tch(peak) = Tc + ∆Tch = Tc + Pd PW T { PW PW θch-c + 1 – θch-c(PW) ……………(1) T T ( ) } ( ) = Tch(peak) – Tc = ∆Tch …………………………………………………(2) θch-c Pd Pd From equations (1) and (2): ( ) = θch-c θch-c PW T { PW PW θch-c(PW) + 1– θch-c T T ( ) } ……………………………………(3) (PW) Normalized transient γs(PW) = θch-c thermal resistance θch-c ………………………………………………(4) ……………………………(5) Repetition ducy cycle n(%) = PW × 100 T From equations (4) and (5).2004 Page 29 of 49 REJ05G0001-0200 . θch-c ( ) = θch-c PW T { ( ) } 2. the AP3-H and AP5-HF series are recommended for these uses. With components with a low withstand voltage of 100 V or below.1 Internal Diode Destruction Explanation of Internal Diode Destruction Internal diode destruction is a destruction mode that occurs when the parasitic diode between the drain and source of a power MOS FET is used actively.Power MOS FET 2. thermal resistance θch-c(PW/T) Channel Temperature Tch (°C) Tj(peak) ∆Tch(p) ∆Tch(AV) Tc Case temperature Tc ∆Tch PW Loss Pd (W) Pd 0 0 Time t (s) Time t (s) Figure 2. destruction countermeasures are incorporated into the component design. and AP4-H series products.

When Q1 is turned on again in this state.23.Power MOS FET 2. and is also called a parasitic diode. motor inductance L regenerative current IF flows through the Q2 internal diode.22 shows the structure and equivalent circuit of a power MOS FET. Source Gate RDS(on) Cgd rg P N– N++ D Body Diode Cds Rb Parasitic Bipolar Transistor N+ G Cgs Drain Device Structure (N-Channel Example) S Power MOS FET Equivalent Circuit Figure 2. Power MOS FET Destruction Mechanisms and Countermeasures Figure 2. As shown in this figure. an internal diode is formed between the source and drain structurally. In this circuit. short-circuit current irr flows and recovers. in this period Q1 and Q2 enter the conduction state. Q1 and Q4 operate and PWM control is performed by the Q1 component. due to the influence of Q2 internal diode reverse recovery time trr.2004 Page 30 of 49 REJ05G0001-0200 . When Q1 current ID1 flows and is then turned off.22 Power MOS FET Component Structure and Equivalent Circuit Rev.21 shows an inverter circuit using general power MOS FETs and the power MOS FET operation waveform in a full bridge circuit.00 Aug.21 Power MOS FET Operation in Full Bridge Figure 2.2. Q4 is always on during the Q1 PWM control period. Input signal(voltage) PWM control Q1 waveform ID1 0 VDS1 0 Irr Current flowing through Q2 diode (current during recirculation) IF 0 Irr VDS2 (3) Current during period trr Q2 IF (2) Current during recovery ID1 Q1 VDD (1) Current during forward rotation Q3 M Input signal(voltage) Q4 0 Figure 2. and at the same time the internal diode voltage (VDS) also recovers.

23. and this makes the parasitic bipolar transistor between the drain and the source turn on in part of the cells around the gate or source electrode and may lead to destruction of the diode. Increase gate resistance Rg of the MOS on the PWM control side to reduce di/dt when the diode is short-circuited. Power MOS FET Destruction Mechanisms and Countermeasures Figure 2. Reduce the wiring inductance of the circuit to reduce dV/dt and the voltage spike during diode recovery.2004 Page 31 of 49 REJ05G0001-0200 .24 shows examples of internal diode destruction circuit countermeasures (usage precautions). trr Cgd rg G Cgs Cds iF 0 di/dt Rb iBip A VDD dV/dt 0 t B irr If di/dt changes sharply during the reverse recovery of diode. and to reduce irr (thus reducing dV/dt) 2. internal diode destruction resistance has improved considerably.00 Aug. an excess recovery current flows and dV/dt rises sharply during the reverse recovery period (period B). When the damaged product is disassembled and examined. parasitic PNP transistors have lower carrier mobility and a lower hfe than NPN transistors. VDD 1. As stated earlier. Destruction occurs while the diode voltage is recovering.23 Internal Diode Destruction Mechanism 2. 3. IF Action 1 Rg Action 2 Thicken wiring NG: Before preventive action OK: After preventive action M Action 3 VDS CR snubber (Between D-S) Figure 2. traces of the destruction are visible around the gate or source electrode.2. so that the problem of destruction almost never occurs during normal use. and structural measures have been taken to inhibit parasitic bipolar transistor operation. the PNP transistors do not turn on as easily and destruction more seldom occurs.4.24 Examples of Internal Diode Destruction Circuit Countermeasures Rev.23 shows the internal diode destruction mechanism.Power MOS FET 2. In P-channel products. D RDS(on) Built-in diode iMOS S irr Figure 2. Therefore.2 Example of Internal Diode Destruction Circuit Countermeasures Figure 2. Insert a snubber circuit to reduce dV/dt and the voltage spike during diode recovery.

Figure 2.25 shows actual data before and after countermeasures for internal diode destruction resistance of 500 V highwithstand-voltage components (now discontinued).00 Aug.1 Destruction Due to Parasitic Oscillation Explanation of Destruction Due to Parasitic Oscillation Gate parasitic oscillation mainly occurs when power MOS FETs are connected in parallel and are directly connected without inserting a gate resistance. AP4-H AP2 series (Bfter preventive action) Test conditions: •VCC = 350 V •VGS = +15V. This parasitic oscillation occurs in a resonant circuit formed by gate-drain capacitance Cgd(Crss) and gate lead inductance Lg when the drain-source voltage is turned on and off at high speed. or the oscillation voltage when the drain-source voltage is turned on and off is superimposed on the Vgs waveform via gate-drain capacitance Cgd and positive feedback occurs. an oscillation voltage much larger than drive voltage Vgs(in) is generated in Vgs between the gate and source. Power MOS FET Destruction Mechanisms and Countermeasures Figure 2. When the resonance condition (ωL = 1/ωC) occurs.5.2004 Page 32 of 49 REJ05G0001-0200 .23. leading to oscillation destruction due to mal operation. AP3/AP5-HF series (high-speed diode included) Internal Diode Destruction Current IF (A) After preventive action AP3-H. Check the waveform in the actual application. –10V •PW = 10µs(1shot) •Tc = 25°C 5 10 20 400 50 100 di/dt (A/µs) 800 1000 2500 3500 dV/dt (V/µs) 200 500 1000 5000 6000 20 10 1k 470 330 100 56 Gate Resistance Rg (Ω) Note: The relationship between gate resistance Rg and di/dt or dV/dt depends on the voltage used and the wiring inductance of the application system.25 Internal Diode Destruction Resistance (500 V/10 A Class Examples) 2.5 2. Rev.2.Power MOS FET 2. as a result of which gate destruction occurs due to a voltage exceeding the gate-source rated voltage.

and therefore the inductance effect is more intense toward the center of the conductor. Generally. and not through the inner part. oscillation voltage Vds(p) passes through gate-drain capacitance Cgd(Crss) due to load wiring inductance Ld when the drain-source voltage is turned on and off at high speed.5. and C QVgs(p) Ld: Drain lead inductance (including wiring on the board) rg: MOS gate resistance Vc = (1/2πfC)I = (1/ωCR)V = QV ⋅⋅⋅⋅⋅⋅⋅⋅⋅(1) Rg: External gate resistance Vgs VL = (2πfL)I = (ωL/R)V = QV ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅(2) Cgs: Gate-source capacitance Cgd: Gate-drain capacitance L Cds: Drain-source capacitance Here. an inductance effect is produced. and particularly when it is turned off. Skin effect: Phenomenon whereby a high-frequency current flows only through the surface of a conductor. and parasitic oscillation is caused. Power MOS FET Destruction Mechanisms and Countermeasures Power MOS FET Parasitic Oscillation Mechanism Figure 2. and a resonant circuit with gate lead inductance Lg is formed. and therefore power MOS FET thermal stress is not a problem. With this parasitic oscillation. When a current is passed through a thick conductor that handles large currents. and as this crossing with the current. and current deviates toward the surface of the conductor. this period is an extremely short time of several ns to several tens of ns. Vds(p) D The voltage oscillation due to resonance changes in proportion to the selectivity Q(=ωL/R=1/ωCR) of the resonant circuit: voltage Vc generated at capacitance C is given by equation (1) and voltage VL generated at inductance L is given by equation (2). when a high-frequency current flows in a thick conductor. Vin Rb Ls 0 Vin R L Ld RDS(on) Cds Cgd Rb Ls Ld RDS(on) Cgd Cds Cgs Cgs C Vc = Q · Vin Lg: Gate lead inductance (including wiring on the board) G S Ls: Source lead inductance (including wiring on the board) Resonant Circuit of R. the crosssectional area through which the current flows is reduced.00 Aug. if transient current balance becomes poor when switching off. high-speed power MOS FET is extremely small. electrical resistance — that is. a magnetic flux is also generated in the conductor. but drain-source oscillation voltage Vds(p) may be logically n times greater than this or more (as Ld also appears to be larger due to the skin effect* since a high-frequency large current actually flows in a transition).26 shows a parallel equivalent circuit. L.2 2. As gate internal resistance rg of a large-current. and when the resonance condition occurs. when there is no gate external resistance Rg.2. When current flows in a conductor. as large-current operation is performed in the case of parallel connection. Consequently.25 Power MOS FET Parasitic Oscillation Mechanism When power MOS FET parallel connection is performed by means of direct connection without using a gate series resistance. In this case. Rev. a parasitic oscillation waveform appears in the gate. between the MOS gate and source). oscillation circuit Q — that is √L/C/R — becomes large. and thus viewed from outside.Power MOS FET 2. In particular. making it difficult for current to pass through. at 1 to 2 Ω. inductance — appears to be large. a magnetic flux is generated around the current. Q = ωL/R = 1/ωCR = C R Power MOSFET Equivalent Circuit Resonance frequency fr = 1 2π LC T f = 1/T Vin: Supplied I voltage Figure 2.2004 Page 33 of 49 REJ05G0001-0200 . a large oscillation voltage is generated between that point and Cgd(Crss) or Lg (that is to say.23. there is a strong inductance effect in the central part. all the currents flow in one MOS FET in a period with deviation of this timing.

7Ω Vout Drive circuit A Drive circuit B R2 R1 R1 Thicken the wiring along large current paths to reduce the wiring inductance.23. and advice on the selection and use of power MOS FET components. Reference value: R1 = 10Ω to 100Ω R2 = 2.00 Aug. 2. in particular.6 Notes on Parallel Connection Notes on mounting covering precautions concerning parallel connection.27 Parasitic Oscillation Reduction and Destruction Countermeasures 2. • Pay attention to parasitic oscillation (see attachment on parasitic oscillation countermeasures) 2. ⇒ ⇒ ⇒ Off-time transient current balance reduction On current balance reduction Heat radiation balance reduction Align Vth(VGS(off)) value (higher value preferable) Align on-resistance RDS(on) Apply adequate gate drive voltage (4 V drive product: VGS = 5 to 10 V.6. If the gate wiring becomes long and is connected in parallel. Vin L R1 R1 R2 R1 R1 R1 R1 Gate and source drive circuit wiring taken from vicinity of source terminal.1 Notes on Mounting • Low-inductance wiring • Make drain and source wiring lengths equal.Power MOS FET 2.27 shows parasitic oscillation and destruction countermeasures in the case of parallel connection. Figure 2. In case of high-frequency operation. Insert series resistance R1 near each gate terminal. Insert a ferrite bead in series with each gate. 10 V drive product: VGS = 10 to 12 V) Avoid avalanche operation as far as possible ⇒ Current concentration in low-withstand-voltage components Rev. are given below. etc.2.2004 Page 34 of 49 REJ05G0001-0200 . Use twisted-pair wires for power-supply lines between the drain and the source.6.2 Advice on Selection and Use of Power MOS FETs Discussion and agreement with the semiconductor manufacturer are necessary. use of mounting with drive wiring inductance made small. Power MOS FET Destruction Mechanisms and Countermeasures Figure 2.2Ω to 4. insert an additional resistor R2. and use twisted-pair wiring.

is applied to a gate.Power MOS FET 2.. shorting between the drain and source. Rev. the gate oxide film is destroyed when static electricity or a surge voltage generated by a human body. (1) Earth human bodies via a 1 MΩ resistance before handling devices.2.7.7 2.1 2.00 Aug.2 Electrostatic Destruction Countermeasures Figure 2.28 Electrostatic Destruction Countermeasures In electrostatic destruction.2004 Page 35 of 49 REJ05G0001-0200 . or increased leakage current. Power MOS FET Destruction Mechanisms and Countermeasures Electrostatic Destruction Explanation of Electrostatic Destruction Electrostatic destruction refers to destruction due to static electricity or a surge voltage from a human body or equipment when a product is handled or is being mounted. insert a gate resistance and Zener diode.) The following three methods are used as countermeasures to electrostatic destruction.7.23. (2) Ensure that equipment is properly earthed.28 shows countermeasures against electrostatic destruction. (See figure 2. Action 1 Action 2 Gate resistance 1MΩ Ground the body Zener diode Zener diode Better result Action 3 Gate resistance Figure 2. mounting equipment. Characteristics seen after destruction are a voltage drop or shorting between the gate and source. etc. (3) To prevent the application of gate surge voltages that may occur after board mounting.29. 2.

The system will not operate.23. and a curve shape of standing to reverse voltage is keeping although leakage current IDSS between the drain and source is large at several hundred mA to several tens of mA. The system operates. ASO destruction of the product Figure 2. and their respective natures are illustrated if the respective destruction products maybe adopted to a set circuit.7. RDS(on) rises. there is almost complete shorting between the gate and source and between the drain and source.29.29 Destruction Progression Modes after Electrostatic Destruction Figure 2. Power MOS FET Destruction Mechanisms and Countermeasures Destruction Progression Modes after Electrostatic Destruction In figure 2. Damaged product A Between gate and source: short-circuit Between drain and source: short-circuit Electrostatic destruction Damaged product B Between gate and source: decrease in impedance (several hundred Ω to several kΩ) Between drain and source: increase in current leakage The product operates as MOS FET. (high-voltage 500V product with gate protection diode) Gate Current Laekage IGSS (µA) + Damaged product A (complete short-circuit) Good product Damaged product B Decreased impedance between G and S 0 [Scale] ID: 2mA/DIV VDSS: 100V/DIV Drain Current ID (mA) Damaged product A (complete short-circuit) Damaged product B Increased current leakage IDSS channel waveform Good product – [Scale] IGSS: 1µA/DIV VGSS: 10V/DIV – + Gate-Source Voltage VGSS (V) VGSS Waveform Drain-Source Voltage VDSS (V) VDSS Waveform Figure 2.30 illustrates the characteristic modes of destruction products A and B.3 2. In the destruction product B mode. In the destruction product A mode. although a certain level of resistance (several tens of Ω or more) is maintained between the gate and source. post-gate-destruction characteristic modes are broadly classified into two kinds.00 Aug.30 Sample Electrostatic Destruction Product VGSS and VDSS Waveforms Rev. The product will not operate as MOS FET.2. Operation continues with a reduced gate impedance.Power MOS FET 2.2004 Page 36 of 49 REJ05G0001-0200 . More heat is generated in MOS FET.

and on-duty D = 0.3. as gate-source resistance value RGS of this destroyed product may well decrease further.7. the component operates adequately. As the gate impedance decreases. a voltage with drive capability is applied between the gate and source. switching operation is performed.2004 Page 37 of 49 REJ05G0001-0200 .2V 22 + 100 RS + RGS Poff = VDD × IDSS × (1 – D) = 24 × 1 × 10–3 × 0. Rev. and eventually component ASO destruction occurs. However. Therefore.2 V and Poff = 16. VGS = RGS 100 × Vin = × 10 ≈ 8.31). a short-circuit current flows between the MOS FET gate and source when power is turned on. and power consumption increases.4 2. When a mode such as the destruction product B mode is temporarily adopted to a set circuit. and generally. so that although drive voltage VGS appears to fall. care must be taken in handling (including component measurement) up to embedding in a circuit. and operation is performed in a state in which VDS(on) has increased as shown in figure 2. VDS(on) increases. when the actual gate drive voltage VGS and off-time power consumption Poff of this component are calculated. in that process gate drive voltage VGS becomes insufficient. This state is illustrated in figure 2.00 Aug. then the loss increases. VGS = Vin when RGS>>RS Figure 2.01 10 RGS VGS = R + R × Vin S GS In the normal product. gate input voltage Vin = 10 V. since drain-source withstand voltage is maintained (although when leakage current IDSS is large. and destruction traces increase. In a case such as this. VGS = 8.8mW However. RGS ≈ ∞. on-resistance increases (a complete on-resistance operation onstate is not established.8 mW as shown below.2. gate signal source resistance RS = 22 Ω. according to the circuit gate signal source resistance RS constant and gate-source resistance RGS immediately after destruction. for example. but it is possible that the destruction mode constituting the initial trigger was a gate destruction mode. the circuit naturally does not operate. therefore.7 = 16. and 10 finally destruction occurs.Power MOS FET 2. 25 Drain-Source On-Voltage VDS(on) (V) 20 Operating Current ID (A) Destruction 1 All ow ab le (w loss ith he when at sin mou k) nte d 15 ID = 1A Non-saturation region(large loss) 10 Saturation region for on-resistance (low loss) 0. As a result.31. in the case of a logic-level drive component. Power MOS FET Destruction Mechanisms and Countermeasures Mechanism whereby Gate Destruction Product B Come to ASO Destruction When the destruction product A mode is temporarily incorporated in a set circuit. it is extremely difficult to determine whether it is the latter case or not by destroyed product because destruction traces have increased. power consumption increases in the off state and causes a rise in component temperature).23. a destroyed product B mode gate destruction sample with gate-source resistance value RGS = 100 Ω immediately after gate destruction and drain-source leakage current IDSS = 1 mA is temporarily incorporated in an operating circuit with power supply voltage VDD = 24 V.31 Mechanism whereby Gate Destruction Product B Reaches ASO Destruction When.1 5 Ta = 25°C 0 0 2 4 6 8 Gate Driving Voltage VGS (V) 10 30 100 300 1000 Operating Voltage VDS (V) RGS: G-S resistance of product B with its gate damaged RS: Signal source resistance (external) of the circuit Vin: Gate input voltage 0. at the very least. subsequent analysis of the destroyed product shows a close resemblance to thermal destruction due to exceeding of the component ASO.

In figure 2. reducing total loss by optimization in a gate drive voltage VGS range of 5 to 8 V is effective in achieving higher efficiency.2004 Page 38 of 49 REJ05G0001-0200 .Power MOS FET 2.8. te t 50k 100k 200k 500k 1M Operating Frequency f (Hz) 2M Gat 10 eC ha rge 20 Am ou VD 24V S 8 =1 0V 4 0 0 Ga nt Q30 g ( 0 nC) 4 0 Figure 2. applying a gate drive voltage VGS of around 10 V is effective from a total loss standpoint. This figure shows the upper P-channel MOS FET in the off state and the lower N-channel MOS FET in a chopping operating state. it is necessary to achieve a balance with onresistance loss by appropriately setting and controlling the gate drive voltage in the high-frequency region.33.00 Aug. and applicable countermeasures. but as the lower N-channel MOS FET is now turned on and VDD changes to 0 V.0 MOSFET Loss P (W) 1.32 shows “power MOS FET main loss frequency dependence and relationship to main characteristics” in the case of use in a DC-DC converter.2.8 2. the upper and lower components go to the on state simultaneously. DC/DC Converter Example of HAT2064R (Calculated Values) Vin = 5V. Vout = 1.33 illustrates arm shorting in a small motor drive application. and excessively large loss is caused. VGS = 15 to 17 V) is not really recommendable as drive loss only increases.23. Applying a higher voltage (for example. In order to make full use of component performance and reduce total loss.2 Malfunction (Arm Shorting) Countermeasures in Motor Application Figure 2.5 Drive loss 16 Qg = 20nC (V 40nC 20 ID 0A =1 On-Resistance R DS(on) (mΩ) 1. in order to minimize on-resistance.32 Power MOS FET Main Loss Frequency Dependence and Relationship to Main Characteristics 2. When this ∆VGS(t) peak voltage exceeds Vth of the P-channel MOS FET. lt Vo 4 urce total loss is reduced by means of gate drive voltage So o VGS optimization.5 Qg = (V GS = 15 GS = 4 10V . when P-channel and N-channel MOS FETs are used in combination. a charge current flows transiently via Crss and Ciss of the upper P-channel MOS FET. an arm short-circuit current flows. and a ∆VGS(t) = {Crss/(Ciss+Crss)}∆VDS(t) peak voltage is generated between the gate and source.6V ID = 10A High Side Relationship between Loss and Main Characteristics 2. At high-frequency operation of f = 500 kHz or more. Switching loss and drive loss increase at higher frequencies.5V) ) 12 10 On-resistance loss 5 0 10k 20k 12 (V) S 8 age VG In the high-frequency region (500 kHz or above).8.1 2. Power MOS FET Destruction Mechanisms and Countermeasures Usage Notes Power MOS FET Main Loss Frequency Dependence and Relationship to Main Characteristics Figure 3. the voltage waveform at point A is as shown in the figure.0 Switching loss 0. when a logic-level drive component is operated at operating frequency f = 200 to 300 kHz or below. Rev. In general.

1.2. 1.2004 Page 39 of 49 REJ05G0001-0200 . 3. and set low impedance between the gate and source. 2. the other arm is also similarly susceptible to the occurrence of this phenomenon with an N-channel component. More likely to occur the faster the switching operation (especially turn-on time) and the steeper dV/dt 2. Power MOS FET Destruction Mechanisms and Countermeasures In the case of use in an H bridge circuit. select an component with a small KS and high Vth. item 4. M Nch PWM signal R1 Make resistance R1 large and suppress dv/dt at point A. power supply voltage VDD is determined by the application and cannot be changed. Nch Figure 2. make (KS = {Crss/(Ciss+C1+Crss)}VDD smaller.00 Aug. Slow the turn-on time to suppress dV/dt (make gate resistance R1 in the figure larger).23. Make gate off-time signal source resistance RG (MOS FET driver signal source resistance RS and off-time external resistance constant Rg) smaller. The upper/lower component shorting phenomenon at the time of this transition is liable to occur under the following conditions. Insert capacitance C1 between the gate and source.Power MOS FET 2. and insert C1 between G-S if necessary. More likely to occur the higher power supply voltage VDD Of items 1 to 4. and provide a margin. so countermeasures are shown for remaining items 1 to 3. VDD Vgs(t) Shortcircuit current Pch •Sample Preventive Action VDD Ciss R2 C1 Vgs(t) VDD Crss R3 Pch Voltage at point A VDD 0 Current ID 0 Input signal VGS 0 PWM control (f = 20kHz or more) Shortcircuit current Point A dv/dt M Id Set a lowish resistance value that does not compromise switching loss (efficiency). Also. More likely to occur the larger the Crss/Ciss values of the components used (KS = {Crss/(Ciss+Crss)} · VDD is a larger value than Vth of the component) 4. More likely to occur the larger signal source resistance RG (gate off-time constant) 3.33 Malfunction (Arm Shorting) Countermeasures In Motor Application Rev.

10ns) T PWM Control IC Vout Crss M Hi-Side VGS (5V/DIV) Ch1 Ch3 Math 10. due to the design emphasizing high speed.Power MOS FET 2. and Q2. it is necessary to make both Ciss and Crss smaller in component design for high-frequency operation (1 MHz or above) and also make improvements that take account of the ratio of Ciss and Crss (Crss<<Ciss). •Smaller.0V Ch2 2.00 Aug.0V 40. Insert a capacitance C externally between the gate and source of the low-side component and (by making (KS = (Crss/Ciss + Crss) smaller) improve the self-turn-on margin. the following two circuit countermeasures can be used. Regarding the low-side component characteristics. Make only the high-side component turn-on time slower (suppress dV/dt). Crss) increase Conditions susceptible to self-turn-on (Both component and circuit) Vout PW = Vin T Vin Hi-Side Q1 dV/dt Lo-Side VGS (2V/DIV) VDS: 10V/DIV VGS: 5V. This phenomenon occurs at the switching timing at which high-side component Q1 is turned on while low-side component Q2 is off.0V M 40. and therefore there is a tendency for the capacitance relationship (Ciss. is turned on. Ciss is charged via Crss of Q2.0ns T 50. due to large-current operation.23. As a future trend.8.3 2. 2. Figure 3.00V 5. Also.34 illustrates the low-side self-turn-on phenomenon in a non-isolated synchronous rectification circuit.00V 10.34 Problems in Synchronous Rectification Circuit Rev. when VGS(Q2) = (Crss/Ciss + Crss) × dV(t) (equation (1)) exceeds Vth of Q2.40% Ciss Lo-Side Q2 Crss VGS(Q2) = Ciss + Crss dVds(t) t: 40ns/DIV Self-Turn-On Waveform • Lower impedance when gate is off • Reduced wiring inductance Figure 2. self-turn-on occurs. As a result. That is to say. thinner →higher frequency •Lower-voltage CPU core Tek stoppage Narrow pulse control from hi-side Lo-side large-current operation (lower Ron) Self-turn-on Hi-Side VDS Hi-side component high-speed Hi-dV/dt control Lo-side component capacitance (Ciss. and when the Q2 drain-source voltage changes abruptly from VDS ≈ 0 to VDS = Vin.2. Q1 and Q2 become on simultaneously. 1. Regarding the high-side component characteristics. it is necessary not only to implement component improvements.0ns A Ch1 20. This suggests a tendency of susceptibility to the self-turn-on phenomenon. but also to make the impedance between the gate and source when Q2 is off (RS + jωLS) as small as possible from the circuit design and mounting standpoints (since the above VGS(Q2) expression essentially holds true when (RS + jωLS) >> 1/jωCiss). and dV/dt becomes steeper. Generally. and component performance can be fully exploited by means of these techniques. high-speed switching characteristics are implemented. leading to degradation of efficiency. Power MOS FET Destruction Mechanisms and Countermeasures Non-Isolated Synchronous Rectification Converter Low-Side Self-Turn-On Phenomenon In appearance. low RDS(on) design is necessary.2004 Page 40 of 49 REJ05G0001-0200 . Crss) to be large. and excessive loss is generated. this is similar to the above-described arm shorting phenomenon. component heat radiation and a temperature rise are caused.2V/DIV Lo-Side VDS 1 2 Self-turn-on (ts = approx. which should really be off.

23.1 Power MOS FET Applications Application Map Figure 3. 3.2.Power MOS FET Application Note 3.1 Power MOS FET and IGBT Applications Rev.1 shows a power MOS FET and IGBT application map.00 Aug.2004 Page 41 of 49 REJ05G0001-0200 . 500 IGBT 200 Starter generator systems EPS control 50 VRM 20 Airbags Ignition Engine control Solenoid drive Lamps Relay switching Step-up/Down DC/DC power supply control ABS Solenoids Pump relays Injector Drive EV 100 Automotive field UPS Inverters Drain Current ID (A) 10 DC/DC converters Power management switches 5 Discharge lamp Discharge/Boosting 2 10 SW power supplies 30 50 100 200 Drain to Source Voltage VDSS (V) 500 1000 20 Figure 3.

2.2 Sample Automobile ABS Application Figure 3.2 Technological Trends in Automotive Electrical Equipment 3.00 Aug.2004 Page 42 of 49 REJ05G0001-0200 Hydraulic Motor Typical Models 2SK2788 .) D7 Pch 100V (built-in protection and diagnostic functions) i mode Map information offer DVD Wireless access control DAD Video Radar PC HID 400V D6-H VB Motor MPU Navigation DC/DC Traffic Safety Support System Injector 100V D7-L HEV Inverter 5th Generation IGBT HEV Power Supply DC/DC Converter 500V AP5-H (Vin=160 to 400V → Vout=14V/80A) VSC 60V D7-L Small SMD ASV (Advanced Safety Vehicle) Figure 3.Power MOS FET 3.3 Sample Automobile ABS Application Rev. Power MOS FET Applications Automotive Applications Technological Trends in Automotive Electrical Equipment Figure 3.3 shows a sample automobile ABS application.23.) High output 42V Load 14V(rating) DC/DC 16V(max.2.2 illustrates technological trends in automotive electrical equipment.1 3. 80-100V MOS FET M Starter M Generator 42V(rating) 58V(max.2.) 14V Load converter 14V 80-100V MOS FET 42V 42V Battery Starter+Generator (D7-L large-current detection function included) In-Vehicle LAN Door Mirror Keyless System Thermal FET (HSOP20 etc.2 3. Typical Models 2SK3135 2SK3553 Power Supply System Fail-Safe IC Dedicated Linear IC Predriver IC Charge Pump IC Battery Control CPU Lamp Sensors Typical Models 2SK2869 2SK2926 HAT2033RJ HAT2038RJ Figure 3.

4 shows a sample automobile power steering application.4 Sample Automobile Power Steering Application 3.2.23. Power MOS FET Applications Sample Automobile Power Steering Application Steering Typical Models 2SK3163 2SK3136 2SK3418 Figure 3.00 Aug.4 Sample Automobile HID Headlamp Control Application Figure 3.2.5 Sample Automobile HID Headlamp Control Application Rev.5 shows a sample automobile HID headlamp control application.3 Figure 3.Power MOS FET 3.2. 60V NMOS Reverse Connection Prevention Circuit Power MOS FET Battery Control IC Control IC HID Control IC 200 to 250V NMOS Step-Up Power Supply Circuit 500V NMOS Discharge Control Circuit Figure 3.2004 Page 43 of 49 REJ05G0001-0200 . VB Battery Fail-Safe IC Control CPU Forward/Reverse Control Predriver IC VB Dedicated IC Hydraulic Valve Actuator Monitor Torque sensor Current sensor 3.

6 Sample Switching Power Supply Application Rev.2004 Page 44 of 49 REJ05G0001-0200 . (N+1) RAID Application Blocks MOS FET Application 500V PFC PFC+PWM 500V DC/DC Secondary-side 30 to 60V synchronous rectification 20 to 30V Hot swap VRM 20 to 30V * : Under development Server (PC. WS (workstations).Power MOS FET 3. Power MOS FET Applications Power Supply Applications Switching Power Supplies • Application equipment Network servers.00 Aug.5V Control IC HA16142 HA16158* HA16341 HA16342 5V DC/DC converter — HAT2211RP 1.6 shows a sample switching power supply application.3. Network) Built-in Schottky diode HAT2180RP 12V PWM IC (under 5V development) 2.1 3.2. RAID Figure 3.3 3.8V PFC DC/DC Secondary-side synchronous rectification Hot swap H7N0307LM × n 2SK3235 × n Vin AC PFC AUX 2SK3235 × n Main Synchronous Current Share SW Rectification Hot Swap DC/DC Secondary IC HA16342 5V Voltage Detector Primary IC HA16142 Figure 3.23.

lithium-ion battery pack overcharging protection Figure 3.7 Sample DC/DC Converter Application Rev.3V Memory Load PWM IC HAT2071R Vb HAT2219R HAT1054R 5.5V Battery Cells 1 cell 2 cells 8.2Z AC Adapter Charger PWM IC Monitoring IC HAT1048R HAT1072H FY7BCH-02F for main MOS driver Micro FET 2SJ576 2SK3289 Battery Pack Application Cellular phones (GSM.Power MOS FET 3. mini-discs Camcorders. on-board power supply secondary side.2 DC/DC Converters 3. CDMA) PDCs.5V CPU Example of Lithium-Ion Battery Overcharging Protection Circuit Use Example of Notebook PC DC/DC Converter System Use Figure 3.5V Lithium-Ion Battery Pack DC/DC Converter Power Supply Power Management Switch HAT1048R × 2 + HZM6.5V PWM IC HAT2195R × n Vb HAT2180RP 2.2004 Page 45 of 49 REJ05G0001-0200 .0V HDD CD-ROM DVD HAT2064R 2. DSCs. VCR cameras.3. DVCs Notebook PCs 2.9 cells 4 series 2 parallel 3 series 3 parallel MPU (Power Management) Vb HAT1048R Vb HAT2211RP HAT1054R 3. Power MOS FET Applications • Application equipment Notebook PCs.2.23.00 Aug. Number of MOS FETs Used TFT Backlight Power Supply AC Adapter Charger DC/DC converter Power management TFT Backlight Total Number of Li Ion DC/DC switch Power Supply MOS FETs Used 2 to 4pcs 8 to 10pcs 4 to 6pcs 1 to 2pcs 15 to 22pcs DC/DC Converter AC Adapter Power Management Switch HAT2198R × n 1.7 shows a sample DC-DC converter application.

notebook PCs.0 200 Vout 1. Vin = 12V Hi-Side PWM Control IC 3.2.6 1.8 Sample VRM Application Rev.6V CPU Lo-Side 3 Phase to 4 Phase Output Voltage Vout (V) CPU Carrier Frequency fc (GHz) Vin = 12V Multi Phase 2.5 1.5 PWM Control IC Vout 1. Power MOS FET Applications Single Phase Vout 1.3 er 1.Power MOS FET 3. WS (workstations) Figure 3.3V CPU 1.2 rri Ca U Hz) PU CP (G High End C fc u eq en Iout 1. network servers.0 150 100 Iout 0.0 Fr 1.3.00 Aug.2004 Page 46 of 49 REJ05G0001-0200 Supply Current Iout (A) cy .1 1.3 VRM (Voltage Regulator Module) • Application equipment Desktop PCs.8 shows a sample VRM application.23.5 Note PC Notebook PC Capacity Increase 90W → 120W 2003 2004 2005 50 Control IC 0 2000 2001 2002 0 Year Circuit Topology Figure 3.

Power MOS FET 3.6kV DC48V DC/DC AC-DC Machinery room High-pressure change board AC-DC DC/DC Communication machine room AC-DC Power supply room Battery UPS AC-DC SMPS System Rectifier Diode Base Station Synchronous Rectifier MOS FET Input PWM Rectifier PFC DC/DC Main Switch Control IC Hot Swap Error Voltage Detector Circuit Vout = 48V Vin(AC) 200V Control PWM IC C PWM IC SBD SBD C 2SK3228 Shunt Reg IC (2 to 4pcs/unit) H5N5005PL H5N5004PL 250V AP5-HF(Built-in Fast Recovery Diode) H5N2507P High 500V AP5-HF(Built-in Voltage Fast Recovery Diode) D6/D7-L Ultra Low RDS(on) Low Voltage HA17341 Figure 3.23.9 shows a sample base station SMPS application. Power MOS FET Applications Base Station SMPS (Switch-Mode Power Supply) AC 6.2.9 Sample Base Station SMPS Application Rev.2004 Page 47 of 49 REJ05G0001-0200 .4 Figure 3. 3.3.00 Aug.

10 shows a sample communication equipment DC/DC converter application.0V at η = 90%↑ 2.3.0 Trends in Output Voltages and Current Demand for DC/DC Output Current Vout Current Slew Rate 1. Power MOS FET Applications Figure 3.0 V Output Voltage Vout (V) 1.23.2004 Page 48 of 49 REJ05G0001-0200 Output Current Iout (A) Current Slew Rate (A/µs) DC 48V DC/DC main switch Secondary-side SBD rectification → MOS synchronous synchronous rectification system Voltage fluctuation increase rectifier detection control Vout = 1.0 0.2 1.5 to 2.Power MOS FET 3.5 150 1.2.6 200 .5 V to 2.3 V → 1.9mΩ/LFPAK(HAT2099H) 0 2000 2001 2002 2003 2004 2005 0 Year Figure 3.0mΩ/SOP-8(HAT2064R) 30V/2.0 0. 3.5 50 HAT2058R 200V to 250V AP5-H Low Ron/Qgd HAT2077R H5N2508DS Control IC Shunt regurator IC HA17L431ALP D7-L Ultra Low Ron & Low Qg/Qgd 30V/5.10 Sample Communication Equipment DC/DC Converter Application Rev.8 100 Inrush current control circuit Control IC Shunt Reg IC 1.5 Communication Equipment DC/DC Converter 3.5 1.00 Aug. Unit DC/DC Converter Power Supply System Power THM(Thermal Temperature Resistor) Thermistor → to MOS FET Lower future LSI operating voltage: 5 V.3 1.

Power MOS FET Applications Motor Drive Applications Small Motor Drive Function HDD (voice coil motor) Camera motor.2. printer (paper feed motor. electronic throttle HDD (spindle motor) PPC.2004 Page 49 of 49 REJ05G0001-0200 .23.11 shows sample small motor drive applications. (Spindle motor drive) M U V W R Sense Figure 3.1 Application H bridge 3-phase 3. •Camera (H bridge) •PPC. Printer Laser diode Polygon mirror Toner Drum Paper feed motor +VDD +VDD •HDD of Server.00 Aug.4.Power MOS FET 3.4 3. polygon mirror) • Application equipment Figure 3.11 Sample Small Motor Drive Applications Rev. etc.

2004 Published by: Edited by: Sales Strategic Planning Div. Renesas Technology Corp.Power MOS FET Application Note Publication Date: Rev. Printed in Japan.00. Renesas Technology Corp. All rights reserved..2.. Ltd. . August 23.  2004. Technical Documentation & Information Department Renesas Kodaira Semiconductor Co.

Power MOS FET Application Note REJ05G0001-0200 .