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P.S. Gandhi Mechanical Engineering IIT Bombay

PRASANNA S GANDHI 1

Logic design

What is design? Given a problem develop a solution using available resources to meet some specific design performance parameters Logic design? Converting application task inputs and outputs to specifications in terms of 0s and p p 1s. (encoding) several possible ways Establishing mathematical relationship and developing combination of basic elements to achieve the goal several possible ways Selection of optimum design

PRASANNA S GANDHI 2

representation: "0", "1" on a wire

set of wires (e.g., for binary integers)

sequential statements: A; B; C conditionals: if x == 1 then y loops: for ( i = 1 ; i == 10, i++) procedures: A; proc(...); B;

PRASANNA S GANDHI 3

Study how these are implemented in hardware and compose into computational structures

Encoding/Mapping

Physical world to binary

PRASANNA S GANDHI

Combinational vs sequential

Combinational :

Output values depend only on current input Logic gates we have been talking so far (AND, OR, NOT, NAND, NOR gates)

Seque t a Sequential:

Output values depend not only on current inputs but also on previous inputs Concept of Memory needs clock to keep track of sequence

PRASANNA S GANDHI 5

In reality,

Outputs do not change instantaneously Why not? Time delay associated with charging etc.

So the definitions of combinational or sequential are based on steady state observation. System has settled down Sequential circuits have memory even after the system is settled down or in steady state

PRASANNA S GANDHI 6

Memory of a system is represented as its state Changes in system state are only allowed to occur at specific times controlled by an external periodic clock Clock period is the time that elapses between state changes. it must be sufficiently long so that the system reaches a steady-state before the next state change steadyat the end of the period

PRASANNA S GANDHI 7

Combinational logic

Input A, B Wait for clock edge Observe C Wait for clock edge Observe C again : SAME Input A, B Wait for clock edge Observe C Wait for clock edge Observe C again :

A B logic Circuit

Sequential logic

CLOCK

DIFFERENT

PRASANNA S GANDHI

Combinational logic

NOT gate AND, OR, NOR, NAND gates

Sequential logic

Fli flops, RS flip flop Flip fl fli fl Set-Rest flip-flop: Setflip Basic data storage device that holds data until RESET occurs

PRASANNA S GANDHI

clock S

RS f/f

Q

9

Sequential: Example

SetSet-Rest flip-flop: flip Timing diagram

R 0 1 0 1

S 1 0 0 1

Q 1 0 X Qn

Q 0 1 X Qn

PRASANNA S GANDHI

10

Calender: Calender:

Problem statement

Given a month and a leap year flag as inputs, determine the number of days in month as output

Application: digital watch display

No of Days

PRASANNA S GANDHI

11

What is logic in c program you can come up with? ith?

integer number_of_days ( month, leap_year_flag) { switch (month) { case 1: return (31); Month case 2: if (leap_year_flag == 1) then return (29) else return (28); Leap flag case 3: return (31); ... case 12: return (31); default: return (0); } PRASANNA S GANDHI }

logic logi

No of Days

12

ENCODING FOR DIGITAL CIRCIUT No of Days DESIGN/IMPLEMENTATION d28 How to encode the input of Month d29 month and leap flag? Logic d30 How many minimum inputs in Circuit terms of 0 and 1 can represent d31 Leap flag all the months? : ans 4 think why? Leap year flag can be 1 if leap We do not require year and 0 if not leap year 5 digit binary no. Outputs are either 28, 29, 30 or saving 1 output PRASANNA S GANDHI 13 31. so 4 one-hot encoding one-

TRUTH TABLE (combinational)

Develop truth table for considering the encoding in previous case. Notice dont care - input No of Days d28 d29 Logic Circuit Leap flag d30 d31

PRASANNA S GANDHI 14

Month

LOGIC GATES d28 = 1 when month is 0010 AND leap flag is 0 d28 = m8m4m2m1leap m8m4m2m1

AND NOT

d29 = 1 when month is 0010 AND leap flag is 1 l fl i d29 = m8m4m2m1 leap m8m4m2 d30 = (m8'm4m2'm1') + (m8'm4m2' (m8'm4m2 (m8'm4m2m1') + OR (m8m4'm2' (m8m4'm2'm1) + PRASANNA S GANDHI (m8m4'm2 (m8m4'm2m1)

15

LOGIC GATES d31 = (m8'm4'm2'm1)+ (m8'm4'm2'm1)+ (m8'm4'm2 (m8'm4'm2m1) + (m8'm4m2' (m8'm4m2'm1) + (m8'm4m2 (m8'm4m2m1) + (m8m4'm2' (m8m4'm2'm4') + (m8m4'm2 (m8m4'm2m1') + (m8m4m2' (m8m4m2'm1')

PRASANNA S GANDHI

16

LOGIC GATES logic circuit d28 = m8m4m2m1leap m8m4m2m1

m8 m4 m2 2 m1 leap

PRASANNA S GANDHI 17

d28

LOGIC GATES logic circuit d29 = m8m4m2m1leap m8m4m2m1

m8 m4 m2 2 m1 leap

PRASANNA S GANDHI 18

d29

LOGIC GATES logic circuit d29 = m8m4m2m1leap m8m4m2m1

m8 m4 m2 2 m1 leap

NAND for actual circuit

PRASANNA S GANDHI

CMOS circuit

d29

19

LOGIC GATES logic circuit CMOS circuit d30 = (m8'm4m2'm1') + (m8'm4m2m1') + (m8'm4m2' (m8'm4m2 (m8m4'm2' (m8m4'm2'm1) + (m8m4'm2m1) (m8m4'm2

m8 m4 m2 m1

PRASANNA S GANDHI

20

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