ISSCC 2012 / SESSION 27 / DATA CONVERTER TECHNIQUES / 27.

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27.7 A 70dB DR 10b 0-to-80MS/s Current-Integrating SAR ADC with Adaptive Dynamic Range
to shift the CM voltage from the mid-supply value used during sampling to around 225mV, which is the optimal value for the charge-sharing ADC phase. Some extra, smaller MOM capacitors are also used as shown in Fig. 27.7.2 to further control the common mode. To limit the power consumption needed to switch the MOS bias, the NMOS and PMOS drain/source nodes are first shorted briefly to re-use the PMOS charge in the NMOS, before connecting them to Vdd or Gnd. A 2-times interleaved topology with bootstrapped switched is used: two capacitors are alternately used for integration and digitization. Since the integration is fixed to a full clock period, the VGT is always used, but obviously other timing strategies could have been used for extra variable gain functionality. The core of the ADC function is detailed in Fig. 27.7.3, and is based on the charge-sharing SAR ADC concept [1]. While the original design needed a linear input capacitor to transfer the input voltage linearly into a sampled charge to be processed, the circuit here uses the charge that is linearly generated by integrating the VGT’s output current. In each of the 10 steps of the successive-approximation controller, the sign of the charge is determined by activating a dynamic comparator and a binary-scaled reference charge is added to or subtracted from the total charge by passive charge sharing. This involves only closing a switch towards one of the elements of a binary-scaled capacitor array, which has been precharged previously to a fixed reference voltage. A 1b redundancy with a lownoise (but higher-power) comparator is used as in [2] to correct errors in the comparator, whose design is based on [5]. A die micrograph of the IC is shown in Fig. 27.7.7. The circuit is implemented in a 1.1V 40nm LP digital CMOS technology, and occupies a core area of 175×455μm2. The maximum total power consumption is 5.45mA at the maximum VGT gain and the maximum sampling speed of 80MS/s. The power consumption of the ADC core scales linearly with the sampling speed. For a given sampling speed (and the related integration time) and input signal amplitude, the number of required Gm cells can be determined. Figure 27.7.4 shows measured DNL and INL at 40MS/s, which is limited to +0.72/-0.45 LSB and +0.68/-0.7 LSB. The sinc function discussed earlier is measured in Fig. 27.7.5a for a sampling frequency of 40MS/s and constant input amplitude. Figure 27.7.5b shows the SNDR and SFDR vs. input frequency when the input amplitude is changed to result in full-scale outputs. For 40MS/s and 80MS/s, the peak SNDR obtained is 56.85dB and 54.2dB, which corresponds to 9.15 ENOB and 8.71 ENOB and an FoM of 63fJ/conversion-step and 85fJ/conversion-step respectively, excluding the VGT power consumption. Figure 27.7.6a shows a FFT spectrum for a sampling frequency of 80MS/s and an input frequency of 19.008MHz. Thanks to the VGT, the DR could be extended by varying the number of transconductors used as shown in Fig. 27.7.6b, a DR of 70dB is obtained at 40MS/s. The system is thus a low-power alternative for the conventional VGA/ADC combination in wireless receivers since it optimizes the power consumption and offers a wide dynamic range for the system.

Badr Malki1,2, Takaya Yamamoto3, Bob Verbruggen1, Piet Wambacq1,2, Jan Craninckx1
1 2

imec, Leuven, Belgium Vrije Universiteit Brussel, Brussels, Belgium 3 Renesas Electronics, Takasaki, Japan The constant demand for wireless systems pushes engineers and researchers to develop more innovative systems to improve performance. Remarkable improvements have been recently realized on charge-domain SAR ADCs to reach the speed of a few tens of MS/s with medium resolution and low power consumption [1,2]. This has shifted the power bottleneck to the preceding block in a wireless receiver, conventionally the Variable-Gain Amplifier (VGA) that has to charge a few pF of ADC sampling capacitor with rail-to-rail voltage within a few ns with 10b linearity. This paper shows that a charge-domain SAR ADC with built-in variable gain provides improved system-level power efficiency compared to its voltage-domain counterpart by eliminating the issues related to large input capacitors. As depicted in Fig. 27.7.1, the presented circuit combines the functionality of a traditional VGA and ADC. The input voltage is converted to a current through the variable-gain transconductor (VGT) and to a charge on the sampling capacitor after integrating this current during a certain time interval [3]. Due to the sin(f)/f input response of this arrangement it is not suited for near-Nyquist input signals, but this is not a problem in most wireless receivers where a certain oversampling ratio (OSR) is always used to relax the analog filtering requirements. With an OSR of only 2, the signal content at half-Nyquist is attenuated by 0.9dB, which is easily corrected in the digital post-processing. Moreover, the sinc transfer function even helps in attenuating interferers and blockers at higher frequencies. As shown in Fig. 27.7.1, the input variable-gain transconductor (VGT) itself is inverter-based, with source degeneration that is used also for CMFB. For the variable-gain function, the total available transconductance of 17.6mS is split into 16 units that can be individually activated, with a current consumption of 185μA/unit. A channel length of 0.5μm is used, both for high output impedance and low 1/f noise. The ADC input sampling stage is shown in Fig. 27.7.2. The main challenge for this circuit is to ensure sufficient linearity for the voltage-to-charge conversion, despite the fact that the output voltage will show significant signal swing during the integration time. Input-related nonlinearity is less of an issue, since the input signal has only passed the RF gain stages of the receiver. The output swing could be limited by using a larger integrating capacitor but this will result in smaller voltages at the comparator input, and hence more erroneous decisions due to comparator noise. Leveraging the fact that a charge-domain ADC is not influenced by capacitor nonlinearity, a large but very nonlinear MOS capacitor of 23pF in inversion mode can be used during the integration phase, with a small voltage swing and no output swing problems for the transconductor. After sampling, the biasing of MOS capacitors is changed to depletion mode [4], the value of the capacitance becomes 8pF, such that the sampled voltage is passively amplified, and the effect of comparator noise suppressed. The ratio between the two capacitance values is determined by the aspect ratio of the MOS capacitors. A trade-off exists between the capacitance ratio and the speed of the passive amplification: a length of few μm will result in a high capacitance ratio but requires more time to settle due to Non-Quasi Static Effects. The passive amplification is done in two steps: one before the MSB decision and the second after to avoid voltage clipping. During the successive-approximation A/D conversion, the nonlinearities due to the MOS capacitor are not an issue as the ADC operates in the charge domain. Both NMOS and PMOS capacitors are used for sampling. It should be noted that when shifting the source/drain bias after sampling, the common-mode voltage changes. By choosing the proper ratio of PMOS/NMOS capacitors, it is possible

References: [1] J. Craninckx and G. Van der Plas, “A 65fJ/Conversion-Step, 0-to-50MS/s 0-to-0.7mW 9b Charge Sharing SAR ADC in 90nm Digital CMOS”, ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2007. [2] V. Giannini, et al., ”An 820μW 9b 40MS/s Noise Tolerant Dynamic SAR ADC in 90nm Digital CMOS”, ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2008. [3] L. Carley and T. Mukherjee, “High-Speed Low-Power Integrating CMOS Sample-and-Hold Amplifier Architecture” Proc. IEEE Custom Integrated Circuits Conf., pp. 543-546, 1995. [4] S. Ranganathan and Y. Tsividis, “Discrete-Time Parametric Amplification Based on a Three-Terminal MOS Varactor: Analysis and Experimental Results”, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2087-2093, Dec. 2003. [5] M. Miyahara, et al., “A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs,” IEEE Asian Solid-State Circuits Conf., pp. 269–272, Nov. 2008.

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• 2012 IEEE International Solid-State Circuits Conference

978-1-4673-0377-4/12/$31.00 ©2012 IEEE

6: (a) FFT @ 80MS/s with 7 Gm cells.3: Charge-sharing ADC core. (b) DR vs input voltage amplitude.5: (a) Sinc function @ 40MS/s with 3 Gm cells used. DIGEST OF TECHNICAL PAPERS • 471 .7.ISSCC 2012 / February 22. Figure 27. (b) SNDR and SFDR vs.7. Figure 27. Figure 27.7.1: Architecture of the VGA/ADC.7.2: Current-integrating input sampling capacitor.7.4: DNL/INL measurements @ 40MS/s with 3 Gm cells. Figure 27. 2012 / 4:45 PM Figure 27. input frequency.7. 27 Figure 27.

• 2012 IEEE International Solid-State Circuits Conference 978-1-4673-0377-4/12/$31.7.00 ©2012 IEEE .7: Chip micrograph.ISSCC 2012 PAPER CONTINUATIONS Figure 27.

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