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Bo co Kin Trc my tnh

M t chung Trong bi bo co chng ti s thit k 1 b ng x l (coprocessor) cho vi x l NIOS , mt kin trc RISC trn nn Altera. B ng x l s tnh ton chc nng m ha ca chun DES ( Data Encryption Standard ) u tin chng ti s thit k 1 module DES vi 1 giao din n gin v sau m phng trn Modelsim. Sau khi thnh cng, chng ti s tng hp b ng x l ny vi Cadence RC cho cng ngh ASIC 65nm nh gi chi ph v hiu qu ca n Thit k 1 module phn cng DES ( s dng VDHL) To ra 1 project vi tn l DES4Nios, lu code ngun des_pkg vo trong a ch ca project ny cng vi khung ca DES (des skeleton) Cc thng s k thut :

Tn clk clk_en

Kch thc hng u 1 vo u 1 vo

Miu t Clock. Module des s ng b theo chiu tng ca clk Clock Enable. Mi hot ng ni ca module des s ngng nu clk_en= '0' Reset. ng b v hot ng cao. Cc m-un des s ti khi to ng b khi thit lp (reset = '1 '). Chc nng reset c u tin cao hn so vi chc nng clock enable;cc thanh ghi ni b phi c khi to khi reset c khi to, ngay c khi clk_en khng hot ng. Start Execution. Khi bt u t ng m ha. Tin trnh x l ko di khong 16 chu k. Trong qu trnh x l cc bus u ra mang gi tr trung gian nn c b qua bi h thng. Sau khi giai on tr, bus u ra gi on

reset

u 1 vo u 1 vo

start

data_in

64

key _in data_out

64 64

done

kt qu on m ha ( the resulting cipher text ) cho n khi 1 ch c l khc bt u. Data Input .Cc bus 64 bit c s dng bi h thng u xung quanh cc on u vo (input plain text). u vo vo khng thay i trong qu trnh m ha Key Input. Cc bus 64 bit c s dng bi h thng u xung quanh cc phm b mt u vo. u vo khng vo thay i trong qu trnh m ha Data Output. Bus 64 bit c s dng cung cp cc u ra on m ha ti h thng xung quanh Execution Complete.Khi hot ng, cho bit vic thi hnh y v bus u ra mang on m. Thi gian: u ra mt chu k ng h

c tnh vt l in nng tiu th tit kim in nng, khi cc m-un des khng c s dng cc thanh ghi ni b ca n, cc thanh ghi ni b nn c ngng hot ng v kt qu u ra ca n khng nn thay i. Ngay c trong mt tnh ton, c gng cng trnh bt k hot ng khng cn thit: khng thay i ni dung ca ng k nu n l v ch. Din tch v tc Chng ti cn xy dng cc m-un des nhanh nht c th, nhng quan trng nht l , kch thc phi nh. Thit k phi c mt trng hp duy nht ca phn cng cn thit tnh ton mt vng DES v n s ti s dng n 16 ln. Mt qu trnh x l hon thin s c khong 16 chu k. Kin trc ny c ti u ha u tin cho khu vc silicon v sau cho tc : cc m-un des l cng nh cng tt v chy tn s cao nht c th. Vn cn v l do hiu sut c gng gim bt cng nhiu nh bn c th u vo v logic u ra, l, logic t hp gia cc yu t u vo tiu hc v ng k ni b v logic t hp gia cc thanh ghini b v kt qu u ra chnh. L tng nht, cc yu t u vo ch yu hu ht phi qua mt s lng nh ca Multiplexers trc khi chng c lu tr trong s ng k ni b v kt qu u rachnh trc tip phi c kt ni ng k kt qu u ra. Trong gi des_pkg c cung cp, n nh ngha mt tp hp rt hon chnh cc hng s, chng loi, chng trnh con Thit k mt mi trng m phng (s dng VHDL )

Thit k mt mi trng m phng m-un DES , vi cc u vo ngu nhin v so snh kt qu u ra ca n vi mt m hnh tham kho trong thut ton (Bt u t b xng c cung cp Thm ch gii m M-un des ca chng ti by gi l 100% chc nng ... nhng n thiu mt tnh nng rt quan trng : gii m. S dng cc kin trc sau y l mt im khi u v thch ng vi m-un trong des ca bn h tr c hai ch . Lu rng mt u vo mi l cn thit: Tn ch v thay vo bng cch sdng cc loi std_ulogic cho n, s dng cc loienc_mode tuyn b trong gi des_pkg. Giao din mi l:

Tn Mod e

Kch thc

hng u 1 vo

Miu t M ha (des_encrypt) hoc gii m (des_decrypt). u vo khng thay i trong qu trnh hot ng

Thch ng vi mi trng m phng ca bn v xc nhn phin bn mi ca cc mun des bng cch m phng. Cui cng, tng hp thit k ca bn vi Cadence RC v, nh trong hng dn v tng hp, c gng c c nh nht v cng l mt trong nhanh nht. Lu cho cc thng s chnh nh sau: Tn s MHz Tng s trng hp S cc trng hp lien tip Din tch Silicon Slack in ps Tn s clock ti a Chu k hot ng Thng lng ti a Crack time tnh ton thi gian crack time cho rng bn sn xut 1 cm chip c cha nhiu mun des cng tt, chy tn s cao nht c th. Gi s rng bn xy dng mt my nt nhng 1000 ca cc chip nh vy v rng bn s dng n tn cng brute-

force DES. l, chng ti gi nh rng chng ta bit mt vn bn r rng cypher cp vn bn v chng ti c gng tm cha kha b mt bng cch c gng cho h tt c (nh l loi tn cng ny c th d dng c song song chng ti s khai thc y my nt ca chng ti). Cui cng, gi s bn lkhng may mn tt c v kha b mt l mt trong nhng cui cng bn c gng. Thi gian crack cathit k ca bn l thi gian n s c c tm cha kha b mt. Part2 Thit k 1 h thng xung quanh 1 CPU 32 bits v ng b n Lu : cc lnh s c vit ra vi k t bt u l : $ M t chung: Trong phn ny, chng ti s s dng cng c Builder SOPC t Altera xy dng 1 h thng nh vi 1 CPU NIOS 32 bit,1 RAM,1 giao tip ni tip,1 b nh gi v mt giao tip song song dng iu khin mt s n LED v g li (debug). Vi cng c Quartus II (cng ca Altera cung cp ), sau chng ti s tng hp ny h thng v cu hnh FPGA trn Nios board. S dng b kit pht trin c to ra bi SOPC Builder cho h thng ca chng ti, pht trin ngn ng C thc hin phn mm ca thut ton DES v cng lm testbench n gin xc nhn cc chc nng. B m thi gian phn cng tesbench s cung cp cho chng ta chnh xc s chu k ng h cn thit tnh ton mt tin trnh m ha (encipherment) hoc gii m ( decipherment ). Chng ta s cu bng c Instruction Set Simulator ( ISS )ca CPU NIOS v trn phn cng thc t. Chng ti cng s chy v h s khc thc hin cc phn mm, c bit n rng ri nh DES nhanh nht trn tri t (v c da trn cc ch OpenSSL DES). Ny h s th hai s cung cp cho chng ta l mt c tnh ca bin ti u ha phn mm tinh khit. Ci t mi trng Chng ti s dng 2 loi board khc nhau, 6 board nhng trn EP1S10F780C6 Altera FPGA 3 board khc c nhng trn EP1S40F780C5 Altera FPGA. Trc khi s dng cng c tng hp, chng ti s thit lp mi trng, trc khi s dng Modelsim hoc Cadence RC. Lu tp ny l alterarc trong th mc home, v g : $ . ~/.alterarc Thm Thit k 1 h thng Nios nh (dng SOPC Builder) S dng SOPC Builder to ra 1 h thng Nios n gin bao gm : CPU Nios II 32 bt Cng giao tip (JTAG UART) giao tip vi my ch PC thng qua cp USB CPU s dng 1 giao tip vi 1 Mbytes SRAM lm vic vi b nh v lu tr cc phn ca phn mm

1 mch cu 3 trng thi c s dng thch ng vi cc BUS Nios 1 b nh thi Giao tip u ra 8 bt song song iu khin bi LEDs hin th trn board H thng ID ca thit b ngoi vi xc nh h thng Nios To 1 th mc lu cho phn ny ?? Create a new directory for the lab. Save the provided Makefile and the companion TCL script in this directory. Edit the TCL script and adapt it to your board type: select the device type of your FPGA board (eitherEP1S10F780C6 or EP1S40F780C5) by uncommenting one of the two lines near the beginning. Type make prj to create and initialize the Quartus IIproject. Launch SOPC Builder: $ sopc_builder & V s dng n thit k h thng Nios II u tin SOPC Builder s yu cu tn ca h thng v ngn ng phn cng c s dng, ta chn tn DES4Nio v ngn ng lp trnh l VHDL, i tn clock thnh clk. Chn Stratrix trong Target Device Familmy Thm b x l Nios II ( chn trong mc Component Library pha tri v click Add). Ta bt u Nios CPU wizard v khng thay i cc gi tr mc nh ca cc thng s. Click vo Finish. Trong bng thng bo di cng, ta c th nhn thy cc khuyn ngh cnh bo an ton . Cho rng h thng cha hon thnh. Bn c th b qua mt cch an ton . T Interface Protocols/Serial ca th vin chn JTAG UART. Board FPGA v my tnh s giao tip thng JTAG UART v cp USB. Cc phn mm s chy trn board s c ti v t my tnh thng qua JTAG UART. Cc thng bo m bn s thc hin trong qu trnh s c chuyn n my tnh thng qua cng mt JTAG UART trc khi c hin th trn mn hnh ca bn (v trn board khng c mn hnh). Khng thay i cc ty chn v bm vo nt Finish. Tip tc t Memories and memory Controllers/SRAM c trong th vin chn IDT71V416 SRAM. Nu xem xt cn thn trn board, ta s thy hai gi nha mu en gc di cng bn phi vi con s phn vit trn chng. l hai Static RAM dung lng 256Kx16 t Integrated Device Technology,Inc t chc nh mt bank ca RAM 256Kx32. Chng ti c mt s thnh phn b nh khc trn board (v d : SDRAM, flash, Compact flash) nhng cho phn ny, chng ti s ch s dng ny 1 Mbyte bank Static RAM l . Cc thnh phn c b sung vo h thng NIOS l mt giao din chuyn dng vi b nh Static RAM bn ngoi. Khng thay i cc ty chn v bm vo nt Finish. Nhp chut phi vo cc module mi c to ra v chn tn l : SRAM.

Nu nhn vo bng thng bo di cng, ta s thy mt thng bo li mi. SRAM yu cu mt cu 3 trng thi Avalon-MM Tristate Bridge. Tht vy, b nh Static RAM c mt tr khng cao, Bus d liu s dng cho c c v ghi trong khi Bus Avalon (Bus xng sng ca bt k 1 h thng Nios no) khng h tr cu hnh ny. Nh vy chng ta khng th ch cm Bus Avalon trn Bus d liu Static RAM. Thng bo li cho bit chng ta s cn mt cu ni gia chng. Trong Bridges and Adapters/Memory Mapped ca th vin chn cu Avalon-MM Tristate Bridge. Khng thay i cc ty chn v bm vo nt Finish. Di chuyn chut qua cc phn ca bng iu khin lm vic i din cho mi lin kt gia cc thnh phn ca h thngta s thy cc chm en v trng xut hin ch ra nhng g c kt ni. Bn c th sa cha cc thng bo li? B qua cc thng bo li mi, chng ti s sa cha chng sau ny. T Peripherals/Microcontroller Peripherals trong th vin chn mt b m thi gian Interval timer v PIO (Parallel I / O). T Peripherals/Debug and Performance, chn mt ID h thng ngoi vi. Khng thay i cc ty chn ca b m thi gian v PIO. ID ca h thng khng c ty chn tt c. B m thi gian s c s dng tnh thi gian x l trn CPU NIOS. PIO s c s dng trong ch u ra iu khin 8 n LED trn board . ID h thng ch c thit b ngoi vi tr v mt nh danh duy nht ca h thng NIOS. Phn mm thit k v bin son vi Nios II Integrated Development Environment (IDE) kim tra ID ny ti thi gian ti trnh chy mt phn mm bin dch cho mt kin trc phn cng khc nhau. i tn thnh timer, led_pio v sysid. Cui cng ta xem xt n cc mi lin kt.Khi h thng Nios gn nh hon tt. By gi chng ta phi gn a ch ca cc thnh phn khc nhau trong s a ch ca ton b h thng. Chuyn nhng ny s c s dng bi cc Bus Avalon nh tuyn mt cch chnh xc cc yu cu c / ghi. Trong bng iu khin lm vic cc ct base v end cho thy s phn cng. Nu c sai st, ta c th sa bng tay hoc yu cu SOPC Builder giao li (re-assign) mt cch t ng : trong menu System, chn AutoAssign Base Address. Tng t, s lng ngt phi c ch nh (trong ct IRQ ). C hai thnh phn c th to ra ngt bo hiu cc s kin vi CPU, s lng cng thp,th u tin cng cao hn. Bi v chng ta mun m thi gian 1 cch chnh xc nht c th nn c ch nh mt s lng thp hn so vi JTAG UART. Nu n khng phi l trng hp sa cha n. Cui cng, m mt ln na NIOS CPU wizard (nhp p chut vo tn module) v xc nh b nh ni m cc thit lp li v vect ngoi l s c lu tr. Nh chng ti ch c mt b nh khng c s la chn tt c. Hai vect chuyn hng s dng nhy ng a ch khi b vi x l c t li hoc khi mt ngoi l c nng ln. Kim tra ln cui cng bng tin

nhn v di chuyn sang bc tip theo bng cch nhn vo nt Next di cng ca ca s. /* Trong tab b chn h thng th h m phng. To tp tin d n m phng. N tng tc qu trnh, v th h anyway, chng ti s khng m phng VHDL to ra. Click vo nt Generate di cng ca ca s, chp nhn ngh lu cc thit k ca bn ... v chun b ch i mt vi pht. y c th l thi gian vit mt ci g trong bo co phng th nghim ca bn. Mt khi th h qua, thot khi SOPC Builder.By gi chng ta c th tng hp ton b h thng v to ra cc tp tin cu hnh cho FPGAmc tiu. Tp tin cu hnh cha tt c cc d liucn thit xc nh cc chc nng ca mi yu t hp l trong FPGA l g v cng c cc mi lin kt l nhng g gia chng. l tp tin m chng ta s ti v trong FPGA thng qua cp USB kt ni my tnh ca bn vo cng JTAG ca hi ng qun tr. G lnh $ make syn ...v chun b ch i mt vi pht. y c th l thi gian tip tc lm vic trn bo cophng th nghim ca bn ... hoc bt u lmvic trn phn tip theo (kt qu tng hp khng cn thit cho cc bc u tin). Sau khi hon thnh, phn tch cc bo co khc nhau nh bn lm trong phng th nghim trc y cho cc m-un DES mt mnh (thi gian bo co, s dng ti nguyn, vv) To 1 phn mm thc thi tham chiu cho DES Some useful material:

a C header file a C file with the basic functions of DES already designed a C header file used by the test bench a C test bench a Makefile

Trong th mc d n ca bn to ra mt th mc con c tn l C v lu Makefile cung cp v cc tp tin m ngun C trong n. Bt u t vt liuny, thit k mt phn mm thc hin tham chiuca DES. Chnh sa des_ref.c v thit k c th ca hai chc nng des_set_key v des ctuyn b vo cui ca tp tin. c k tt c cc kin trong tp tin trc khi m ha, m t cc loi d liu c s dng v hnh vi d kin ca hai chc nng. Xc nhn m ca bn trn my tnh ca bn bng cch bin dch v chy n: $ make

Chy 1 phm mm thc thi DES trn h thng Nios vi Nios II Instruction Set Simulator (ISS) Truy cp vo Nios II IDE $ nios2-ide & Vo Develop Software Using the Nios II IDE , to 1 project :

Trong menu Window chn Open Perspective --> Nios II C/C++. Trong menu File chn New -> Nios II C/C++ Application to 1 project mi : + Chn tn l des + Chn mc tiu phn cng bng cch duyt chn file DES4Nios.ptf + Chn 1 template tn l : Blnk Project + Click chn nt Next + Chn chc nng Create a new system library named...
+ Click Finish Trong tab Nios II C/C++ Projects
perspective you have now two folders: des which is where you will add your own software source files, and des_syslib [DES4Nios] where the tool will build the other software components. Right click on the desfolder and select System Library Properties. Edit the default settings in order to use the hardware timer as a timestamp timer instead of a system clock timer (you cannot have both with a single hardware timer). Click on OK. Right click again on the des folder and select Import... and thenGeneral and then File system and then browse and select the Csubdirectory. Click OK. Check the radio buttons on front of the C source files and header files and click on the Finish button (see why GUIs are sometimes not that helpful?).

Click chut phi vo folder des v chn Run As -> Nios II Instruction Set Simulator
Now, we will try to profile this software implementation of DES, that is, measure how many clock cycles it takes to encipher or decipher. Because we embedded a timer in our Nios system this profiling is easy and accurate. The following code snippet shows how to use the hardware timer for profiling: #include "system.h" #include "sys/alt_timestamp.h" #include "alt_types.h" ... alt_timestamp_type time1, time2; ... if(alt_timestamp_start() < 0) printf("No timestamp device available\n"); else { printf("Running frequency: %u Hz\n", (unsigned int)(alt_timestamp_freq())); time1 = alt_timestamp(); function_to_profile(); time2 = alt_timestamp();

printf("Time in function_to_profile: %u ticks\n", (unsigned int)(time2 time1)); }

Chnh file ngun tests.c v cho thm code vo than hm speed_tests. Yu cu code cn t c : Bt u m thi gian v kim tra xem c mt b m thi gian du thi gian c sn. Nu khng in mt thng bo li v dng li . Ghi li cc gi tr ca b m thi gian trong mt bin v ghi li n mt ln na ngay lp tc bin khc.S khc bit s cung cp cho bn thi gian cn c cc gi tr ca b m thi gian ny. Lu tr nyc b p trong mt bin. S dng cc phm b mt ca cc vect th nghimu tin v tnh ton mt lch trnh quan trng. Ghi li cc gi tr ca b m thi gian trong mt bin, chy 10 m ha trn ng bng vn bn utin ca cc vect th nghim, ghi nhn gi tr ca b m thi gian trong mt bin khc. In mt thng bo cho bit s lng cc chu k v mili giy cho mi m ha v tn s chy. Lm tng t 10 decryptions. Tho lun ra cc cuc gi n cc chc nng functional_tests trong chnh (n mt qu nhiu thi gian v chng ti kim tra ny). Chy vi ISS vlu nhng con s c in. Chng ta c th ti u ha tc x l DES cachng ti bng cch thay i cc ty chn trnh bin dch tng tc thc hin: nhp chut phi vo th mc des v chn Properties. Trong C / C + + Xydng phn chuyn i cu hnh pht hnh, thay icc ty chn Tng NVHDNM Compiler II. Chn mc ti u ha cao nht v v hiu ha cc debug.Xy dng v chy li vi ISS. Lu chn in v s lng in. L n nhanh hn? L n nh hn?