CPLD-Oriented Design Projects for the First Course in Digital Systems
David J. Ahlgren Department of Engineering Trinity College Hartford, CT 06106
Abstract - This paper reports on enhanced educational outcomes that have been achieved at Trinity College by introducing complex programmable logic devices (CPLD’s) and the hardware description language VHDL in the first course in digital design. Using Altera’s Max + Plus II package and concurrent engineering practices, a team of eight students implemented a fully operational four-bit “tiny” CPU as a three-week final design project. Such successes demonstrate that modern CAD tools and use of CPLD's encourage creativity and system-level thinking in the first course.These basic outcomes are realized primarily through a sequence of introductory laboratory design projects. Based on the standard LSTTL family, these projects have included traffic light controllers, adders and subtractors, and minicommunication networks. Design has been facilitated by the use of a a user-friendly schematic-capture and simulation program, B^2Logic, that runs on Macintosh and PC machines. (B^2Logic is available from Beige Bag Software, Ann Arbor, MI.) Students use B^2Logic to enter and verify their LSTTL-based designs before constructing them thereby reducing hardware debugging time significantly. Still, the scope of student designs is limited by breadboard space and wiring complexity. The basic educational outcomes listed above have been augmented by the following enhanced outcomes: • completion of a large, team-based design project that requires use of hierarchical design and concurrent engineering methods; • experience in the use of an advanced CAD toolset; • working knowledge of a useful subset of the standard hardware description language, VHDL. Underlying the enhanced outcomes is the belief that tackling problems large enough to require teamwork develops new skills that will prove useful in advanced courses, senior design projects (e.g. in digital signal processing and robotics), and on the job. Moreover, successful large projects would instill pride and be seen as exciting and contemporary.
This paper focuses on educational outcomes that have been achieved by introducing complex programmable logic devices (CPLD's) in the introductory digital design course at Trinity College. It describes the pedagogical approaches and CAD tools used to engage students in large-scale projects that require teamwork and concurrent engineering methods. The paper introduces the CPU221/97 design, a working four-bit "tiny" processor that was developed by a team of eight students during a three-week period in Fall, 1997. This introductory course, ENGR 221L, is taken primarily by sophomores pursuing concentrations in electrical or computer engineering. It also attracts computer science majors. ENGR 221L has three one-hour lectures and a three-hour laboratory session each week. The basic outcomes expected of students are: • a working knowledge of logic gates, flip-flops, synchronous sequential networks, and memory elements and their implementation in a standard logic family (LSTTL, primarily); • the ability to design digital circuitry using standard methods (e.g., K-maps, state transition diagrams); • the ability to use CAD tools for schematic capture and simulation; • the ability to build and debug hardware circuits; • familiarity with programmable logic devices (e.g. GAL22V10) and an associated hardware description language (ABEL or CUPL); • the ability to complete a term project working closely with other students; • the ability to write clear and complete documentation.
The keys to achieving the enhanced outcomes were twofold. First, the teaching of VHDL was integrated throughout the course. Whenever logic gates, MSI components, flip-flops, counters, and registers were introduced in class, students were given VHDL descriptions of them. These examples provided a basic knowledge of language structure and syntax and introduced a VHDL subset sufficient to develop CPLDbased designs. (This subset consists of the VHDL constructs: ENTITY, ARCHITECTURE, SIGNAL, TYPE, PORT, PROCESS, IF-THEN-ELSE, CASE..WHEN, WHEN...ELSE conditional assignment structure, and ‘EVENT.) Second, the laboratory provided a smooth
control unit states. and 4) to illustrate the application of a finite state machine as the
In previous years. which were carried out using LSTTL chips. the necessary register transfers at each microinstruction cycle of the CPU. Of the twelve enrolled students.g. programmed the design into a single Altera EPM5032 device. addressing logic. and the timing of internal register transfers and data path multiplexer select signals. status register SR. This exercise paved the way for the CPU221/97 final design project. Students were given a tutorial handout that included the following: 1) block diagram of the previous year's processor showing CPU sub-systems and their interconnections (ALU. In addition to the CPU design. and the final project report was due on December 17. In the next lab. teams divided the CPU into sub-systems and assigned design and verification of a sub-system to each pair of students. and three teamed up to design a digital stopwatch. students organized themselves instead by job category.) The planning matrix was the key instructional tool for this project. control unit including control logic and finite-state machine). and serial ASCII interface. A one-page project prospectus was due on November 24. bi-directional data bus interface. The first four lab projects. for each machine instruction.transition between designing with standard logic circuits and CPLD's. calculator. This transition was eased by the CAD toolset used in ENGR 221L: Altera's Max + Plus II. 4) initial instruction set and op-code list (Table I below) (Students were encouraged to revise this set. students developed a full understanding of the state transitions and data transfers necessary to execute each machine instruction. Max + Plus II and VHDL became the preferred design tools for the rest of the semester.
control element in a programmable system.
Final Design Projects
With the background provided by these exercises. students improved a skeletal design for an arithmetic logic unit (ALU) by increasing the word size and adding new logical operations. and tested the programmed chip. (Assignment handouts are available from the author. simulated the overall system. They added a BCDto-seven segment decoder developed in VHDL. but it encouraged students to develop their own ideas. In the next week's lab. The fifth lab design--a 4-bit adder/subtractor--was built first using LSTTL chips. 3) programming model showing CPU registers (accumulator A. Similar projects had been completed by ENGR 221L students each year since 1994. a pattern that they were expected to continue. The problem required the development of a four-bit processor and associated EEPROM and RAM circuitry. pairs could be combined to form larger teams. they were able to develop a Boolean expression for every data path select signal and register transfer enable signal in the CPU. as follows: 1) team leader (one student). 2) programming and hardware design (three Instruction Load A immediate Load A direct Load A indexed Add immediate Add indexed NAND indexed Store A direct Store A indexed NAND immediate Unused Load X immediate Load X direct Store X direct Update X Immediate Branch uncond’l Branch if zero Mnemonic LDAI LDAD LDAX ADDI ADDX NANDX STAD STAX NANDI * LDXI LDXD STXD UDXI BRA BEQ Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Table I: Initial Instruction Set
. Students had worked in pairs throughout the term.. Handed out four weeks before the end of the term. and array summation program). suggested projects included a vending machine. address register MAR. From the matrix. By completing it. 5) planning matrix where students recorded. 3) to introduce the concept of address and (bi-directional) data busses. connected the modules together using the Max + Plus II graphic editor. Specific project goals included: 1) to introduce the stored program concept. using Beige Bag Software's B^Logic. students entered the same design with the Max + Plus II graphic editor using LSTTL equivalent cells from the Altera library. 2) timing diagram showing the two-phase system clock. one worked on the calculator. In 1997. students gained appreciation for the productivity increase that results from the use of VHDL and CPLD's. the assignment included project suggestions. program counter PC. students were able to tackle their final design projects using Max + Plus II and Altera CPLD's. subtraction program. and index register X). temporary register B. eight teamed up to work on the CPU. 2) to introduce memory interfacing. digital stopwatch. From these VHDL exercises. The CPU project implicitly led students to achieve the enhanced outcomes. As a result. and wiring and debugging circuits on a breadboard.). took students through the basics of applying standard synthesis methods for combinational logic (K-Maps). and 6) program examples (e. To attack final design projects. shutter speed tester.
Toronto. For example.
Appendix: Getting Started
Altera CPLD technology and development tools are available from the Altera University Program. The team made the following improvements to the initial design: • expansion of the address bus from 7 bits to 8 bits.altera. Each element of this tiny computer. the equivalent of approximately 5000 logic gates. 4) librarian. which enabled team-based design by supporting concurrent engineering of sub-systems and the hierarchical integration of these modules. This success was made possible by the CAD tools. By running the CPU at a slow clock rate. . In addition. The MAX9320 and MAX7064 devices.com. (AHDL is the Altera Hardware Description Language. especially in the application of digital design to robotics and DSP hardware development. the modules were integrated using the graphic editor. participating schools receive the University Program Design Laboratory Package. The design experience provided in ENGR 221L has served as a springboard for independent study and senior design projects. The success of this project and earlier CPU design projects in ENGR 221L has been a source of pride for students and has motivated the further study of digital electronics. After this step. in CPU221/97’s machine language. for example. including CPU. The tools also encourage creativity. The first programmed chip executed programs correctly. Altera donates software and CPLD chips to schools that offer courses in digital systems.students). and IBM RISC 6000 UNIX machines. 3) memory system. the CPU221/97 design was programmed into an Altera MAX9320 84-pin CPLD. wiring. and several students have applied what they have learned about VHDL and CPLD’s in ENGR 221L to their senior design projects. • deletion of the STAX instruction in the initial design and addition of op-codes OUTI and OUTX. the CPU221/97 processor from standard SSI and MSI components. complete.51 or higher and on HP. Sun SPARC. in short time frames. They programmed a second Altera CPLD (type MAX7064) as a buffer to drive the LED monitors. in the space of three weeks. chief simulator. to play "Mary Had a Little Lamb" and "Jingle Bells". (These adapters are available from Technological Arts. Almost all students who have taken ENGR 221L go on to take a more advanced course in digital electronics. and writing (three students). and programmer (one student). In addition.com o r on the Web at http://www. was verified using Max + Plus II. and document large projects that require teamwork and concurrent engineering approaches. An advantage of incorporating CPLD's in the introductory course is that students can
. the team could observe register transfers and state changes during the execution of each machine instruction. Altera is eager to receive course materials and student papers that may be shared with other University Program schools. There are no charges to the school for software support and maintenance. the latter just in time for the holidays. the texts - have proved to
All ENGR 221L students achieved the basic outcomes of the course listed earlier in the paper. Modern CAD tools and CPLD's encourage system-level thinking in the first course by enabling the completion of such large projects.) In addition. Reference  includes a number of excellent VHDL templates that have helped ENGR221L students to understand language syntax and structure.) To demonstrate their system. Altera provides to member schools multiple copies of Max + Plus II software and documentation for PC's or workstations. Enrollment in the University Program is straightforward and may be accomplished through the Web site. were interfaced to a standard breadboard using convenient PLCC-to-DIP adapters. The wiring group created a bank of LED's that displayed data and address bus activity. Altera provides clear documentation about Max + Plus II installation and operation  and very readable manuals on VHDL and AHDL . The tone generator is a table-driven presettable downcounter that divides a 30kHz external clock to yield a twooctave musical scale. it would be impractical for sophomores to build. external ROM and RAM. allowing the processor to access 256 locations--128 in ROM and 128 in RAM. both contained in 84-pin PLCC packages. which contains Max + Plus II Student Edition software and device programming hardware. the programmers developed code. • design of a tone generator interfaced via a new CPU register sk and controlled by OUTI and OUTX. Max + Plus II runs on appropriately-configured PCs equipped with Windows 95 or NT 3. register contents.
approach. and sound generator. Then. producing a clean circuit layout. The design required 272 logic cells of the 320 available on the chip. and machine states. they developed a working knowledge of CPLD-based design and the use of VHDL as a means for describing and synthesizing digital systems. ENGR 221L students were able quickly to design and implement a tone generator for CPU221/97 using VHDL. and full verification was carried out at the system level. which can be contacted via the e-mail address university@altera. support for hardware description languages (VHDL and AHDL) and interfaces to other EDA tools.
and they are recommended by the author. Altera Corporation.  F.be helpful references for both teacher and students. 1997.  P. 1996. Patrick Hannon.  K.
Acknowledgements The author thanks the Altera University Program for its generous support. Altera Corporation. Boston. San Jose. Kluwer. Altera Corporation.  Z. 1997. VHDL and AHDL. San Jose. and Customization. Sheldon Provost. San Jose. The Designer’s Guide to VHDL. 1998. and Brian Jackson
. Salcic. 1996. Addison Wesley. The author also acknowledges the hard work of the CPU221/97 design team: Amir Tamrakar.VHDL for Programmable Logic. Steve Baker. Scarpino. Prototyping. Michael Lock. VHDL and FPLDs in Digital Systems Design.  Max+Plus II AHDL. Ashenden. 1997. 1997. Nick Allen. San Francisco. Prentice-Hall.
 Getting Started With Max+Plus II. Michael Kornhauser.  Max+Plus II VHDL. Morgan-Kaufman. Skahill.