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Combinational circuits demultiplexer, magnitude

are

adders

subtractors

multiplexers

comparator, parity generator/checker etc. Arithmetic circuits are used for addition, subtraction multiplication division Half adder is used for addition of two binary numbers. Full adder is used to perform addition of more tharr2 bits Serial adder require one full adder for one additional bit while parallel adders requires N full adders for n bit addition. Two more adders are look ahead carry adder and BCD adder. Half subtractor subtracts two numbers we get 2 output variables i e difference and borrow Full subtractor is subtraction of 3 bits. Encoder converts human language into machine language. Decoder is used to convert machine language to human language. Multiplexers are universal circuits which selects one input out of multiple inputs and give it as a result Demultiplexer receives information on single line and distribute to the 2 lines where n are selection lines. Magnitude comparator is used to compare 2 binary numbers Code converters are those which converts a given code to some other code Examples are:

(a) Gray to Binary code converter (b) Binary to Gray code converter (c) Binary to Excess 3 code converter etc. Parity generator is a logic circuit which generates the parity bits for even or odd parity Parity generator is used at the transmitter. Parity checker is used at the receiver. BCD display drive is basically the BCD to seven segment display code converter In this binary coded decimal is displayed on the seven segment displays

Q 1. List the applications of decoders.

Ans. 1 Decoders are used in counter systems 2. Decoders are used for A/D conversion. 3 Decoders are used for D/A conversion 4. Decoders are used in seven segment digital displays.

Q 2 Give functional block diagram of 2 1 MUX

To subtract two numbers i e two Input variables A and B we get two output variable i e difference ‘D’ and borrow ‘Bo’ It is known as half subtractor Functional diagram is shown: Its truth table is as shown: Thus. Q 3 Explain half subtractor with the help of its internal circuit Ans. the minimized logic functions are: .Ans.

The circuit diagram is as shown: Q 4. Ans. Implement half adder circuit using 4 : 1 MUX or multiplexers only. Truth table of half adder is as shown: .

The implementation table is as shown: Implementation: Q 6. Implement using 4: 1 MUX Ans. Design 3 bit Gray Code to binary converters Ans. The truth table for 3 bit Gray Code to binary conversion is as shown: .Q 5.

K-Maps: For 82: For B1: For Bo: .

BCD to Excess-3 Code Converter: The input variables are BCD’s (A. C and D) and output variables are excess-3 code (E3. E2. B. E1 and E0) Truth Table .Circuit Implementation is as shown: Q 7. Design BCD to Excess-3 code converter. Ans.

Minimization Using K-map: For E3 E3 = A + BD + BS For E2 .e. mark don’t care i.e. 1001 BCD.After ‘9’ i. ‘X’.

For E1 For E0 Implementation of Excess-3 Code Converter: .

Q 8. Draw the logic circuit for the expression Ans. . Logic circuit representation.

D3. D4.Q 9 Draw the logic circuit for 3 line to 8 line decoder Ans. A. 3 line to 8 line decoder circuit is as shown: It has three input lines i. D6 and D7 Q 10 Draw the logic circuit for the expression Ans . B and C and has eight output lines i. D0.e. D5. D2. D1.e.

It has priorities given to the input lines from highest priority input line to lowest priority input line. How many select lines are there for a 30 to 1 MUX? Ans. ‘1’ or high at the same time.e. If two or more input lines are active i. then the input line with highest priority will be considered first.Logic Circuit: Q 11. 4 select lines are for 16 : . Give significance of priority encoder. Ans. 5 select lines are required. Q 12. Priority encoder in a special type of encoder. For 30: 1 MUX.

Design full subtractor using NAND gates. Q 14. What are the various type of parity checkers and where do we use them? Ans. (i) Odd parity checker (ii) Even parity checker. Broadly parity checkers are of two types. 5 select lines are needed. Parity checkers are used at the receiver part.Thus. = 32. They check the parity of the received word and produces its output. .1 MUX’s and 1 select line for 2: 1 MUX. Where n = number of select lines and M are the number of inputs for a MUX. = M formula is used. Q 13.

It is used for 16 bit comparator. Truth-table of full-subtractor is: Q 15. Ans. Full subtractor is used to subtract three bits and generate difference and borrow.Ans. Construct 16-bit comparator using 4-bit comparator as a building block. . 4 bit comparator IC in 7485.

4 IC’S are used. How can a DEMUX be used as a decoder? Ans. What is a parity checker? . Q 17. which is as shown: Q 16. The selection lines of the DEMUX can be used as input lines of decoder and if the data input of the demultiplexer is used as the enable input of the decoder then we can use the demultiplexer as a decoder.Thus.

Implement using 4 x 1 MUX Ans. Q 18.Ans. Obtain the truth table for a combinational circuit that accepts a three bit ‘number and generates an output binary number equal to the square of the input number. . Ans. A parity bit is an additional bit which is added to a binary word in order to make the number of one’s in the new word format as even for even parity and odd for odd parity. Truth table is as shown for inputs and the corresponding square outputs. Parity checker is a logic circuit that checks the parity binary word. Q 19.

Q 20 Describe the operations performed by an encoder and a decoder. Implement the following function using 3 to 8 decoder . that converts n input binary information to 2 output lines e g 2 to 4 line decoder 3 to 8 line decoder etc 2 It is used at the receiver part to decode the information Q 21. Operations Performed by Encoder: 1 Encoder is a combinational circuit which encodes one digital input code to them digital output code like octal to binary encoder Decimal to BCD encoder etc 2 It provides the security for the data by encoding it 3 It saves the bandwidth over the channels Operations Performed by Decoder 1 A decoder is a combinational circuit. Ans.

Ans. it has n input lines and unique output lines Let us take an example of 2 to 4 line decoder to convert the decoder into a demultiplexer. . Implementation using 3 to 8 decoder: Q 22 Define a demultiplexer Show how to convert a decoder into a demultiplexer indicate how to add a strobe to this system OR What is demultiplexer’ Explain the difference between DMIJX and MUX Ans. Demultiplexer: Demultiplexer is a device which has single input line and many i e output lines The relation of specific output line is controlled by the value of n’ selection lines It performs the inverse operation of multiplexer In case of decoder.

Stroke signal is also added to all the AND gates simultaneously as shown in fig. Strobe signal is similar to enable signal for chip selection. D1.2 to 4 line Decoder: It can be converted into demultiplexer if D1 i e data Input line is converted to all the AND gates simultaneously. It is an active low signal. If high signal is applied to stroke the chip will be disable because i = 0 goes to all the AND gates And we receive no output at D0. D2 and D3 Difference between DMUX and MUX: .

Q 23 Design a Gray-to Excess-3 Code converter using NAND gates Ans. Gray to Excess3 code converter: K-maps for Excess 3-codes are .

Circuit Diagram: .

Design a 3-bit carry-look-ahead adder. Ans. . 3-bit look ahead adder : The bit look ahead carry adder speeds up The process by eliminating ripple carry delay. It examines all the input bits simultaneously and generates carry-in-bits for all stages simultaneously. It is done with two additional functions carry generate and carry propagate function.Q 24.

The carry generate function indicates as to when a carry-out would be generated by full-adder. B Carry propagate (GP) = A B . This condition is expressed as the AND function of the two bits A and B. Carry generate (CG) = A . A carry-out is generated only when both the inputs bits are 1.

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