You are on page 1of 1108

TMS320C6000 Chip Support Library API Reference Guide

Literature Number SPRU401J August 2004

Printed on Recycled Paper

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

Copyright © 2004, Texas Instruments Incorporated

Preface

Read This First
About This Manual
The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on--chip peripherals for ease of use, compatibility between various C6000 devices and hardware abstraction. This will shorten development time by providing standardization and portability. The C6000 Chip Support Library (SPRC090) supports the following devices: C6201, C6202, C6203, C6204, C6205, C6211, C6410, C6412, C6413, C6414, C6415, C6416, C6418, C6701, C6711, C6712, C6713, DA610, DM640, DM641 and DM642. Some of the advantages offered by the CSL include: peripheral ease of use, a level of compatibility between devices, shortened development time, portability, and standardization. A version of the CSL is available for all TMS320C6000 devices. This document is organized as follows: - Introduction -- a high level overview of the CSL - 27 CSL API module chapters - HAL macro chapter - Using CSL APIs Without DSP/BIOS - Register description - How to Use the CSL - Cache register comparison - Glossary

How to Use This Manual
The information in this document describes the contents of the TMS320C6000 chip support library (CSL) as follows:
- Chapter 1 provides an overview of the CSL, includes a table showing CSL

API module support for various C6000 devices, and lists the API modules.

Read This First

iii

Notational Conventions

- Each additional chapter discusses an individual CSL API module and

provides:
J J J J

A description of the API module A table showing the APIs within the module and a page reference for more specific information A table showing the macros within the module and a page reference for more specific information A module API Reference section in alphabetical order listing the CSL API functions, enumerations, type definitions, structures, constants, and global variables. Examples are given to show how these elements are used.

- Chapter 28 describes the hardware abstraction layer (HAL) and provides

a HAL macro reference section.
- Appendix A provides an example of using CSL independently of

DSP/BIOS.
- Appendix B provides a list of the registers associated with current

TMS320C6000 DSP devices.
- Appendix C provides a comparison of the old and new CACHE register

names, as they have recently been changed.
- Appendix D provides a glossary.

Notational Conventions
This document uses the following conventions:
- Program listings, program examples, and interactive displays are shown

in a special typeface.
- In syntax descriptions, the function or macro appears in a bold typeface

and the parameters appear in plainface within parentheses. Portions of a syntax that are in bold should be entered as shown; portions of a syntax that are within parentheses describe the type of information that should be entered.
- Macro names are written in uppercase text; function names are written in

lowercase.
- TMS320C6000 devices are referred to throughout this reference guide as

C6201, C6202, etc.
iv

Related Documentation From Texas Instruments

Related Documentation From Texas Instruments
The following books describe the TMS320C6000 devices and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477−8924. When ordering, please identify the book by its title and literature number. Many of these documents can be found on the Internet at http://www.ti.com. TMS320C62x/C67x Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x digital signal processors, development tools, and third-party support. TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the TMS320C6000™ CPU architecture, instruction set, pipeline, and interrupts for these digital signal processors. TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) tells you how to invoke the TMS320C6x™ simulator and emulator versions of the C source debugger interface. This book discusses various aspects of the debugger, including command entry, code execution, data management, breakpoints, profiling, and analysis. TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) describes the peripherals available on the C6000 platform of devices. TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for the TMS320C6000™ DSPs and includes application program examples. TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C6000™ generation of devices. TMS320C6000 Optimizing Compiler User’s Guide (literature number SPRU187) describes the TMS320C6000™ C compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code and produces assembly language source code for the TMS320C6000 generation of devices. The assembly optimizer helps you optimize your assembly code. TMS320C62x DSP Library (literature number SPRU402) describes the 32 high-level, C-callable, optimized DSP functions for general signal processing, math, and vector operations.
Read This First v

Related Documentation From Texas Instruments

TMS320C64x Technical Overview (SPRU395) The TMS320C64x technical overview gives an introduction to the TMS320C64x™ digital signal processor, and discusses the application areas that are enhanced by the TMS320C64x VelociTI™. TMS320C62x Image/Video Processing Library (literature number SPRU400) describes the optimized image/video processing functions including many C-callable, assembly-optimized, general-purpose image/video processing routines. TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU266) describes the operation of the external memory interface (EMIF) in the digital signal processors of the TMS320C6000 DSP family. TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234) describes the operation of the EDMA controller in the digital signal processors of the TMS320C6000 DSP family. This document also describes the quick DMA (QDMA) used for fast data requests by the CPU. TMS320C6000 DSP EMAC/MDIO Module Reference Guide (literature number SPRU628) describes the EMAC and MDIO module in the digital signal processors of the TMS320C6000 DSP family. TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584) describes the general-purpose input/output (GPIO) peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family. TMS320C6000 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU578) describes the host−port interface (HPI) in the digital signal processors (DSPs) of the TMS320C6000 DSP family that external processors use to access the memory space. TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646) describes the interrupt selector, interrupt selector registers, and the available interrupts in the digital signal processors (DSPs) of the TMS320C6000 DSP family. TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175) describes the I2C module that provides an interface between a TMS320C6000 digital signal processor (DSP) and any I2C-bus-compatible device that connects by way of an I2C bus. TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041) describes the multichannel audio serial port (McASP) in the digital signal processors (DSPs) of the TMS320C6000 DSP family.
vi

Related Documentation From Texas Instruments

TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU580) describes the operation of the multichannel buffered serial port (McBSP) in the digital signal processors (DSPs) of the TMS320C6000 DSP family. TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (literature number SPRU581) describes the peripheral component interconnect (PCI) port in the digital signal processors (DSPs) of the TMS320C6000 DSP family. The PCI port supports connection of the DSP to a PCI host via the integrated PCI master/slave bus interface. TMS320C6000 DSP Software Programmable Phase-Locked Loop (PLL) Controller RG (literature number SPRU233) describes the operation of the software-programmable phase-locked loop (PLL) controller in the digital signal processors (DSPs) of the TMS320C6000 DSP family. TMS320C6000 DSP 32-Bit Timer Reference Guide (literature number SPRU582) describes the 32-bit timer in the TMS320C6000 DSP family. TMS320C64x DSP Turbo-Decoder Coprocessor (TCP) Reference Guide (literature number SPRU534) describes the operation and programming of the turbo decoder coprocessor (TCP) embedded in the TMS320C6416 digital signal processor (DSP) of the TMS320C6000 DSP family. TMS320C64x DSP Viterbi-Decoder Coprocessor (VCP) Reference Guide (literature number SPRU533) describes the operation and programming of the Viterbi-decoder coprocessor (VCP) embedded in the TMS320C6416 digital signal processor (DSP) of the TMS320C6000 DSP family. TMS320C64x DSP Video Port/ /VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629) describes the video port and VCXO interpolated control (VIC) port in the TMS320C64x digital signal processors (DSPs) of the TMS320C6000 DSP family. TMS320C64x DSP Universal Test and Operations Interface for ATM (UTOPIA) Reference Guide (literature number SPRU583) describes the universal test and operations PHY interface for asynchronous transfer mode (UTOPIA) in the TMS320C64x digital signal processors (DSPs) of the TMS320C6000 DSP family. TMS320C62x DSP Expansion Bus (XBUS) Reference Guide (literature number SPRU579) describes the expansion bus (XBUS) used by the CPU to access off-chip peripherals, FIFOs, and peripheral component interconnect (PCI) interface devices in the TMS320C62x digital signal processors (DSPs) of the TMS320C6000 DSP family.
Read This First vii

Trademarks

TMS320C620x/C670x DSP Program and Data Memory Controller/DMA Controller Reference Guide (literature number SPRU577) describes the program memory modes, program and data memory organizations, and the program and data memory controller in the TMS320C620x/C670x digital signal processors (DSPs) of the TMS320C6000 DSP family.

Trademarks
The Texas Instruments logo and Texas Instruments are registered trademarks of Texas Instruments. Trademarks of Texas Instruments include: TI, Code Composer Studio, DSP/BIOS, and TMS320C6000. All other brand or product names are trademarks or registered trademarks of their respective companies or organizations.

viii

Contents

Contents
1 CSL Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides an overview of the chip support library (CSL), shows which TMS320C6000 devices support the various APIs, and lists each of the API modules. 1.1 CSL Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1 Benefits of the CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.2 CSL Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.3 Interdependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 CSL Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 CSL Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 CSL Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.1 Peripheral Initialization via Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 CSL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 CSL Symbolic Constant Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Resource Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.7.1 Using CSL Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 CSL API Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.8.1 CSL Endianess/Device Support Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.2 1.3 1.4 1.5 1.6 1.7 1.8 2

CACHE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the CACHE module, gives a description of the two CACHE architectures, lists the functions and macros within the module, and provides a CACHE API reference section. . . . 2.1 2.2 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

3

CHIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the CHIP module, lists the API functions and macros within the CHIP module, and provides a CHIP API reference section. 3.1 3.2 3.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

4

CSL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Describes the CSL module, shows the single API function within the module, and provides a CSL API reference section. 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
ix

Contents

4.2 5

Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 5-1

DAT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the DAT module, lists the API functions within the module, discusses how the module manages the DMA/EDMA peripheral, and provides a DAT API reference section. 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 DAT Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 DAT Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 DMA/EDMA Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Devices With DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 Devices With EDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-2 5-2 5-3 5-3 5-3 5-3 5-4

6

DMA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Describes the DMA module, lists the API functions and macros within the module, and provides a DMA API reference section. 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.1 Using a DMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3 Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.4.2 DMA Global Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.4.3 DMA Auxiliary Functions, Constants, and Macros . . . . . . . . . . . . . . . . . . . . . . 6-23 EDMA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Describes the EDMA module, lists the API functions and macros within the module, discusses how to use an EDMA channel, and provides an EDMA reference section. 7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.1 Using an EDMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.4.1 EDMA Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.4.2 EDMA Auxiliary Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 EMAC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Describes the EMAC module, lists the API functions and macros within the module, and provides an EMAC reference section. 8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Describes the EMIF module, lists the API functions and macros within the module, and provides an EMIF API reference section. 9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

7

8

9

x

Contents

9.2 9.3 9.4

Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

10 EMIFA/EMIFB Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Describes the EMIFA and EMIFB modules, lists the API functions and macros within the modules, and provides an API reference section. 10.1 10.2 10.3 10.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10-3 10-5 10-7

11 GPIO Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Describes the GPIO module, lists the API functions and macros within the module, and provides an GPIO API reference section. 11.1 11.2 11.3 11.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.1.1 Using GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.4.1 Primary GPIO Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.4.2 Auxiliary GPIO Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

12 HPI Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Describes the HPI module, lists the API functions and macros within the module, and provides an HPI API reference section. 12.1 12.2 12.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

13 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Describes the I2C module, lists the API functions and macros within the module, and provides an I2C API reference section. 13.1 13.2 13.3 13.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.1.1 Using an I2C Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4.2 Auxiliary Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.4.3 Auxiliary Functions Defined for C6410, C6413 and C6418 . . . . . . . . . . . . . . 13-22

14 IRQ Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Describes the IRQ module, lists the API functions and macros within the module, and provides an IRQ API reference section. 14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Contents xi

Contents

14.2 14.3 14.4

Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.4.1 Primary IRQ Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.4.2 Auxiliary IRQ Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15

15 McASP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Describes the McASP module, lists the API functions and macros within the module, discusses using a McASP device, and provides a McASP API reference section. 15.1 15.2 15.3 15.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.1 Using a McASP Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.4.2 Parameters and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.4.3 Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.4.4 Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30

16 McBSP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Describes the McBSP module, lists the API functions and macros within the module, and provides a McBSP API reference section. 16.1 16.2 16.3 16.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.1.1 Using a McBSP Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 16.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 16.4.2 Auxiliary Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.4.3 Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23

17 MDIO Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 Describes the MDIO module, lists the API functions and macros within the module, and provides an MDIO reference section. 17.1 17.2 17.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

18 PCI Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Describes the PCI module, lists the API functions and macros within the module, discusses the three application domains, and provides a PCI API reference section. 18.1 18.2 18.3
xii

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6

Contents

18.4

Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7

19 PLL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 Describes the PLL module, lists the API functions and macros within the module, discusses the three application domains, and provides a PLL API reference section. 19.1.1 Using the PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19-4 19-6 19-7

19.2 19.3 19.4

20 PWR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 Describes the PWR module, lists the API functions and macros within the module, and provides a PWR API reference section. 20.1 20.2 20.3 20.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20-3 20-5 20-6

21 TCP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 Describes the TCP module, lists the API functions and macros within the module, discusses how to use the TPC, and provides a TCP API reference section. 21.1 21.2 21.3 21.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.1.1 Using the TCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13

22 TIMER Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 Describes the TIMER module, lists the API functions and macros within the module, discusses how to use a TIMER device, and provides a TIMER API reference section. 22.1 22.2 22.3 22.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.1 Using a TIMER Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.4.1 Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.4.2 Auxiliary Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11

23 UTOPIA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 Describes the UTOPIA module, lists the API functions and macros within the module, discusses how to use the UTOPIA interface, and provides a UTOP API reference section. 23.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.1.1 Using UTOPIA APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
Contents xiii

Contents

23.2 23.3 23.4

Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7

24 VCP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 Describes the VCP module, lists the API functions and macros within the module, discusses how to use the VCP, and provides a VCP API reference section. 24.1 24.2 24.3 24.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.1 Using the VCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11

25 VIC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 Describes the VIC module, lists the API functions and macros within the module, and provides a VIC reference section. 25.1 25.2 25.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

26 VP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 Describes the VP module, lists the API functions and macros within the module, and provides a VP reference section 26.1 26.2 26.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9

27 XBUS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 Describes the XBUS module, lists the API functions and macros within the module, discusses how to use the XBUS device, and provides an XBUS API reference section. 27.1 27.2 27.3 27.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27-2 27-4 27-5

28 Using the HAL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 Describes the hardware abstraction layer (HAL), gives a summary of the HAL macros, discusses RMK macros and macro token pasting, and provides a HAL macro reference section. 28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.1.1 HAL Macro Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.1.2 HAL Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.1.3 HAL Macro Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic Macro Notation and Table of Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28-2 28-2 28-3 28-4

28.2
xiv

Contents

28.3

28.4 A

General Comments Regarding HAL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.3.1 Right-Justified Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.3.2 _OF Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.3.3 RMK Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8 28.3.4 Macro Token Pasting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11 28.3.5 Peripheral Register Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11 HAL Macro Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12

Using CSL APIs Without DSP/BIOS ConfigTool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Provides an example of using CSL independently of the DSP/BIOS configuration tool. A.1 Using CSL APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.1 Using DMA_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.2 Using DMA_configArgs() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compiling and Linking With CSL Using Code Composer Studio IDE . . . . . . . . . . . . . . . A.2.1 CSL Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.2 Using the Code Composer Studio Project Environment . . . . . . . . . . . . . . . . . . . A-2 A-2 A-5 A-7 A-7 A-7

A.2

B

TMS320C6000 CSL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Shows the registers associated with current TMS320C6000 DSPs. B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 B.10 B.11 B.12 B.13 B.14 B.15 B.16 B.17 B.18 B.19 B.20 B.21 B.22 B.23 B.24 B.25 Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Direct Memory Access (DMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17 Enhanced DMA (EDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-31 EMAC Control Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60 EMAC Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64 External Memory Interface (EMIF) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-122 General-Purpose Input/Output (GPIO) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-149 Host Port Interface (HPI) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-159 Inter-Integrated Circuit (I2C) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-168 Interrupt Request (IRQ) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-203 Multichannel Audio Serial Port (McASP) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-207 Multichannel Buffered Serial Port (McBSP) Registers . . . . . . . . . . . . . . . . . . . . . . . . . B-284 MDIO Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-311 Peripheral Component Interconnect (PCI) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . B-328 Phase-Locked Loop (PLL) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-353 Power-Down Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-359 TCP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-360 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-382 UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-386 VCP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-396 VIC Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-409 Video Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-413 Video Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-427 Video Display Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-462 Video Port GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-504
Contents xv

Contents

B.26 Expansion Bus (XBUS) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-529 C D Old and New CACHE APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

xvi

Figures

Figures
1−1 5−1 A−1 B−1 B−2 B−3 B−4 B−5 B−6 B−7 B−8 B−9 B−10 B−11 B−12 B−13 B−14 B−15 B−16 B−17 B−18 B−19 B−20 B−21 B−22 B−23 B−24 B−25 B−26 B−27 B−28 B−29 B−30 B−31 B−32 B−33 API Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2D Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Defining the Target Device in the Build Options Dialog Box . . . . . . . . . . . . . . . . . . . . . . . A-8 Cache Configuration Register (CCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 L2 EDMA Access Control Register (EDMAWEIGHT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 L2 Writeback Base Address Register (L2WBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 L2 Writeback Word Count Register (L2WWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 L2 Writeback−Invalidate Base Address Register (L2WIBAR) . . . . . . . . . . . . . . . . . . . . . . . . B-6 L2 Writeback−Invalidate Word Count Register (L2WIWC) . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 L2 Invalidate Base Address Register (L2IBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 L2 Writeback−Invalidate Word Count Register (L2IWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 L2 Allocation Registers (L2ALLOC0−L2ALLOC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 L1P Invalidate Base Address Register (L1PIBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9 L1P Invalidate Word Count Register (L1PIWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9 L1D Writeback−Invalidate Base Address Register (L1DWIBAR) . . . . . . . . . . . . . . . . . . . . B-10 L1D Writeback−Invalidate Word Count Register (L1DWIWC) . . . . . . . . . . . . . . . . . . . . . . B-10 L1P Invalidate Base Address Register (L1PIBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11 L1D Invalidate Word Count Register (L1DIWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11 L2 Writeback All Register (L2WB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12 L2 Writeback−Invalidate All Register (L2WBINV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13 L2 Memory Attribute Registers (MAR0−MAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14 L2 Memory Attribute Registers (MAR96−MAR111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15 L2 Memory Attribute Registers (MAR128−MAR191) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16 DMA Auxiliary Control Register (AUXCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17 DMA Channel Primary Control Register (PRICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19 DMA Channel Secondary Control Register (SECCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24 DMA Channel Source Address Register (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28 DMA Channel Destination Address Register (DST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28 DMA Channel Transfer Counter Register (XFRCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29 DMA Global Count Reload Register (GBLCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29 DMA Global Index Register (GBLIDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30 DMA Global Address Reload Register (GBLADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30 EDMA Channel Options Register (OPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-32 EDMA Channel Source Address Register (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-36 EDMA Channel Transfer Count Register (CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37 EDMA Channel Destination Address Register (DST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Contents xvii

Figures

B−34 B−35 B−36 B−37 B−38 B−39 B−40 B−41 B−42 B−43 B−44 B−45 B−46 B−47 B−48 B−49 B−50 B−51 B−52 B−53 B−54 B−55 B−56 B−57 B−58 B−59 B−60 B−61 B−62 B−63 B−64 B−65 B−66 B−67 B−68 B−69 B−70 B−71 B−72 B−73 B−74 B−75 B−76
xviii

EDMA Channel Index Register (IDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Count Reload/Link Register (RLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Selector Register 0 (ESEL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Selector Register 1 (ESEL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Selector Register 3 (ESEL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Priority Queue Allocation Register (PQAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Priority Queue Status Register (PQSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Priority Queue Status Register (PQSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Pending Register (CIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Pending Low Register (CIPRL) . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Pending High Register (CIPRH) . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Enable Register (CIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Enable Low Register (CIERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Enable High Register (CIERH) . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Chain Enable Register (CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Chain Enable Low Register (CCERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Chain Enable High Register (CCERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Register (ER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1EDMA Event High Register (ERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Enable Register (EER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Enable Low Register (EERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Enable High Register (EERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Clear Register (ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Clear Low Register (ECRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Clear High Register (ECRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Set Register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Set Low Register (ESRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Set High Register (ESRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Polarity Low Register (EPRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Polarity High Register (EPRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Control Module Transfer Control Register (EWTRCTRL) . . . . . . . . . . . . . . . . . . . . EMAC Control Module Interrupt Control Register (EWCTL) . . . . . . . . . . . . . . . . . . . . . . . . EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) . . . . . . . . . . . . . . . Transmit Identification and Version Register (TXIDVER) . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Control Register (TXCONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Teardown Register (TXTEARDOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Identification and Version Register (RXIDVER) . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Control Register (RXCONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Teardown Register (RXTEARDOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Unicast Set Register (RXUNICASTSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Unicast Clear Register (RXUNICASTCLEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Maximum Length Register (RXMAXLEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-38 B-38 B-39 B-40 B-41 B-42 B-43 B-43 B-44 B-45 B-45 B-46 B-47 B-47 B-48 B-49 B-49 B-50 B-51 B-52 B-53 B-53 B-54 B-55 B-55 B-56 B-57 B-57 B-58 B-59 B-60 B-62 B-63 B-67 B-68 B-69 B-70 B-71 B-72 B-73 B-78 B-80 B-82

Figures

B−77 Receive Buffer Offset Register (RXBUFFEROFFSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-83 B−78 Receive Filter Low Priority Packets Threshold Register (RXFILTERLOWTHRESH) . . . B-84 B−79 Receive Channel n Flow Control Threshold Registers (RXnFLOWTHRESH) . . . . . . . . . B-85 B−80 Receive Channel n Free Buffer Count Registers (RXnFREEBUFFER) . . . . . . . . . . . . . . B-86 B−81 MAC Control Register (MACCONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-87 B−82 MAC Status Register (MACSTATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-89 B−83 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) . . . . . . . . . . . . . . . . . B-93 B−84 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) . . . . . . . . . . . . . . . . B-94 B−85 Transmit Interrupt Mask Set Register (TXINTMASKSET) . . . . . . . . . . . . . . . . . . . . . . . . . . B-95 B−86 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) . . . . . . . . . . . . . . . . . . . . . B-97 B−87 MAC Input Vector Register (MACINVECTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-99 B−88 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) . . . . . . . . . . . . . . . . B-100 B−89 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) . . . . . . . . . . . . . . . B-101 B−90 Receive Interrupt Mask Set Register (RXINTMASKSET) . . . . . . . . . . . . . . . . . . . . . . . . . B-102 B−91 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) . . . . . . . . . . . . . . . . . . . . B-104 B−92 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) . . . . . . . . . . . . . . . . . B-106 B−93 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) . . . . . . . . . . . . . . . . B-107 B−94 MAC Interrupt Mask Set Register (MACINTMASKSET) . . . . . . . . . . . . . . . . . . . . . . . . . . B-108 B−95 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) . . . . . . . . . . . . . . . . . . . . . . B-109 B−96 MAC Address Channel n Lower Byte Register (MACADDRLn) . . . . . . . . . . . . . . . . . . . . B-110 B−97 MAC Address Middle Byte Register (MACADDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-110 B−98 MAC Address High Bytes Register (MACADDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-111 B−99 MAC Address Hash 1 Register (MACHASH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-112 B−100 MAC Address Hash 2 Register (MACHASH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113 B−101 Backoff Test Register (BOFFTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-114 B−102 Transmit Pacing Test Register (TPACETEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-115 B−103 Receive Pause Timer Register (RXPAUSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-116 B−104 Transmit Pause Timer Register (TXPAUSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-117 B−105 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) . . . . . . . . . . . . . B-118 B−106 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) . . . . . . . . . . . . . B-118 B−107 Transmit Channel n Interrupt Acknowledge Register (TXnINTACK) . . . . . . . . . . . . . . . . B-119 B−108 Receive Channel n Interrupt Acknowledge Register (RXnINTACK) . . . . . . . . . . . . . . . . B-120 B−109 Statistics Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-121 B−110 EMIF Global Control Register (GBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-123 B−111 . EMIF Global Control Register (GBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-126 B−112 EMIF Global Control Register (GBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-128 B−113 EMIF CE Space Control Register (CECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-131 B−114 EMIF CE Space Control Register (CECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-133 B−115 EMIF CE Space Control Register (CECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-135 B−116 EMIF CE Space Secondary Control Register (CESEC) . . . . . . . . . . . . . . . . . . . . . . . . . . B-137 B−117 EMIF SDRAM Control Register (SDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-139 B−118 EMIF SDRAM Control Register (SDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-141 B−119 EMIF SDRAM Control Register (SDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-143 B−120 EMIF SDRAM Timing Register (SDTIM) (C620x/C670x) . . . . . . . . . . . . . . . . . . . . . . . . . B-145
Contents xix

Figures

B−121 B−122 B−123 B−124 B−125 B−126 B−127 B−128 B−129 B−130 B−131 B−132 B−133 B−134 B−135 B−136 B−137 B−138 B−139 B−140 B−141 B−142 B−143 B−144 B−145 B−146 B−147 B−148 B−149 B−150 B−151 B−152 B−153 B−154 B−155 B−156 B−157 B−158 B−159 B−160 B−161 B−162 B−163 B−164
xx

EMIF SDRAM Timing Register (SDTIM) (C621x/C671x/C64x) . . . . . . . . . . . . . . . . . . . . EMIF SDRAM Extension Register (SDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Peripheral Device Transfer Control Register (PDTCTL) . . . . . . . . . . . . . . . . . . . . . GPIO Enable Register (GPEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register (GPDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Value Register (GPVAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Delta High Register (GPDH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO High Mask Register (GPHM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Delta Low Register (GPDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Low Mask Register (GPLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Global Control Register (GPGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interrupt Polarity Register (GPPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Control Register (HPIC)—C620x/C670x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Control Register (HPIC)—C621x/C671x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Control Register (HPIC)—C64x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Transfer Request Control Register (TRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Own Address Register (I2COAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Interrupt Enable Register (I2CIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Status Register (I2CSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Roles of the Clock Divide-Down Values (ICCL and ICCH) . . . . . . . . . . . . . . . . . . . . . . . . I2C Clock Low-Time Divider Register (I2CCLKL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Clock High-Time Divider Register (I2CCLKH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Data Count Register (I2CCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Data Receive Register (I2CDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Slave Address Register (I2CSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Data Transmit Register (I2CDXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Mode Register (I2CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit . . . . . . . . I2C Interrupt Source Register (I2CISRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Extended Mode Register (I2CEMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Prescaler Register (I2CPSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Peripheral Identification Register 1 (I2CPID1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Peripheral Identification Register 2 (I2CPID2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Function Register (I2CPFUNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Direction Register (I2CPDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Data Input Register (I2CPDIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Data Output Register (I2CPDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Data Set Register (I2CPDSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Data Clear Register (I2CPDCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Multiplexer High Register (MUXH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Multiplexer Low Register (MUXL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Polarity Register (EXTPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Identification Register (PID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down and Emulation Management Register (PWRDEMU) . . . . . . . . . . . . . . . . .

B-145 B-146 B-148 B-149 B-150 B-151 B-152 B-153 B-154 B-155 B-156 B-158 B-162 B-163 B-164 B-167 B-169 B-170 B-171 B-177 B-177 B-178 B-179 B-180 B-181 B-182 B-183 B-190 B-191 B-192 B-193 B-194 B-195 B-196 B-197 B-198 B-199 B-201 B-202 B-203 B-205 B-206 B-212 B-213

Figures

B−165 B−166 B−167 B−168 B−169 B−170 B−171 B−172 B−173 B−174 B−175 B−176 B−177 B−178 B−179 B−180 B−181 B−182 B−183 B−184 B−185 B−186 B−187 B−188 B−189 B−190 B−191 B−192 B−193 B−194 B−195 B−196 B−197 B−198 B−199 B−200 B−201 B−202 B−203 B−204 B−205 B−206 B−207 B−208

Pin Function Register (PFUNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Direction Register (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Data Output Register (PDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Data Input Register (PDIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Data Set Register (PDSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDCLR Pin Data Clear Register (PDCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Control Register (GBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Mute Control Register (AMUTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Loopback Control Register (DLBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIT Mode Control Register (DITCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Global Control Register (RGBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Format Unit Bit Mask Register (RMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Bit Stream Format Register (RFMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Frame Sync Control Register (AFSRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Clock Control Register (ACLKRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive High-Frequency Clock Control Register (AHCLKRCTL) . . . . . . . . . . . . . . . . . . Receive TDM Time Slot Register (RTDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Interrupt Control Register (RINTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Status Register (RSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Receive TDM Time Slot Register (RSLOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Clock Check Control Register (RCLKCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver DMA Event Control Register (REVTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Global Control Register (XGBLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Format Unit Bit Mask Register (XMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Bit Stream Format Register (XFMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Frame Sync Control Register (AFSXCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Clock Control Register (ACLKXCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit High Frequency Clock Control Register (AHCLKXCTL) . . . . . . . . . . . . . . . . . . Transmit TDM Time Slot Register (XTDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Interrupt Control Register (XINTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Status Register (XSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Transmit TDM Time Slot Register (XSLOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Clock Check Control Register (XCLKCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter DMA Event Control Register (XEVTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serializer Control Registers (SRCTLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIT Left Channel Status Registers (DITCSRA0−DITCSRA5) . . . . . . . . . . . . . . . . . . . . . DIT Right Channel Status Registers (DITCSRB0−DITCSRB5) . . . . . . . . . . . . . . . . . . . . DIT Left Channel User Data Registers (DITUDRA0−DITUDRA5) . . . . . . . . . . . . . . . . . . DIT Right Channel User Data Registers (DITUDRB0−DITUDRB5) . . . . . . . . . . . . . . . . . Transmit Buffer Registers (XBUFn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Buffer Registers (RBUFn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Receive Register (DRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Register (DXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents

B-214 B-216 B-219 B-221 B-223 B-225 B-227 B-230 B-234 B-235 B-236 B-238 B-239 B-242 B-243 B-245 B-247 B-248 B-250 B-253 B-254 B-256 B-257 B-260 B-261 B-264 B-265 B-267 B-269 B-270 B-272 B-275 B-276 B-278 B-279 B-281 B-281 B-282 B-282 B-283 B-283 B-284 B-285 B-285
xxi

Figures

B−209 B−210 B−211 B−212 B−213 B−214 B−215 B−216 B−217 B−218 B−219 B−220 B−221 B−222 B−223 B−224 B−225 B−226 B−227 B−228 B−229 B−230 B−231 B−232 B−233 B−234 B−235 B−236 B−237 B−238 B−239 B−240 B−241 B−242 B−243 B−244 B−245 B−246 B−247 B−248 B−249
xxii

Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Control Register (XCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Rate Generator Register (SRGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Channel Enable Register (RCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Channel Enable Register (XCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced Receive Channel Enable Registers (RCERE0−3) . . . . . . . . . . . . . . . . . . . . . . Enhanced Transmit Channel Enable Registers (XCERE0−3) . . . . . . . . . . . . . . . . . . . . . MDIO Version Register (VERSION) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Control Register (CONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO PHY Alive Indication Register (ALIVE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO PHY Link Status Register (LINK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Link Status Change Interrupt Register (LINKINTRAW) . . . . . . . . . . . . . . . . . . . . . MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) . . . . . . . . . MDIO User Command Complete Interrupt Register (USERINTRAW) . . . . . . . . . . . . . . MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO User Access Register 0 (USERACCESS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO User Access Register 1 (USERACCESS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO User PHY Select Register 0 (USERPHYSEL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO User PHY Select Register 1 (USERPHYSEL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Reset Source/Status Register (RSTSRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management DSP Control/Status Register (PMDCSR) . . . . . . . . . . . . . . . . . . . . PCI Interrupt Source Register (PCIIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interrupt Enable Register (PCIIEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Master Address Register (DSPMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Address Register (PCIMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Master Control Register (PCIMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current DSP Address (CDSPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current PCI Address Register (CPCIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Byte Count Register (CCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Address Register (EEADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Data Register (EEDAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Control Register (EECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Transfer Halt Register (HALT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Transfer Request Control Register (TRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Controller Peripheral Identification Register (PLLPID) . . . . . . . . . . . . . . . . . . . . . . . . PLL Control/Status Register (PLLCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Control Register (PLLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-290 B-293 B-296 B-299 B-301 B-305 B-306 B-307 B-309 B-312 B-313 B-315 B-316 B-317 B-318 B-319 B-320 B-321 B-322 B-323 B-324 B-326 B-327 B-329 B-332 B-335 B-338 B-341 B-342 B-343 B-344 B-344 B-345 B-346 B-347 B-348 B-350 B-351 B-353 B-354 B-356

. . . . . Clock Detect Register (CDR) . . . . . . . TCP Status Register (TCPSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 5 (TCPIC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 11 (TCPIC11) . Error Interrupt Enable Registers (EIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Endian Mode Register (VCPEND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Control Register (UCR) . . . TCP Input Configuration Register 0 (TCPIC0) . Power-Down Control Register (PDCTL) . . . . . . . . . . . . . Timer Period Register (PRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Input Configuration Register 0 (VCPIC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Status Register 0 (VCPSTAT0) . . . . . . . . . . VCP Status Register 1 (VCPSTAT1) . TCP Error Register (TCPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 8 (TCPIC8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Interrupt Pending Register (UIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register (CTL) . . . . VCP Input Configuration Register 1 (VCPIC1) . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 9 (TCPIC9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Error Register (VCPERR) . . . . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 7 (TCPIC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Input Configuration Register 3 (VCPIC3) . . . . . . . . . . . . VCP Input Configuration Register 5 (VCPIC5) . . VIC Input Register (VICIN) . . . . . . . . . . . . . . . . . . . . . VCP Execution Register (VCPEXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Interrupt Enable Register (UIER) . . . . . . . . . . . TCP Input Configuration Register 3 (TCPIC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 6 (TCPIC6) . . . . . VCP Output Register 0 (VCPOUT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Execution Register (TCPEXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 4 (TCPIC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIC Control Register (VICCTL) . . . . . . . . . . . . . . . . . Contents B-357 B-358 B-359 B-361 B-363 B-364 B-365 B-366 B-367 B-369 B-370 B-371 B-372 B-373 B-374 B-375 B-376 B-377 B-378 B-380 B-382 B-385 B-385 B-386 B-389 B-390 B-391 B-392 B-394 B-397 B-398 B-399 B-399 B-400 B-401 B-402 B-403 B-404 B-405 B-406 B-407 B-408 B-409 B-411 xxiii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Input Configuration Register 2 (VCPIC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 10 (TCPIC10) . . . . . . . . . . . . . VCP Input Configuration Register 4 (VCPIC4) . . . . . . . . . . . . . Timer Count Register (CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . .Figures B−250 B−251 B−252 B−253 B−254 B−255 B−256 B−257 B−258 B−259 B−260 B−261 B−262 B−263 B−264 B−265 B−266 B−267 B−268 B−269 B−270 B−271 B−272 B−273 B−274 B−275 B−276 B−277 B−278 B−279 B−280 B−281 B−282 B−283 B−284 B−285 B−286 B−287 B−288 B−289 B−290 B−291 B−292 B−293 PLL Controller Divider Register (PLLDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Input Configuration Register 2 (TCPIC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Interrupt Pending Register (EIPR) . . . . Oscillator Divider 1 Register (OSCDIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Output Register 1 (VCPOUT1) . . . . . . . . . . . . . . . . TCP Output Parameter Register (TCPOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Endian Register (TCPEND) . . . . . . . . . . . . . . . TCP Input Configuration Register 1 (TCPIC1) . . .

. . Video Display Field 2 Timing Register (VDFLDT2) . . . . . Video Capture Channel B Control Register (VCBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCBEVTCT) . . . . . . . . . . . Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 1 Image Offset Register (VDIMGOFF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSI System Time Clock LSB Register (TSISTCLKL) . . . . . . . . . . . . . . . . Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Capture Channel x Threshold Register (VCATHRLD. . . . . . . . . . . . . . TSI Clock Initialization MSB Register (TSICLKINITM) . . . . . . . . . . . . . . . . . . . . . . . Video Display Control Register (VDCTL) . B-412 B-414 B-417 B-418 B-421 B-429 B-431 B-436 B-438 B-439 B-440 B-441 B-444 B-445 B-446 B-451 B-453 B-454 B-455 B-456 B-457 B-458 B-459 B-460 B-461 B-463 B-465 B-470 B-471 B-473 B-474 B-476 B-477 B-479 B-480 B-481 B-483 B-484 B-485 B-486 B-488 B-489 B-490 B-491 . Video Port Control Register (VPCTL) . . . . . . . Video Display Threshold Register (VDTHRLD) . . . . . TSI System Time Clock Compare LSB Register (TSISTCMPL) . . . . . . . . . Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) . . . . Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) . . . . . . . . . . . . . . . . . . . . . . . . . . Video Capture Channel x Event Count Register (VCAEVTCT. . . . . . . . Video Capture Channel x Vertical Interrupt Register (VCAVINT. . . . Video Port Status Register (VPSTAT) . . . . . . Video Capture Channel x Field 2 Start Register (VCASTRT2. . . TSI System Time Clock Compare MSB Register (TSISTCMPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 2 Image Size Register (VDIMGSZ2) . . . . . . . . . . . . . . . . . . . . Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) . . . . . Video Display Horizontal Blanking Register (VDHBLNK) . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCBSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCBSTRT1) . . . . Video Display Field 1 Timing Register (VDFLDT1) . . . . . . . . . . . . . . . . . Video Display Frame Size Register (VDFRMSZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSI Capture Control Register (TSICTL) . . . . Video Capture Channel x Field 2 Stop Register (VCASTOP2. . . . . . . . . . . . . . . Video Display Field 2 Image Offset Register (VDIMGOFF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCBVINT) . . . . . . . . . . . . . . . . Video Display Field 1 Image Size Register (VDIMGSZ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Capture Channel x Field 1 Start Register (VCASTRT1. . . . . . . TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSI Clock Initialization LSB Register (TSICLKINITL) . . . . . . . . Video Port Interrupt Enable Register (VPIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCBTHRLD) . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Horizontal Synchronization Register (VDHSYNC) . . . . Video Port Interrupt Status Register (VPIS) . . TSI System Time Clock MSB Register (TSISTCLKM) . . . . . . . . . . . . . . . . . . . . . . . TSI System Time Clock Ticks Interrupt Register (TSITICKS) . Video Display Status Register (VDSTAT) . . . . . . . . . . . . . . . . . . . VCBSTOP1) . . . . . . . . . . . . . . . . Video Capture Channel x Field 1 Stop Register (VCASTOP1. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) . . . TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCBSTRT2) . . . . . . . . . . . . . . . . . Video Capture Channel x Status Register (VCASTAT. . . . . . . . . . . . . . . . . . . . .Figures B−294 B−295 B−296 B−297 B−298 B−299 B−300 B−301 B−302 B−303 B−304 B−305 B−306 B−307 B−308 B−309 B−310 B−311 B−312 B−313 B−314 B−315 B−316 B−317 B−318 B−319 B−320 B−321 B−322 B−323 B−324 B−325 B−326 B−327 B−328 B−329 B−330 B−331 B−332 B−333 B−334 B−335 B−336 B−337 xxiv VIC Clock Divider Register (VICDIV) . . . . . . . . . . . . . . Video Capture Channel A Control Register (VCACTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCBSTOP2) . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Pin Interrupt Enable Register (PIEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Default Display Value Register (VDDEFVAL) . . . . . Video Display Clipping Register (VDCLIP) . . . . . . . . . . . . . . . . . . Video Port Pin Direction Register (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-492 B-493 B-494 B-495 B-496 B-497 B-498 B-499 B-501 B-502 B-505 B-506 B-508 B-510 B-513 B-515 B-517 B-519 B-521 B-523 B-525 B-527 B-529 B-531 B-533 B-535 B-535 B-536 B-536 Contents xxv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Figures B−338 B−339 B−340 B−341 B−342 B−343 B−344 B−345 B−346 B−347 B−348 B−349 B−350 B−351 B−352 B−353 B−354 B−355 B−356 B−357 B−358 B−359 B−360 B−361 B−362 B−363 B−364 B−365 B−366 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) . . . . . . . . . . . . . . . . . . Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expansion Bus Host Port Interface Control Register (XBHC) . . . . . . . . . . . . . . . . Video Port Pin Interrupt Clear Register (PICLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expansion Bus External Address Register (XBEA) . . Video Display Counter Reload Register (VDRELOAD) . Video Port Pin Function Register (PFUNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Pin Data Clear Register (PDCLR) . . . . . Video Port Pin Interrupt Polarity Register (PIPOL) . . . . . . . . . . . Video Port Pin Interrupt Status Register (PISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Pin Data Output Register (PDOUT) . . . . . . . . . . . . Expansion Bus Global Control Register (XBGC) . . . . . . . Expansion Bus XCE Space Control Register (XCECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expansion Bus Data Register (XBD) . . . . . . . . Video Port Pin Data Input Register (PDIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Pin Data Set Register (PDSET) . . . . . . Video Port Peripheral Control Register (PCR) . . . . . . . . . . . . . . . . . . . . Video Port Peripheral Identification Register (VPPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expansion Bus Internal Slave Address Register (XBISA) . . . . . . . . . . . Expansion Bus Internal Master Address Register (XBIMA) . . . . . . . . . . Video Display Vertical Interrupt Register (VDVINT) . . . . . . . . . . . . . . . . . . . . . . . . Video Display Display Event Register (VDDISPEVT) . . . . . . . . . . . . . . . . . . . . . . Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field Bit Register (VDFBIT) . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 EDMA Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 EMIFA/EMIFB APIs . . . . . . . . . . 2-4 CACHE Macros that Construct Register and Field Values . 7-2 EDMA APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 EMIFA/EMIFB Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 DMA APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 EMIF APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 CSL Data Types . . . . . . . . . . . . . . . 9-2 EMIF Macros that Access Registers and Fields . . . . 1-3 CSL Naming Conventions . . . . . . 5-2 DMA Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 CHIP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 CSL API Module Support for TMS320C641x and DM64x Devices . . . . . . . . . . . . . . 1-6 Generic CSL Functions . . . . . . . 1-12 CSL API Module Support for TMS320C6000 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 EMAC APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 CHIP APIs . . . . . . . . . . . . . . . . . . . . . . 4-2 DAT APIs . . . . . . . . . . . . . . . . . . . . . . 1-16 CSL Device Support Library Name and Symbol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 CACHE Macros that Access Registers and Fields . . . . . . . . . . . . . 8-4 EMAC Macros that Construct Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 EDMA Configuration Structure . . . . . . . . . . . . . 1-17 CACHE APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 . . . . . . . . . . 1-11 Generic CSL Symbolic Constants . . . . . . . . . . . . . . . . 8-2 EMAC Macros That Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Generic CSL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 CSL API . . . . . . . . . . . . . . . . . . . . . . 7-2 EDMA Macros That Access Registers and Fields . . . . . . . . . .Tables Tables 1−1 1−2 1−3 1−4 1−5 1−6 1−7 1−8 1−9 1−10 2−1 2−2 2−3 3−1 3−2 3−3 4−1 5−1 6−1 6−2 6−3 6−4 7−1 7−2 7−3 7−4 8−1 8−2 8−3 8−4 9−1 9−2 9−3 9−4 10−1 10−2 xxvi CSL Modules and Include Files . . . . . . . . . . . . 7-6 EMAC Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 EMIF Macros that Construct Register and Field Values . . . . . . 3-2 CHIP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 EMIF Configuration Structure . . . . . . . . . . . . . . 6-2 DMA Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 DMA Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Generic CSL Handle-Based Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Configuration Structure . . . . . . . . . . . . . . TCP Macros that Construct Register and Field Values . . . . . . . . . . . . . I2C APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . IRQ Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tables 10−3 10−4 11−1 11−2 11−3 11−4 12−1 12−2 12−3 13−1 13−2 13−3 13−4 14−1 14−2 14−3 14−4 15−1 15−2 15−3 15−4 16−1 16−2 16−3 16−4 17−1 17−2 17−3 18−1 18−2 18−3 18−4 19−1 19−2 19−3 19−4 20−1 20−2 20−3 20−4 21−1 21−2 21−3 21−4 EMIFA/EMIFB Macros that Access Registers and Fields . . . . . . . . . . . . . . . MDIO Macros That Access Registers and Fields . I2C Macros that Construct Register and Field Values . . . . IRQ APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Configuration Structure . . . . . . . . . . . . IRQ Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . GPIO Macros that Construct Register and Field Values . . . . PLL APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP APIs . . . . . . TCP Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents 10-3 10-4 11-2 11-2 11-5 11-6 12-2 12-3 12-4 13-2 13-2 13-5 13-6 14-2 14-2 14-4 14-5 15-2 15-2 15-5 15-6 16-2 16-2 16-5 16-6 17-2 17-3 17-3 18-2 18-2 18-4 18-5 19-2 19-2 19-4 19-5 20-2 20-2 20-3 20-4 21-2 21-2 21-7 21-7 xxvii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . EMIFA/EMIFB Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP APIs . . . . . . . . . PCI Macros that Access Registers and Fields . . . . . . . . . . . PWR Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWR Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP Macros that Construct Register and Field Values . . . McASP Macros that Access Registers and Fields . . . . . . . . . . . PLL Macros that Access Registers and Fields . . . HPI Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWR Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWR APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI APIs . . . . . . . . . . . . . PLL Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP APIs . . . . . . . . . . . . . . TCP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . 27-2 XBUS APIs . . . . . . . . . . . . . . . . . . . . . . . . 22-4 TIMER Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 XBUS Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 VIC Macros That Access Registers and Fields . . . . . . . 24-5 VCP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 XBUS Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 L2 Writeback Base Address Register (L2WBAR) Field Values . . . . . . . . . . . . . B-8 L1P Invalidate Base Address Register (L1PIBAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16 . . . . . . . . . . . . . . . . . . . 25-3 VIC Macros That Construct Register and Field Values . . . . . . . . . . . . . . . . . . . 28-5 CSL Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15 L2 Memory Attribute Registers (MAR128−MAR191) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Cache Configuration Register (CCFG) Field Values . . . . . . . . . . . . . . . . . . . 26-2 VP APIs and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 L2 Writeback−Invalidate Base Address Register (L2WIBAR) Field Values . . . . . . . B-6 L2 Writeback−Invalidate Word Count Register (L2WIWC) Field Values . . . . . . . 22-2 TIMER Macros that Access Registers and Fields . . . . A-7 Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 L2 Allocation Registers (L2ALLOC0−L2ALLOC3) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 L2 EDMA Access Control Register (EDMAWEIGHT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 XBUS Configuration Structure . . . . . . . B-10 L1D Invalidate Base Address Register (L1DIBAR) Field Values . . B-9 L1P Invalidate Word Count Register (L1PIWC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9 L1D Writeback−Invalidate Base Address Register (L1DWIBAR) Field Values . . . . . . . . . . . . . . . . . . . B-7 L2 Invalidate Word Count Register (L2IWC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . B-12 L2 Writeback−Invalidate All Register (L2WBINV) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 TIMER APIs . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 L2 Writeback Word Count Register (L2WWC) Field Values . . . . . . . . . . . . . . . . 23-2 UTOPIA APIs . . . . . . . . . . . . . . . . . . . . . . . . . B-11 L1D Invalidate Word Count Register (L1DIWC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 VCP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 VIC Functions and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13 L2 Memory Attribute Registers (MAR0−MAR15) Field Values . . . . . . . . . . . . . . . . . . . . . . . . 23-2 UTOP Macros that Access Registers and Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tables 22−1 22−2 22−3 22−4 23−1 23−2 23−3 23−4 24−1 24−2 24−3 24−4 25−1 25−2 25−3 26−1 26−2 27−1 27−2 27−3 27−4 28−1 A−1 B−1 B−2 B−3 B−4 B−5 B−6 B−7 B−8 B−9 B−10 B−11 B−12 B−13 B−14 B−15 B−16 B−17 B−18 B−19 B−20 B−21 xxviii TIMER Configuration Structure . . . . . . . . . . . . . . . . . 24-2 VCP APIs . . . . . . . . . . . . . . . . 23-4 UTOP Macros that Construct Register and Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10 L1D Writeback−Invalidate Word Count Register (L1DWIWC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 UTOPIA Configuration Structure . . . . . . . . . . 27-3 CSL HAL Macros . . . . . . . . . 25-3 Configuration Structures (Macros) . . . . . . . . . . . B-7 L2 Invalidate Base Address Register (L2IBAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 VCP Configuration Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11 L2 Writeback All Register (L2WB) Field Values . . . . . . . . B-14 L2 Memory Attribute Registers (MAR96−MAR111) Field Values . .

. . . . . . . . . . . . . EDMA Event Selector Register 0 (ESEL3) Field Values . . . . EDMA Channel Interrupt Enable High Register (CIERH) Field Values . . . . . . EDMA Event Low Register (EERL) Field Values . . . . EDMA Channel Destination Address Register (DST) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . .Tables B−22 B−23 B−24 B−25 B−26 B−27 B−28 B−29 B−30 B−31 B−32 B−33 B−34 B−35 B−36 B−37 B−38 B−39 B−40 B−41 B−42 B−43 B−44 B−45 B−46 B−47 B−48 B−49 B−50 B−51 B−52 B−53 B−54 B−55 B−56 B−57 B−58 B−59 B−60 B−61 B−62 B−63 B−64 B−65 DMA Registers . . . . . . . . . . . . . . . EDMA Channel Chain Enable Register (CCER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Source Address Register (SRC) Field Values . . . . . . . . . . . . . . . . . . . . . . Priority Queue Status Register (PQSR) Field Values . . . . . . . . . . . . . . . Priority Queue Status Register (PQSR) Field Values . . . . EDMA Channel Chain Enable High Register (CCERH) Field Values . . . . . . . . . . . . . . . . . . . . EDMA Event Enable High Register (EERH) Field Values . . . . . . . . . . . . . . . EDMA Event Set Low Register (ESRL) Field Values . . . . . . . . . . . . . . DMA Auxiliary Control Register (AUXCTL) Field Values . . . . . EDMA Channel Count Reload/Link Register (RLD) Field Values . . . . . . . . . . DMA Channel Primary Control Register (PRICTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents B-17 B-18 B-19 B-24 B-28 B-28 B-29 B-29 B-30 B-30 B-31 B-33 B-36 B-37 B-37 B-38 B-38 B-39 B-40 B-41 B-42 B-43 B-43 B-44 B-45 B-45 B-46 B-47 B-47 B-48 B-49 B-49 B-50 B-51 B-51 B-52 B-53 B-53 B-54 B-55 B-55 B-56 B-57 B-57 xxix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Global Index Register (GBLIDX) Field Values . . . . . . . EDMA Event Set Register (ESR) Field Values . . . . . . . . . . . . . . DMA Global Count Reload Register (GBLCNT) Field Values . . . . . . . . . . . . . . . . . . . . EDMA Event Register (ER) Field Values . . . . EDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Clear Register (ERC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Pending High Register (CIPRH) Field Values . . . . . . . . . . . . . . . . Priority Queue Allocation Register (PQAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Global Address Reload Register (GBLADDR) Field Values . . . . . . . . . . . . . . . DMA Channel Source Address Register (SRC) Field Values . . . . . . . . . . . . . . EDMA Event Selector Register 0 (ESEL0) Field Values . . . . . . . . . DMA Channel Transfer Counter Register (XFRCNT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Clear High Register (ECRH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event High Register (ERH) Field Values . . . . . . . . . . . . . . EDMA Channel Interrupt Enable Low Register (CIERL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Clear Low Register (ERCL) Field Values . . . . . . . . . . . C621x/C671x: Channel Interrupt Enable Register (CIER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Set High Register (ESRH) Field Values . . . . . . . . . . . . . . . . . . . . . EDMA Event Selector Register 0 (ESEL1) Field Values . . . . . DMA Channel Destination Address Register (DST) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Options Register (OPT) Field Values . . . . . . . . . . . . EDMA Event Enable Register (EER) Field Values . . . . . . . . DMA Channel Secondary Control Register (SECCTL) Field Values . . . . . . . . . . . . . . . . . . . . EDMA Channel Chain Enable Low Register (CCERL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Index Register (IDX) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Pending Register (CIPR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Event Low Register (ERL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Interrupt Pending Low Register (CIPRL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Channel Transfer Count Register (CNT) Field Values . . . . . . . . .

. . . . . . . . . . . . . . . . . . . B-73 Receive Unicast Set Register (RXUNICASTSET) Field Values . . . . . . . . . . . . . B-85 Receive Channel n Free Buffer Count Registers (RXnFREEBUFFER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . B-68 Transmit Teardown Register (TXTEARDOWN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-78 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-82 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Values . . . B-113 . . . . . . . . . . B-59 EMAC Control Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-63 EMAC Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-72 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Values . . . . . . . . . . . . . . . . B-108 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B-107 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Values . . . . . . . . . . B-111 MAC Address Hash 1 Register (MACHASH1) Field Values . . . . .Tables B−66 B−67 B−68 B−69 B−70 B−71 B−72 B−73 B−74 B−75 B−76 B−77 B−78 B−79 B−80 B−81 B−82 B−83 B−84 B−85 B−86 B−87 B−88 B−89 B−90 B−91 B−92 B−93 B−94 B−95 B−96 B−97 B−98 B−99 B−100 B−101 B−102 B−103 B−104 B−105 B−106 xxx EDMA Event Polarity Low Register (EPRL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-97 MAC Input Vector Register (MACINVECTOR) Field Values . . . B-67 Transmit Control Register (TXCONTROL) Field Values . B-104 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Values . . . B-101 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Values . . . . . . . . . B-62 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Values . . B-84 Receive Channel n Flow Control Threshold Registers ( RXnFLOWTHRESH) Field Values . . . . . . . . . . . . . . . . . . B-58 EDMA Event Polarity High Register (EPRH) Field Values . . . . . . B-112 MAC Address Hash 2 Register (MACHASH2) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B-106 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-61 EMAC Control Module Interrupt Control Register (EWCTL) Field Values . . . . . . . . . . . . B-69 Receive Identification and Version Register (RXIDVER) Field Values . . B-102 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Values . . . . . B-83 Receive Filter Low Priority Packets Threshold Register (RXFILTERLOWTHRESH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70 Receive Control Register (RXCONTROL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60 EMAC Control Module Transfer Control Register (EWTRCTRL) Field Values . . . . . . B-99 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . B-110 MAC Address High Bytes Register (MACADDRH) Field Values . . . . . . . . . . . . . . B-94 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Values . B-87 MAC Status Register (MACSTATUS) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-80 Receive Maximum Length Register (RXMAXLEN) Field Values . . . . . . B-90 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-86 MAC Control Register (MACCONTROL) Field Values . . . . . . . . . . . B-93 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Values . . . . . B-109 MAC Address Channel n Lower Byte Register (MACADDRLn) Field Values . B-95 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Values . . . . B-71 Receive Teardown Register (RXTEARDOWN) Field Values . . . . . . . . . . . . B-64 Transmit Identification and Version Register (TXIDVER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . B-110 MAC Address Middle Byte Register (MACADDRM) Field Values . . . . . . . . . . . . . B-100 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Values . . . . . . . . . . . . . . . . . . . .

. . . . . . B−146 I2C Status Register (I2CSTR) Field Values . . . . . . . . . . . . . . . . . . . B−122 EMIF CE Space Secondary Control Register (CESEC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−114 Receive Channel n Interrupt Acknowledge Register (RXnINTACK) Field Values . . . . . . . . . . . . . . . . B−119 EMIF CE Space Control Register (CECTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−144 I2C Own Address Register (I2COAR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−118 EMIF Global Control Register (GBLCTL) Field Values . . . . B−120 EMIF CE Space Control Register (CECTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B−116 EMIF Global Control Register (GBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . B−135 GPIO Delta Low Register (GPDL) Field Values . . . . B−126 EMIF SDRAM Timing Register (SDTIM) Field Values . . . . . . . B−108 Transmit Pacing Test Register (TPACETEST) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−121 EMIF CE Space Control Register (CECTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−136 GPIO Low Mask Register (GPLM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−117 EMIF Global Control Register (GBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−129 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−138 GPIO Interrupt Polarity Register (GPPOL) Field Values . . . . . . . . . . . . . . . . . . . B−110 Transmit Pause Timer Register (TXPAUSE) Field Values . . B−130 GPIO Enable Register (GPEN) Field Values . . . . . . B−145 I2C Interrupt Enable Register (I2CIER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−143 I2C Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−147 I2C Clock Low-Time Divider Register (I2CCLKL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B−139 HPI Registers for C62x/C67x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−131 GPIO Direction Register (GPDIR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−115 EMIF Registers . . . . . . . B−137 GPIO Global Control Register (GPGC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−127 EMIF SDRAM Extension Register (SDEXT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−111 . . . . . . . . . . . . . . . . . . . B−141 HPI Control Register (HPIC) Field Values . . . . . . . . . . . . . . . . . . . . . . . B−125 EMIF SDRAM Control Register (SDCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−140 HPI Registers for C64x DSP . . . . . . . . . . . . . . . . . . . . . . . . Contents B-114 B-115 B-116 B-117 B-118 B-118 B-119 B-120 B-122 B-123 B-126 B-128 B-131 B-133 B-135 B-137 B-139 B-141 B-143 B-145 B-146 B-148 B-149 B-150 B-150 B-151 B-152 B-153 B-154 B-155 B-156 B-158 B-159 B-159 B-165 B-167 B-168 B-169 B-170 B-172 B-178 xxxi . . . . . . . . . . . . . . . . . . . .Tables B−107 Backoff Test Register (BOFFTEST) Field Values . . . . . . . . B−132 GPIO Value Register (GPVAL) Field Values . . . . . . . . . B−112 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−134 GPIO High Mask Register (GPHM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Values . . . . . . . . . . . B−113 Transmit Channel n Interrupt Acknowledge Register (TXnINTACK) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−142 HPI Transfer Request Control Register (TRCTL) Field Values . . . . B−133 GPIO Delta High Register (GPDH) Field Values . . . . . . . B−123 EMIF SDRAM Control Register (SDCTL) Field Values . . . . . . . . . . . . . . . . . . B−109 Receive Pause Timer Register (RXPAUSE) Field Values . . . . . . . . . . . . . . . B−124 EMIF SDRAM Control Register (SDCTL) Field Values . B−128 EMIF Peripheral Device Transfer Control Register (PDTCTL) Field Values . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . I2C Data Count Register (I2CCNT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-178 B-179 B-180 B-181 B-182 B-183 B-189 B-189 B-191 B-192 B-193 B-194 B-195 B-196 B-197 B-198 B-200 B-201 B-202 B-203 B-204 B-205 B-206 B-207 B-211 B-212 B-213 B-215 B-217 B-220 B-222 B-224 B-226 B-228 B-231 B-234 B-235 B-236 B-238 B-239 B-242 B-244 B-245 B-247 . . . . . . . . . . . . . . . . . . . . STT. . . . . . . . . . . . I2C Peripheral Identification Register 2 (I2CPID2) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Direction Register (PDIR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIT Mode Control Register (DITCTL) Field Values . I2C Prescaler Register (I2CPSC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Direction Register (I2CPDIR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Mode Register (I2CMDR) Field Values . . . . . Pin Data Output Register (PDOUT) Field Values . . . . I2C Pin Function Register (I2CPFUNC) Field Values . . . . . . . . . . . . . . . . . . . Global Control Register (GBLCTL) Field Values . . . . . . . . . . . . . . . . How the MST and FDF Bits Affect the Role of TRX Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Slave Address Register (I2CSAR) Field Values . . . . . . . . Receive Frame Sync Control Register (AFSRCTL) Field Values . . . . . . . . . . . . . . . . McASP Registers Accessed Through Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tables B−148 B−149 B−150 B−151 B−152 B−153 B−154 B−155 B−156 B−157 B−158 B−159 B−160 B−161 B−162 B−163 B−164 B−165 B−166 B−167 B−168 B−169 B−170 B−171 B−172 B−173 B−174 B−175 B−176 B−177 B−178 B−179 B−180 B−181 B−182 B−183 B−184 B−185 B−186 B−187 B−188 B−189 B−190 B−191 xxxii I2C Clock High-Time Divider Register (I2CCLKH) Field Values . . . . . . . . . . . External Interrupt Polarity Register (EXTPOL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Bit Stream Format Register (RFMT) Field Values . . . . . Pin Function Register (PFUNC) Field Values . . . . . . . . . I2C Peripheral Identification Register 1 (I2CPID1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Identification Register (PID) Field Values . . . . . . . . . . . . . . . . . . . . Receiver Global Control Register (RGBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Data Input Register (I2CPDIN) Field Values . . . . Interrupt Multiplexer Low Register (MUXL) Field Values . . . . . . . . . . . . . . . . . and STP Bits . . . . . Receive Format Unit Bit Mask Register (RMASK) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Registers . . . . . . . . . . . . . . . . . . . . I2C Extended Mode Register (I2CEMDR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Data Clear Register (PDCLR) Field Values . Pin Data Input Register (PDIN) Field Values . . . . . . . . . . . . . . . Power Down and Emulation Management Register (PWRDEMU) Field Values . . . . . . . . . . . . . . . . McASP Registers Accessed Through Configuration Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Data Transmit Register (I2CDXR) Field Values . . . . . . Digital Loopback Control Register (DLBCTL) Field Values . . . . . . . . . . . . . . Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Values . . . . . . . . . . . . . . . . . Master-Transmitter/Receiver Bus Activity Defined by RM. . . . . . . . . . Interrupt Multiplexer High Register (MUXH) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Data Receive Register (I2CDRR) Field Values . . . . . . . . . I2C Pin Data Output Register (I2CPDOUT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . Audio Mute Control Register (AMUTE) Field Values . . . . . . I2C Pin Data Set Register (I2CPDSET) Field Values . . . . . . . . . . . . . . . Pin Data Set Register (PDSET) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Pin Data Clear Register (I2CPDCLR) Field Values . . . . . . . . . . . . . Receive Clock Control Register (ACLKRCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive TDM Time Slot Register (RTDM) Field Values . . . . . . . . . . . . . . . . . . I2C Interrupt Source Register (I2CISRC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Clock Check Control Register (XCLKCHK) Field Values . . . . . . MDIO Version Register (VERSION) Field Values . . . . . . . . . . . . . . . . . . Contents B-248 B-250 B-253 B-254 B-256 B-257 B-260 B-261 B-264 B-266 B-267 B-269 B-270 B-273 B-275 B-276 B-278 B-279 B-284 B-284 B-285 B-286 B-290 B-294 B-296 B-299 B-301 B-305 B-306 B-307 B-308 B-309 B-310 B-311 B-312 B-313 B-315 B-316 B-317 B-318 B-319 B-320 xxxiii . . . . . . . . . . . . Data Transmit Register (DXR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Values . Current Receive TDM Time Slot Register (RSLOT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Status Register (RSTAT) Field Values . . Serial Port Control Register (SPCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Transmit TDM Time Slot Register (XSLOT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . Receive Clock Check Control Register (RCLKCHK) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Frame Sync Control Register (AFSXCTL) Field Values . . . . . .Tables B−192 B−193 B−194 B−195 B−196 B−197 B−198 B−199 B−200 B−201 B−202 B−203 B−204 B−205 B−206 B−207 B−208 B−209 B−210 B−211 B−212 B−213 B−214 B−215 B−216 B−217 B−218 B−219 B−220 B−221 B−222 B−223 B−224 B−225 B−226 B−227 B−228 B−229 B−230 B−231 B−232 B−233 Receiver Interrupt Control Register (RINTCTL) Field Values . . . . . Transmit TDM Time Slot Register (XTDM) Field Values . . . . . . . . . . . . . . . . . . MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Values . . . . . . . Transmit Bit Stream Format Register (XFMT) Field Values . . . . . . . . . Transmit Clock Control Register (ACLKXCTL) Field Values . . . . . . . . Serializer Control Registers (SRCTLn) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Link Status Change Interrupt Register (LINKINTRAW) Field Values . . . . . . . . . . . Pin Control Register (PCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Enable Bits in RCEREn for a 128-Channel Data Stream . . . . . . . . . . . . . . McBSP Registers . . Transmit Control Register (XCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO User Command Complete Interrupt Register (USERINTRAW) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO PHY Link Status Register (LINK) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Global Control Register (XGBLCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Control Register (RCR) Field Values . . . . . . . . . . . . . . . . . . . . . Transmitter DMA Event Control Register (XEVTCTL) Field Values . Enhanced Transmit Channel Enable Registers (XCERE0−3) Field Values . . . . Receive Channel Enable Register (RCER) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Channel Enable Register (XCER) Field Values . . . . . . . . . . . . . . . . . MDIO Control Register (CONTROL) Field Values . . . . . . . . . . . . . . . . . . Enhanced Receive Channel Enable Registers (RCERE0−3) Field Values . . . . Transmitter Interrupt Control Register (XINTCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Status Register (XSTAT) Field Values . . . . . . . . . . . . Transmit Format Unit Bit Mask Register (XMASK) Field Values . MDIO PHY Alive Indication Register (ALIVE) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Control Register (MCR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Module Registers . . . . . . . Channel Enable Bits in XCEREn for a 128-Channel Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver DMA Event Control Register (REVTCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Receive Register (DRR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Rate Generator Register (SRGR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . B−247 PCI Master Control Register (PCIMC) Field Values . . . . . . . . . . . B−266 TCP Input Configuration Register 2 (TCPIC2) Field Values . . . . . . . . . . . . . . B−260 PLL Controller Divider Register (PLLDIV) Field Values . . . . . . . . . . . B−268 TCP Input Configuration Register 4 (TCPIC4) Field Values . . . . . . B−258 PLL Control/Status Register (PLLCSR) Field Values . . . B−275 TCP Input Configuration Register 11 (TCPIC11) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−249 Current PCI Address Register (CPCIA) Field Values . . . . . . . . . . . . . . . . . . . . . . . B−248 Current DSP Address (CDSPA) Field Values . . . . B−259 PLL Multiplier Control Register (PLLM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−246 PCI Master Address Register (PCIMA) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−236 MDIO User Access Register 0 (USERACCESS0) Field Values . . . . . . . . . B−245 DSP Master Address Register (DSPMA) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−265 TCP Input Configuration Register 1 (TCPIC1) Field Values . B−243 PCI Interrupt Source Register (PCIIS) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−244 PCI Interrupt Enable Register (PCIIEN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−262 Power-Down Control Register (PDCTL) Field Values . B−256 PLL Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−257 PLL Controller Peripheral Identification Register (PLLPID) Field Values . . . . . . . . B−263 TCP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−264 TCP Input Configuration Register 0 (TCPIC0) Field Values . . . . . . . . . . . . . . . . . . . . . .Tables B−234 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Values . . B−252 EEPROM Data Register (EEDAT) Field Values . . . . . . . . . . B−240 PCI Memory-Mapped Registers . . . . . . . . . . . . B−251 EEPROM Address Register (EEADD) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−255 PCI Transfer Request Control Register (TRCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−271 TCP Input Configuration Register 7 (TCPIC7) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−241 DSP Reset Source/Status Register (RSTSRC) Field Values . . . . . . . . B−273 TCP Input Configuration Register 9 (TCPIC9) Field Values . . . B−269 TCP Input Configuration Register 5 (TCPIC5) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−242 Power Management DSP Control/Status Register (PMDCSR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−267 TCP Input Configuration Register 3 (TCPIC3) Field Values . . . . . . . B−235 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Values . . . . . . . . . . . . . . . . . . B−261 Oscillator Divider 1 Register (OSCDIV1) Field Values . . . . B−274 TCP Input Configuration Register 10 (TCPIC10) Field Values . . B−254 PCI Transfer Halt Register (HALT) Field Values . . . . . . . . . . . . . . . . B−253 EEPROM Control Register (EECTL) Field Values . . . . . . . . . . . . . . . . . . B−237 MDIO User Access Register 1 (USERACCESS1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−270 TCP Input Configuration Register 6 (TCPIC6) Field Values . . . . . . B−239 MDIO User PHY Select Register 1 (USERPHYSEL1) Field Values . . . . . . . . . . xxxiv B-321 B-322 B-323 B-325 B-326 B-327 B-328 B-329 B-332 B-335 B-338 B-341 B-342 B-343 B-344 B-344 B-345 B-346 B-347 B-348 B-350 B-352 B-353 B-354 B-355 B-356 B-357 B-358 B-359 B-360 B-361 B-363 B-364 B-365 B-366 B-367 B-369 B-370 B-371 B-372 B-373 B-374 . . . . . . . . . . . . B−272 TCP Input Configuration Register 8 (TCPIC8) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−250 Current Byte Count Register (CCNT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B−238 MDIO User PHY Select Register 0 (USERPHYSEL0) Field Values . . . .

. . . . . . . . . . . . . . . . . . . . TCP Error Register (TCPERR) Field Values . . . . . . . . . . Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Input Configuration Register 3 (VCPIC3) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Input Configuration Register 4 (VCPIC4) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Output Register 0 (VCPOUT0) Field Values . . . . . . . VCP Input Configuration Register 0 (VCPIC0) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Capture Channel x Status Register (VCxSTAT) Field Values . . . TCP Status Register (TCPSTAT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIC Clock Divider Register (VICDIV) Field Values . . . . . . . . TCP Execution Register (TCPEXE) Field Values . . . . . . . Video Port Operating Mode Selection . UTOPIA Control Register (UCR) Field Values . . . . . VCP Error Register (VCPERR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents B-375 B-376 B-377 B-378 B-380 B-382 B-383 B-385 B-385 B-386 B-387 B-389 B-390 B-391 B-393 B-394 B-396 B-397 B-398 B-399 B-399 B-400 B-401 B-402 B-403 B-404 B-405 B-406 B-407 B-408 B-409 B-410 B-411 B-412 B-413 B-414 B-416 B-417 B-418 B-421 B-427 B-429 B-431 B-437 xxxv . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Count Register (CNT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Interrupt Enable Register (UIER) Field Values . . . . . . . . Timer Control Register (CTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Capture Channel A Control Register (VCACTL) Field Values . . . . . . . . . . . . . VIC Input Register (VICIN) Field Values . . . . . . . Timer Period Register (PRD) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Bus Accesses Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Capture Control Registers . . . . . . . . VCP Status Register 0 (VCPSTAT0) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Output Register 1 (VCPOUT1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Interrupt Pending Register (EIPR) Field Values . . . . . . . . . . Video Port Control Register (VPCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Interrupt Pending Register (UIPR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Endian Mode Register (VCPEND) Field Values . . . . . . . . . . . . . . . . . . . . . . . VIC Control Register (VICCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Interrupt Enable Register (VPIE) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP Execution Register (VCPEXE) Field Values . . . . . . . . . . . VCP Input Configuration Register 2 (VCPIC2) Field Values . . . . . . . . . . . . VCP Input Configuration Register 1 (VCPIC1) Field Values . . . . . . . . . . . . . .Tables B−276 B−277 B−278 B−279 B−280 B−281 B−282 B−283 B−284 B−285 B−286 B−287 B−288 B−289 B−290 B−291 B−292 B−293 B−294 B−295 B−296 B−297 B−298 B−299 B−300 B−301 B−302 B−303 B−304 B−305 B−306 B−307 B−308 B−309 B−310 B−311 B−312 B−313 B−314 B−315 B−316 B−317 B−318 B−319 TCP Output Parameter Register (TCPOUT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Registers . . . . . . . Video Port Control Registers . . . . . . . . Video Port Status Register (VPSTAT) Field Values . . . . . . . . VCP Status Register 1 (VCPSTAT1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCP Endian Register (TCPEND) Field Values . . . . . . VIC Port Registers . . . . . . . . . . . . . . . . . VCP Input Configuration Register 5 (VCPIC5) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Detect Register (CDR) Field Values . . . . . . Error Interrupt Enable Register (EIER) Field Values . . . . . . . . . . . . . . . . . . . . . Video Port Interrupt Status Register (VPIS) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . Video Display Counter Reload Register (VDRELOAD) Field Values . . . . Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Values . . . . . . . . . . . . . . . . . . . . . . . Video Capture Channel x Field 2 Stop Register (VCxSTOP2) Field Values . . . . . Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Clipping Register (VDCLIP) Field Values . . . . . . . . . . . . . . . . TSI System Time Clock Compare LSB Register (TSISTCMPL) Field Values . . . . . . . . . . . . . . . . . . . . Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Values . . . . . . . Video Display Threshold Register (VDTHRLD) Field Values . . . . . . . . . . . . . . TSI System Time Clock LSB Register (TSISTCLKL) Field Values . . . . . . . . . . . Video Display Display Event Register (VDDISPEVT) Field Values . . . . . . . . . . . . . . . . . . Video Display Frame Size Register (VDFRMSZ) Field Values . . . . . . . TSI Capture Control Register (TSICTL) Field Values . . . . . . . . TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) Field Values . . Video Display Horizontal Synchronization Register (VDHSYNC) Field Values . . . . . . . . . . . . . . . . . . TSI System Time Clock MSB Register (TSISTCLKM) Field Values . . . . . . . . . . . . . . . . . . . . . . Video Display Field 2 Image Size Register (VDIMGSZ2) Field Values . . . . . . . . . . . . . . . . . . Video Capture Channel B Control Register (VCBCTL) Field Values . . . . . . . . . . . . . . . . . . . . TSI Clock Initialization MSB Register (TSICLKINITM) Field Values . . . . . . . . . . . . . . . . . . Video Display Control Registers . . . . . . . . . . . . . . Video Capture Channel x Event Count Register (VCxEVTCT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tables B−320 B−321 B−322 B−323 B−324 B−325 B−326 B−327 B−328 B−329 B−330 B−331 B−332 B−333 B−334 B−335 B−336 B−337 B−338 B−339 B−340 B−341 B−342 B−343 B−344 B−345 B−346 B−347 B−348 B−349 B−350 B−351 B−352 B−353 B−354 B−355 B−356 B−357 B−358 B−359 B−360 xxxvi Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Field Values . . . . . . Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Capture Channel x Field 2 Start Register (VCxSTRT2) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Capture Channel x Threshold Register (VCxTHRLD) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 1 Timing Register (VDFLDT1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 2 Timing Register (VDFLDT2) Field Values . . . . . . . . . . . . . . . . . . . Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Field Values . . . . . . . Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Field Values . . . . . TSI System Time Clock Ticks Interrupt Register (TSITICKS) Field Values . . . . . . . . . . . Video Display Horizontal Blanking Register (VDHBLNK) Field Values . . . TSI Clock Initialization LSB Register (TSICLKINITL) Field Values . . . . . . . . Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Values . . . . . . . . . . . . . . . . . . Video Display Field 1 Image Size Register (VDIMGSZ1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . TSI System Time Clock Compare MSB Register (TSISTCMPM) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Control Register (VDCTL) Field Values . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) Field Values . . . . . . . . . . . TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) Field Values . . . . . . . Video Capture Channel x Vertical Interrupt Register (VCxVINT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Field Values . . . . . . . Video Display Status Register (VDSTAT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-438 B-439 B-440 B-442 B-444 B-445 B-446 B-451 B-453 B-454 B-455 B-456 B-457 B-458 B-459 B-460 B-461 B-462 B-464 B-465 B-470 B-472 B-473 B-475 B-476 B-478 B-479 B-480 B-482 B-483 B-484 B-485 B-487 B-488 B-489 B-490 B-491 B-492 B-493 B-494 B-495 . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . B-516 Video Port Pin Data Set Register (PDSET) Field Values . . . . . . . . . . . . . . . B-501 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Values . . . . . . . . . . . . . . B-504 Video Port Peripheral Identification Register (VPPID) Field Values . . . . . . . . . . B-533 Expansion Bus Internal Master Address Register (XBIMA) Field Values . . . . . . . . . . . . . . . . . B-505 Video Port Peripheral Control Register (PCR) Field Values . . . . . . . . B-528 Expansion Bus Registers . . . . . . . . . . . . . . . . . . . . . C-3 Contents xxxvii . . . . . . .Tables B−361 B−362 B−363 B−364 B−365 B−366 B−367 B−368 B−369 B−370 B−371 B−372 B−373 B−374 B−375 B−376 B−377 B−378 B−379 B−380 B−381 B−382 B−383 B−384 B−385 B−386 C−1 C−2 C−3 C−4 Video Display Default Display Value Register (VDDEFVAL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . B-503 Video Port GPIO Registers . . . . . . . . . . . . . . B-500 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-536 Expansion Bus Internal Slave Address Register (XBISA) Field Values . . . . . . . . . . . . . . . . . . . . . B-535 Expansion Bus External Address Register (XBEA) Field Values . B-531 Expansion Bus Host Port Interface Control Register (XBHC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Mapping of Old L2 Register Names to New L2 Register Names . . . . . . . . . B-507 Video Port Pin Function Register (PFUNC) Field Values . . . . . . . . B-510 Video Port Pin Data Input Register (PDIN) Field Values . . . . . . . . . . . . . B-508 Video Port Pin Direction Register (PDIR) Field Values . . . . . . . . B-529 Expansion Bus Global Control Register (XBGC) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-535 Expansion Bus Data Register (XBD) Field Values . . . . . . . . . . . . . . . . B-498 Video Display Field Bit Register (VDFBIT) Field Values . . . . . B-520 Video Port Pin Interrupt Enable Register (PIEN) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-536 CSL APIs for L2 Cache Operations . . . . . . . . . . . . . . . . . . . . . . . . . B-497 Video Display Vertical Interrupt Register (VDVINT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 CSL APIs for L1 Cache Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-514 Video Port Pin Data Out Register (PDOUT) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-522 Video Port Pin Interrupt Polarity Register (PIPOL) Field Values . . . . . . . . . . . . . . . . . . . . . . . . B-524 Video Port Pin Interrupt Status Register (PISTAT) Field Values . . . . . . . . . . . . . B-530 Expansion Bus XCE Space Control Register (XCECTL) Field Values . B-518 Video Port Pin Data Clear Register (PDCLR) Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-526 Video Port Pin Interrupt Clear Register (PICLR) Field Values . . . . . . . . . . . . . . . . . . . . . C-2 Mapping of New L2ALLOCx Bit Field Names to Old Bit Field Names (C64x only) . . . .

. . . . . . . . . . . . . . . Topic 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1. . . . . . . . . . . . . . . . . . . 1-12 Resource Management . . . . . . . . . .3 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Chapter 1 CSL Overview This chapter provides an overview of the chip support library (CSL). . 1-13 CSL API Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 CSL Naming Conventions . . . . . . . . . . . . . . 1-9 CSL Symbolic Constant Values . . . . . . . . . shows which TMS320C6000™ devices support the various application programming interfaces (APIs). . . 1-6 CSL Functions . . . . .1 1. . . . . . . . . . . . .7 1. . . . . . . . . . . . . . . . . . and lists each of the API modules. .8 Page CSL Introduction . . . . . . . . . . . . . . . . . . . .5 1. . . . . . . . . . . . . . . . . . . .4 1. . . . . . . . . . . . . . 1-15 1-1 . . . . . . . . . . . . . . . . . . . . . . . 1-7 CSL Macros . .6 1. . . . . . . . . . . . . . . . . . . . . 1-5 CSL Data Types . . . . . . . . . . .

2 CSL Architecture The CSL granularity is designed such that each peripheral is covered by a single API module.1 CSL Introduction The chip support library (CSL) provides a C-language interface for configuring and controlling on-chip peripherals. It consists of discrete modules that are built and archived into a library file. shortened development time.Symbolic Peripheral Descriptions As a side benefit to the creation of the CSL. Hence. 1-2 . and so on. . a complete symbolic description of all peripheral registers and register fields has been created.Basic Resource Management Basic resource management is provided through the use of Open and Close functions for many of the peripherals.CSL Introduction 1. a multichannel buffered serial port (McBSP) API module for the McBSP peripheral. and functions to implement the various operations of each peripheral. This is especially helpful for peripherals that support multiple channels. Specifically. the CSL offers: .Standard Protocol-to-Program Peripherals The CSL provides a standard protocol for programming the on-chip peripherals. You will find it advantageous to use the higher−level protocols described in the first two benefits. Each module relates to a single peripheral with the exception of several modules that provide general programming support. thus making it easier to migrate your code to newer versions of TI DSPs. and the CHIP module which allows the global setting of the chip. 1. because these are less device−specific. hardware abstraction. This includes data types and macros to define a peripheral’s configuration. . The symbolic constants used to program any peripheral are listed in its peripheral reference guide among the register descriptions.1 Benefits of the CSL The benefits of the CSL include peripheral ease of use.1. such as the interrupt request (IRQ) module which contains APIs for interrupt management. 1.1. there is a direct memory access (DMA) API module for the DMA peripheral. and a level of standardization and compatibility among devices. portability.

h csl_emifa. MCBSP TIMER .CSL Introduction Figure 1−1 illustrates some of the individual API modules (see section 1.h csl_dma. however. These components must be included in your application. Table 1−1 lists general and peripheral modules with their associated include file and the module support symbol. Figure 1−1. CSL Modules and Include Files Peripheral Module (PER) CACHE CHIP CSL DAT DMA EMAC EDMA EMIF EMIFA EMIFB GPIO Description Cache module Chip-specific module Top-level module Device independent data copy/fill module Direct memory access module Ethernet media access controller module Enhanced direct memory access module External memory interface module External memory interface A module External memory interface B module General-Purpose input/output module Include File csl_cache.h csl_emac. Table 1−1. This architecture allows for future expansion of the CSL because new API modules can be added as new peripheral devices emerge.h Module Support Symbol† CACHE_SUPPORT CHIP_SUPPORT NA DAT_SUPPORT DMA_SUPPORT EMAC_SUPPORT EDMA_SUPPORT EMIF_SUPPORT EMIFA_SUPPORT EMIFB_SUPPORT GPIO_SUPPORT CSL Overview 1-3 .h csl. This depends on if the device actually has the peripheral to which an API relates.h csl_emif.h csl_chip... Other modules such as the interrupt request (IRQ) module. the enhanced direct memory access (EDMA) API module is not supported on a C6201 because this device does not have an EDMA peripheral..h csl_edma.h csl_gpio. are supported on all devices. For example.h csl_dat. It is important to note that not all devices support all API modules..8 for a complete list). API Module Architecture CACHE CHIP CSL DAT DMA .h csl_emifb.

h csl_mdio.h csl_vic. there exists some interdependency between the modules.3 Interdependencies Although each API module is unique.h csl_irq.h csl_pwr. 1.h csl_pci.CSL Introduction Peripheral Module (PER) HPI I2C IRQ McASP McBSP MDIO PCI PWR TCP TIMER UTOP VCP VIC VP XBUS † Description Host port interface module Inter−Integrated circuit module Interrupt controller module Multichannel audio serial port module Multichannel buffered serial port module Management data I/O module Peripheral component interconnect interface module Power-down module Turbo decoder coprocessor module Timer module Utopia interface module Viterbi decoder coprocessor module VCXO interpolated control Video port module Expansion bus module Include File csl_hpi. the IRQ module automatically gets linked also.h csl_vcp.h csl_timer.h csl_vp. 1-4 . This comes into play when linking code because if you use the DMA module. For example.h csl_tcp.h csl_mcbsp.h csl_xbus. the DMA module depends on the IRQ module.h csl_i2c.h csl_mcasp.h csl_utop.1.h Module Support Symbol† HPI_SUPPORT I2C_SUPPORT IRQ_SUPPORT MCASP_SUPPORT MCBSP_SUPPORT MDIO_SUPPORT PCI_SUPPORT PWR_SUPPORT TCP_SUPPORT TIMER_SUPPORT UTOP_SUPPORT VCP_SUPPORT VIC_SUPPORT VP_SUPPORT XBUS_SUPPORT See definition in the related CSL module.

CSL Naming Conventions

1.2 CSL Naming Conventions
Table 1−2 shows the conventions used when naming CSL functions, macros, and data types.

Table 1−2. CSL Naming Conventions
Object Type Function Variable Macro Typedef Function Argument Structure Member

Naming Convention PER_funcName()† PER_varName† PER_MACRO_NAME† PER_Typename† funcArg memberName

PER is the placeholder for the module name.

- All functions, variables, macros, and data types start with PER_ (where

PER is the module/peripheral name) in caps (uppercase letters)
- Function names follow the peripheral name and use all small (lower-case)

letters. Capital letters are used only if the function name consists of two separate words, such as PER_getConfig()
- Macro names follow the peripheral name and use all caps, for example,

DMA_PRICTL_RMK
- Data types start with uppercase letters followed by lowercase letters, such

as DMA_Handle Note: CSL Macro and Function Names The CSL macro and constant names are defined for each register and each field in CSL include files. Therefore, you will need to be careful not to redefine macros using similar names. Because many CSL functions are predefined in CSL libraries, you will need to name your own functions carefully.

CSL Overview

1-5

CSL Data Types

1.3 CSL Data Types
The CSL provides its own set of data types. Table 1−3 lists the CSL data types as defined in the stdinc.h file.

Table 1−3. CSL Data Types
Data Type Uint8 Uint16 Uint32 Uint40 Int8 Int16 Int32 Int40 Description unsigned char unsigned short unsigned int unsigned long char short int long

These data types are available to all CSL modules. Additional data types are defined within each module and are described by each module’s chapter.

1-6

CSL Functions

1.4 CSL Functions
Table 1−4 provides a generic description of the most common CSL functions where PER indicates a peripheral as listed in Table 1−1. Because not all of the functions are available for all the modules, specific descriptions and functions are listed in each module chapter. The following conventions are used and are shown in Table 1−4.
- Italics indicate variable names. - Brackets [...] indicate optional parameters. J J

[handle] is required only for the handle-based peripherals: DAT, DMA, EDMA, GPIO, McBSP, and TIMER. See section 1.7.1. [priority] is required only for the DAT peripheral module.

Table 1−4. Generic CSL Functions
Function handle = PER_open( channelNumber, [priority] flags ) PER_config( [handle,] *configStructure ) Writes the values of the configuration structure to the peripheral registers. You can initialize the configuration structure with: - Integer constants - Integer variables - CSL symbolic constants, PER_REG_DEFAULT (See Section 1.6 CSL Symbolic Constant Values) - Merged field values created with the PER_REG_RMK macro Writes the individual values (regval_n) to the peripheral registers. These values can be any of the following: - Integer constants - Integer variables - CSL symbolic constants, PER_REG_DEFAULT - Merged field values created with the PER_REG_RMK macro Description Opens a peripheral channel and then performs the operation indicated by flags; must be called before using a channel. The return value is a unique device handle to use in subsequent API calls. The priority parameter applies only to the DAT module.

PER_configArgs( [handle,] regval_1, . . . regval_n ) PER_reset( [handle] ) PER_close( handle )

Resets the peripheral to its power-on default values.

Closes a peripheral channel previously opened with PER_open(). The registers for the channel are set to their power-on defaults, and any pending interrupt is cleared.

CSL Overview

1-7

CSL Functions

1.4.1

Peripheral Initialization via Registers
The CSL provides two types of functions for initializing the registers of a peripheral: PER_config() and PER_configArgs() (where PER is the peripheral as listed in Table 1−1).
- PER_config() initializes the control registers of the PER peripheral,

where PER is one of the CSL modules. This function requires an address as its one parameter. The address specifies the location of a structure that represents the peripherals register values. The configuration structure data type is defined for each peripheral module that contains the PER_config() function. Example 1−1 shows an example of this method.

Example 1−1. Using PER_config() with the configuration structure PER_Config
PER_Config MyConfig = { reg0, reg1, … }; … PER_config(&MyConfig); - PER_configArgs() allows you to pass the individual register values as

arguments to the function, which then writes those individual values to the register. Example 1−2 shows an example of this method. You can use these two initialization functions interchangeably but you still need to generate the register values. To simplify the process of defining the values to write to the peripheral registers, the CSL provides the PER_REG_RMK (make) macros, which form merged values from a list of field arguments. Macros are discussed in Section 1.5, CSL Macros.

Example 1−2. Using PER_configArgs
PER_configArgs(reg0, reg1, …);

1-8

CSL Macros

1.5 CSL Macros
Table 1−5 provides a generic description of the most common CSL macros, where:
- PER indicates a peripheral. (e.g., DMA) - REG indicates, if applicable, a register name (e.g., PRICTL0, AUXCTL) - FIELD indicates a field in a register (e.g., ESIZE) - regval indicates an integer constant, an integer variable, a symbolic

constant (PER_REG_DEFAULT), or a merged field value created with the peripheral field make macro, PER_FMK().
- fieldval indicates an integer constant, integer variable, or symbolic

constant (PER_REG_FIELD_SYMVAL) as explained in section 1.6); all field values are right justified
- x indicates an integer constant, integer variable. - sym indicates a symbolic constant - CSL also offers equivalent macros to those listed in Table 1−5, but instead

of using REG to identify which channel the register belongs to, it uses the handle value. The handle value is returned by the PER_open() function (see section 1.7). These macros are shown in Table 1−6. Each API chapter provides specific descriptions of the macros within that module. Page references to the macros in the hardware abstraction layer (Chapter 28, Using the HAL Macros), are provided for additional information.

CSL Overview

1-9

CSL Macros

Table 1−5. Generic CSL Macros
Macro PER_REG_RMK( fieldval_n, . . . fieldval_0 ) Description Creates a value to store in the peripheral register; _RMK macros make it easier to construct register values based on field values. The following rules apply to the _RMK macros: - Include only fields that are writable. - Specify field arguments as most-significant bit first. - Whether or not they are used, all writable field values must be included. - If you pass a field value exceeding the number of bits allowed for that particular field, the _RMK macro truncates that field value. Returns the value in the peripheral register. Writes the value to the peripheral register.

PER_RGET(REG ) PER_RSET(REG, regval ) PER_FMK (REG, FIELD, fieldval ) PER_FGET(REG, FIELD ) PER_FSET(REG, FIELD, fieldval ) PER_REG_ADDR(REG ) PER_FSETS (REG, FIELD, sym ) PER_FMKS (REG, FIELD, sym )

Creates a shifted version of fieldval that you could OR with the result of other _FMK macros to initialize register REG. This allows the user to initialize few fields in REG as an alternative to the _RMK macro, which requires that ALL register fields be initialized. Returns the value of the specified FIELD in the peripheral register.

Writes fieldval to the specified FIELD in the peripheral register.

If applicable, gets the memory address (or subaddress) of the peripheral register REG. Writes the symbol value to the specified field in the peripheral.

Creates a shifted version of the symbol value that you can OR with the result of other _FMK/_FMKS macros to initialize register REG. (See also PER_FMK() macro.)

1-10

CSL Macros

Table 1−6. Generic CSL Handle-Based Macros
Macro PER_ADDRH (h, REG ) PER_RGETH (h, REG ) PER_RSETH (h, REG, x ) PER_FGETH (h, REG, FIELD ) PER_FSETH (h, REG, FIELD, x ) PER_FSETSH (h, REG, FIELD, SYM ) Description Returns the address of a memory-mapped register for a given handle.

Returns the value of a register for a given handle.

Sets the register value to x for a given handle.

Returns the value of the field for a given handle.

Sets the field value to x for a given handle.

Sets the field value to the symbol value for a given handle.

Handle-based CSL macros are applicable to the following peripherals:
-

DMA EDMA GPIO McBSP TIMER I2C McASP VP

CSL Overview

1-11

CSL Symbolic Constant Values

1.6 CSL Symbolic Constant Values
To facilitate initialization of values in your application code, the CSL provides symbolic constants for registers and writable field values as described in Table 1−7, where:
- PER indicates a peripheral - REG indicates a peripheral register - FIELD indicates a field in the register - SYMVAL indicates the symbolic value of a register field

Each API chapter provides specific descriptions of the symbolic constants within that module. Page references to the constants in the hardware abstraction layer (Chapter 28, Using the HAL Macros), are provided for additional information.

Table 1−7. Generic CSL Symbolic Constants
(a) Constant Values for Registers Constant PER_REG_DEFAULT Description Default value for a register; corresponds to the register value after a reset or to 0 if a reset has no effect.

(b) Constant Values for Fields Constant PER_REG_FIELD_SYMVAL Description Symbolic constant to specify values for individual fields in the specified peripheral register. See the CSL Registers in Appendix B for the symbolic values. Default value for a field; corresponds to the field value after a reset or to 0 if a reset has no effect.

PER_REG_FIELD_DEFAULT

1-12

Resource Management

1.7 Resource Management
CSL provides a limited set of functions that enable resource management for applications which may support multiple algorithms, such as two McBSP or two TIMERs, and may reuse the same type of peripheral device. Resource management in CSL is achieved through API calls to the PER_open() and PER_close() functions. The PER_open() function normally takes a device number and a reset flag as the primary arguments and returns a pointer to a handle structure that contains information about which channel (DMA) or port (McBSP) was opened, then set “Allocate” flag defined in the handle structure to 1, meaning the channel or port is in use. When given a specific device number, the open function checks a global “allocate” flag to determine its availability. If the device/channel is available, then it returns a pointer to a predefined handle structure for this device. If the device has already been opened by another process, then an invalid handle is returned whose value is equal to the CSL symbolic constant, INV. Note that CSL does nothing other than return an invalid handle from PER_open(). You must use this to insure that no resource-usage conflicts occur. It is left to the user to check the value returned from the PER_open() function to guarantee that the resource has been allocated. A device/channel may be freed for use by other processes by a call to PER_close(). PER_close() clears the allocate flag defined under the handle structure object and resets the device/channel. All CSL modules that support multiple devices or channels, such as McBSP and DMA, require a device handle as a primary argument to most API functions. For these APIs, the definition of a PER_Handle object is required.

1.7.1

Using CSL Handles
Handles are required only for peripherals that have multiple channels or ports, such as DMA, EDMA, GPIO, McBSP, TIMER, I2C, and VP. You obtain a handle by calling the PER_open() function. When you no longer need a particular channel, free those resources by calling the PER_close() function. The PER_open() and PER_close() functions ensure that you do not initialize the same channel more than once. CSL handle objects are used to uniquely identify an open peripheral channel/port or device. Handle objects must be declared in the C source, and initialized by a call to a PER_open() function before calling any other API functions that require a handle object as an argument. PER_open() returns a value of “INV” if the resource is already allocated.
CSL Overview 1-13

Resource Management

DMA_Handle myDma; /* Defines a DMA_Handle object, myDma */

Once defined, the CSL handle object is initialized by a call to PER_open.
• •

myDma = DMA_open (DMA_CHA0, DMA_OPEN_RESET);

/* Open DMA channel 0 */

The call to DMA_open initializes the handle, myDma. This handle can then be used in calls to other API functions.
if(myDma != INV) { DMA_start (myDma);
• •

/* Begin transfer */ /* Free DMA channel */

DMA_close (myDma); }

1-14

CSL API Module Support

1.8 CSL API Module Support
Not all CSL API modules are supported on all devices. For example, the EDMA API module is not supported on the C6201 because the C6201 does not have EDMA hardware. When an API module is not supported, all of its header file information is conditionally compiled out, meaning the declarations will not exist. Because of this, calling an EDMA API function on devices not supporting EDMA will result in a compiler and/or linker error. Note: To build the program with the right library, the device support symbol must be set in the compiler option window. For example, if using C6201, the compiler option set in the preprocessor tab would be −dCHIP_6201. Table 1−8 and Table 1−9 show which devices support the API modules.

Table 1−8. CSL API Module Support for TMS320C6000 Devices
Module CACHE CHIP DAT DMA EDMA EMIF GPIO HPI I2C IRQ McASP McBSP PCI PLL PWR TIMER XBUS X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 6201 X X X X 6202 X X X X 6203 X X X X 6204 X X X X 6205 X X X X X X X 6211 X X X 6701 X X X X X X X X X X X X X X X X X X X X X X X X 6711 X X X 6712 X X X 6713 X X X DA610 X X X

CSL Overview

1-15

CSL API Module Support

Table 1−9. CSL API Module Support for TMS320C641x and DM64x Devices
Module CACHE CHIP DAT DMA EDMA EMAC EMIFA EMIFB EMU GPIO HPI IRQ McASP McBSP MDIO PCI PWR TCP TIMER UTOP VCP VIC VP X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 6414 X X X 6415 X X X 6416 X X X 6410 X X X 6413 X X X 6418 X X X DM642 X X X DM641 X X X DM640 X X X

1-16

CSL API Module Support

1.8.1

CSL Endianess/Device Support Library

Table 1−10. CSL Device Support Library Name and Symbol Conventions
Device C6201 C6202 C6203 C6204 C6205 C6211 C6701 C6711 C6712 C6713 C6414 C6415 C6416 DA610 DM642 DM641 DM640 C6410 C6413 C6418 Little Endian Library csl6201.lib csl6202.lib csl6203.lib csl6204.lib csl6205.lib csl6211.lib csl6701.lib csl6711.lib csl6712.lib csl6713.lib csl6414.lib csl6415.lib csl6416.lib cslDA610.lib cslDM642.lib cslDM641.lib cslDM640.lib csl6410.lib csl6413.lib csl6418.lib Big Endian Library csl6201e.lib csl6202e.lib csl6203e.lib csl6204e.lib csl6205e.lib csl6211e.lib csl6701e.lib csl6711e.lib csl6712e.lib csl6713e.lib csl6414e.lib csl6415e.lib csl6416e.lib cslDA610e.lib cslDM642e.lib cslDM641e.lib cslDM640e.lib csl6410.lib csl6413.lib csl6418.lib Device Support Symbol CHIP_6201 CHIP_6202 CHIP_6203 CHIP_6204 CHIP_6205 CHIP_6211 CHIP_6701 CHIP_6711 CHIP_6712 CHIP_6713 CHIP_6414 CHIP_6415 CHIP_6416 CHIP_DA610 CHIP_DM642 CHIP_DM641 CHIP_DM640 CHIP_6410 CHIP_6413 CHIP_6418

CSL Overview

1-17

Chapter 2

CACHE Module
This chapter describes the CACHE module, gives a description of the two CACHE architectures, lists the functions and macros within the module, and provides a CACHE API reference section.

Topic
2.1 2.2 2.3

Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-1

Overview

2.1 Overview
The CACHE module functions are used for managing data and program cache. Currently, TMS320C6x devices use three cache architectures. The first type, as seen on the C620x device, provides program cache by disabling on-chip program RAM and turning it into cache. The second and third types, seen on C621x/C671x and C64x devices respectively, are the two−level (L2) cache architectures. For the differences between C621x/C671x and C64x cache architectures, refer to SPRU610 TMS320C64x DSP Two Level Internal Memory Reference Guide. The CACHE module has APIs that are specific for the L2 cache and specific for the older program cache architecture. However, the API functions are callable on both types of platforms to make application code portable. On devices without L2, the L2-specific cache API calls do nothing but return immediately. Table 2−1 shows the API functions within the CACHE module.

Table 2−1. CACHE APIs
Syntax CACHE_clean{ CACHE_enableCaching CACHE_flush{ CACHE_getL2Mode CACHE_getL2SramSize CACHE_invalidate { CACHE_invAllL1p CACHE_invL1d CACHE_invL1p CACHE_invL2 CACHE_L1D_LINESIZE Type Description F F F F F F F F F F C Cleans a specific cache region Enables caching for a specified block of address space Flushes a region of cache Gets the L2 cache mode Returns current L2 size configured as SRAM Invalidates a region of cache L1P invalidate all L1D block invalidate (C64x only) L1P block invalidate L2 block invalidate (C64x only) A compile time constant whose value is the L1D line size. See page ... 2-6 2-7 2-9 2-19 2-10 2-10 2-11 2-11 2-12 2-13 2-14

Note: F = Function; C = Constant; M = Macro † This API function is provided for backward compatibility. Users should use the new APIs. ‡ Only for C6414, C6415, C6416 devices

2-2

Overview

Table 2−1. CACHE APIs (Continued)
Syntax CACHE_L1P_LINESIZE CACHE_L2_LINESIZE CACHE_reset CACHE_resetEMIFA CACHE_resetEMIFB‡ CACHE_resetL2Queue CACHE_ROUND_TO_LINESIZE (CACHE,ELCNT,ELSIZE) CACHE_setL2Mode CACHE_setL2Queue CACHE_setPriL2Req CACHE_setPccMode CACHE_SUPPORT CACHE_wait CACHE_wbAllL2 CACHE_wbInvL1d CACHE_wbInvAllL2 CACHE_wbInvL2 CACHE_wbL2 Type Description C C F F F F M F F F F C F F F F F F A compile time constant whose value is the L1P line size. A compile time constant whose value is the L2 line size. Resets cache to power-on default Resets the MAR registers dedicated to the EMIFA Resets the MAR registers dedicated to the EMIFB Resets the queue length of a given queue to default value Rounds to cache line size Sets L2 cache mode Sets the queue length of a given L2 queue Sets the L2 requestor priority level Sets program cache mode A compile time constant whose value is 1 if the device supports the CACHE module Waits for completion of the last cache operation L2 writeback all L1D block writeback and invalidate L2 writeback and invalidate all L2 block writeback and invalidate L2 block writeback See page ... 2-14 2-15 2-15 2-15 2-15 2-16 2-16 2-17 2-20 2-20 2-21 2-21 2-21 2-22 2-23 2-24 2-25 2-26

Note: F = Function; C = Constant; M = Macro † This API function is provided for backward compatibility. Users should use the new APIs. ‡ Only for C6414, C6415, C6416 devices

CACHE Module

2-3

Macros

2.2 Macros
There are two types of CACHE macros: those that access registers and fields, and those that construct register and field values. Table 2−2 lists the CACHE macros that access registers and fields, and Table 2−3 lists the CACHE macros that construct register and field values. The macros themselves are found in Chapter 28, Using the HAL Macros. CACHE macros are not handle-based.

Table 2−2. CACHE Macros that Access Registers and Fields
Macro CACHE_ADDR(<REG>) CACHE_RGET(<REG>) CACHE_RSET(<REG>,x) CACHE_FGET(<REG>,<FIELD>) CACHE_FSET(<REG>,<FIELD>,fieldval) CACHE_FSETS(<REG>,<FIELD>,<SYM>) CACHE_RGETA(addr,<REG>) CACHE_RSETA(addr,<REG>,x) CACHE_FGETA(addr,<REG>,<FIELD>) CACHE_FSETA(addr,<REG>,<FIELD>, fieldval) CACHE_FSETSA(addr,<REG>,<FIELD>, <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page... 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17

2-4

Macros

Table 2−3. CACHE Macros that Construct Register and Field Values
Macro CACHE_<REG>_DEFAULT CACHE_<REG>_RMK() CACHE_<REG>_OF() CACHE_<REG>_<FIELD>_DEFAULT CACHE_FMK() CACHE_FMKS() CACHE_<REG>_<FIELD>_OF() CACHE_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of ... Field default value Field make Field make symbolically Field value of ... Field symbolic value See page ... 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24

CACHE Module

2-5

CACHE_clean

2.3 Functions

CACHE_clean

Cleans a range of L2 cache

Note: This function is provided for backward compatibility only. The user is strongly advised to use the new functions as shown in Appendix D. Function void CACHE_clean( CACHE_Region region, void *addr, Uint32 wordCnt ); region Specifies which cache region to clean; must be one of the following: - CACHE_L2 - CACHE_L2ALL Beginning address of range to clean; word aligned Number of 32-bit words to clean. IMPORTANT: Maximum allowed wordCnt is 65535.

Arguments

addr wordCnt

Return Value Description

none Cleans a range of L2 cache. All lines within the range defined by addr and wordCnt are cleaned out of L2. If CACHE_L2ALL is specified, then all of L2 is cleaned, addr and wordCnt are ignored. A clean operation involves writing back all dirty cache lines and then invalidating those lines. This routine waits until the operation completes before returning. Note: This function does nothing on devices without L2 cache.

Example

If you want to clean a 4K-byte range that starts at 0x80000000 out of L2, use:
CACHE_clean(CACHE_L2,(void*)0x80000000,0x00000400);

If you want to clean all lines out of L2 use:
CACHE_clean(CACHE_L2ALL,(void*)0x00000000,0x00000000); 2-6

CACHE_enableCaching

CACHE_enableCaching Specifies block of ext. memory for caching Function void CACHE_enableCaching( Uint32 block ); block Specifies a block of external memory to enable caching for; must be one of the following: For devices other than C64x− - CACHE_CE33 −(0xB3000000 to 0xB3FFFFFF) - CACHE_CE32 −(0xB2000000 to 0xB2FFFFFF) - CACHE_CE31 −(0xB1000000 to 0xB1FFFFFF) - CACHE_CE30 −(0xB0000000 to 0xB0FFFFFF) - CACHE_CE23 −(0xA3000000 to 0xA3FFFFFF) - CACHE_CE22 −(0xA2000000 to 0xA2FFFFFF) - CACHE_CE21 −(0xA1000000 to 0xA1FFFFFF) - CACHE_CE20 −(0xA0000000 to 0xA0FFFFFF) - CACHE_CE13 −(0x93000000 to 0x93FFFFFF) - CACHE_CE12 −(0x92000000 to 0x92FFFFFF) - CACHE_CE11 −(0x91000000 to 0x91FFFFFF) - CACHE_CE10 −(0x90000000 to 0x90FFFFFF) - CACHE_CE03 −(0x83000000 to 0x83FFFFFF) - CACHE_CE02 −(0x82000000 to 0x82FFFFFF) - CACHE_CE01 −(0x81000000 to 0x81FFFFFF) - CACHE_CE00 −(0x80000000 to 0x80FFFFFF) For C6414, C6415, and C6416 EMIFB - CACHE_EMIFB_CE00 −(60000000h to 60FFFFFFh) - CACHE_EMIFB_CE01 −(61000000h to 61FFFFFFh) - CACHE_EMIFB_CE02 −(62000000h to 62FFFFFFh) - CACHE_EMIFB_CE03 −(63000000h to 63FFFFFFh) - CACHE_EMIFB_CE010 −(64000000h to 64FFFFFFh) - CACHE_EMIFB_CE011 −(65000000h to 65FFFFFFh) - CACHE_EMIFB_CE012 −(66000000h to 66FFFFFFh) - CACHE_EMIFB_CE013 −(67000000h to 67FFFFFFh) - CACHE_EMIFB_CE020 −(68000000h to 68FFFFFFh) - CACHE_EMIFB_CE021 −(69000000h to 69FFFFFFh) - CACHE_EMIFB_CE022 −(6A000000h to 6AFFFFFFh) - CACHE_EMIFB_CE023 −(6B000000h to 6BFFFFFFh) - CACHE_EMIFB_CE030 −(6C000000h to 6CFFFFFFh) - CACHE_EMIFB_CE031 −(6D000000h to 6DFFFFFFh) - CACHE_EMIFB_CE032 −(6E000000h to 6EFFFFFFh) - CACHE_EMIFB_CE033 −(6F000000h to 6FFFFFFFh)
CACHE Module 2-7

Arguments

CACHE_enableCaching

For EMIFA CE0− - CACHE_EMIFA_CE00 −(80000000h to 80FFFFFFh) - CACHE_EMIFA_CE01 −(81000000h to 81FFFFFFh) - CACHE_EMIFA_CE02 −(82000000h to 82FFFFFFh) - CACHE_EMIFA_CE03 −(83000000h to 83FFFFFFh) - CACHE_EMIFA_CE04 −(84000000h to 84FFFFFFh) - CACHE_EMIFA_CE05 −(85000000h to 85FFFFFFh) - CACHE_EMIFA_CE06 −(86000000h to 86FFFFFFh) - CACHE_EMIFA_CE07 −(87000000h to 87FFFFFFh) - CACHE_EMIFA_CE08 −(88000000h to 88FFFFFFh) - CACHE_EMIFA_CE09 −(89000000h to 89FFFFFFh) - CACHE_EMIFA_CE010 −(8A000000h to 8AFFFFFFh) - CACHE_EMIFA_CE011 −(8B000000h to 8BFFFFFFh) - CACHE_EMIFA_CE012 −(8C000000h to 8CFFFFFFh) - CACHE_EMIFA_CE013 −(8D000000h to 8DFFFFFFh) - CACHE_EMIFA_CE014 −(8E000000h to 8EFFFFFFh) - CACHE_EMIFA_CE015 −(8F000000h to 8FFFFFFFh) For CACHE_EMIFA_CE1, CACHE_EMIFA_CE2, and CACHE_EMIFA_CE3 the symbols are the same as CACHE_EMIFA_CE0, with start addresses 90000000h, A0000000h, and B0000000h, respectively. Return Value Description none Enables caching for the specified block of memory. This is accomplished by setting the CE bit in the appropriate memory attribute register (MAR). By default, caching is disabled for all memory spaces. Note: This function does nothing on devices without L2 cache. Example To enable caching for the range of memory from 0x80000000 to 0x80FFFFFF use:
For C64x − CACHE_enableCaching(CACHE_EMIFA_CE00);

For other devices −
CACHE_enableCaching(CACHE_CE00);

2-8

CACHE_flush CACHE_flush Flushes region of cache (obsolete)
Note: This function is provided for backward compatibility only. The user is strongly advised to use the new functions as shown in Appendix D. Function void CACHE_flush( CACHE_Region region, void *addr, Uint32 wordCnt ); region Specifies which cache region to flush from; must be one of the following: - CACHE_L2 - CACHE_L2ALL - CACHE_L1D Beginning address of range to flush; word aligned Number of 32-bit words to flush. IMPORTANT: Maximum allowed wordCnt is 65535.

Arguments

addr wordCnt Return Value Description none

Flushes a range of L2 cache. All lines within the range defined by addr and wordCnt are flushed out of L2. If CACHE_L2ALL is specified, then all of L2 is flushed; addr and wordCnt are ignored. A flush operation involves writing back all dirty cache lines, but the lines are not invalidated. This routine waits until the operation completes before returning. Note: This function does nothing on devices without L2 cache.

Example

If you want to flush a 4K-byte range that starts at 0x80000000 out of L2, use:
CACHE_flush(CACHE_L2,(void*)0x80000000,0x00000400);

If you want to flush all lines out of L2, use:
CACHE_flush(CACHE_L2ALL,(void*)0x00000000,0x00000000);

CACHE Module

2-9

then all of L1D is invalidated. none size Returns number of bytes of on-chip SRAM This function returns the current size of L2 that is configured as SRAM.CACHE_getL2SramSize CACHE_getL2SramSize Returns current size of L2 that is configured as SRAM Function Arguments Return Value Description Uint32 CACHE_getL2SramSize(). region Specifies which cache region to invalidate. Function void CACHE_invalidate( CACHE_Region region. Note: This function does nothing on devices without L2 cache.CACHE_L1P Invalidate L1P . 2-10 . addr and wordCnt are ignored. addr and wordCnt are ignored. must be one of the following: . void *addr. The user is strongly advised to use the new functions as shown in Appendix D. CACHE_invalidate Invalidates a region of cache (obsolete) Note: This function is provided for backward compatibility only. Arguments addr wordCnt Return Value Description none Invalidates a range from cache. word aligned Number of 32-bit words to invalidate. Example SramSize = CACHE_getL2SramSize().CACHE_L1DALL Invalidate all of L1D Beginning address of range to invalidate. Likewise. Uint32 wordCnt ). then all of L1P is invalidated. All lines within the range defined by addr and wordCnt are invalidated from region. IMPORTANT: Maximum allowed wordCnt is 65535.CACHE_L1PALL Invalidate all of L1P . This routine waits until the operation completes before returning. If CACHE_L1PALL is specified. if CACHE_L1DALL is specified.

(void*)0x00000000. blockPtr byteCnt Pointer to the beginning of the block Number of bytes in the block.0x00000400). use: CACHE_invalidate(CACHE_L1P. Example CACHE_invL1d Function L1D block invalidate (C64x only) void CACHE_invL1d( void *blockPtr. Wait flag: .CACHE_invAllL1p Note: This function does nothing on devices without L2 cache. Example If you want to invalidate a 4K-byte range that starts at 0x80000000 from L1P. Please see the TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (literature number SPRU609) and the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation. int wait ). If you want to invalidate all lines from L1D. This value must be a multiple of four. CACHE_invAllL1p L1P invalidates all Function Arguments Return Value Description void CACHE_invAllL1p(). use: CACHE_invalidate(CACHE_L1DALL.0x00000000). none none This function issues an L1P invalidate all command to the cache controller.CACHE_WAIT − wait until the operation completes Arguments wait Return Value none CACHE Module 2-11 . Uint32 byteCnt.CACHE_NOWAIT − return immediately .(void*)0x80000000. CACHE_invAllL1p(). The largest size this can be in 65535*4.

Although the block size can be specified in number of bytes. in order to prevent lockout of interrupts.. 1024. This value must be a multiple of four. /* call with wait flag set */ CACHE_invL1d(buffer..CACHE_NOWAIT − return immediately . The largest size this can be in 65535*4. Uint32 byteCnt.CACHE_WAIT − wait until the operation completes Arguments wait Return Value 2-12 none . CACHE_NOWAIT). . Example char buffer[1024]. This function is only supported on C64x devices. .. regardless of whether the operation has completed. Please see the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation. 1024. If the user specifies CACHE_NOWAIT..CACHE_invL1p Description This function issues an L1D block invalidate command to the cache controller. . the function waits for its completion before initiating the new operation. int wait ). CACHE_invL1p Function L1P block invalidate void CACHE_invL1p( void *blockPtr. CACHE_WAIT). The user can call CACHE_wait() afterwards to wait for the operation to complete. Wait flag: . If a previous cache operation is still active. /* call without the wait flag set */ CACHE_invL1d(buffer. then the function returns immediately. the cache controller operates on whole cache lines only.. blockPtr byteCnt Pointer to the beginning of the block Number of bytes in the block. CACHE_wait()..

. 1024. CACHE_wait(). If the user specifies CACHE_NOWAIT.. Wait flag: . Although the block size can be specified in number of bytes.. then the function returns immediately. CACHE_invL2 Function L2 block invalidate (C64x devices only) void CACHE_invL2( void *blockPtr.CACHE_invL2 Description This function issues an L1P block invalidate command to the cache controller.. the function waits for its completion before initiating the new operation. regardless of whether the operation has completed. The user can call CACHE_wait() afterwards to wait for the operation to complete. If a previous cache operation is still active. CACHE_NOWAIT). CACHE_WAIT).. This value must be a multiple of four.. Example char buffer[1024]. . Please see the TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (literature number SPRU609) and the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation. in order to prevent lockout of interrupts.. /* call with wait flag set */ CACHE_invL1p(buffer. 1024. . the cache controller operates on whole cache lines only.CACHE_NOWAIT − return immediately . blockPtr byteCnt Pointer to the beginning of the block Number of bytes in the block. /* call without the wait flag set */ CACHE_invL1p(buffer. The largest size this can be in 65535*4.CACHE_WAIT − wait until the operation completes Arguments wait Return Value none CACHE Module 2-13 . int wait ). Uint32 byteCnt.

If a previous cache operation is still active. CACHE_wait(). CACHE_L1D_LINESIZE L1D line size Constant Description Example CACHE_L1D_LINESIZE Compile-time constant that is set equal to the L1D cache line size of the device. #pragma DATA_ALIGN(array. . Although the block size can be specified in number of bytes. This function is supported on C64x devices only. 1024. CACHE_L1D_LINESIZE) CACHE_L1P_LINESIZE L1P line size Constant Description Example 2-14 CACHE_L1P_LINESIZE Compile-time constant that is set equal to the L1P cache line size of the device..CACHE_L1D_LINESIZE Description This function issues an L2 block invalidate command to the cache controller.. #pragma DATA_ALIGN(array. To prevent unintended behavior. Example char buffer[1024]. . in order to prevent lockout of interrupts. /* call with wait flag set */ CACHE_invL2(buffer. . blockPtr and byteCnt should be multiples of the cache line size. the cache controller operates on whole cache lines only.. then the function returns immediately. 1024. CACHE_NOWAIT). Please see the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation. CACHE_L1P_LINESIZE) ... /* call without the wait flag set */ CACHE_invL2(buffer. If the user specifies CACHE_NOWAIT. CACHE_WAIT). The user can call CACHE_wait() afterwards to wait for the operation to complete. the function waits for its completion before initiating the new operation.. regardless of whether the operation has completed.

Example CACHE_reset(). CACHE_enableCaching(CACHE_EMIFB_CE00). CACHE Module 2-15 . CACHE_enableCaching(CACHE_EMIFA_CE00). C6415 and C6416 devices. CACHE_resetEMIFA Resets the MAR registers dedicated to the EMIFA CE spaces Function Arguments Return Value Description Example void CACHE_resetEMIFA(). none none Resets cache to power-on default.CACHE_L2_LINESIZE CACHE_L2_LINESIZE L2 line size Constant Description Example CACHE_L2_LINESIZE Compile-time constant that is set equal to the L2 cache line size of the device. CACHE_L2_LINESIZE) CACHE_reset Function Arguments Return Value Description Resets cache to power-on default void CACHE_reset(). CACHE_resetEMIFB(). none none This function resets the MAR registers dedicated to the EMIFA CE spaces. flush it out first. If you want to preserve this data. Devices with L2 Cache: All MAR bits are cleared Devices without L2 Cache: PCC field of CSR set to zero (mapped) Note: If you reset the cache. CACHE_resetEMIFB Function Arguments Return Value Description Example Resets the MAR registers dedicated to the EMIFB CE spaces void CACHE_resetEMIFB(). none none This function resets all the MAR registers dedicated to the EMIFB CE spaces. any dirty data will be lost. #pragma DATA_ALIGN(array. CACHE_enableCaching(CACHE_EMIFA_CE13). CACHE_enableCaching(CACHE_EMIFB_CE13). CACHE_resetEMIFA(). This is defined only for C6414.

CACHE_L2Q0 . Arguments Return Value Description Example CACHE_ROUND_TO_LINESIZE Rounds to cache line size Macro CACHE_ROUND_TO_LINESIZE( CACHE. Arrays located in external memory that require user-controlled coherence maintenance must be aligned at a cache line boundary and be a multiple of cache lines large to prevent incoherency problems.CACHE_L2Q3 none This functions allows the user to reset the queue length of the given L2 queue to its default value. 2-16 . EDMA_resetL2Queue(CACHE_L2Q2). L1P.4). EDMA_setL2Queue(CACHE_L2Q2. ELSIZE ). queueNum Queue number to be reset to the default length: The following constants may be used for L2 queue number: . Please see the TMS320C6000 DSP Cache User’s Guide (literature number SPRU656) for details. ELCNT.CACHE_L2Q2 . See the CACHE_setL2Queue() function.CACHE_L2Q1 . or L2 Element count Element size Arguments Rounded up element count This macro rounds an element up to make an array size a multiple number of cache lines. CACHE ELCNT ELSIZE Return Value Description Cache type: L1D.CACHE_resetL2Queue CACHE_resetL2Queue Function Resets the queue length of the L2 queue to its default value void CACHE_resetL2Queue( Uint32 queueNum ).

CACHE_48KSRAM . newMode New L2 cache mode.CACHE_32KCACHE .CACHE_48KCACHE .CACHE_32KCACHE . CACHE_L2_LINESIZE) /* array y spans 7 full lines and 104 bytes of the next line*/ short y[500].CACHE_64KCACHE Arguments CACHE Module 2-17 .CACHE_0KSRAM . 500. must be one of the following: (For C6711/C6211) .CACHE_224KSRAM .CACHE_48KCACHE . CACHE_L2_LINESIZE) #pragma DATA_ALIGN(x.CACHE_32KSRAM .CACHE_240KSRAM .CACHE_64KCACHE (For C6713 and DA610) . i.CACHE_64KSRAM . sizeof(short))] CACHE_setL2Mode Function Sets L2 cache mode CACHE_L2Mode CACHE_setL2Mode( CACHE_L2Mode newMode ).CACHE_192KSRAM .e.CACHE_16KSRAM .CACHE_16KCACHE .CACHE_256KSRAM .CACHE_208KSRAM . /* the array element count is increased such that the array x spans a multiple number of cache lines.CACHE_0KCACHE . 8 lines */ short x[CACHE_ROUNT_TO_LINESIZE(L2.CACHE_0KCACHE .CACHE_setL2Mode Example /* assume an L2 line size of 128 bytes */ /* align arrays y and x at the cache line border */ #pragma DATA_ALIGN(y.CACHE_16KCACHE .

DM640 and DM641) CACHE_128KSRAM CACHE_0KCACHE CACHE_96KSRAM CACHE_32KCACHE CACHE_64KSRAM CACHE_64KCACHE CACHE_128KCACHE - (For C6413) .CACHE_256KSRAM .CACHE_64KSRAM .CACHE_128KCACHE .CACHE_992KSRAM .CACHE_64KCACHE .CACHE_224KSRAM .CACHE_setL2Mode (For C6414/C6415/C6416) .CACHE_0KCACHE .CACHE_192KSRAM .CACHE_896KSRAM .CACHE_768KSRAM .CACHE_960KSRAM .CACHE_256KCACHE (For C6410.CACHE_128KSRAM .CACHE_128KCACHE .CACHE_32KCACHE .CACHE_0KCACHE .CACHE_1024KSRAM .CACHE_32KCACHE .CACHE_256KCACHE (For C6418) CACHE_512KSRAM CACHE_0KCACHE CACHE_480KSRAM CACHE_32KCACHE CACHE_448KSRAM CACHE_64KCACHE CACHE_384KSRAM CACHE_128KCACHE CACHE_256KSRAM 2-18 .

A decrease in cache size 2. then the mode is changed. all of L2 is writeback-invalidated. If there is data in the SRAM that should not be lost.CACHE_128KSRAM .CACHE_224KSRAM . there are 64KBytes of L2.CACHE_256KSRAM . on the C6211.CACHE_64KCACHE . For example. OldMode = CACHE_setL2Mode(CACHE_32KCACHE).CACHE_0KCACHE .CACHE_192KSRAM . Some of the cache modes are identical. it must be preserved before changing cache modes.CACHE_256KCACHE Return Value Description oldMode Returns old cache mode. the part of SRAM that is about to be turned into cache is writeback-invalidated from L1D and all of L2 is writeback-invalidated. None CACHE Module 2-19 . this will not be the case. An increase in cache size 3. Note: This function does nothing on devices without L2 cache. Nothing happens when there is no change. This function sets the mode of the L2 cache. If the cache size increases.CACHE_256KCACHE (For DM642) .CACHE_32KCACHE .CACHE_getL2Mode . CACHE_getL2Mode Returns Level 2 Cache mode Function Arguments voide CACHE_getL2Mode(). There are three conditions that may occur as a result of changing cache modes: 1. Example CACHE_L2Mode OldMode. then the mode is changed. Increasing cache size means that some of the SRAM is lost. if the L2 size changes on a future device. one of those listed above. hence. CACHE_16KSRAM is equivalent to CACHE_48KCACHE. However.CACHE_128KCACHE .CACHE_0KSRAM . No change in cache size If the cache size decreases.

If L2 cache is not supported. The following constants may be used: .CACHE_L2Q3 Queue length to be set Arguments length Return Value Description Example none This function allows the user to set the queue length of a specified L2 also CACHE_resetL2Queue() function.CACHE_L2PRIHIGH (1) . Uint32 length ).CACHE_L2PRIMED (2) . CACHE_setL2Queue Function Sets the queue length of the L2 queue void CACHE_setL2Queue( Uint32 queueNum.CACHE_L2PRILOW (3) Arguments 2-20 . The following constants may be used for L2 queue number: .CACHE_setL2Queue Return Value Description Example Leve 2 Cache mode (listed under CACHE_setL2Mode function explanation) This retuns the current L2 cache mode. it returns CACHE_0KCACHE. CACHE_setL2Queue(CACHE_L2Q1. queueNum Queue number to be set. priority Priority request level to be set.5). CACHE_setPriL2Req Function Sets the L2 priority level “P” of the CCFG register void CACHE_setPriL2Req( Uint32 priority ). CACHE_L2Mode oldMode: OldMode = CACHE_getL2Mode().CACHE_L2Q0 .CACHE_L2Q2 .CACHE_L2Q1 .CACHE_L2PRIURG (0) .

See the TMS320C6000 Peripherals Reference Guide (SPRU190) for the meaning of the cache modes. Example #if (CACHE_SUPPORT) /* user cache configuration */ #endif CACHE_wait Function Arguments Waits for completion of the last cache operation int CACHE_wait().CACHE_PCC_MAPPED . CACHE_setPriL2Req(CACHE_L2PRIHIGH). You are not required to use this constant. none CACHE Module 2-21 . this function does nothing. Example CACHE_SUPPORT Compile time constant Constant Description CACHE_SUPPORT Compile time constant that has a value of 1 if the device supports the CACHE module and 0 otherwise. all devices support this module. To enable the program cache in normal mode. For devices that do have an L2 cache such as the C6211. Currently.CACHE_PCC_ENABLE Returns the old program cache mode.CACHE_PCC_MAPPED .CACHE_setPccMode Return Value Description Example none This function allows the user to set the L2 priority level “P” of the CCFG register. newMode New program cache mode. use: CACHE_Pcc OldMode. CACHE_setPccMode Sets program cache mode Function CACHE_Pcc CACHE_setPccMode( CACHE_Pcc newMode ). OldMode = CACHE_setPccMode(CACHE_PCC_ENABLE). will be one of the following: .CACHE_PCC_ENABLE Arguments Return Value OldMode Description This function sets the program cache mode for devices that do not have an L2 cache. must be one of the following: .

.CACHE_WAIT − wait until the operation completes Arguments Return Value Description none This function issues an L2 writeback all command to the cache controller. . CACHE_wbAllL2 Function L2 writeback all void CACHE_wbAllL2( int wait ). CACHE_wait().CACHE_NOWAIT − return immediately . Please see the TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (literature number SPRU609) and the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation.. .. This function ONLY works in conjunction with the following operations: - CACHE_wbL2() CACHE_invL2() CACHE_wbInvL2() CACHE_wbAllL2() CACHE_wbInvAllL2() CACHE_invL1d() CACHE_wbInvL1d() CACHE_invL1p() Example CACHE_wbInvAllL2(CACHE_NOWAIT). 2-22 . regardless of whether the operation has completed. wait Wait flag: . then the function returns immediately. The user can call CACHE_wait() afterwards to wait for the operation to complete. If the user specifies CACHE_NOWAIT..CACHE_wbAllL2 Return Value Description none This function waits for the completion of the last cache operation.

. regardless of whether the operation has completed.CACHE_NOWAIT − return immediately . CACHE_wbInvL1d L1D block writeback and invalidate Function void CACHE_wbInvL1d( void *blockPtr. This value must be a multiple of four. Although the block size can be specified in number of bytes. CACHE Module 2-23 . CACHE_wait(). The largest size this can be in 65535*4. If the user specifies CACHE_NOWAIT. If a previous cache operation is still active.CACHE_WAIT − wait until the operation completes Arguments wait Return Value Description none This function issues an L1D block writeback and invalidate command to the cache controller. Please see the TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (literature number SPRU609) and the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation. blockPtr byteCnt Pointer to the beginning of the block Number of bytes in the block. int wait ). The user can call CACHE_wait() afterwards to wait for the operation to complete. /* call without the wait flag set */ CACHE_wbAllL2(CACHE_NOWAIT).. the cache controller operates on whole cache lines only.CACHE_wbInvL1d Example /* call with wait flag set */ CACHE_wbAllL2(CACHE_WAIT). Uint32 byteCnt. in order to prevent lockout of interrupts.. the function waits for its completion before initiating the new operation. . . Wait flag: . then the function returns immediately..

. CACHE_wait().CACHE_WAIT − wait until the operation completes Arguments Return Value Description none This function issues an L2 writeback and invalidate all command to the cache controller. . /* call without the wait flag set */ CACHE_wbInvL1d(buffer. If the user specifies CACHE_NOWAIT. . then the function returns immediately. /* call with wait flag set */ CACHE_wbInvL1d(buffer. regardless of whether the operation has completed. 1024. /* call without the wait flag set */ CACHE_wbInvAllL2(CACHE_NOWAIT).. CACHE_wbInvAllL2 L2 writeback and invalidate all Function void CACHE_wbInvAllL2( int wait ). 1024.. The user can call CACHE_wait() afterwards to wait for the operation to complete. 2-24 . CACHE_NOWAIT). Please see the TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (literature number SPRU609) and the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation.. wait Wait flag: ...CACHE_NOWAIT − return immediately .. .CACHE_wbInvAllL2 Example char buffer[1024]. CACHE_WAIT).. ..... Example /* call with wait flag set */ CACHE_wbInvAllL2(CACHE_WAIT). CACHE_wait().. .

blockPtr and byteCnt should be multiples of the cache line size. Uint32 byteCnt. 1024. CACHE_NOWAIT).CACHE_WAIT − wait until the operation completes Arguments wait Return Value Description none This function issues an L2 block writeback and invalidate command to the cache controller. The user can call CACHE_wait() afterwards to wait for the operation to complete... CACHE_WAIT). the cache controller operates on whole cache lines only. blockPtr byteCnt Pointer to the beginning of the block Number of bytes in the block. 1024. .. Example char buffer[1024]. /* call without the wait flag set */ CACHE_wbInvL2(buffer. /* call with wait flag set */ CACHE_wbInvL2(buffer.. Wait flag: .CACHE_NOWAIT − return immediately . in order to prevent lockout of interrupts. To prevent unintended behavior. CACHE_wait(). regardless of whether the operation has completed. This value must be a multiple of four. Please see the TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (literature number SPRU609) and the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation. the function waits for its completion before initiating the new operation. int wait ). Although the block size can be specified in number of bytes. If the user specifies CACHE_NOWAIT. .CACHE_wbInvL2 CACHE_wbInvL2 Function L2 block writeback and invalidate void CACHE_wbInvL2( void *blockPtr. The largest size this can be in 65535*4. . CACHE Module 2-25 . then the function returns immediately.. If a previous cache operation is still active..

. To prevent unintended behavior. blockPtr and byteCnt should be multiples of the cache line size. If the user specifies CACHE_NOWAIT... Although the block size can be specified in number of bytes. . . int wait ). 1024. the function waits for its completion before initiating the new operation. 1024. Please see the TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (literature number SPRU609) and the TMS320C64x DSP Two Level Internal Memory Reference Guide (literature number SPRU610) for details of this operation for details of this operation. Wait flag: . blockPtr byteCnt Pointer to the beginning of the block Number of bytes in the block. If a previous cache operation is still active. The user can call CACHE_wait() afterwards to wait for the operation to complete.. CACHE_wait(). regardless of whether the operation has completed. 2-26 . /* call with wait flag set */ CACHE_wbL2(buffer. . then the function returns immediately. Uint32 byteCnt. CACHE_NOWAIT). The largest size this can be in 65535*4.CACHE_wbL2 CACHE_wbL2 Function L2 block writeback void CACHE_wbL2( void *blockPtr.CACHE_NOWAIT − return immediately . CACHE_WAIT). the cache controller operates on whole cache lines only. /* call without the wait flag set */ CACHE_wbL2(buffer.. in order to prevent lockout of interrupts. This value must be a multiple of four. Example char buffer[1024].CACHE_WAIT − wait until the operation completes Arguments wait Return Value Description none This function issues an L2 block writeback command to the cache controller..

. . . . . . . . . . . . . . . . . . . Topic 3. . . . . . . . . . 3-2 Macros . . . . . and provides a CHIP API reference section. . . . . . . . . . . . . . . . . . . . .1 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3. . . . . . . . . . . . . . . 3-3 Functions . . . 3-4 3-1 . . . .Chapter 3 CHIP Module This chapter describes the CHIP module. . . . . . . .3 Page Overview . . . .

Table 3−1 shows the API functions within the CHIP module. C6712C. C6412. CHIP APIs Syntax CHIP_6XXX CHIP_getCpuId CHIP_getEndian CHIP_getMapMode CHIP_getRevId CHIP_SUPPORT CHIP_config† CHIP_getConfig† CHIP_configArgs † Type Description C F F F F C F F F Current device identification symbols Returns the CPU ID field of the CSR register Returns the current endian mode of the device Returns the current map mode of the device Returns the CPU revision ID A compile time constant whose value is 1 if the device supports the CHIP module Set device configuration Get device configuration Set device configuration See page . DM640.Overview 3. C6413 and C6418 devices. and CPU and REV IDs. DM642. Currently. 3-2 . This module has the potential to grow in the future as more devices are placed on the market. DM641. DA610. C6711C.1 Overview The CHIP module is where chip-specific and chip-related code resides... memory map mode if applicable. C6410. 3-4 3-5 3-5 3-6 3-6 3-6 3-7 3-7 3-7 Note: F = Function. CHIP has some API functions for obtaining device endianess. C = Constant † Only for C6713. The CHIP_Config structure contains a single field which holds the unsigned device configuration value. Table 3−1.

fieldval) CHIP_FSETS(<REG>.<FIELD>. Table 3−2 lists the CHIP macros that access registers and fields. The macros themselves are found in Chapter 28.<FIELD>) CHIP_FSET(<REG>.<FIELD>. CHIP Macros that Construct Register and Field Values Macro CHIP_<REG>_DEFAULT CHIP_<REG>_RMK() CHIP_<REG>_OF() CHIP_<REG>_<FIELD>_DEFAULT CHIP_FMK() CHIP_FMKS() CHIP_<REG>_<FIELD>_OF() CHIP_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of ..2 Macros There are two types of CHIP macros: those that access registers and fields. and those that construct register and field values.x) CHIP_RGET(<REG>) CHIP_RSET(<REG>.. Table 3−2..<SYM>) Description/Purpose Gets the value of CPU register Sets the value of CPU register Returns the value in the memory-mapped register Writes the value to the memory-mapped register Returns the value of the specified field in the register Writes fieldval to the specified field of the register Writes the symbol value to the specified field in the peripheral See page.Macros 3. CHIP Macros that Access Registers and Fields Macro CHIP_CRGET(<REG>) CHIP_CRSET(<REG>. and Table 3−3 lists the CHIP macros that construct register and field values. 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 CHIP Module 3-3 .x) CHIP_FGET(<REG>. 28-12 28-13 28-18 28-20 28-13 28-15 28-17 Table 3−3.... Using the HAL Macros. Field default value Field make Field make symbolically Field value of ... Field symbolic value See page. CHIP macros are not handle-based.

3 Functions CHIP_6XXX Constant Current chip identification symbols CHIP_6201 CHIP_6202 CHIP_6203 CHIP_6204 CHIP_6205 CHIP_6211 CHIP_6414 CHIP_6415 CHIP_6416 CHIP_6701 CHIP_6711 CHIP_6712 CHIP_6713 CHIP_DA610 CHIP_6410 CHIP_6413 CHIP_6418 CHIP_DM642 CHIP_DM641 CHIP_DM640 These are the current chip identification symbols. When using the CSL. you have to select the right chip type under Global Setting module. You may also use these symbols to perform conditional compilation. for example: #if (CHIP_6201) /* user CHIP configuration for 6201 / #elif (CHIP_6211) / user CHIP configuration for 6211 */ #endif Description 3-4 . They are used throughout the CSL code to make compile-time decisions. The chip type will generate the associated macro CHIP_6XXX.CHIP_6XXX 3.

Uint32 CpuId. if (Endian == CHIP_ENDIAN_BIG) { /* user big endian configuration / } else { / user little endian configuration */ } CHIP Module 3-5 . Uint32 Endian. 0 Endian = CHIP_getEndian(). none CPU ID Returns the CPU ID This function returns the CPU ID field of the CSR register.CHIP_ENDIAN_BIG . CpuId = CHIP_getCpuId(). CHIP_getEndian Function Arguments Return Value Returns current endian mode of device int CHIP_getEndian().CHIP_ENDIAN_LITTLE Description Example Returns the current endian mode of the device as determined by the EN bit of the CSR register.CHIP_getCpuId CHIP_getCpuId Function Arguments Return Value Description Example Returns CPU ID field of CSR register Uint32 CHIP_getCpuId(). none endian mode Returns the current endian mode of the device. will be one of the following: .

CHIP_getMapMode CHIP_getMapMode Function Arguments Return Value Returns current map mode of device int CHIP_getMapMode(). Currently. Uint32 RevId. RevId = CHIP_getRevId().CHIP_MAP_0 . none revision ID Returns CPU revision ID This function returns the CPU revision ID as determined by the Revision ID field of the CSR register.CHIP_MAP_1 Description Example Returns the current MAP mode of the device as determined by the MAP bit of the EMIF global control register. none map mode Returns current device MAP mode. CHIP_SUPPORT Constant Description Compile-time constant CHIP_SUPPORT Compile-time constant that has a value of 1 if the device supports the CHIP module and 0 otherwise. all devices support this module. Uint32 MapMode. Example #if (CHIP_SUPPORT) /* user CHIP configuration */ #endif 3-6 . if (MapMode == CHIP_MAP_0) { /* user map 0 configuration / } else { / user map 1 configuration */ } CHIP_getRevId Function Arguments Return Value Description Example Returns CPU revision ID Uint32 CHIP_getRevId(). will be one of the following: . 0 MapMode = CHIP_getMapMode(). You are not required to use this constant.

This value is written to the devcfg field of the structure.CHIP_SUPPORT CHIP_config Function Set device configuration void CHIP_config( CHIP_Config *config ). Arguments Return Value Description CHIP Module 3-7 . Address of config structure None Writes the device configuration value held in the config structure to config address Arguments Return Value Description CHIP_getConfig Function Gets the device configuration void CHIP_getConfig( CHIP_Config *config ). devcfg None Writes the devcfg value to the device configuration address. Address of config structure None Gets the device configuration value stored in the config structure to configuration address. Arguments Return Value Description CHIP_configArgs Function Sets the device configuration void CHIP_configArgs( unit32 devcfg ).

. . . . . . . 4-3 4-1 . . . . . . . . . 4-2 Functions . Topic 4. . . . . and provides a CSL API reference section. . . . . . . . . . .Chapter 4 CSL Module This chapter describes the CSL module. . . . . . . . . . . . .1 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . shows the single API function within the module.2 Page Overview . . . . . . . . . . . . . . . . . . . . . . .

CSL API Syntax CSL_init Note: F = Function Type Description F Initializes the CSL library See page .. Table 4−1 shows the only function exported by the CSL module. The CSL_init() function must be called once at the beginning of your program before calling any other CSL API functions..Overview 4.1 Overview The CSL module is the top-level API module whose primary purpose is to initialize the library. 4-3 4-2 . Table 4−1.

none none The CSL module is the top-level API module whose primary purpose is to initialize the library.CSL_init 4. Only one function is exported: CSL_init() The CSL_init() function must be called once at the beginning of your program before calling any other CSL API functions. CSL Module 4-3 . Example CSL_init().2 Functions CSL_init Function Arguments Return Value Description Calls initialization function of all CSL API modules void CSL_init().

and provides a DAT API reference section. . . . . . . . . . . . . . . . . . . . . . . . . . . discusses how the DAT module manages the DMA/EDMA peripheral. . . . 5-2 Functions . . . . . . . . . . . . . . . . . . . . . . . .Chapter 5 DAT Module This chapter describes the DAT module. . . . . . . . . . . 5-4 5-1 . . . . . . . . . . . . . .2 Page Overview . . .1 5. . . Topic 5. . . . lists the API functions within the DAT module. . . . . . . . . . . . . . . . . . . . . .

C = Constant Type Description F F F F F F F C F Checks to see if a previous transfer has completed Closes the DAT module Copies a linear block of data from Src to Dst using DMA or EDMA hardware Performs a 2-dimensional data copy using DMA or EDMA hardware.1 Overview The data module (DAT) is used to move data around by means of DMA/EDMA hardware. there is API support that enables waiting until a given copy/fill operation completes.Overview 5. It works like this: call one of the copy/fill functions and get an ID number as a return value. These operations occur in the background on dedicated DMA hardware independent of the CPU. application code that uses the DAT module is compatible across all current devices regardless of which type of DMA controller it has. the CPU can block on completion of the operation before moving on. Table 5−1 shows the API functions within the DAT module. Then as needed. This allows the operation to be submitted and performed in the background while the CPU performs other tasks in the foreground.1. Then use this ID number later on to wait for the operation to complete. Table 5−1. 5-2 . DAT APIs Syntax DAT_busy DAT_close DAT_copy DAT_copy2d DAT_fill DAT_open DAT_setPriority DAT_SUPPORT DAT_wait Note: F = Function. Fills a linear block of memory with the specified fill value using DMA or EDMA hardware Opens the DAT module Sets the priority CPU vs DMA/EDMA A compile time constant whose value is 1 if the device supports the DAT module Waits for a previous transfer to complete See page . Because of this asynchronous nature. Therefore. This module serves as a level of abstraction such that it works the same for devices that have the DMA peripheral as for devices that have the EDMA peripheral.. There are routines to copy data from one location to another and routines to fill a region of memory.. 5-4 5-4 5-5 5-6 5-8 5-10 5-11 5-12 5-13 5.1 DAT Routines The DAT module has been intentionally kept simple.

3 DMA/EDMA Management Since the DAT module uses the DMA/EDMA peripheral. To ensure that this does not happen. the first one will be programmed into the DMA hardware immediately but the second one will have to wait until the first completes. DAT Module 5-3 . transfer completion is determined by monitoring EDMA transfer complete codes (interrupt flags). This ID number is then used by the user so that the transfer can be completed. In other words. Opening the DAT module allocates a DMA channel for exclusive use. Each call into the DAT_copy() or DAT_fill() function returns a unique transfer ID number. it must not use a DMA channel that is already allocated by the application. the DAT module uses the quick DMA feature.1. Note: For devices that have EDMA. the DAT module must be opened before use. The ID number allows the library to distinguish between multiple pending transfers. only one request may be active at once since only one DMA channel is used. The completion interrupt is not actually enabled to eliminate the overhead of taking an interrupt.4 Devices With DMA On devices that have the DMA peripheral. but the interrupt flag is still active. If you submit two requests one after the other.2 DAT Macros There are no register and field access macros dedicated to the DAT module. it must do so in a managed way. 5. The only macros used by DAT are equivalent to the DMA or EDMA macros. 5. However. This means that the module does not have to internally allocate a DMA channel.5 Devices With EDMA On devices with EDMA. 5. the DMA resource may be freed up by closing the DAT module with DAT_close().1. it is possible to have multiple requests pending because of hardware request queues. If the module is no longer needed. this is accomplished using the DAT_open() API function.1.Overview 5. you are still required to open the DAT module before use. such as the 6201. The APIs will block (spin) if called while a request is still busy by polling the transfer complete interrupt flag.1. As with the DMA.

returned by one of the DAT copy or DAT fill routines. 0). DAT_close(). DAT_close Function Arguments Return Value Description Example Closes DAT module void DAT_close().dst. DAT_PRI_LOW.. zero otherwise. while (DAT_busy(transferId)). Returns non-zero if transfer is still busy. First. any DMA channels used by the DAT module are closed.. none none Closes the DAT module. 5-4 . id busy Transfer identifier. DAT_open(DAT_CHAANY. Checks to see if a previous transfer has completed or not. identified by the transfer ID.. .len).DAT_busy 5.. any pending requests are allowed to complete. .2 Functions DAT_busy Function Arguments Return Value Description Example Checks to see if a previous transfer has completed Uint32 DAT_busy( Uint32 id). transferId = DAT_copy(src. then if applicable.

The arguments are checked for alignment and the DMA is submitted accordingly.DAT_PRI_LOW. For best efficiency. For best performance in devices other than C64x devices. A maximum of 65.0). the source and destination addresses should be aligned on an 8-byte boundary. … DAT Module 5-5 . the EDMA uses a 64-bit bus (8 bytes) to L2 SRAM. src dst byteCnt Return Value Description xfrId Pointer to source data Pointer to destination location Number of bytes to copy Transfer ID Arguments Copies a linear block of data from Src to Dst using DMA or EDMA hardware. See DAT_open(). with the transfer rate a multiple of eight.BuffB.DAT_copy DAT_copy Function Copies linear block of data from Src to Dst using DMA or EDMA hardware Uint32 DAT_copy( void *src. For C64x devices. The DAT module must be opened before calling this function. the function will block and wait for completion before submitting this request. A byteCnt of zero has unpredictable results. DAT_copy(BuffA. The return value is a transfer identifier that may be used later on to wait for completion. void *dst. If the DMA channel is busy with one or more previous requests. Example #define DATA_SIZE 256 Uint32 BuffA[DATA_SIZE/sizeof(Uint32)].535 bytes may be copied. you should ensure that the source and destination addresses are aligned on a 4-byte boundary and the transfer length is a multiple of four. Uint32 BuffB[DATA_SIZE/sizeof(Uint32)]. Uint16 byteCnt ). See DAT_wait().DATA_SIZE). depending on the device. … DAT_open(DAT_CHAANY.

The 1D part of the transfer is just a linear block of data. The 2D part is illustrated in Figure 5−1. void *dst. The arguments are checked for alignment and the hardware configured accordingly. For C64x devices. the number of bytes copied is lineLen × lineCnt. Uint16 linePitch ).DAT_copy2d DAT_copy2d Function Performs 2-dimensional data copy Uint32 DAT_copy2d( Uint32 type. This is specified using the type argument. In all cases. 2D to 1D. Note: The DAT module must be opened with the DAT_OPEN_2D flag before calling this function. For best efficiency. 5-6 . Uint16 lineCnt. If the channel is busy with previous requests.DAT_2D2D Pointer to source data Pointer to destination location Number of bytes per line Number of lines Number of bytes between start of one line to start of next line Transfer ID Arguments src dst lineLen lineCnt linePitch Return Value Description xfrId Performs a 2-dimensional data copy using DMA or EDMA hardware. There are three ways to submit a 2D transfer: 1D to 2D. the source and destination addresses should be aligned on an 8-byte boundary with the transfer rate a multiple of eight. void *src. this function will block (spin) and wait until it frees up before submitting this request. For best performance on devices other than C64x devices. and 2D to 2D. the EDMA uses a 64-bit bus (8 bytes) to L2 SRAM. type Transfer type: .DAT_1D2D . you should ensure that the source address and destination address are aligned on a 4-byte boundary and that the lineLen and linePitch are multiples of 4-bytes. depending on the device. Uint16 lineLen.DAT_2D1D . See DAT_open().

32).DAT_copy2d Figure 5−1. and linePitch. buffA. The return value is a transfer identifier that may be used later on to wait for completion. Example DAT_copy2d (DAT_1D2D. DAT Module 5-7 . lineCnt. 2D Transfer LineLen LineLen = 5 LineCnt = 6 LinePitch = 8 LineCnt LinePitch If a 2D to 2D transfer is specified. See DAT_wait(). 8. buffB. both the source and destination have the same lineLen. 16.

the fill value should contain 0xA5A5A5A5 before calling this function. For devices other than C64x devices. then the DMA transfer element size is set to 32-bits to maximize performance.535 bytes may be filled. Finally. the fill value. a 16-bit element size is used. If you want to fill the memory region with a value of 0x1234. For example. if you want to fill a region of memory with the value 0xA5.DAT_fill DAT_fill Function Fills linear block of memory with specified fill value using DMA hardware Uint32 DAT_fill( void *dst. For best performance. For C64x devices. the fill value is 8-bits in size but must be contained in a 32-bit word. A maximum of 65. It is a good idea to always fill in the entire 32-bit fill value to eliminate any endian issues. See DAT_open(). you should ensure that the destination address is aligned on a 4-byte boundary and the transfer length is a multiple of 4. must be 32-bits in size. the 8-bit fill value must be repeated to fill the 32-bit value. This is due to the way the DMA hardware works. The EDMA transfer element size is set to 64-bits. the pointer should point to two consecutive 32-bit words set to 0x12341234 value . Uint16 byteCnt. The DAT module must be opened before calling this function. The arguments are checked for alignment and the DMA is submitted accordingly. the fill count must be a multiple of 8 bytes. Uint32 *fillValue ). dst byteCnt fillValue Return Value Description xfrId Pointer to destination location Number of bytes to fill Pointer to fill value Transfer ID Arguments Fills a linear block of memory with the specified fill value using DMA hardware. This means that the source of the transfer. If the arguments are 32-bit aligned. So. an 8-bit element size is used. The EDMA uses a 64-bit bus to store data in L2 SRAM. 5-8 . If the DMA channel is busy with a previous request. A pointer of 64-bit value must be passed to the “fillvalue” parameter (a set of 8 consecutive bytes. If the arguments are 16-bit aligned. the function will block and wait for completion before submitting this request. aligned). if any of the arguments are 8-bit aligned.

… DAT_open(DAT_CHAANY. Uint32 buff[BUFF_SIZE/sizeof(Uint32)]. DAT_fill(buff. Uint32 fillValue = 0xA5A5A5A5. Uint32 fillValue[2] = {0x12341234.DAT_PRI_LOW. DAT Module 5-9 . Note: You should be aware that if the fill value is in cache.BUFF_SIZE. … DAT_open(DAT_CHAANY.0x12341234}. it is important not to write to it while the fill is in progress.DAT_PRI_LOW.DAT_fill The return value is a transfer identifier that may be used later on to wait for completion. For 64x devices: Uint32 BUFF_SIZE 256. DAT_fill(buff. It is up to you to ensure that the fill value is flushed before calling this function.&fillValue). /* 8 * 8bytes */ Uint32 buff[BUFF_SIZE/sizeof(Uint32)]. See DAT_wait().0). since the user specifies a pointer to the fill value.&fillValue). the DMA always uses the external address and not the value that is in cache. Uint32 *fillValuePtr = fillValue. Also.BUFF_SIZE.0). Example Uint32 BUFF_SIZE 256.

DAT_CHA3 Specifies the priority of the DMA channel.DAT_open DAT_open Function Opens DAT module Uint32 DAT_open( int chaNum. Arguments priority flags Return Value success for failure are: Description This function opens up the DAT module and must be called before calling any of the other DAT API functions.The DAT module is already open. chaNum Specifies which DMA channel to allocate.DAT_PRI_HIGH sets the DMA channel up for DMA priority For EDMA Devices: . Uint32 flags ).ChaNum specifies which DMA channel to use .DAT_OPEN_2D Returns zero on failure and non-zero if successful. .DAT_CHA2 .DAT_PRI_LOW sets the DMA channel up for CPU priority . Reasons .DAT_PRI_LOW . The ChaNum argument specifies which DMA channel to open for exclusive use by the DAT module.DAT_CHA1 .DAT_PRI_HIGH Miscellaneous open flags .DAT_CHAANY .Required resources could not be allocated.DAT_CHA0 . must be one of the following: . must be one of the following: . the ChaNum argument is ignored because the quick DMA is used which does not have a channel associated with it. int priority. For devices with EDMA. For DMA Devices: .ChaNum is ignored 5-10 .

Interrupts are not enabled but the completion flags in CIPR are used. Specifying this flag for devices with the DMA peripheral will cause allocation of one global count reload register and one global index register. DAT_PRI_HIGH. To open the DAT module using DMA channel 2 in high-priority mode.DAT_PRI_HIGH sets HIGH priority Once the DAT module is opened.0). use: DAT_open(DAT_CHA2. DAT_OPEN_2D). and the PRI of OPT register for devices supporting EDMA.DAT_PRI_HIGH.DAT_setPriority . These global registers are freed when DAT_close() is called. See also DAT_open() function. The priority value can be set by using the following predefined constants: DAT Module 5-11 Arguments Return Value Description Priority bit value . the DAT_OPEN_2D flag must be specified.DAT_PRI_LOW sets LOW priority . If 2D transfers are planned via DAT_copy2d. use: DAT_open (DAT_CHAANY. remain allocated. The DAT module uses interrupt completion codes 1 through 4 which amounts to a mask of 0x00000001E in the CIPR register. priority none Sets the priority bit value PRI of PRICTL register for devices supporting DMA. If you use the DAT module on devices with EDMA. Also used is the channel interrupt pending register (CIPR). DAT_setPriority Function Sets the priority of DMA or EDMA channel void DAT_setPriority( int priority ). You can call DAT_close() to free these resources. Note: For devices with EDMA.DAT_PRI_LOW. the DAT module uses the EDMA registers to submit transfer requests. any resources allocated. you must avoid using transfer completion codes 1 through 4. use: DAT_open(DAT_CHAANY. To open the DAT module for 2D copies.0). Example To open the DAT module using any available DMA channel. such as DMA channels.

DAT_SUPPORT Constant Description Compile-time constant DAT_SUPPORT Compile-time constant that has a value of 1 if the device supports the DAT module and 0 otherwise. Note: The DAT module is supported by all devices that have an EDMA or DMA peripheral.DAT_PRI_HIGH Example /* Open DAT channel with priority Low */ DAT_open(DMA_CHAANY.DAT_PRI_LOW . You are not required to use this constant.0) /* Set transfer with priority high */ DAT_setPriority(DAT_PRI_HI).DAT_SUPPORT . Example #if (DAT_SUPPORT) /* user DAT configuration */ #endif 5-12 .DAT_PRI_LOW.

… transferId = DAT_copy(src. returned by one of the DAT copy or DAT fill routines. identified by the transfer ID. Interrupts are not disabled during the wait. Uint32 transferId. If the transfer has already completed. Two predefined transfer IDs may be used: . /* user DAT configuration */ DAT_wait(transferId). DAT_PRI_LOW.DAT_XFRID_WAITALL . Example DAT Module 5-13 .DAT_wait DAT_wait Function Waits for previous transfer to complete identification by transfer ID void DAT_wait( Uint32 id ). 0).len).dst. id Transfer identifier. This can be useful as the first operation in a pipelined copy sequence. Arguments Return Value Description none This function waits for a previous transfer to complete. … DAT_open(DAT_CHAANY.DAT_XFRID_WAITNONE Using DAT_XFRID_WAITALL means wait until all transfers have completed. Using DAT_XFRID_WAITNONE means do not wait for any transfers to complete. this function returns immediately.

. . . . . . . . . . . . 6-7 Functions . .3 6. . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6.4 Page Overview . . . . 6-9 6-1 . . . . . . . . . . . . 6-5 Configuration Structures . . . . . . . . . discusses how to use a DMA channel. . . . . . . . . . . . . . . and provides a DMA API reference section. .2 6. . . . . . . . 6-2 Macros . . . . . . . . . . . . . . . . . . . . Topic 6. . . . . . . . . . . . . . . . . . .Chapter 6 DMA Module This chapter describes the DMA module. . . . . . . . . . . . . . . . . . . . . . .

DMA APIs (a) DMA Primary Functions Syntax DMA_close DMA_config DMA_configArgs DMA_open DMA_pause DMA_reset DMA_start DMA_stop Note: Type Description F F F F F F F F Closes a DMA channel opened via DMA_open() Sets up the DMA channel using the configuration structure Sets up the DMA channel using the register values passed in Opens a DMA channel for use Pauses the DMA channel by setting the START bits in the primary control register appropriately Resets the DMA channel by setting its registers to power-on defaults Starts a DMA channel running without auto−initialization Stops a DMA channel by setting the START bits in the primary control register appropriately See page .1 Overview Currently..Overview 6. Devices such as the C6201™ have the DMA peripheral.. Table 6−1. DMA Configuration Structures Structure DMA_Config DMA_GlobalConfig Purpose DMA structure that contains all local registers required to set up a specific DMA channel Global DMA structure that contains all global registers that you may need to initialize a DMA channel See page .. 6-9 6-9 6-10 6-11 6-12 6-12 6-13 6-13 F = Function. Table 6−2 lists the functions and constants available in the CSL DMA module. C = Constant. whereas the C6211™ has the EDMA peripheral. The two architectures are different enough to warrant a separate API module for each. 6-7 6-8 Table 6−2. Table 6−1 lists the configuration structures for use with the DMA functions. M = Macro 6-2 . the are two DMA architectures used on TMS320C6x™ devices are: DMA and EDMA (enhanced DMA)..

C = Constant. 6-14 6-16 6-16 6-17 6-18 6-19 6-20 6-22 6-22 6-23 (c) DMA Auxiliary Functions. M = Macro DMA Module 6-3 . 6-23 6-24 6-24 6-24 6-24 6-25 6-25 6-25 6-25 6-25 F = Function... DMA APIs (Continued) (b) DMA Global Register Functions Syntax DMA_allocGlobalReg DMA_freeGlobalReg DMA_getGlobalReg DMA_getGlobalRegAddr DMA_globalAlloc DMA_globalConfig DMA_globalConfigArgs DMA_globalFree DMA_globalGetConfig DMA_setGlobalReg Type Description F F F F F F F F F F Provides resource management for the DMA global registers Frees a global DMA register previously allocated by calling DMA_AllocGlobalReg() Reads a global DMA register that was previously allocated by calling DMA_AllocGlobalReg() Gets DMA global register address Allocates DMA global registers Configures entry for DMA configuration structure Configures entry for DMA registers Frees Allocated DMA global register Returns the entry for the DMA configuration structure Sets value of a global DMA register previously allocated by calling DMA_AllocGlobalReg() See page ...Overview Table 6−2. Constants. and Macros Syntax DMA_autoStart DMA_CHA_CNT DMA_CLEAR_CONDITION DMA_GBLADDRA DMA_GBLADDRB DMA_GBLADDRC DMA_GBLADDRD DMA_GBLCNTA DMA_GBLCNTB DMA_GBLIDXA Note: Type Description F C M C C C C C C C Starts a DMA channel with auto−initialization Number of DMA channels for the current device Clears condition flag DMA global address register A mask DMA global address register B mask DMA global address register C mask DMA global address register D mask DMA global count reload register A mask DMA global count reload register B mask DMA global index register A mask See page .

you must first open it and obtain a device handle using DMA_open(). M = Macro 6. there are DMA_RMK (make) macros that construct register values based on field values. there are symbol constants that may be used for the field values.1. The channel may be configured by passing a DMA_Config structure to DMA_config() or by passing register values to the DMA_configArgs() function.1 Using a DMA Channel To use a DMA channel. C = Constant. DMA APIs (Continued) DMA_GBLIDXB DMA_GET_CONDITION DMA_getConfig DMA_getEventId DMA_getStatus DMA_restoreStatus DMA_setAuxCtl DMA_SUPPORT DMA_wait Note: C M F F F F F C F DMA global index register B mask Gets condition flag Reads the current DMA configuration structure Returns the IRQ event ID for the DMA completion interrupt Reads the status bits of the DMA channel Restores the status from DMA_getStatus() by setting the START bit of the PRICTL primary control register Sets the DMA AUXCTL register A compile time constant whose value is 1 if the device supports the DMA module Enters a spin loop that polls the DMA status bits until the DMA completes 6-26 6-26 6-26 6-27 6-27 6-27 6-28 6-28 6-29 F = Function. and DMA_getGlobalReg(). Once opened. To assist in creating register values.Overview Table 6−2. 6-4 . you use the device handle to call the other API functions. DMA_allocGlobalReg(). DMA_setGlobalReg(). DMA_freeGlobalReg(). In addition. There are functions for managing shared global DMA registers.

.<FIELD>) DMA_FSET(<REG>. and Table 6−4 lists the DMA macros that construct register and field values.<REG>) DMA_RSETA(addr. and those that construct register and field values. Table 6−3.<REG>) DMA_RGETH(h.<FIELD>.x) DMA_FGET(<REG>.<REG>.<REG>. Using the HAL Macros. The macros themselves are found in Chapter 28.<SYM>) DMA_RGETA(addr.<REG>. Table 6−3 lists the DMA macros that access registers and fields. <SYM>) DMA_ADDRH(h.<REG>.<FIELD>) DMA_FSETH(h. The DMA module includes handle-based macros.x) DMA_FGETA(addr.<REG>. DMA Macros that Access Registers and Fields Macro DMA_ADDR(<REG>) DMA_RGET(<REG>) DMA_RSET(<REG>.x) DMA_FGETH(h.<REG>) DMA_RSETH(h.<FIELD>) DMA_FSETA(addr..<REG>.Macros 6.fieldval) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address Returns the address of a memory-mapped register for a given handle Returns the value of a register for a given handle Sets the register value to x for a given handle Returns the value of the field for a given handle Sets the field value to x for a given handle See page .<FIELD>.fieldval) DMA_FSETS(<REG>.<REG>.<FIELD>. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 28-12 28-19 28-21 28-14 28-16 DMA Module 6-5 .<FIELD>.<FIELD>.2 Macros There are two types of DMA macros: those that access registers and fields.fieldval) DMA_FSETSA(addr.

. Field symbolic value See page .Macros Table 6−4. DMA Macros that Construct Register and Field Values Macro DMA_<REG>_DEFAULT DMA_<REG>_RMK() DMA_<REG>_OF() DMA_<REG>_<FIELD>_DEFAULT DMA_FMK() DMA_FMKS() DMA_<REG>_<FIELD>_OF() DMA_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of .. Field default value Field make Field make symbolically Field value of ... 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 6-6 ...

You create and initialize this structure and then pass its address to the DMA_config() function.3 Configuration Structures Because the DMA has both local and global registers for each channel. Example DMA Module 6-7 .&MyConfig). as well as src/dst page registers. /* dst */ 0x00200040 /* xfrcnt */ }. DMA_Config Structure Members DMA configuration structure used to set up DMA channel DMA_Config Uint32 prictl Uint32 secctl Uint32 src Uint32 dst Uint32 xfrcnt DMA primary control register value DMA secondary control register value DMA source address register value DMA destination address register value DMA transfer count register value Description This DMA configuration structure is used to set up a DMA channel. /* secctl */ 0x80000000.DMA_Config 6. and include element/frame indexes and reload registers. the CSL DMA module has two configuration structures: . /* src */ 0x80010000.DMA_Config (channel configuration structure) contains all the local registers required to set up a specific DMA channel. /* prictl */ 0x00000080. DMA_Config MyConfig = { 0x00000050. These global registers are resources shared across the different DMA channels. You can use literal values or the _RMK macros to create the structure member values. . You can use literal values or the _RMK macros to create the structure member values.DMA_GlobalConfig (global configuration structure) contains all the global registers needed to initialize a DMA channel. … DMA_config(hDma.

You create and initialize this structure. then pass its address to the DMA_globalConfig() function. Global address register D value. /* Global Address Register C */ 0x00000000. Uint32 addrD. DMA_globalConfig(dmaGblRegMsk. Uint32 dmaGblRegMsk. Uint32 idxB. Uint32 addrB. /* Global Index Register B */ 0x00000000. Uint32 addrC. /* Global Address Register B */ 0x80002000. Global address register B value. addrA addrB addrC addrD idxA idxB cntA cntB Global address register A value. Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC.DMA_GlobalConfig DMA_GlobalConfig DMA global register configuration structure Structure typedef struct { Uint32 addrA. &dmaGblCfg). Uint32 cntB. Global count reload register A value. Global count reload register B value. } DMA_GlobalConfig. /* Global Count Reload Register A */ 0x00000000 /* Global Count Reload Register B */ }. /* Global Address Register D */ 0x00000000. Members Description This is the DMA global register configuration structure used to set up a DMA global register configuration. /* Global Index Register A */ 0x00000000. Global index register B value. DMA_GlobalConfig dmaGblCfg = { 0x00000000. Uint32 idxA. dmaGblRegMsk = DMA_globalAlloc(dmaGblRegId). Example 6-8 . /* Global Address Register A */ 0x80001000. Global index register A value. Uint32 cntA. Global address register C value.

see DMA_open() Example DMA_config Function Sets up DMA channel using configuration structure void DMA_config( DMA_Handle hDma. See also DMA_configArgs() and DMA_Config. DMA_Config MyConfig = { 0x00000050. DMA_Config *Config ). DMA_close(hDma). The values of the structure are written to the DMA registers. The registers for the DMA channel are set to their power-on defaults and the completion interrupt is disabled and cleared. hDma none This function closes a DMA channel previously opened via DMA_open(). /* prictl */ 0x00000080.4 Functions 6.DMA_close 6.&MyConfig). … DMA_config(hDma. The primary control register (prictl) is written last. hDma Config Handle to DMA channel. DMA Module 6-9 Example .4. /* dst */ 0x00200040 /* xfrcnt */ }. /* src */ 0x80010000. DMA_close Function Arguments Return Value Description Handle to DMA channel. /* secctl */ 0x80000000.1 Primary Functions Closes DMA channel opened via DMA_open() void DMA_close( DMA_Handle hDma ). See DMA_open() Pointer to an initialized configuration structure Arguments Return Value Description none Sets up the DMA channel using the configuration structure.

/* prictl 0x00000080. hDma prictl secctl src dst xfrcnt Handle to DMA channel. Uint32 xfrcnt ). Uint32 prictl. Uint32 secctl. Uint32 dst. */ */ */ */ */ 6-10 . /* src 0x80010000. See also DMA_config(). You may use the _RMK macros to create the register values based on field values. /* dst 0x00200040 /* xfrcnt ). Uint32 src. The primary control register (prictl) is written last. /* secctl 0x80000000. You may use literal values for the arguments or for readability. Example DMA_configArgs(hDma. The register values are written to the DMA registers. See DMA_open() Primary control register value Secondary control register value Source address register value Destination address register value Transfer count register value Arguments Return Value Description none Sets up the DMA channel using the register values passed in.DMA_configArgs DMA_configArgs Function Sets up DMA channel using register values passed in void DMA_configArgs( DMA_Handle hDma. 0x00000050.

… hDma = DMA_open(DMA_CHAANY. The return value is a unique device handle that you use in subsequent DMA API calls. Uint32 flags ). Once opened.DMA_CHA2 . If the open fails.DMA_CHA1 . Example DMA_Handle hDma.DMA_CHA3 Open flags (logical OR of DMA_OPEN_RESET) Arguments flags Return Value Description Device Handle Handle to newly opened device Before a DMA channel can be used.DMA_CHA0 .DMA_CHAANY . INV is returned. the DMA channel registers are set to their power-on defaults and the channel interrupt is disabled and cleared. See DMA_close(). If the DMA_OPEN_RESET is specified.DMA_open DMA_open Function Opens DMA channel for use DMA_Handle DMA_open( int chaNum. it cannot be opened again until closed. DMA Module 6-11 . chaNum DMA channel to open: . it must first be opened by this function. You have the option of either specifying exactly which physical channel to open or you can let the library pick an unused one for you by specifying DMA_CHAANY.DMA_OPEN_RESET).

Arguments Return Value Description Handle to DMA channel. Arguments Return Value Description Handle to DMA channel. hDma none This function pauses the DMA channel by setting the START bits in the primary control register accordingly. hDma none Resets the DMA channel by setting its registers to power-on defaults and disabling and clearing the channel interrupt. DMA_pause(hDma). and DMA_autoStart(). / reset all DMA channels */ DMA_reset(INV).DMA_pause DMA_pause Function Pauses DMA channel by setting START bits in primary control register void DMA_pause( DMA_Handle hDma ). See also DMA_start(). /* reset an open DMA channel / DMA_reset(hDma). See DMA_open() Example 6-12 . See DMA_open() Example DMA_reset Function Resets DMA channel by setting its registers to power-on defaults void DMA_reset( DMA_Handle hDma ). DMA_stop(). You may use INV as the device handle to reset all channels.

DMA_start DMA_start Function Starts DMA channel running without auto−initialization void DMA_start( DMA_Handle hDma ). see DMA_open() Example DMA_stop Function Stops DMA channel by setting START bits in primary control register void DMA_stop( DMA_Handle hDma ). and DMA_autoStart(). DMA_stop(). See also DMA_pause(). Arguments Return Value Description Handle to DMA channel. hDma none Starts a DMA channel running without auto−initialization by setting the START bits in the primary control register accordingly. Arguments Return Value Description Handle to DMA channel. DMA_start(hDma). and DMA_autoStart(). See DMA_open() Example DMA Module 6-13 . DMA_stop(hDma). See also DMA_pause(). hDma none Stops a DMA channel by setting the START bits in the primary control register accordingly. DMA_start().

2 DMA Global Register Functions DMA_allocGlobalReg Function Allocates global DMA register Uint32 DMA_allocGlobalReg( DMA_Gbl regType.DMA_GBL_INDEX .DMA_GBL_SPLIT Value to initialize the register to Arguments initVal Return Value Description Global Register ID Unique ID number for the global register Since the DMA global registers are shared. Uint32 initVal ). Will allocate one of the following DMA registers: J J J Global Address Register B Global Address Register C Global Address Register D .DMA_allocGlobalReg 6.DMA_GBL_ADDRRLD . regType Global register type. they must be controlled using resource management. If the register cannot be allocated. The register ID may directly be used with the DMA_PRICTL_RMK macro. Allocating a register ensures that it will not be reallocated until it is freed. must be one of the following: . a register ID of 0 is returned.DMA_GBL_CNTRLD . The register ID may then be used to get or set the register value by calling DMA_getGlobalReg() and DMA_setGlobalReg() respectively.4. Will allocate one of the following DMA registers: J J 6-14 Global Index Register A Global Index Register B .DMA_GBL_INDEX Allocate global index register for use as DMA INDEX. . This is done using DMA_allocGlobalReg() and DMA_freeGlobalReg() functions.DMA_GBL_ADDRRLD Allocate global address register for use as DMA DST RELOAD or DMA SRC RELOAD.

… /* allocate global index register and initialize it */ RegId = DMA_allocGlobalReg(DMA_GBL_ INDEX.0x00200040).DMA_GBL_CNTRLD Allocate global count reload register for use as DMA CNT RELOAD. DMA Module 6-15 . Will allocate one of the following DMA registers: J J Global Count Reload Register A Global Count Reload Register B .DMA_allocGlobalReg .DMA_GBL_SPLIT Allocate global address register for use as DMA SPLIT. Will allocated one of the following DMA registers: J J J Global Address Register A Global Address Register B Global Address Register C Example Uint32 RegId.

0x00200040). regId none This function frees a global DMA register that was previously allocated by calling DMA_allocGlobalReg(). … /* some time later on when you’re done with it */ DMA_freeGlobalReg(RegId). You should be aware that use of predefined register IDs precludes the use of alloc/free. Arguments Return Value Description Global register ID obtained from DMA_allocGlobalReg(). … /* allocate global index register and initialize it */ RegId = DMA_allocGlobalReg(DMA_GBL_INDEX. regId Global register ID obtained from DMA_allocGlobalReg().DMA_freeGlobalReg DMA_freeGlobalReg Frees global DMA register that was previously allocated Function void DMA_freeGlobalReg( Uint32 regId ). the register is available for reallocation. the predefined register IDs may be used. Once freed. Example DMA_getGlobalReg Function Reads global DMA register that was previously allocated Uint32 DMA_getGlobalReg( Uint32 regId ). If you prefer not to use the alloc/free paradigm for the global register management. The list of predefined IDs are shown below: 6-16 . Arguments Return Value Description Register Value Value read from register This function returns the register value of the global DMA register that was previously allocated by calling DMA_allocGlobalReg(). Uint32 RegId.

0x00200040). Uint32 regAddr. Example Uint32 RegId. DMA_getGlobalRegAddr Gets DMA global register address Function Uint32 DMA_getGlobalRegAddr( Uint32 regId ). regAddr = DMA_getGlobalRegAddr(regId). … RegValue = DMA_getGlobalReg(RegId). Uint32 regId = DMA_GBL_ADDRRLDB. … /* allocate global index register and initialize it / RegId = DMA_allocGlobalReg(DMA_GBL_ INDEX. DMA Module 6-17 .DMA_getGlobalRegAddr DMA_GBL_ADDRRLDB DMA_GBL_ADDRRLDC DMA_GBL_ADDRRLDD DMA_GBL_INDEXA DMA_GBL_INDEXB DMA_GBL_CNTRLDA DMA_GBL_CNTRLDB DMA_GBL_SPLITA DMA_GBL_SPLITB DMA_GBL_SPLITC - Note: DMA_GBL_ADDRRLDB denotes the same physical register as DMA_GBL_SPLITB and DMA_GBL_ADDRRLDC denotes the same physical register as DMA_GBL_SPLITC. regId Uint32 DMA global registers ID DMA global register address corresponding to regId Arguments Return Value Description Example Get DMA global register address and return the address value. Uint32 RegValue.

DMA_globalAlloc DMA_globalAlloc Function Allocates DMA global registers Uint32 DMA_globalAlloc( Uint32 regs ). regs Uint32 DMA global registers ID Allocated DMA global registers mask Arguments Return Value Description Allocates DMA global registers and returns a mask of allocated DMA global registers. Uint32 dmaGblRegMsk. Mask depends on DMA global register ID and the availability of the register. DmaGblRegMsk = DMA_globalAlloc(regs). Uint32 regs = DMA_GBLADDRB | DMA_GBLADDRC. Example 6-18 .

/* Global Index Register B */ 0x00000000. dmaGblRegMsk = DMA_globalAlloc(dmaGblRegId). Arguments DMA global register mask Pointer to an initialized configuration structure. /* Global Address Register A */ 0x80001000. Example DMA Module 6-19 . Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC. /* Global Address Register D */ 0x00000000. The values of the structure that are written to the DMA global registers depend on the DMA global register mask. &dmaGblCfg). regs cfg Return Value Description none Sets up the DMA global registers using the configuration structure. /* Global Address Register C */ 0x00000000. /* Global Address Register B */ 0x80002000. DMA_GlobalConfig dmaGblCfg = { 0x00000000. /* Global Index Register A */ 0x00000000. Uint32 dmaGblRegMsk. DMA_GlobalConfig *cfg ). DMA_globalConfig(dmaGblRegMsk.DMA_globalConfig DMA_globalConfig Sets up the DMA global registers using the configuration structure Function void DMA_globalConfig( Uint32 regs. /* Global Count Reload Register A */ 0x00000000 /* Global Count Reload Register B */ }.

Global index register A value. DMA global register mask value. Global count reload register B value. The register values that are written to the DMA global registers depend on the DMA global register mask. Global address register A value. Global address register C value. Uint32 addrB. Uint32 addrA. Uint32 idxA.DMA_globalConfigArgs DMA_globalConfigArgs Function Establishes DMA global register value void DMA_globalConfigArgs( Uint32 regs. Uint32 addrD. Global count reload register A value. Uint32 cntB ). regs addrA addrB addrC addrD idxA idxB cntA cntB none Sets up the DMA global registers using the register values passed in. Uint32 idxB. Uint32 cntA. Arguments Return Value Description 6-20 . Global address register B value. Global index register B value. Global address register D value. Uint32 addrC.

addrD. Uint32 idxA = 0x00000000. idxB. addrA. Uint32 cntB = 0x00000000. DMA_globalConfigArgs( dmaGblRegMsk. cntA. Uint32 cntA = 0x00000000. Uint32 addrA = 0x00000000.DMA_globalConfigArgs Example Uint32 dmaGblRegMsk. dmaGblRegMsk = DMA_globalAlloc(dmaGblRegId). Uint32 idxB = 0x00000000. Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC. Uint32 addrC = 0x80002000. Uint32 addrB = 0x80001000. addrC. addrB. idxA. DMA Module 6-21 . Uint32 addrD = 0x00000000. cntB ).

Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC. 6-22 . DMA_globalGetConfig(dmaGblRegId. regs cfg DMA global register ID Pointer to an initialized configuration structure. depends on regs. DMA_GlobalConfig *cfg ). regs none Frees previously allocated DMA global registers. DMA_globalFree(dmaGblRegId). DMA_GlobalConfig dmaGblCfg.DMA_globalFree DMA_globalFree Function Frees allocated DMA global registers Void DMA_globalFree( Uint32 regs ). &dmaGblCfg). Arguments Return Value Description Example DMA global registers ID DMA_globalGetConfig Function Gets current DMA global register configuration value void DMA_globalGetConfig( Uint32 regs. Uint32 dmaGblRegId = DMA_GBLADDRB | DMA_GBLADDRC. Arguments Return Value Description Example none Gets DMA global registers current configuration value depending on DMA global register ID.

0x12345678). Constants.3 DMA Auxiliary Functions. Uint32 val ). regId val Global register ID obtained from DMA_allocGlobalReg(). … DMA_setGlobalReg(RegId. Arguments Return Value Description Handle to DMA channel.DMA_setGlobalReg DMA_setGlobalReg Function Sets value of global DMA register that was previously allocated void DMA_setGlobalReg( Uint32 regId. 6. … /* allocate global index register and initialize it / RegId = DMA_allocGlobalReg(DMA_GBL_INDEX. See also DMA_pause(). Value to set register to Arguments Return Value Description Example none This function sets the value of a global DMA register that was previously allocated by calling DMA_allocGlobalReg().0x00200040). DMA_autoStart(hDma).4. DMA_stop(). and DMA_start(). see DMA_open() Example DMA Module 6-23 . Uint32 RegId. hDma none Starts a DMA channel running with autoinitialization by setting the START bits in the primary control register accordingly. and Macros DMA_autoStart Function Starts DMA channel with autoinitialization void DMA_autoStart( DMA_Handle hDma ).

DMA_globalConfig(). See the TMS320C6000 Peripherals Reference Guide (SPRU190) for a description of the condition flags. must be one of the following: .DMA_SECCTL_LASTCOND . See DMA_globalAlloc(). DMA_GBLADDRB DMA global address register B mask Constant Description DMA_GBLADDRB This constant allows selection of the global address register B.DMA_SECCTL_BLOCKCOND . Clears one of the condition flags in DMA secondary control register DMA_CLEAR_CONDITION Macro DMA_CLEAR_CONDITION( hDma. hDma COND Handle to DMA channel. See DMA_globalAlloc(). DMA_CLEAR_CONDITION(hDma. and DMA_globalConfigArgs() functions. COND ).DMA_SECCTL_FRAMECOND .DMA_SECCTL_BLOCKCOND).DMA_SECCTL_WDROPCOND Arguments Return Value Description none This macro clears one of the condition flags in the DMA secondary control register. DMA_globalConfig(). 6-24 . see DMA_open() Condition to clear.DMA_SECCTL_SXCOND . Example DMA_GBLADDRA DMA global address register A mask Constant Description DMA_GBLADDRA This constant allows selection of the global address register A. and DMA_globalConfigArgs() functions.DMA_CHA_CNT DMA_CHA_CNT Constant Description Number of DMA channels for current device DMA_CHA_CNT This constant holds the number of physical DMA channels for the current device.DMA_SECCTL_RDROPCOND .

DMA_globalConfig(). See DMA_globalAlloc(). DMA_globalConfig(). See DMA_globalAlloc(). and DMA_globalConfigArgs() functions.DMA_GBLADDRC DMA_GBLADDRC DMA global address register C mask Constant Description DMA_GBLADDRC This constant allows selection of the global address register C. See DMA_globalAlloc(). See DMA_globalAlloc(). DMA_globalConfig(). DMA_GBLADDRD DMA global address register D mask Constant Description DMA_GBLADDRD This constant allows selection of the global address register D. DMA_GBLCNTA Constant Description DMA global count reload register A mask DMA_GBLCNTA This constant allows selection of the global count reload register A. and DMA_globalConfigArgs() functions. DMA_GBLCNTB Constant Description DMA global count reload register B mask DMA_GBLCNTB This constant allows selection of the global count reload register B. DMA_GBLIDXA Constant Description DMA global index register A mask DMA_GBLIDXA This constant allows selection of the global index register A. DMA_globalConfigArgs(). and DMA_globalConfig() functions. and DMS_globalConfigArgs() functions. See DMA_globalAlloc(). DMA Module 6-25 . and DMA_globalConfigArgs() functions. DMA_globalConfig().

must be one of the following: . 0 if clear. DMA_GET_CONDITION Macro Gets one of the condition flags in DMA secondary control register DMA_GET_CONDITION( hDma. hDma config DMA handle. See DMA_open() Pointer to a configuration structure Arguments 6-26 . if (DMA_GET_CONDITION(hDma.DMA_GBLIDXB DMA_GBLIDXB Constant Description DMA global index register B mask DMA_GBLIDXB This constant allows selection of the global index register B. 1 if set Arguments Return Value Description Condition This macro gets one of the condition flags in the DMA secondary control register.DMA_SECCTL_RDROPCOND . COND ). See DMA_globalAlloc().DMA_SECCTL_WDROPCOND Condition. and DMA_globalConfigArgs() functions. DMA_Config *config ).DMA_SECCTL_BLOCKCOND)) { /* user DMA configuration */ } Example DMA_getConfig Function Reads the current DMA configuration values void DMA_getConfig( DMA_Handle hDma. hDma COND Handle to DMA channel.DMA_SECCTL_SXCOND . DMA_globalConfig(). See the TMS320C6000 Peripherals Reference Guide (SPRU190) for a description of the condition flags.DMA_SECCTL_BLOCKCOND .DMA_SECCTL_FRAMECOND .DMA_SECCTL_LASTCOND . See DMA_open() Condition to get.

DMA_getEventId Return Value Description Example none Get DMA current configuration value DMA_config dmaCfg. see DMA_open() Current DMA channel status: .DMA_STATUS_AUTORUNNING Arguments Return Value Description Example This function reads the STATUS bits of the DMA channel.DMA_STATUS_PAUSED . See DMA_open() Status from DMA_getStatus() function DMA Module 6-27 Arguments . DMA_getConfig(hDma. IRQ_enable(EventId). Uint32 status ). Use this ID to manage the event using the IRQ module. DMA_getStatus Function Reads status bits of DMA channel Uint32 DMA_getStatus( DMA_Handle hDma ).DMA_STATUS_RUNNING .DMA_STATUS_STOPPED . EventId = DMA_getEventId(hDma). DMA_restoreStatus Restores the status from DMA_getStatus() Function void DMA_restoreStatus( Uint32 hDma. hDma status Handle to DMA channel. while (DMA_getStatus(hDma)==DMA_STATUS_RUNNING). See DMA_open() IRQ Event ID for DMA Channel Arguments Return Value Description Example Returns the IRQ Event ID for the DMA completion interrupt. hDma Status Value Handle to DMA channel. hDma Event ID Handle to DMA channel. DMA_getEventId Function Returns IRQ event ID for DMA completion interrupt Uint32 DMA_getEventId( DMA_Handle hDma ). &dmaCfg).

status). Example #if (DMA_SUPPORT) /* user DMA configuration / #elif (EDMA_SUPPORT) / user EDMA configuration */ #endif 6-28 . You are not required to use this constant.. status = DMA_getStatus(hDma). In these cases. DMA_restoreStatus(hDma. . You may use the DMA_AUXCTL_RMK macro to construct the register value based on field values. the EDMA module is supported instead. DMA_setAuxCtl Function Sets DMA AUXCTL register void DMA_setAuxCtl( Uint32 auxCtl ).DMA_setAuxCtl Return Value Description Example none Restores the status from DMA_getStatus() by setting the START bit of the PRICTL primary control register. The default value for this register is DMA_AUXCTL_DEFAULT.. Note: The DMA module is not supported on devices that do not have the DMA peripheral. auxCtl none This function sets the DMA AUXCTL register. Arguments Return Value Description Value to set AUXCTL register to Example DMA_SUPPORT Constant Description Compile time constant DMA_SUPPORT Compile time constant that has a value of 1 if the device supports the DMA module and 0 otherwise. DMA_setAuxCtl(0x00000000).

Arguments Return Value Description Handle to DMA channel. Interrupts are not disabled during this loop. This function is equivalent to the following line of code: while (DMA_getStatus(hDma)&DMA_STATUS_RUNNING). DMA Module 6-29 . hDma none This function enters a spin loop that polls the DMA status bits until the DMA completes. See DMA_open() Example DMA_wait(hDma).DMA_wait DMA_wait Function Enters spin loop that polls DMA status bits until DMA completes void DMA_wait( DMA_Handle hDma ).

. . . . . . . . . . . . . . 7-8 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Functions . . . . . . . . . . . . . . . . . . . . . discusses how to use an EDMA channel. . . . . . . . . . and provides an EDMA API reference section. .4 Page Overview . . . . 7-2 Macros . . . .3 7. . . . . .1 7. Topic 7. . . . .Chapter 7 EDMA Module This chapter describes the EDMA module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . .2 7. . . . . . . . . . . . . . . . . . 7-5 Configuration Structure . . . . . . . . . . . . . . . . . . .

C = Constant Type Description F F C F F F Allocates a parameter RAM table from PRAM Allocates set of parameter RAM tables from PRAM Number of EDMA channels Sets the TCC. The two architectures are different enough to warrant a separate API module for each. EDMA Configuration Structure Structure EDMA_Config Purpose The EDMA configuration structure used to set up an EDMA channel See page .. 7-16 7-17 7-17 7-18 7-19 7-20 7-2 .Overview 7. Table 7−2 lists the functions and constants available in the CSL EDMA module.1 Overview Currently. 7-8 7-8 7-9 7-10 7-15 (b) EDMA Auxiliary Functions and Constants Syntax EDMA_allocTable EDMA_allocTableEx EDMA_CHA_CNT EDMA_chain EDMA_clearChannel EDMA_clearPram Note: F = Function.TCINT fields of the parent EDMA handle Clears the EDMA event flag in the EDMA channel event register Clears the EDMA parameter RAM (PRAM) See page . Devices such as the C6201™ have the DMA peripheral whereas C6211™ devices have the EDMA peripheral.. EDMA APIs (a) EDMA Primary Functions Syntax EDMA_close EDMA_config EDMA_configArgs EDMA_open EDMA_reset Type Description F F F F F Closes a previously opened EDMA channel Sets up the EDMA channel using the configuration structure Sets up the EDMA channel using the EDMA parameter arguments Opens an EDMA channel Resets the given EDMA channel See page . 7-7 Table 7−2. there are two DMA architectures used on C6x devices: DMA and EDMA (Enhanced DMA).. Table 7−1... Table 7−1 lists the configuration structures for use with the EDMA functions..

Overview Table 7−2. EDMA APIs (Continued) Syntax EDMA_disableChaining EDMA_enableChaining EDMA_disableChannel EDMA_enableChannel EDMA_freeTable EDMA_freeTableEx EDMA_getChannel EDMA_getConfig EDMA_getPriQStatus EDMA_getScratchAddr EDMA_getScratchSize EDMA_getTableAddress EDMA_intAlloc EDMA_intClear EDMA_intDefaultHandler EDMA_intDisable EDMA_intDispatcher EDMA_intEnable EDMA_intFree EDMA_intHook EDMA_intTest EDMA_link EDMA_qdmaConfig EDMA_qdmaConfigArgs Note: F = Function... C = Constant Type Description F F F F F F F F F F F F F F F F F F F F F F F F Disables EDMA chaining Enables EDMA chaining Disables an EDMA channel Enables an EDMA channel Frees up a PRAM table previously allocated Frees a previously allocated set of parameter RAM tables Returns the current state of the channel event Reads the current EDMA configuration values Returns the value of the priority queue status register (PQSR) Returns the starting address of the EDMA PRAM used as non-cacheable on-chip SRAM (scratch area) Returns the size (in bytes) of the EDMA PRAM used as non-cacheable on-chip SRAM (scratch area) Returns the 32-bit absolute address of the table Allocates a transfer complete code Clears EDMA transfer completion interrupt pending flag Default function called by EDMA_intDispatcher() Disables EDMA transfer completion interrupt Calls an ISR when CIER[x] and CIPR[x] are both set Enables EDMA transfer completion interrupt Frees a transfer complete code previously allocated Hooks to an ISR channel which is called by EDMA_intDispatcher() Tests EDMA transfer completion interrupt pending flag Links two EDMA transfers together Sets up QDMA registers using configuration structure Sets up QDMA registers using arguments See page . 7-20 7-20 7-21 7-21 7-22 7-22 7-23 7-23 7-24 7-24 7-24 7-25 7-25 7-25 7-26 7-26 7-26 7-27 7-27 7-28 7-29 7-29 7-30 7-31 EDMA Module 7-3 .

In addition. use the device handle to call the other API functions..Overview Table 7−2. (PRAM) tables: 7-4 .1. To assist in creating register values. the _RMK (make) macros construct register values based on field values. C = Constant Type Description F F F F F C C Resets all EDMA channels supported by the chip device Resets the Priority queue length to the default value Triggers an EDMA channel by writing to the appropriate bit in the event set register (ESR) Sets the polarity of the event associated with the EDMA handle. The channel may be configured by passing an EDMA_Config structure to EDMA_config() or by passing register values to the EDMA_configArgs() function. 7-32 7-32 7-32 7-33 7-33 7-34 7-34 7. EDMA APIs (Continued) Syntax EDMA_resetAll EDMA_resetPriQLength EDMA_setChannel EDMA_setEvtPolarity EDMA_setPriQLength EDMA_SUPPORT EDMA_TABLE_CNT Note: F = Function. Two functions manage the parameter RAM EDMA_allocTable() and EDMA_freeTable()..1 Using an EDMA Channel To use an EDMA channel. the symbol constants may be used for the field values. Once opened. you must first open it and obtain a device handle using EDMA_open(). Sets the length of a given priority queue allocation register A compile-time constant whose value is 1 if the device supports the EDMA module A compile-time constant that holds the total number of parameter table entries in the EDMA PRAM See page .

EDMA Macros That Access Registers and Fields Macro EDMA_ADDR(<REG>) EDMA_RGET(<REG>) EDMA_RSET(<REG>.<FIELD>) EDMA_FSETH(h. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 28-12 28-19 28-21 28-14 28-16 28-18 EDMA Module 7-5 . The macros themselves are found in Chapter 28.<FIELD>) EDMA_FSET(<REG>. Using the HAL Macros.x) EDMA_FGETH(h.<FIELD>) EDMA_FSETA(addr.2 Macros There are two types of EDMA macros: those that access registers and fields.<FIELD>.<REG>.<REG>.<REG>..<FIELD>. and Table 7−4 lists the EDMA macros that construct register and field values.<FIELD>. Table 7−3 lists the EDMA macros that access registers and fields. Table 7−3.<REG>) EDMA_RSETH(h.<REG>.<REG>) EDMA_RGETH(h.<FIELD>..<REG>.<REG>.x) EDMA_FSETSH(h.x) EDMA_FSETSA(addr.<FIELD>.x) EDMA_FSETS(<REG>.<REG>. The EDMA module includes handle-based macros.Macros 7.x) EDMA_FGET(<REG>.<SYM>) EDMA_RGETA(addr. <SYM>) Description/Purpose Register address Returns the current value of a register Register set Returns the value of the specified field in a register Writes fieldval to the specified field in a register Writes the symbol value to the specified field in the peripheral Gets register value for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address Returns the address of a memory-mapped register for a given handle Returns the value of a register for a given handle Sets the register value to x for a given handle Returns the value of the field for a given handle Sets the field value to x for a given handle Sets the field symbolically for a given handle See page. and those that construct register and field values.x) EDMA_FGETA(addr.<FIELD>. <SYM>) EDMA_ADDRH(h.<REG>) EDMA_RSETA(addr.<REG>.

Field default value Field make Field make symbolically Field value of .. 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 7-6 .. EDMA Macros that Construct Register and Field Values Macro EDMA_<REG>_DEFAULT EDMA_<REG>_RMK() EDMA_<REG>_OF() EDMA_<REG>_<FIELD>_DEFAULT EDMA_FMK() EDMA_FMKS() EDMA_<REG>_<FIELD>_OF() EDMA_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of . Field symbolic value See page...Macros Table 7−4...

3 Configuration Structure EDMA_Config Structure Members EDMA configuration structure used to set up EDMA channel EDMA_Config Uint32 opt Uint32 src Uint32 cnt Uint32 dst Uint32 idx Uint32 rld Options Source address Transfer count Destination address Index Element count reload and link address Description This is the EDMA configuration structure used to set up an EDMA channel. /* src */ 0x00000040. You create and initialize this structure and then pass its address to the EDMA_config() function. /* cnt */ 0x80010000. … EDMA_config(hEdma.&myConfig). /* dst */ 0x00000004. Example EDMA Module 7-7 . EDMA_Config myConfig = { 0x41200000. /* idx */ 0x00000000 /* rld */ }.EDMA_Config 7. /* opt */ 0x80000000.

Pointer to an initialized configuration structure Arguments Return Value Description none Sets up the EDMA channel using the configuration structure.From EDMA_allocTable() 7-8 .From EDMA_open() .1 EDMA Primary Functions EDMA_close Function Closes previously opened EDMA channel void EDMA_close( EDMA_Handle hEdma ). EDMA_Config *config ). EDMA_config Function Sets up EDMA channel using configuration structure void EDMA_config( EDMA_Handle hEdma. hEdma none Closes a previously opened EDMA channel. See EDMA_open(). Arguments Return Value Description Example EDMA_close(hEdma). See EDMA_open() and EDMA_allocTable(). The options value (opt) is written last. This function accepts the following device handle: From EDMA_open() Device handle. The values of the structure are written to the EDMA PRAM entries. This function accepts the following device handles: . See also EDMA_configArgs() and EDMA_Config. hEdma config Device handle.EDMA_close 7.4.4 Functions 7.

Uint32 idx.EDMA_configArgs Example EDMA_Config myConfig = { 0x41200000. Uint32 src. /* opt */ 0x80000000. See EDMA_open() and EDMA_allocTable(). Uint32 cnt. /* idx */ 0x00000000 /* rld */ }. /* dst */ 0x00000004. Options Source address Transfer count Destination address Index Element count reload and link address .&myConfig). … EDMA_config(hEdma. hEdma opt src cnt dst idx rld Return Value Description none Sets up the EDMA channel using the EDMA parameter arguments. /* cnt */ 0x80010000. The options value (opt) is written last. The values of the arguments are written to the EDMA PRAM entries. Uint32 opt. Uint32 rld ). See also EDMA_config(). This function accepts the following device handles: EDMA Module 7-9 Arguments Device handle. /* src */ 0x00000040. EDMA_configArgs Sets up EDMA channel using EDMA parameter arguments Function void EDMA_configArgs( EDMA_Handle hEdma. Uint32 dst.

/* dst */ 0x00000004.EDMA_CHA_EXTINT7 .EDMA_CHA_ANY . chaNum EDMA channel to open: (For C6201. /* cnt */ 0x80010000.EDMA_CHA_EXTINT5 .EDMA_CHA_XEVT1 .EDMA_CHA_EXTINT4 .EDMA_CHA_TINT0 Arguments 7-10 .EDMA_CHA_DSPINT . /* src */ 0x00000040.EDMA_CHA_TCC8 . EDMA_open Function Opens EDMA channel EDMA_Handle EDMA_open( int chaNum. C6203.EDMA_CHA_DSPINT .EDMA_CHA_TCC9 . Uint32 flags ).EDMA_CHA_SDINT . /* idx */ 0x00000000 /* rld */ ). C6712 and C6712C) .EDMA_CHA_EXTINT6 .EDMA_CHA_REVT0 . C6701.EDMA_CHA_TCC10 . C6205.EDMA_CHA_XEVT0 .EDMA_CHA_REVT1 . 0x41200000. C6711. C6204. C6711C.EDMA_CHA_TCC11 .EDMA_CHA_ANY .EDMA_open . /* opt */ 0x80000000.EDMA_CHA_TINT1 .From EDMA_allocTable() Example EDMA_configArgs(hEdma.EDMA_CHA_TINT0 . C6202.From EDMA_open() . C6211.

EDMA_CHA_GPINT2 EDMA Module 7-11 .EDMA_CHA_GPINT6 .EDMA_CHA_GPINT5 .EDMA_CHA_DSPINT . C6415.EDMA_CHA_GPINT6 .EDMA_CHA_TINT0 . C6412.EDMA_CHA_GPINT4 . C6414.EDMA_CHA_GPINT2 (For C6713.EDMA_CHA_GPINT0 . DM640.EDMA_CHA_GPINT7 .EDMA_CHA_TCC8 .EDMA_CHA_GPINT7 . for C6711C and C6712C) .EDMA_CHA_TCC10 .EDMA_CHA_TINT1 .EDMA_CHA_TCC9 .EDMA_CHA_SDINT . C6416. DA610.EDMA_CHA_EXTINT7 . DM641.EDMA_CHA_EXTINT5 . DM642. and C6418) .EDMA_CHA_EXTINT6 . C6413.EDMA_CHA_ANY .EDMA_CHA_GPINT1 .EDMA_open - EDMA_CHA_TINT1 EDMA_CHA_SDINT EDMA_CHA_EXTINT4 EDMA_CHA_EXTINT5 EDMA_CHA_EXTINT6 EDMA_CHA_EXTINT7 EDMA_CHA_TCC8 EDMA_CHA_TCC9 EDMA_CHA_TCC10 EDMA_CHA_TCC11 EDMA_CHA_XEVT0 EDMA_CHA_REVT0 EDMA_CHA_XEVT1 EDMA_CHA_REVT1 (In addition.EDMA_CHA_EXTINT4 .EDMA_CHA_GPINT5 .EDMA_CHA_GPINT4 .

EDMA_CHA_AXEVTO0 .EDMA_CHA_AXEVTE0 .EDMA_CHA_AXEVTE0 . C6413.EDMA_open - EDMA_CHA_TCC11 EDMA_CHA_GPINT3 EDMA_CHA_XEVT0 EDMA_CHA_REVT0 EDMA_CHA_XEVT1 EDMA_CHA_REVT1 EDMA_CHA_GPINT8 EDMA_CHA_GPINT9 EDMA_CHA_GPINT10 EDMA_CHA_GPINT11 EDMA_CHA_GPINT12 EDMA_CHA_GPINT13 EDMA_CHA_GPINT14 EDMA_CHA_GPINT15 (In addition.EDMA_CHA_TINT2 .EDMA_CHA_VCPREVT0# .EDMA_CHA_AREVTE0 .EDMA_CHA_AXEVT1 .EDMA_CHA_AREVTE0 .EDMA_CHA_AREVTE1 .EDMA_CHA_AXEVTO0 .EDMA_CHA_AXEVTE1 .EDMA_CHA_ICXEVT0 .EDMA_CHA_VCPXEVT0# .EDMA_CHA_AXEVT0 .EDMA_CHA_AREVT0 7-12 .EDMA_CHA_AREVTO1 . for C6713 and DA610) .EDMA_CHA_AXEVTO1 .EDMA_CHA_AREVT0 .EDMA_CHA_AREVT1 .EDMA_CHA_ICREVT0 .EDMA_CHA_ICREVT1 . for C6410.EDMA_CHA_AXEVT0 .EDMA_CHA_ICXEVT1 (In addition.EDMA_CHA_AREVTO0 . and C6418) .EDMA_CHA_AREVTO0 .

EDMA_CHA_VP2EVTVB# .EDMA_CHA_VP0EVTVB# .EDMA_CHA_VP1EVTYB# .EDMA_CHA_AREVTE0 .EDMA_CHA_VP0EVTUA .EDMA_CHA_VP1EVTUB# .EDMA_CHA_AXEVT0 .EDMA_CHA_VP0EVTYA .EDMA_CHA_VP2EVTVA@ @ Only for DM642 and DM641 # Only for DM642 EDMA Module 7-13 .EDMA_CHA_VP1EVTUA . for DM642.EDMA_CHA_AXEVTO0 .EDMA_CHA_VP1EVTVA .EDMA_CHA_VP0EVTUB# .EDMA_CHA_VP1EVTYA .EDMA_CHA_VP1EVTVB# .EDMA_CHA_VP2EVTYA@ .EDMA_CHA_ICXEVT0 .EDMA_CHA_VP2EVTUB# .EDMA_open EDMA_CHA_AXEVTE1 EDMA_CHA_AXEVTO1 EDMA_CHA_AXEVT1 EDMA_CHA_AXEVTE1 EDMA_CHA_AXEVTO1 EDMA_CHA_AXEVT1 EDMA_CHA_ICREVT0 EDMA_CHA_ICXEVT0 EDMA_CHA_ICREVT1 EDMA_CHA_ICXEVT1 # Defined only for C6418 - (In addition.EDMA_CHA_ICREVT0 .EDMA_CHA_VP0EVTVA . DM641.EDMA_CHA_VP2EVTUA@ .EDMA_CHA_AXEVTE0 .EDMA_CHA_VP0EVTYB# .EDMA_CHA_VP2EVTYB# .EDMA_CHA_AREVTO0 .EDMA_CHA_TINT2 . and DM640) .EDMA_CHA_AREVT0 .

for C6412) .EDMA_CHA_UXEVT6 .EDMA_CHA_VCPREVT .EDMA_CHA_UREVT7 . C6415 and C6416) . logical OR of any of the following: .EDMA_CHA_PCI .EDMA_CHA_ICXEVT0 flags Open flags.EDMA_CHA_UXEVT1 . .EDMA_CHA_UXEVT3 .EDMA_CHA_PCI .EDMA_CHA_UREVT0 .EDMA_CHA_UREVT6 .EDMA_CHA_MACEVT .EDMA_CHA_UXEVT4 .EDMA_CHA_UXEVT2 .EDMA_CHA_UREVT5 .EDMA_open (In addition.EDMA_OPEN_RESET .EDMA_CHA_UREVT2 .EDMA_OPEN_ENABLE Return Value 7-14 Device Handle Device handle to be used by other EDMA API function calls. for C6414.EDMA_CHA_UREVT1 .EDMA_CHA_UREVT4 .EDMA_CHA_TINT2 .EDMA_CHA_TCPXEVT .EDMA_CHA_UXEVT7 (In addition.EDMA_CHA_UXEVT .EDMA_CHA_TCPREVT .EDMA_CHA_XEVT2 .EDMA_CHA_VCPXEVT .EDMA_CHA_SDINTB .EDMA_CHA_UXEVT0 .EDMA_CHA_UREVT3 .EDMA_CHA_UXEVT5 .EDMA_CHA_UREVT .EDMA_CHA_REVT2 .EDMA_CHA_TINT2 .EDMA_CHA_ICREVT0 .

it cannot be opened again until closed.. INV is returned. .. Note: If the DAT module is open [see DAT_open()]. This function accepts the following device handle: From EDMA_open() Example EDMA_reset(hEdma). You have the option of either specifying exactly which physical channel to open or you can let the library pick an unused one for you by specifying EDMA_CHA_ANY. the EDMA channel is reset and the channel interrupt is disabled and cleared. . INV is returned.The channel event flag is cleared Arguments Return Value Description Device handle obtained by EDMA_open(). the channel will be enabled. hEdma none Resets the given EDMA channel. If the open fails.. then EDMA transfer completion interrupts 1 through 4 are reserved. The return value is a unique device handle that you use in subsequent EDMA API calls. EDMA Module 7-15 . If the channel cannot be opened. hEdma = EDMA_open(EDMA_CHA_TINT0. Once opened. it must first be opened by this function. The following steps are taken: .EDMA_OPEN_RESET). If the EDMA_OPEN_ENABLE flag is specified. See EDMA_close().. If the EDMA_OPEN_RESET is specified. Example EDMA_Handle hEdma. Refer to the TMS320C6000 Peripherals Reference Guide (SPRU190) for details regarding the EDMA channels.EDMA_reset Description Before an EDMA channel can be used.The channel is disabled . EDMA_reset Function Resets given EDMA channel void EDMA_reset( EDMA_Handle hEdma ).

For TMS320C621x/C671x. You use the Reload/Link PRAM tables for linking transfers together. Arguments Return Value Description Device Handle Returns a device handle This function allocates the PRAM tables dedicated to the Reload/Link parameters. and the second table is reserved for CSL code. the first two tables located at 0x01A00180 and 0x01A00198. The first parameter table is initialized to zero. are reserved. –1 for any. then INV is returned. Valid values are 0 to EDMA_TABLE_CNT–1. You can either specify a table number or specify –1 and the function will pick an unused one for you. tableNum Table number to allocate. The first available table for the user starts at address 0x01A00630.0x01A00630 for C64xx devices Example EDMA_Handle hEdmaTable. . with table numbers from 0 to 66. The first available table for the user starts at address 0x01A001B0. There are 67 available tables. If the table could not be allocated. will allocate the Reload/Link parameter table located at: . For TMS320C64xx. 7-16 . If you finish with the table and wish to free it up again. hEdmaTable = EDMA_allocTable(–1).EDMA_allocTable 7. hEdmaTable=EDMA_allocTable(0).. The return value is a device handle and may be used for APIs that require a device handle. respectively. The first parameter table is initialized to zero. the first two tables located at 0x01A00600 and 0x01A00618 are reserved. with table numbers from 0 to 18.2 EDMA Auxiliary Functions and Constants EDMA_allocTable Function Allocates a parameter RAM table from PRAM EDMA_Handle EDMA_allocTable( int tableNum ).4. There are 19 available tables.0x01A001B0 for C621x/C671x devices .. call EDMA_freeTable(). and the second table is reserved for CSL code.

Example EDMA_Handle hEdmaTableArray[16]. } EDMA_CHA_CNT Constant Description Number of EDMA channels EDMA_CHA_CNT Compile time constant that holds the number of EDMA channels. cnt array Return Value Description numAllocated cnt or 0. EDMA_Handle *array ).hEdmaTableArray)) { . It will either be Arguments This function allocates a set of parameter RAM tables from PRAM. call EDMA_freeTableEx()... EDMA Module 7-17 . The tables are not guaranteed to be contiguous in memory. If you finish with the tables and wish to free them up again. .EDMA_allocTableEx EDMA_allocTableEx Allocates set of parameter RAM tables from PRAM Function int EDMA_allocTableEx( int cnt. Number of tables to allocate An array to hold the table handles for each table allocated Returns the actual number of tables allocated.. The array passed in is filled with table handles and each one may be used for APIs that require a device handle. You use PRAM tables for linking transfers together. if (EDMA_allocTableEx(16..

parent nextChannel flag_tcc EDMA handle following the chainable transfer.TCINT setting (and TCCM for C64x devices). only channels from 8 to 11 are chainable. int flag_atcc ). The following constants must be used: . 7-18 . EDMA handle associated with the channel to be chained. Flag for TCC. For C621x/C671x. The following constants must be used: .0 .EDMA_ATCC_SET or 1 Arguments flag_atcc Return Value Description none Sets the TCC.0 .EDMA_chain EDMA_chain Function Sets the TCC.TCINT fields (and TCCM field for C64x devices) of the “parent” EDMA handle based on the “nextChannel” EDMA handle. int flag_tcc. TCINT fields of the parent EDMA handle void EDMA_chain( EDMA_Handle parent.EDMA_TCC_SET or 1 Flag for ATCC. ATCINT setting (C64x devices only). EDMA_Handle nextChannel.

see EDMA_open(). EDMA Module 7-19 . /*Allocate a transfer complete code*/ Tcc=intAlloc(–1).&myConfig). EDMA_clearChannel Clears EDMA event flag in EDMA channel event register Function void EDMA_clearChannel( EDMA_Handle hEdma ). /*Open and Configure parent Channel*/ hEdmaPar=EDMA_open(EDMA_CHA_TINT1.hEdmaChain. This function accepts the following device handle: From EDMA_open() Example EDMA_clearChannel(hEdma). /*Update the TCC.0) /*Enable chaining: CCER (CCERL/CCERH) setting*/ ). (TCCM) fields of the parent channel configuration*/ EDMA_chain(hEdmaPar. /*Open the Channel for the next transfer with TCC value*/ hEdmaChain=EDMA_open(Tcc.EDMA_clearChannel Example EDMA_Handle hEdmaChain. EDMA_enableChaining(hEdmaChain). TCINT.hEdmaPar.EDMA_OPEN_RESET). EDMA_config(hEdmaPar.EDMA_TCC_SET. hEdma none This function clears the EDMA event flag in the EDMA channel event register by writing to the appropriate bit in the EDMA event clear register (ECR). Arguments Return Value Description Device handle. Unit32 Tcc.EDMA_OPEN_RESET).

EDMA handle to be chained Arguments Return Value Description 7-20 . Arguments Return Value Description Example Value to clear the PRAM with EDMA_disableChaining Function Disables EDMA chaining void EDMA_disableChaining( EDMA_Handle hEdma ). hEdma none Disables the CCE bit in the Channel Chaining Enable Register associated with the EDMA handle. val none This function clears all of the EDMA parameter RAM with the value specified. EDMA_enableChaining Enables EDMA chaining Function void EDMA_enableChaining( EDMA_Handle hEdma ). For C621x/C671x.EDMA_clearPram EDMA_clearPram Function Clears the EDMA parameter RAM (PRAM) void EDMA_clearPram( Uint32 val ). EDMA_clearPram(0). hEdma none Enables the CCE bit in the Channel Chaining Enable Register associated with the EDMA handle. EDMA handle to be chained Arguments Return Value Description Example EDMA_enableChaining(hEdmaCha8). EDMA_disableChaining(hEdmaCha8). This function should not be called if EDMA channels are active. only channels from 8 to 11 are chainable. See also EDMA_enableChaining().

Arguments Return Value Description Device handle. When you open an EDMA channel it is disabled. so you must enable it explicitly.EDMA_disableChannel For C621x/C671x. /*Enable chaining*/ EDMA_enableChaining(hEdmaCha8). only channels from 8 to 11 are chainable. See also EDMA_disableChannel(). see EDMA_open(). /*Open the channel related to the TCC*/ hEdmaCha8=EDMA_open(Tcc. see EDMA_open(). . See also EDMA_enableChannel(). hEdma none Enables an EDMA channel by setting the corresponding bit in the EDMA event enable register. hEdma none Disables an EDMA channel by clearing the corresponding bit in the EDMA event enable register. Example EDMA _Handle hEdmaCha8 Uint32 Tcc. /*Allocate the transfer complete code*/ Tcc=EDMA_intAlloc(8). EDMA Module 7-21 Arguments Return Value Description Device handle. EDMA_disableChannel Disables EDMA channel Function void EDMA_disableChannel( EDMA_Handle hEdma ). This function accepts the following device handle: From EDMA_open() Example EDMA_disableChannel(hEdma).EDMA_OPEN_RESET). EDMA_enableChannel Function Enables EDMA channel void EDMA_enableChannel( EDMA_Handle hEdma ).

EDMA_Handle *array ). a PRAM table previously allocated via Device handle. See EDMA_allocTable(). The array that is passed in must contain the table handles for each one to be freed. EDMA_freeTable Function Frees up PRAM table previously allocated void EDMA_freeTable( EDMA_Handle hEdma ). } .hEdmaTableArray). Arguments Return Value Description This function accepts the following device handle: From EDMA_allocTable() Example EDMA_freeTableEx Function EDMA_freeTable(hEdmaTable). hEdma none This function frees up EDMA_allocTable(). You use PRAM tables for linking transfers together...hEdmaTableArray)) { .. cnt array Number of table handles in array to free An array containing table handles for each table to be freed Arguments Return Value Description none This function frees a set of parameter RAM tables that were previously allocated. Example 7-22 .... Frees a previously allocated set of parameter RAM tables void EDMA_freeTableEx( int cnt. EDMA_Handle hEdmaTableArray[16]. EDMA_freeTableEx(16.EDMA_freeTable This function accepts the following device handle: From EDMA_open() Example EDMA_enableChannel(hEdma). . if (EDMA_allocTableEx(16.

See EDMA_open().0 – event not detected . hEdma config Device handle. Arguments Return Value Description Example none Get EDMA current configuration value EDMA_Config edmaCfg.1 – event detected Arguments Return Value Description Returns the current state of the channel event by reading the event flag from the EDMA channel event register (ER).&edmaCfg). hEdma Channel Flag Device handle. This function accepts the following device handle: From EDMA_open() Example flag = EDMA_getChannel(hEdma). EDMA_getConfig(hEdma. EDMA_Config *config ). EDMA Module 7-23 . Pointer to a configuration structure.EDMA_getChannel EDMA_getChannel Function Returns current state of channel event Uint32 EDMA_getChannel( EDMA_Handle hEdma ). EDMA_getConfig Function Reads the current EDMA configuration values void EDMA_getConfig( EDMA_Handle hEdma. Channel event flag: . See EDMA_open().

See also EDMA_getScratchSize(). none Scratch Address 32-bit starting address of PRAM scratch area There is a small portion of the EDMA PRAM that is not used for parameter tables and is free for use as non-cacheable on-chip SRAM. Example EDMA_getScratchSize Returns size (in bytes) of EDMA PRAM scratch area Function Arguments Return Value Description Uint32 EDMA_getScratchSize(). This function returns the starting address of this scratch area. This function returns the size of this scratch area in bytes. EDMA_getScratchAddr Returns starting address of EDMA PRAM scratch area Function Arguments Return Value Description Uint32 EDMA_getScratchAddr().EDMA_getPriQStatus EDMA_getPriQStatus Returns value of priority queue status register (PQSR) Function Arguments Return Value Description Uint32 EDMA_getPriQStatus().0x00000004 – PQ2 Example pqStat = EDMA_getPriQStatus(). May be the logical OR of any of the following: . none Status Returns status of the priority queue Returns the value of the priority queue status register (PQSR). none Scratch Size Size of PRAM scratch area in bytes There is a small portion of the EDMA PRAM that is not used for parameter tables and is free for use as non-cacheable on-chip SRAM.0x00000001– PQ0 . See also EDMA_getScratchAddr().0x00000002– PQ1 . scratchSize = EDMA_getScratchSize(). scratchWord = (Uint32*)EDMA_getScratchAddr(). Uint32 *scratchWord. Example 7-24 .

EDMA_intAlloc(43). hEdma Device handle obtained by EDMA_allocTable(). or –1 otherwise. intNum Transfer-completion interrupt number [0. EDMA Module 7-25 Arguments .. EDMA_intAlloc(5). This function accepts the following device handle: From EDMA_allocTable() Example addr = EDMA_getTableAddress(hEdmaTable). tcc=EDMA_intAlloc(−1). this function returns the 32-bit absolute address of the table. EDMA_intAlloc Function Allocates a transfer complete code int EDMA_intAlloc( int tcc ). the first available TCC number is allocated.EDMA_getTableAddress EDMA_getTableAddress Returns 32-bit absolute address of table Function Uint32 EDMA_getTableAddress( EDMA_Handle hEdma ).31]. tcc tccReturn Transfer-complete code number or −1 Transfer-complete code number or –1 Arguments Return Value Description This function allocates the transfer-complete code passed in and returns the same TCC number if successful. Arguments Return Value Description Table Address 32-bit address of table Given a device handle obtained from EDMA_allocTable(). Example EDMA_intClear Function Clears EDMA transfer-completion interrupt-pending flag void EDMA_intClear( Uint32 intNum ).. If −1 is used as an argument.

it just returns. Note: If the DAT module is open [see DAT_open()]. Example EDMA_intDefaultHandler Function EDMA_intClear(12).. Channel completion number Arguments Return Value Description EDMA_intDisable Function Disables EDMA transfer-completion interrupt void EDMA_intDisable( Uint32 intNum ). intNum none This function disables a transfer-completion interrupt by modifying the CIER register appropriately. then EDMA transfer-completion interrupts 1 through 4 are reserved. tccNum none This is the default function that is called by EDMA_intDispatcher(). Arguments Return Value Description Example EDMA_intDisable(12). Default function called by EDMA_intDispatcher() void EDMA_intDefaultHandler( int tccNum ). Note: If the DAT module is open [see DAT_open()].31]. none Arguments 7-26 . Transfer-completion interrupt number [0. EDMA_intDispatcher Calls an ISR when CIER[x] and CIPR[x] are both set Function void EDMA_intDispatcher( void ). See also EDMA_intDispatcher() and EDMA_intHook(). then EDMA transfer-completion interrupts 1 through 4 are reserved.EDMA_intDefaultHandler Return Value Description none This function clears a transfer-completion interrupt flag by modifying the CIPR register appropriately. It does nothing.

tcc none This function frees a transfer-complete code number previously allocated. EDMA_intDispatcher().. Example EDMA_intEnable Function Enables the EDMA transfer-completion interrupt void EDMA_intEnable( Uint32 intNum ).EDMA_intEnable Return Value Description none This function checks for CIER and CIPR for all those bits which are set in both the registers and calls the corresponding ISR. For example. .31]. however. this ISR is EDMA_intHandler(). Arguments Return Value Description Example EDMA_intEnable(12). EDMA_intAlloc(17). intNum none This function enables a transfer completion interrupt by modifying the CIER register appropriately. this can be changed by EDMA_intHook().. Note: If the DAT module is open [see DAT_open()]. EDMA_intFree(17). EDMA Module 7-27 Arguments Return Value Description Example Transfer-complete code number to be free . See also EDMA_intDefaultHandler() and EDMA_intHook(). if CIER[14] = 1 and CIPR[14] =1 then it calls the ISR corresponding to channel 14.. EDMA_intFree Function Frees the transfer-complete code number void EDMA_intFree( int tcc ). then EDMA transfer-completion interrupts 1 through 4 are reserved. Transfer-completion interrupt number [0. By default.

tccIntNum Interrupt mask of interrupt to be reset None A single interrupt can be turned off using this function. See also EDMA_intDefaultHandler() and EDMA_intDispatcher().EDMA_intHook EDMA_intHook Function Hooks an isr to a channel. channel 13 complete). EDMA_intReset(0x1). //turn off interrupt related to bit 1 of CIER (or CIERL in case of C64xx devices) Arguments Return Value Description Example 7-28 . tccNum funcAddr Channel to which the ISR is to be hooked ISR name Arguments Return Value Description IntHandler Returns the old ISR address This function hooks an ISR to the specified channel. When the tcint is ’1’ and tccNum is specified in the EDMA options. which by default is nothing. Example void complete(). This function turns off the corresponding bit for the interrupt number in the CIERL or CIERH in case of C64xx devices and int the CIER in case of others. To change this default ISR to a different one. If the corresponding bit in the CIER register is also set. the EDMA controller sets the corresponding bit in the CIPR register. then calling EDMA_intDispatcher() would call the ISR corresponding the the tccNum. Only when an ISR is hooked this way would it be called. use EDMA_intHook(). which is called by EDMA_intDsipatcher() EDMA_IntHandler EDMA_intHook( int tccNum EDMA_IntHandler funcAddr ). //Hooks complete function to EDMA_intReset Function Resets a specified interrupt void EDMA_intReset( Uint32 tccIntNum ). EDMA_intHook(13.

then EDMA transfer-completion interrupts 1 through 4 are reserved. Result: 0 = flag was clear 1 = flag was set Arguments Return Value Description This function tests a transfer-completion interrupt flag by reading the CIPR register appropriately. Example if (EDMA_intTest(12)) { .EDMA_intResetAll EDMA_intResetAll Resets all interrupts for the device Function Arguments Return Value Description void EDMA_intResetAll(). None None This function resets the CIER register (CIERL and CIERH in case of C64xx devices) so that all interrupts are disabled.. EDMA_Handle child ). } EDMA_link Function Links two EDMA transfers together void EDMA_link( EDMA_Handle parent. Note: If the DAT module is open [see DAT_open()]. EDMA_intTest Function Tests EDMA transfer-completion interrupt-pending flag Uint32 EDMA_intTest( Uint32 intNum )... It also sets all the bits of the CIPR register (CIPRL and CIPRH in case of C64xx devices). parent child Handle of the parent (link from parent) Handle of the child (link to child) EDMA Module 7-29 Arguments . intNum Uint32 Transfer-completion interrupt number [0.31].

EDMA_map Function Maps EDMA event to a channel void EDMA_map( int eventNum. dst.hEdmaTable). since the QDMA does not support reloads or linking. Both parent and child handles may be from EDMA_open(). EDMA_link(hEdma. hEdmaTable = EDMA_allocTable(–1). or a combination of both. hEdma = EDMA_open(EDMA_CHA_TINT1. //Maps event 12 to channel 3 Arguments Return Value Description Example EDMA_qdmaConfig Function Sets up QDMA registers using configuration structure void EDMA_qdmaConfig( EDMA_Config *config ). parent–>child Note: This function does not attempt to set the LINK field of the OPT parameter. then the opt value is written to the pseudo-OPT register which initiates the transfer. The src.0). Example EDMA_Handle hEdma. . EDMA_allocTable(). The rld member of the structure is ignored. int chNum eventNum EDMA event to be mapped to channel chNum Channel to which event is to be mapped int Returns channel selected for mapping This function maps the given EDMA event to specified channel EDMA_map(12.. EDMA_link(hEdmaTable. this is still up to the user.EDMA_map Return Value Description none This function links two EDMA transfers together by setting the LINK field of the parent’s RLD parameter appropriately. See also EDMA_qdmaConfigArgs() and EDMA_Config. cnt. Pointer to an initialized configuration structure Arguments Return Value Description 7-30 . config none Sets up the QDMA registers using the configuration structure. 3). and idx values are written to the normal QDMA registers. EDMA_Handle hEdmaTable.hEdmaTable)..

See also EDMA_qdmaConfig() and EDMA_Config. /* opt */ 0x80000000. /* src 0x00000040. The src. EDMA_qdmaConfigArgs Sets up QDMA registers using arguments Function void EDMA_qdmaConfigArgs( Uint32 opt. Uint32 idx ). dst. /* src */ 0x00000040. /* opt 0x80000000. /* cnt 0x80010000. /* cnt */ 0x80010000. opt src cnt dst idx Return Value Description none Sets up the QDMA registers using the arguments passed in. */ */ */ */ */ Arguments Options Source address Transfer count Destination address Index Example EDMA Module 7-31 . … EDMA_qdmaConfig(&myConfig). /* idx */ 0x00000000 /* rld will be ignored */ }.EDMA_qdmaConfigArgs Example EDMA_Config myConfig = { 0x41200000. cnt. and idx values are written to the normal QDMA registers. /* dst 0x00000004 /* idx ). Uint32 src. Uint32 dst. EDMA_qdmaConfigArgs( 0x41200000. then the opt value is written to the pseudo-OPT register which initiates the transfer. Uint32 cnt. /* dst */ 0x00000004.

EDMA_Q1 . See also EDMA_setPriQLength() function /* Sets the queue length of the PQAR0 register */ EDMA_setPriQLength(EDMA_Q0. disabling and clearing the channel interrupt registers. EDMA_resetAll(). EDMA_setChannel Triggers EDMA channel by writing to appropriate bit in ESR Function void EDMA_setChannel( EDMA_Handle hEdma ). none none This function resets all EDMA channels supported by the device by disabling EDMA enable bits.EDMA_Q3 Arguments Return Value Description Example none Resets the queue length of the associated priority queue allocation register to the default value. Example EDMA_resetPriQLength Function Resets the priority queue length (C64x devices only) void EDMA_resetPriQLength( Uint32 priNum ) priNum Queue Number [0–3] associated to the following constants: . and clearing the PRAM tables associated to the EDMA events.EDMA_Q0 . Arguments 7-32 . hEdma Device handle obtained by EDMA_open().4).EDMA_Q2 .EDMA_resetAll EDMA_resetAll Function Arguments Return Value Description Resets all EDMA channels supported by the chip device void EDMA_resetAll(). /* Resets the queue length of the PQAR0 */ EDMA_resetPriQLength(EDMA_Q0).

EDMA_Q2 . falling-edge of EDMA_setPriQLength Sets the priority queue length (C64x devices only) Function EDMA_setPriQLength( Uint32 priNum. int polarity ).EDMA_Q0 .EDMA_EVT_LOWHIGH (0) .0).EDMA_Q1 . priNum Queue Number [0–3] associated to the following constants: . hEdma Device handle associated with the EDMA channel obtained by EDMA_open() Event polarity (0 or 1) .EDMA_setEvtPolarity Return Value Description none Software triggers an EDMA channel by writing to the appropriate bit in the EDMA event set register (ESR). /* Sets the polarity of the event to transition*/ hEdma=EDMA_open(EDMA_CHA_TINT1. EDMA_setEvtPolarity(hEdma. Uint32 length ).EDMA_EVT_HIGHLOW (1) Arguments polarity Return Value Description Example none Sets the polarity of the event associated with the EDMA channel. EDMA_setEvtPolarity Sets the event polarity associated with an EDMA channel Function void EDMA_setEvtPolarity( EDMA_handle hEdma.EDMA_EVT_HIGHLOW).EDMA_Q3 length of the queue EDMA Module 7-33 Arguments length . This function accepts the following device handle: From EDMA_open() Example EDMA_setChannel(hEdma).

) /* Sets the queue length of the PQAR1 register to 4 */ EDMA_setPriQLength(EDMA_Q1. the DMA module is supported instead.EDMA_SUPPORT Return Value Description Example none Sets the queue length of the associated priority queue allocation register (See EDMA_resetPriQLength() function. 7-34 . Example #if (EDMA_SUPPORT) /* user EDMA configuration / #elif (DMA_SUPPORT) / user DMA configuration */ #endif EDMA_TABLE_CNT Constant Description Compile-time constant EDMA_TABLE_CNT Compile-time constant that holds the total number of reload/link parameter-table entries in the EDMA PRAM. Note: The EDMA module is not supported on devices that do not have the EDMA peripheral.4). EDMA_SUPPORT Constant Description Compile-time constant EDMA_SUPPORT Compile-time constant that has a value of 1 if the device supports the EDMA module and 0 otherwise. EDMA_resetPriQLength(EDMA_Q1). In these cases. You are not required to use this constant.

. . . . . . . . . . . . . . . . . . . . . . . . 8-13 8-1 . . . .4 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8. . . . . . . . . . . . . . . . Topic 8. . .Chapter 8 EMAC Module This chapter describes the EMAC module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . and provides an EMAC reference section. . . . . . . . . . . . . . . .2 8. . . . 8-6 Functions . . . . . . . . . . . . . . .3 8. . . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . 8-2 Macros . . . . .

It is the responsibility of the application to assure adherence to this restriction. in either half or full duplex. Table 8−1 lists the configuration structures for use with the EMAC functions. no EMAC function may be called while another EMAC function is operating on the same device handle in another thread. with hardware flow control and quality-of-service (QOS) support.1 Overview The ethernet media access controller (EMAC) module provides an efficient interface between the DSP core processor and the networked community.Overview 8. Note: When used in a multitasking environment. The EMAC supports both 10Base-T (10Mbits/sec) and 100BaseTX (100Mbits/sec). Table 8−1. EMAC APIs Syntax EMAC_close EMAC_enumerate EMAC_getReceiveFilter EMAC_getStatistics EMAC_getStatus EMAC_open EMAC_setReceiveFilter Type Description F F F F F F F Closes the EMAC peripheral indicated by the supplied instance handle Enumerates the EMAC peripherals installed in the system and returns an integer count Called to get the current packet filter setting for received packets. Called to get the current device statistics Called to get the current device status Opens the EMAC peripheral at the given physical index Called to set the packet filter for received packets See page 8-13 8-13 8-14 8-15 8-16 8-17 8-18 8-2 . Table 8−2 lists the functions and constants available in the CSL EMAC module. EMAC Configuration Structure Structure EMAC_Config EMAC_Pkt EMAC_Status EMAC_Statistics Purpose The config structure defines how the EMAC device should operate The packet structure defines the basic unit of memory used to hold data packets for the EMAC device The status structure contains information about the MAC’s run-time status The statistics structure is used to retreive the current count of various packet events in the system See page 8-6 8-8 8-10 8-11 Table 8−2.

EMAC APIs (Continued) Syntax EMAC_setMulticast EMAC_sendPacket EMAC_serviceCheck EMAC_SUPPORT EMAC_timerTick Type Description F F F C F Called to install a list of multicast addresses for use in multicast address filtering Sends a Ethernet data packet out the EMAC device This function should be called every time there is an EMAC device interrupt A compile-time constant whose value is 1 if the device supports the EMAC module This function should be called for each device in the system on a periodic basis of 100 mS See page 8-19 8-20 8-21 8-22 8-22 EMAC Module 8-3 .Overview Table 8−2.

<IDX>.x) EMAC_RSETI(<REGBASE>.x) EMAC_FGET(<REG>. and Table 8−3 lists the EMAC macros that construct register and field values.x) EMAC_FSETS(<REG>.<IDX>.2 Macros There are two types of EMAC macros: those that access registers and fields. Using the HAL Macros. <FIELD>. Table 8−3. and those that construct register and field values. EMAC Macros That Access Registers and Fields Macro EMAC_ADDR(<REG>) EMAC_RGET(<REG>) EMAC_RGETI(<REGBASE>.<IDX>) EMAC_RSET(<REG>. Table 8−3 lists the EMAC macros that access registers and fields.<FIELD>. <FIELD>.Macros 8.<SYM>) EMAC_FSETSI(<REGBASE>.<FIELD>) EMAC_FGETI(<REGBASE>. The macros themselves are found in Chapter 28.<FIELD>.fieldval) EMAC_FSETI(<REGBASE>.<IDX>. <FIELD>) EMAC_FSET(<REG>.<IDX>.<SYM>) Description/Purpose Register address Returns the value in the peripheral register Returns the value of register at position IDX from REGBASE Register set Sets the value of register at position IDX from REGBASE Returns the value of the specified field in the peripheral register Returns the value of field of register at position IDX from REGBASE Writes fieldval to the specified field in the peripheral register Sets the value of field of register at position IDX from REGBASE Writes the symbol value to the specified field in the peripheral Writes the symbol value to field of register at position IDX from REGBASE 28-17 28-15 28-13 28-20 See page 28-12 28-18 8-4 .

EMAC Macros that Construct Registers and Fields Macro EMAC_<REG>_DEFAULT EMAC_<REG>_RMK() EMAC_<REG>_OF() EMAC_<REG>_<FIELD>_DEFAULT EMAC_FMK() EMAC_FMKS() EMAC_<REG>_<FIELD>_OF() EMAC_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of Field default value Field make Field make symbolically Field value of Field symbolic value See page 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 EMAC Module 8-5 .Macros Table 8−4.

/* Callback function */ void (*pfcbStatistics)(Handle hApplication). These functions are REQUIRED for operation. /* Callback function */ EMAC_Pkt *(*pfcbRxPacket)(Handle hApplication. The same callback table can be used for multiple driver instances. Uint8 MacAddr[6]. A list of callback functions is used to register callback functions with a particular instance of the EMAC peripheral. /* Callback function */ void (*pfcbFreePacket)(Handle hApplication. Uint TxChannels. EMAC_Pkt *pPacket). Callback functions are used by EMAC to communicate with the application.EMAC_Config 8. /* Callback function */ Description The config structure defines how the EMAC device should operate. /*Callback function */ void (*pfcbStatus)(Handle hApplication). but mostly occur during calls to EMAC_statusIsr() and EMAC_statusPoll(). EMAC_Pkt *pPacket). It is passed to the device when the device is opened. and remains in effect until the device is closed. /* Configuation Mode Flags */ /* csl_mdio Mode Flags (see csl_mdio.h) */ /* Number of Tx Channels to use (1−8) */ /* Mac Address */ /* Max Rx packet buffers to get from pool */ EMACPkt EMAC_Pkt * (*pfcbGetPacket)(Handle hApplication). Uint RxMaxPktPool. 8-6 .3 Configuration Structure EMAC_Config Members EMAC configuration defines how the EMAC device should operate Uint ModeFlags: Uint MdioModeFlags. The callback functions can be used by EMAC during any EMAC function.

The applicaiton must accept the packet. structure fields other than pDataBuffer and BufferLen are in an undefined state. This function also returns a pointer to a free packet to replace the received packet on the EMAC free list. It returns NULL when no free packets are available.* pfcbStatus Called to indicate to the application that it should call EMAC_getStatus() to read the current device status.* pfcbRxPacket Called to give a received data packet to the application layer. EMAC Module 8-7 . . it can return it to its own free queue.EMAC_Config . The hApplication calling calling argument is the application’s handle as supplied to the EMAC device in the EMAC_open() function.* pfcbFreePacket Called by EMAC to give a free packet buffer back to the application layer. The return packet is the same as would be returned by pfcbGetPacket.* pfcbStatistics Called to indicate to the application that it should call EMAC_getStatistics() to read the current Ethernet statistics. plus any application buffer padding (DataOffset). When the application is finished with the packet. The size of the packet buffer must be large enough to accommodate a full sized packet (1514 or 1518 depending on the EMAC_CONFIG_MODEFLG_RXCRC flag). Note that at the time of the call.* pfcbGetPacket Called by EMAC to get a free packet buffer from the application layer for receive data. This function should return NULL is no free packets are available. . Therefore. This function is used to return transmit packets. Called when the statistic counters are to the point of overflow. if a newly received packet is not desired. it can simply be returned to EMAC via the return value. This call is made when device status changes. . .

Note that for receive buffer packets. A packet is comprised of one or more packet buffers. Uint8 *pDataBuffer. In all instances. (ValidLen+DataOffet)<=BufferLen. DataOffset is the byte offset from the start of the data buffer to the first byte of valid data. Each packet buffer contains a packet buffer header. ValidLen holds the length of the valid data currently contained in the data buffer. This allows the application to reserve space at the top of data buffer for private use. Uint32 Flags. The pDataBuffer field points to the packet data. Therefore.EMAC_Pkt EMAC_Pkt Defines the basic unit of memory used to hold data packets for the EMAC Uint32 AppPrivate. The EMAC_Pkt structure defines the packet buffer header. the 8-8 . and is not altered. and is not altered. /*For use by the application /*Previous record */ /*Next record */ /*Pointer to Data Buffer (read only) */ /*Physical Length of buffer (read only) */ /*Packet Flags */ /*Length of valid data in buffer */ /*Byte offset to valid data */ /*Tx/Rx Channel/Priority 0−7 (SOP only) */ /*Length of Packet (SOP only) */ /*(same as ValidLen on single frag Pkt) */ /*Number of frags in packet (SOP only) */ /*(frag is EMAC_Pkt record − normally 1)*/ Members Description The packet structure defines the basic unit of memory used to hold data packets for the EMAC device. This is set when the buffer is allocated. Uint32 PktFrags. This size is set by the entity that originally allocates the buffer. struct _EMAC_Pkt *pNext. Uint32 PktLength. Uint32 ValidLen. Uint32 BufferLen. The Flags field contains additional information about the packet. and a pointer to the buffer data. struct _EMAC_Pkt *pPrev. the DataOffset field may be assigned before there is any valid data in the packet buffer. BufferLen holds the the total length of the data buffer that is used to store the packet (or packet fragment). Uint32 DataOffset. Uint32 PktChannel.

the next packet structure pointed to by the pNext field will contain the next fragment in the packet. The PktLength field holds the size of the entire packet. but allows for up to eight transmit channels. Transmit channels can be treated as round−robin or priority queues. then the packet is not fragmented. On single frag packets (both SOP and EOP set in BufFlags). These fields contain additional information about the packet. In systems where the packet resides in cacheable memory. The data portion of the packet buffer represents a packet or a fragment of a larger packet. If more than 1 frag is present. with corresponding fields validated. or what channel it should be transmitted on. The PktChannel field detetmines what channel the packet has arrived on. the SOP bit is set in Flags. PktLength. If the EOP bit is also set. On multi-fragment packets. the data buffer must start on a cache line boundary and be an even multiple of cache lines in size. Otherwise. On either type of buffer. PktLength and ValidLen will be equal. the following modes must be set: RxCrc Flag : RXCRC Mode in EMAC_Config RxErr Flags : PASSERROR Mode in EMAC_Config RxCtl Flags : PASSCONTROL Mode in EMAC_Config RxPrm Flag : EMAC_RXFILTER_ALL in EMAC_setReceiveFilter() EMAC Module 8-9 . The PktFrags field holds the number of fragments (EMAC_Pkt records) usedto describe the packet.Each frag/record must be linked list using the pNext field. Some of the packet Flags can only be set if the device is in the proper configuration to receive the corresponding frames. At the start of every packet.EMAC_Pkt DataOffset field must be valid for all packets handled by EMAC. This is determined by the Flags parameter. In order to enable these flags. the first recordmust have EMAC_PKT_FLAGS_SOP flag set. and the finalfrag/record must have EMAC_PKT_FLAGS_EOP flag set and pNext=0. then the PktChannel. The EMAC library supports only a single receive channel. when the SOP bit is set in Flags. Note: It is up to the caller to assure that all packet buffers residing in cacheable memory are not currently stored in L1 or L2 cache when passed to any EMAC function. The EMAC_Pkt header must not appear in the same cache line as the data portion of the packet. some packet fragments may reside in cacheable memory where others do not. and PktFrags fields must also be valid.

TxPktHeld.h) */ /* Current PHY device in use (0−31) */ /* Number of packets held for Rx */ /* Number of packets held for Tx */ /* Fatal Error when non-zero */ Description The status structure contains information about the MAC’s run-time status. /* csl_mdio Link status (see csl_mdio.h) .MdioLinkStatus Current link status (non-zero on link) (see csl_mdio.RxPktHeld Current number of Rx packets held by the EMAC device .EMAC_Status EMAC_Status Members Contains Information about the MAC’s run-time status uint uint uint uint uint dioLinkStatus.TxPktHeld Current number of Tx packets held by the EMAC device . The following is a short description of the configuration fields: .FatalError Fatal Error Code 8-10 .PhyDev Current PHY device in use (0−31) . RxPktHeld. FatalError. PhyDev.

Uint32 TxCollision. Uint32 RxBCastFrames. Uint32 TxLateColl. Uint32 TxUnderrun. Uint32 RxFiltered. Uint32 TxDeferred. /* Good Frames Received */ /* Good Broadcast Frames Received */ /* Good Multicast Frames Received */ /* PauseRx Frames Received */ /* Frames Received with CRC Errors */ /* Frames Received with Alignment/Code Errors */ /* Oversized Frames Received */ /* Jabber Frames Received */ /* Undersized Frames Received */ /* Rx Frame Fragments Received */ /* Rx Frames Filtered Based on Address */ /* Rx Frames Filtered Based on QoS Filtering */ /* Total Received Bytes in Good Frames */ /* Good Frames Sent */ * Good Broadcast Frames Sent */ /* Good Multicast Frames Sent */ /* PauseTx Frames Sent */ /* Frames Where Transmission was Deferred */ /* Total Frames Sent With Collision */ /* Frames Sent with Exactly One Collision*/ /* Frames Sent with Multiple Colisions */ /* Tx Frames Lost Due to Excessive Collisions */ /* Tx Frames Lost Due to a Late Collision*/ /* Tx Frames Lost with Transmit Underrun Error */ /* Tx Frames Lost Due to Carrier Sense Loss */ /* Total Transmitted Bytes in Good Frames*/ /* Total Tx&Rx with Octet Size of 64 */ /* Total Tx&Rx with Octet Size of 65 to 127 */ /* Total Tx&Rx with Octet Size of 128 to EMAC Module 8-11 . Uint32 RxJabber. Uint32 TxCarrierSLoss. Uint32 TxExcessiveColl. Uint32 RxQOSFiltered.EMAC_Statistics EMAC_Statistics Retreives the current count of various packet events in the system Members Uint32 RxGoodFrames. Uint32 RxUndersized. Uint32 Frame65t127. Uint32 RxOctets. Uint32 TxMultiColl. Uint32 RxMCastFrames. Uint32 TxMCastFrames. Uint32 TxPauseFrames. Uint32 TxOctets. Uint32 Frame128t255. Uint32 RxFragments. Uint32 TxSingleColl. Uint32 RxPauseFrames. Uint32 RxCRCErrors. Uint32 TxGoodFrames. Uint32 Frame64. Uint32 TxBCastFrames. Uint32 RxAlignCodeErrors. Uint32 RxOversized.

Uint32 RxMOFOverruns. Uint32 Frame1024tUp.EMAC_Statistics 255 */ /* Total Tx&Rx with Octet Size of 256 to 511 */ /* Total Tx&Rx with Octet Size of 512 to 1023 */ /* Total Tx&Rx with Octet Size of >=1024 */ /* Sum of all Octets Tx or Rx on the Network */ /* Total Rx Start of Frame Overruns */ /* Total Rx Middle of Frame Overruns */ /* Total Rx DMA Overruns */ Uint32 Frame256t511. Uint32 NetOctets. These values represent the delta values from the last time the statistics were read. Note: The application is charged with verifying that only one of the following API calls may only be executing at a given time across all threads and all interrupt functions. Description The statistics structure is the used to retrieve the current count of various packet events in the system. 8-12 . Uint32 RxDMAOverruns. Uint32 Frame512t1023. Uint32 RxSOFOverruns.

. uint is defined as unsigned int and Handle as void* EMAC_close Function Closes the EMAC peripheral indicated by the supplied instance handle uint EMAC_close( Handle hEMAC ). EMAC Module 8-13 Example . None uint Enumerates the EMAC peripherals installed in the system and returns an integer count. The EMAC devices are enumerated in a consistent fashion so that each device can be later referenced by its physical index value ranging from ”1” to ”n” where ”n” is the count returned by this function. or an error code on failure. The function returns zero on success. uint numOfEmac.EMAC_close 8. uint retStat. See EMAC_open for more details.. the EMAC device will shutdown both send and receive operations. Possible error codes include: EMAC_ERROR_INVALID − A calling parameter is invalid Arguments Return Value Description Example Handle hEMAC. EMAC_enumerate Enumerates the peripherals installed in the system and returns an integer count Function Arguments Return Value Description uint EMAC_enumerate(). ..4 Functions In the function descriptions.. numOfEmac = EMAC_enumerate(). retStat = EMAC_close(hEMAC). Handle hEMAC uint When called.. and free all pending transmit and receive packets.

or an error code on failure. . The function returns zero on success. Arguments Return Value Description 8-14 . uint retStat. uint *pReceiveFilter ). Handle hEMAC uint *pReceiveFilter uint Called to get the current packet filter setting for received packets.. The current filter value is written to the pointer supplied in pReceiveFilter. uint *pReceiveFilter.. Possible error code include: EMAC_ERROR_INVALID − A calling parameter is invalid Example Handle hEMAC.EMAC_getReceiveFilter EMAC_getReceiveFilter Called to get the current packet filter setting for received packets Function uint EMAC_getReceiveFilter( Handle hEMAC. pReceiveFilter). retStat = EMAC_getReceiveFilter(hEMAC. The filter values are the same as those used in EMAC_setReceiveFilter().

or an error code on failure. Reading the statistics also clears the current statistic counters. .. Handle hEMAC EMAC_Statistics *pStatistics uint Called to get the current device statistics. Possible error code include: EMAC_ERROR_INVALID − A calling parameter is invalid Example uint retVal. Handle hEMAC. pStatistics). The statistics information is copied into the structure pointed to by the pStatistics argument. Arguments Return Value Description EMAC Module 8-15 . EMAC_Statistics *pStatistics. retVal = EMAC_getStatistics(hEMAC.EMAC_getStatistics EMAC_getStatistics Called to get the current device statistics Function uint EMAC_getStatistics( Handle hEMAC. The function returns zero on success. The statistics structure contains a collection of event counts for various packet sent and receive properties. so the values read represent a delta from the last call. EMAC_Statistics *pStatistics )..

Handle hEMAC EMAC_Status *pStatus uint Called to get the current status of the device. Possible error code include: EMAC_ERROR_INVALID − A calling parameter is invalid Arguments Return Value Description Example uint retVal. EMAC_Status *pStatus. The function returns zero on success. 8-16 . EMAC_Status *pStatus ). The device status is copied into the supplied data structure. retVal = EMAC_getStatus(hEMAC. or an error code on failure.EMAC_getStatus EMAC_getStatus Function Called to get the current device status uint EMAC_getStatus( Handle hEMAC. Handle hEMAC. . pStatus)...

EMAC Module 8-17 . The application layer may pass in an hApplication callback handle. or an error code on failure. retVal = EMAC_open(1. In order to change an item in the configuration. phEMAC). Handle *phEMAC. Handle *phEMAC ). An EMAC device handle is written to phEMAC. EMAC_Config *pEMACConfig. hApplication. A device reset is achieved by calling EMAC_close() followed by EMAC_open(). int physicalIndex Handle hApplication EMAC_Config *pEMACConfig Handle *phEMAC uint Opens the EMAC peripheral at the given physical index and initializes it to an embryonic state.. This handle must be saved by the caller and then passed to other EMAC device functions. that will be supplied by the EMAC device when making calls to the application callback functions.EMAC_open EMAC_open Function Opens the EMAC peripheral at the given physical index uint EMAC_open( int physicalIndex. Possible error codes include: EMAC_ERROR_ALREADY − The device is already open EMAC_ERROR_INVALID − A calling parameter is invalid Arguments Return Value Description Example uint retVal. The function returns zero on success. pEMACConfig.. The calling application must supply a operating configuration that includes a callback function table. the the EMAC device must be closed and then re-opened with the new configuration. Data from this config structure is copied into the device’s internal instance structure so the structure may be discarded after EMAC_open() returns. The default receive filter prevents normal packets from being received until the receive filter is specified by calling EMAC_receiveFilter(). Handle hApplication. . Handle hApplication. EMAC_Config *pEMACConfig.

EMAC_setReceiveFilter EMAC_setReceiveFilter Called to set the packet filter for received packets Function uint EMAC_setReceiveFilter( Handle hEMAC. Possible error code include: EMAC_ERROR_INVALID − A calling parameter is invalid Example uint retVal. so BROADCAST would include both BROADCAST and DIRECTED (UNICAST) packets. reception of these must be specified in the device configuration. Handle hEMAC. The filtering level is inclusive... retVal = EMAC_setReceiveFilter(hEMAC. Available filtering modes include the following: EMAC_RXFILTER_NOTHING − Receive nothing EMAC_RXFILTER_DIRECT − Receive only Unicast to local MAC addr EMAC_RXFILTER_BROADCAST − Receive direct and broadcast EMAC_RXFILTER_MULTICAST − Receive above plus multicast in mcast list EMAC_RXFILTER_ALLMULTICAST − Receive above plus all multicast EMAC_RXFILTER_ALL − Receive all packets Note that if error frames and control frames are desired. Arguments Return Value Description 8-18 . Handle hEMAC uint ReceiveFilter uint Called to set the packet filter for received packets. uint ReceiveFilter ). EMAC_RXFILTER_DIRECT). .

When AddrCnt is zero. it is impossible to examine a list of currently installed addresses. Therefore. The function returns zero on success. uint AddrCnt.. Handle hEMAC. NULL). The addresses to install are pointed to by pMCastList. or an error code on failure. 0. Each time this function is called. retVal = EMAC_setMulticast(hEMAC. Arguments Return Value Description EMAC Module 8-19 . Possible error code include: EMAC_ERROR_INVALID − A calling parameter is invalid Example uint retVal.. a set with a list size of zero removes all multicast addresses from the device. Therefore.EMAC_setMulticast EMAC_setMulticast Called to install a list of multicast addresses for use in multicast address filtering Function uint EMAC_setMulticast( Handle hEMAC. The multicast list settings are not altered in the event of a failure code. . The length of this list in bytes is 6 times the value of AddrCnt. Uint8 *pMCastList ). any current multicast configuration is discarded in favor of the new list. Note that the multicast list configuration is stateless in that the list of multicast addresses used to build the configuration is not retained. Uint8 *pMCastList.. the pMCastList parameter can be NULL. Handle hEMAC uint AddrCnt Uint8 *pMCastList uint This function is called to install a list of multicast addresses for use in multicast address filtering.

The packet is returned to the application’s free pool once it has been transmitted. pPacket).EMAC_sendPacket EMAC_sendPacket Sends a Ethernet data packet out the EMAC device Function uint EMAC_sendPacket( Handle hEMAC. the EMAC device has not taken ownership of the packet. Handle hEMAC EMAC_Pkt *pPacket uint Sends a Ethernet data packet out the EMAC device. EMAC_Pkt *pPacket. or an error code on failure. Arguments Return Value Description 8-20 . On a non-error return. Possible error codes include: EMAC_ERROR_INVALID − A calling parameter is invalid EMAC_ERROR_BADPACKET − The packet structure is invalid Example uint retVal. When an error code is returned. retVal = EMAC_sendPacket(hEMAC. Handle hEMAC. The function returns zero on success. .. the EMAC device takes ownership of the packet. EMAC_Pkt *pPacket )..

retVal = EMAC_serviceCheck(hEMAC). .. Possible error codes include: EMAC_ERROR_INVALID − A calling parameter is invalid EMAC_ERROR_MACFATAL − Fatal error in the MAC − Call EMAC_close() Example uint retVal. Note that the application has the responsibility for mapping the physical device index to the correct EMAC_serviceCheck() function.EMAC_serviceCheck EMAC_serviceCheck Called every time there is an EMAC device interrupt Function uint EMAC_serviceCheck( Handle hEMAC ). If more than one EMAC device is on the same interrupt. Handle hEMAC.. It maintains the status the EMAC. Handle hEMAC uint This function should be called every time there is an EMAC device interrupt. Arguments Return Value Description EMAC Module 8-21 . the function must be called for each device.

You are not required to use this constant. 8-22 . Handle hEMAC uint This function should be called for each device in the system on a periodic basis of 100 mS (10 times a second). retVal = EMAC_timerTick(hEMAC). Strict timing is not required. but the application should make a reasonable attempt to adhere to the 100 mS mark. EMAC_timerTICK Function Called for each device in the system on a periodic basis of 100 ms uint EMAC_timerTick( Handle hEMAC ). must also adhere to the 100 mS timing on this function. and to potentially recover from low Rx buffer conditions. Possible error codes include: EMAC_ERROR_INVALID − A calling parameter is invalid Arguments Return Value Description Example uint retVal. A missed call should not be ”made up” by making mulitple sequential calls A ”polling” driver (one that calls EMAC_serviceCheck() in a tight loop). Handle hEMAC.EMAC_SUPPORT EMAC_SUPPORT Description Compile-time constant Compile-time constant that has a value of 1 if the device supports the EMAC module and 0 otherwise. It is used to check the status of the EMAC and MDIO device.

. . . . . . . .1 9. . . . . . . . . . . . . . . . . Note: This module has not been updated for C64x™ devices. . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and provides an EMIF API reference section. . . . . . . . . . . . . . Topic 9. . . . . . . . . . . . . . . . . . . . . . . .4 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . .Chapter 9 EMIF Module This chapter describes the EMIF module. . 9-6 9-1 . . . . . . . . . . . . . 9-5 Functions . 9-3 Configuration Structures . . . 9-2 Macros . . . . . . . . . . . . . . . . .3 9. . . . . . .2 9. . . . . . . . . . . .

The EMIF may be configured by passing an EMIF_Config() structure to EMIF_config() or by passing register values to the EMIF_configArgs() function. 9-6 9-6 9-8 9-8 Note: F = Function. Table 9−1.. EMIF APIs Syntax EMIF_config EMIF_configArgs EMIF_getConfig EMIF_SUPPORT Type Description F F F C Sets up the EMIF using the configuration structure Sets up the EMIF using the register value arguments Reads the current EMIF configuration values A compile time constant that has a value of 1 if the device supports the EMIF module See page . 9-5 Table 9−2. Table 9−1 lists the configuration structure for use with the EMIF functions. there are symbol constants that may be used for the field values. In addition. there are EMIF_MK (make) macros that construct register values based on field values.1 Overview The EMIF module has a simple API for configuring the EMIF registers. C = Constant 9-2 .Overview 9.. Table 9−2 lists the functions and constants available in the CSL EMIF module. To assist in creating register values. EMIF Configuration Structure Structure EMIF_Config Purpose Structure used to set up the EMIF peripheral See page ...

<FIELD>. and Table 9−4 lists the EMIF macros that construct register and field values.x) EMIF_FGETA(addr.<FIELD>.2 Macros There are two types of EMIF macros: those that access registers and fields.Macros 9. Table 9−3 lists the EMIF macros that access registers and fields.<FIELD>. Using the HAL Macros. EMIF macros are not handle based.. and those that construct register and field values.fieldval) EMIF_FSETS(<REG>.fieldval) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address See page . The macros themselves are found in Chapter 28. Table 9−3.<REG>. EMIF Macros that Access Registers and Fields Macro EMIF_ADDR(<REG>) EMIF_RGET(<REG>) EMIF_RSET(<REG>..<REG>) EMIF_RSETA(addr.<FIELD>) EMIF_FSETA(addr.<FIELD>.<REG>. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 EMIF_FSETSA(addr.x) EMIF_FGET(<REG>.<REG>.<REG>.<SYM>) Sets field symbolically for a given address EMIF Module 9-3 .<SYM>) EMIF_RGETA(addr.<FIELD>) EMIF_FSET(<REG>.

. 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 9-4 . EMIF Macros that Construct Register and Field Values Macro EMIF_<REG>_DEFAULT EMIF_<REG>_RMK() EMIF_<REG>_OF() EMIF_<REG>_<FIELD>_DEFAULT EMIF_FMK() EMIF_FMKS() EMIF_<REG>_<FIELD>_OF() EMIF_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of .. Field default value Field make Field make symbolically Field value of ..Macros Table 9−4... Field symbolic value See page ..

3 Configuration Structure EMIF_Config Structure Members Structure used to set up EMIF peripheral EMIF_Config Uint32 gblctl Uint32 cectl0 Uint32 cectl1 Uint32 cectl2 Uint32 sdctl3 Uint32 cectl Uint32 sdtim Uint32 sdext EMIF global control register value CE0 space control register value CE1 space control register value CE2 space control register value CE3 space control register value SDRAM control register value SDRAM timing register value SDRAM extension register value (for 6211/6711 only) Description This is the EMIF configuration structure used to set up the EMIF peripheral. You can use literal values or the EMIF_MK macros to create the structure member values. /* sdtim */ 0x00000000 /* sdext */ }. /* cectl0 */ 0x404F0323. You create and initialize this structure and then pass its address to the EMIF_config() function. … EMIF_config(&MyConfig). /* cectl2 */ 0x00000030. /* cectl3 */ 0x72270000. EMIF Module 9-5 Example . /* cectl1 */ 0x00000030. /* sdctl */ 0x00000410. /* gblctl */ 0x00000040.EMIF_Config 9. EMIF_Config MyConfig = { /* example for 6211/6711 */ 0x00003060.

Arguments Return Value Description Pointer to an initialized configuration structure Example EMIF_configArgs Function Sets up EMIF using register value arguments /* for 6211/6711 only*/ void EMIF_configArgs( Uint32 gblctl. /* sdctl */ 0x00000410. EMIF_Config MyConfig = { /* example for 6211/6711 */ 0x00003060. Uint32 cectl1. Uint32 sdctl. Uint32 sdext 9-6 .4 Functions EMIF_config Function Sets up EMIF using configuration structure void EMIF_config( EMIF_Config *config ). See also EMIF_configArgs() and EMIF_Config. /* cectl3 */ 0x72270000. /* cectl0 */ 0x404F0323. /* cectl2 */ 0x00000030. Uint32 cectl2. /* gblctl */ 0x00000040. The values of the structure are written to the EMIF registers.EMIF_config 9. config none Sets up the EMIF using the configuration structure. /* cectl1 */ 0x00000030. /* sdtim */ 0x00000000 /* sdext */ }. Uint32 cectl3. Uint32 cectl0. … EMIF_config(&MyConfig). Uint32 sdtim.

/* 0x00000040. Uint32 cectl2. /* devices other than 6211/6711 */ gblctl */ cectl0 */ cectl1 */ cectl2 */ cectl3 */ sdctl */ sdtim */ EMIF global control register value CE0 space control register value CE1 space control register value CE2 space control register value CE3 space control register value SDRAM control register value SDRAM timing register value SDRAM extension register value (optional − reserved for 6211/6711 only) EMIF Module 9-7 . Uint32 cectl0. Uint32 cectl1. Uint32 sdctl. /* 0x00000410 /* ). /* 0x00000030.EMIF_configArgs ). The arguments are written to the EMIF registers. /* 0x72270000. /* 0x404F0323. Uint32 cectl3. Arguments gblctl cectl0 cectl1 cectl2 cectl3 sdctl sdtim sdext Return Value Description Example none Sets up the EMIF using the register value arguments. Uint32 sdtim ). EMIF_configArgs( 0x00003060. /* for all other devices*/ void EMIF_configArgs( Uint32 gblctl. See also EMIF_config(). /* 0x00000030.

all devices support this module. config none Get EMIF current configuration value EMIF_config emifCfg.EMIF_getConfig EMIF_getConfig Function Reads the current EMIF configuration values void EMIF_getConfig( EMIF_Config *config ). Arguments Return Value Description Example Pointer to a configuration structure. EMIF_SUPPORT Constant Description Compile time constant EMIF_SUPPORT Compile time constant that has a value of 1 if the device supports the EMIF module and 0 otherwise. EMIF_getConfig(&emifCfg). You are not required to use this constant. Example #if (EMIF_SUPPORT) /* user EMIF configuration / #endif 9-8 . Currently.

. . . . . . . .3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .Chapter 10 EMIFA/EMIFB Modules This chapter describes the EMIFA and EMIFB modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Overview . . . . . . . . 10-3 10. . . . . . . . . . . . . . . .2 Macros . . . . . . . . . . . . . . . . . . . . . .4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Topic Page 10. . . . . . . . . . lists the API functions and macros within the modules. . . . . . . . . 10-5 10. . . 10-7 10-1 . . and provides an API reference section. . . . . . . . . 10-2 10. . . . . . . . . . .

10-7 10-9 10-11 10-11 10-2 .Overview 10. In addition.. Table 10−2 lists the functions and constants available in the CSL EMIFA/EMIFB modules.1 Overview The EMIFA and EMIFB modules have simple APIs for configuring the EMIFA and EMIFB registers respectively. the EMIFA_<REG>_RMK() and EMIFB_<REG>_RMK() (make) macros construct register values based on field values. EMIFA/EMIFB Configuration Structure Syntax EMIFA_Config EMIFB_Config Type Description S Structure used to set up the EMIFA(B) peripheral See page . 10-5 Table 10−2. The EMIFA and EMIFB may be configured by passing a configuration structure to EMIFA_config() and EMIFB_config() or by passing register values to the EMIFA_configArgs() and EMIFB_configArgs() functions. Table 10−1. the symbol constants may be used for the field values... C = Constant Type Description F F F C Sets up the EMIFA(B) using the configuration structure Sets up the EMIFA(B) using the register value arguments Reads the current EMIFA(B) configuration values A compile time constant that has a value of 1 if the device supports the EMIFA and/or EMIFB modules See page . Table 10−1 lists the configuration structure for use with the EMIFA/EMIFB functions. EMIFA/EMIFB APIs Syntax EMIFA_config EMIFB_config EMIFA_configArgs EMIFB_configArgs EMIFA_getConfig EMIFB_getConfig EMIFA_SUPPORT EMIFB_SUPPORT Note: F = Function.. To assist in creating register values.

<REG>.<SYM>) EMIFB_FSETS(<REG>.fieldval) EMIFA_FSETS(<REG>.<REG>.<FIELD>) EMIFA_FSETA(addr.<FIELD>) EMIFA_FSET(<REG>.<FIELD>.<REG>. Table 10−3 lists the EMIFA and EMIFB macros that access registers and fields.<REG>. The macros themselves are found in Chapter 28.x) EMIFB_RSETA(addr.fieldval) EMIFB_FSET(<REG>.<FIELD>) EMIFB_FGET(<REG>. Using the HAL Macros.x) EMIFA_FSETSA(addr.<FIELD>.2 Macros There are two types of macros: those that access registers and fields.<REG>.<REG>. <SYM>) Description/Purpose Register address Return the value in the peripheral register Register set Return the value of the specified field in the peripheral register Write fieldval to the specified field in the peripheral register Write the symbol value to the specified field in the peripheral Get register for a given address Set register for a given address Get field for a given address Set field for a given address Set field symbolically for a given address See page .<REG>) EMIFA_RSETA(addr.<FIELD>.<REG>.x) EMIFB_FSETA(addr. and those that construct register and field values. EMIFA/EMIFB Macros that Access Registers and Fields Macro EMIFA_ADDR(<REG>) EMIFB_ADDR(<REG>) EMIFA_RGET(<REG>) EMIFB_RGET(<REG>) EMIFA_RSET(<REG>. EMIFA and EMIFB macros are not handle-based.x) EMIFA_FGETA(addr.<REG>) EMIFB_RGETA(addr.<FIELD>. <SYM>) EMIFB_FSETSA(addr.Macros 10.<FIELD>.<REG>. 28-12 28-18 28-20 28-13 28-13 28-17 28-19 28-20 28-13 28-16 28-12 EMIFA/EMIFB Modules 10-3 ..x) EMIFB_RSET(<REG>. Table 10−3.<FIELD>..<FIELD>. and Table 10−4 lists the EMIFA and EMIFB macros that construct register and field values.<SYM>) EMIFA_RGETA(addr.<FIELD>.x) EMIFA_FGET(<REG>.<FIELD>) EMIFB_FGETA(addr.

.. Field symbolic value See page .Macros Table 10−4. 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 10-4 .. EMIFA/EMIFB Macros that Construct Register and Field Values Macro EMIFA_<REG>_DEFAULT EMIFB_<REG>_DEFAULT EMIFA_<REG>_RMK() EMIFB_<REG>_RMK() EMIFA_<REG>_OF() EMIFB_<REG>_OF() EMIFA_<REG>_<FIELD>_DEFAULT EMIFB_<REG>_<FIELD>_DEFAULT EMIFA_FMK() EMIFB_FMK() EMIFA_FMKS() EMIFB_FMKS() EMIFA_<REG>_<FIELD>_OF() EMIFB_<REG>_<FIELD>_OF() EMIFA_<REG>_<FIELD>_<SYM> EMIFB_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of . Field default value Field make Field make symbolically Field value of ....

You create and initialize these structures and then pass their addresses to the EMIFA_config() and EMIFB_config() functions. EMIFA/B Modules 10-5 .3 Configuration Structure EMIFA_Config EMIFB_Config Structure Structures used to set up EMIFA and EMIFB peripherals EMIFA_Config EMIFB_Config Uint32 gblctl Uint32 cectl0 Uint32 cectl1 Uint32 cectl2 Uint32 cectl3 Uint32 sdctl Uint32 sdtim Uint32 sdext Uint32 cesec0 Uint32 cesec1 Uint32 cesec2 Uint32 cesec3 EMIFA(B)global control register value CE0 space control register value CE1 space control register value CE2 space control register value CE3 space control register value SDRAM control register value SDRAM timing register value SDRAM extension register value CE0 space secondary control register value CE1 space secondary control register value CE2 space secondary control register value CE3 space secondary control register value Members Description These are the EMIFA and EMIFB configuration structures used to set up the EMIFA and EMIFB peripherals.EMIFA_Config EMIFB_Config 10. respectively. You can use literal values or the EMIFA_<REG>_RMK and EMIFB_<REG>_RMK macros to create the structure member values.

/* cectl3 */ 0x07117000. /* cectl0 */ 0x404F0323. /* gblctl */ 0x00000040. /* cesec1 */ 0x00000000. EMIFB_Config MyConfigB = { 0x00003060. /* sdctl */ 0x00000610. 10-6 . /* cectl1 */ 0x00000030. /* cesec0 */ 0x00000000. /* cesec2 */ 0x00000000 /* cesec3 */ }. /* sdctl */ 0x00000610. /* sdext */ 0x00000000. /* cesec1 */ 0x00000000. EMIFB_config(&MyConfigB). /* sdext */ 0x00000000. /* cectl3 */ 0x07117000. /* gblctl */ 0x00000040. /* cectl2 */ 0x00000030. /* sdtim */ 0x00000000. /* cectl1 */ 0x00000030. /* cesec2 */ 0x00000000 /* cesec3 */ }. /* sdtim */ 0x00000000. /* cesec0 */ 0x00000000. /* cectl2 */ 0x00000030. /* cectl0 */ 0x404F0323. … EMIFA_config(&MyConfigA).EMIFA_Config EMIFB_Config Example EMIFA_Config MyConfigA = { 0x00003060.

The values of the structures are written to the EMIFA and EMIFB registers respectively.4 Functions EMIFA_config EMIFB_config Function Sets up EMIFA and EMIFB using configuration structures void EMIFA_config( EMIFA_Config *config ). void EMIFB_config( EMIFB_Config *config ). Arguments Return Value Description config none Pointer to an initialized configuration structure Sets up the EMIFA and/or EMIFB using the configuration respective structures.EMIFA_config EMIFB_config 10. EMIFA/B Modules 10-7 .

/* cectl1 */ 0x00000030. /* gblctl */ 0x00000040. /* sdext */ 0x00000000. /* cectl2 */ 0x00000030. /* cesec2 */ 0x00000000 /* cesec3 */ }. /* sdext */ 0x00000000. /* cectl3 */ 0x07117000. /* sdctl */ 0x00000610. /* cectl1 */ 0x00000030. /* cesec3 */ }. /* gblctl */ 0x00000040. /* cectl2 */ 0x00000030. /* sdtim */ 0x00000000. /* sdtim */ 0x00000000. /* cesec0 */ 0x00000000. /* cectl0 */ 0x404F0323. /* cesec2 */ 0x00000000. /* sdctl */ 0x00000610. EMIFB_config(&MyConfigB).EMIFA_config EMIFB_config Example EMIFA_Config MyConfigA = { 0x00003060. 10-8 . /* cesec0 */ 0x00000000. /* cectl3 */ 0x07117000. /* cesec1 */ 0x00000000. /* cectl0 */ 0x404F0323. EMIFB_Config MyConfigB = { 0x00003060. … EMIFA_config(&MyConfigA). /* cesec1 */ 0x00000000.

Uint32 cesec0. Arguments gblctl cectl0 cectl1 cectl2 cectl3 sdctl sdtim sdext cesec0 cesec1 EMIFA(B) global control register value CE0 space control register value CE1 space control register value CE2 space control register value CE3 space control register value SDRAM control register value SDRAM timing register value SDRAM extension register value CE0 space secondary register value CE1 space secondary register value EMIFA/B Modules 10-9 . Uint32 sdtim. Uint32 cectl0. Uint32 cectl2. Uint32 sdext. Uint32 sdext. Uint32 cesec3 ). Uint32 sdtim. Uint32 cectl2. Uint32 cectl3.EMIFA_configArgs EMIFB_configArgs EMIFA_configArgs EMIFB_configArgs Sets up EMIFA and EMIFB using register value arguments Function void EMIFA_configArgs( Uint32 gblctl. Uint32 cesec0. Uint32 sdctl. void EMIFB_configArgs( Uint32 gblctl. Uint32 cesec3 ). Uint32 sdctl. Uint32 cectl1. Uint32 cesec1. Uint32 cesec2. Uint32 cectl0. Uint32 cectl1. Uint32 cesec2. Uint32 cesec1. Uint32 cectl3.

/* cectl1 0x00000030. EMIFB_configArgs( 0x00003060. /* cesec2 0x00000000 /* cesec3 ). /* sdctl 0x00000610. EMIFA_configArgs( 0x00003060. /* cesec1 0x00000000. /* cectl1 0x00000030. /* cectl2 0x00000030. /* sdtim 0x00000000. /* sdext 0x00000000. /* cectl2 0x00000030. /* sdtim 0x00000000.EMIFA_configArgs EMIFB_configArgs cesec2 cesec3 Return Value Description none Set up the EMIFA and EMIFB using the register value arguments. The arguments are written to the EMIFA and EMIFB registers respectively. /* cesec2 0x00000000 /* cesec3 ). /* cesec0 0x00000000. /* cesec0 0x00000000. */ */ */ */ */ */ */ */ */ */ */ */ CE2 space secondary register value CE3 space secondary register value Example */ */ */ */ */ */ */ */ */ */ */ */ 10-10 . /* cesec1 0x00000000. /* gblctl 0x00000040. /* cectl3 0x07117000. See also EMIFA_config().EMIFB_config() functions. /* cectl0 0x404F0323. /* cectl0 0x404F0323. /* gblctl 0x00000040. /* sdctl 0x00000610. /* sdext 0x00000000. /* cectl3 0x07117000.

Arguments Return Value Description Example config none Pointer to a configuration structure. void EMIFB_getConfig( EMIFB_Config *config ).EMIFA_getConfig EMIFB_getConfig EMIFA_getConfig EMIFB_getConfig Function Reads the current EMIFA and EMIFB configuration values void EMIFA_getConfig( EMIFA_Config *config ). EMIFA_getConfig(&emifCfgA). EMIFB_getConfig(&emifCfgB). Example #if (EMIFA_SUPPORT) /* user EMIFA configuration / #endif EMIFA/B Modules 10-11 . EMIFB_config emifCfgB. EMIFA_config emifCfgA. EMIFA_SUPPORT EMIFB_SUPPORT Compile-time constants Constant EMIFA_SUPPORT EMIFB_SUPPORT Description Compile time constants that have a value of 1 if the device supports the EMIFA and EMIFB modules respectively. You are not required to use this constant. Currently. Get EMIFA and EMIFB current configuration values. all devices support this module. and 0 otherwise.

. .Chapter 11 GPIO Module This chapter describes the GPIO module. . . . . . . . . . . . . 11-5 11. . . . . . . . . . . . . . . . . . . . . . . . . and provides a GPIO API reference section. . . . .2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11-1 . . . . . . . . . . . . 11-2 11. . . . . . . . . 11-7 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Configuration Structure . . . . .1 Overview . . . . . . . . . . . . . . . . . . . . Topic Page 11. . . . . . . . . . . . . . . . .4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lists the GPIO functions and macros within the module. . . .

the GPIO peripheral provides 16 dedicated general-purpose pins that can be configured as either inputs or outputs.. Table 11−1. Each GPx pin configured as an input can directly trigger a CPU interrupt or a GPIO event. GPIO APIs (a) Primary GPIO Functions Syntax GPIO_close GPIO_config GPIO_configArgs GPIO_open GPIO_reset (b) Auxiliary GPIO Functions Syntax GPIO_clear GPIO_deltaLowClear GPIO_deltaLowGet Type Description F F F Clears the GPIO Delta registers Clears bits of given input pins in Delta Low register Indicates if a given input pin has undergone a high-to-low transition.1 Overview For TMS320C64x™ devices. Returns 0 if the transition is not detected. See page . The properties and functionalities of the GPx pins are covered by a set of CSL APIs.... GPIO Configuration Structure Syntax GPIO_Config Type Description S The GPIO configuration structure used to set the GPIO Global control register See page ... 11-8 11-8 11-9 11-10 11-10 11-2 .Overview 11. Table 11−2 lists the functions and constants available in the CSL GPIO module. 11-11 11-11 11-12 Type Description F F F F C Closes a GPIO port previously opened via GPIO_open() Sets up the GPIO global control register using the configuration structure Sets up the GPIO global control register using the register values passed in Opens a GPIO port for use Resets the given GPIO channel See page . 11-7 Table 11−2. Table 11−1 lists the configuration structure for use with the GPIO functions.

GPIO_GPINT7 Sets the polarity of the GPINTx interrupt/event signals when configured in Pass Through mode Clears the bits of given input pins in Mask Low register Enables given pins to cause a CPU interrupt or EDMA event based on corresponding GPxDL or inverted GPxVAL by setting the associated mask bit. A compile time constant whose value is 1 if the device supports the GPIO module. GPIO_GPINT5. Reads the current GPIO configuration structure Constants dedicated to GPIO interrupt/event signals: GPIO_GPINT0. GPIO_GPINT4. GPIO_GPINT6. 11-12 11-13 GPIO_getConfig GPIO_GPINTx F C 11-13 11-14 GPIO_intPolarity GPIO_maskLowClear GPIO_maskLowSet F F F 11-14 11-15 11-15 GPIO_maskHighClear GPIO_maskHighSet F F 11-16 11-16 GPIO_pinDisable GPIO_pinDirection GPIO_pinEnable GPIO_pinRead GPIO_pinWrite GPIO_PINx GPIO_read GPIO_SUPPORT GPIO_write Note: F = Function. Enables the given pins under the Global Enable register Reads the detected values of pins configured as inputs and the values to be driven on given output pins.. Reads data from a set of pins. Applies only if the corresponding pins are enabled. Writes the values to be driven on given output pins. C = Constant F F F F F C C C C 11-17 11-17 11-18 11-18 11-19 11-19 11-20 11-20 11-20 GPIO Module 11-3 . Constants dedicated to GPIO pins: GPIO_PIN0 –GPIO_PIN15. Clears the bits of input pins in Mask High register Enables given pins to cause a CPU interrupt or EGPIO event based on corresponding GPxDH or GPxVAL by setting the associated mask bit.Overview Syntax GPIO_deltaHighClear GPIO_deltaHighGet Type Description F F Clears the bit of a given input pin in Delta High register Indicates if a given input pin has undergone a low-to-high transition. Returns 0 if the transition is not detected.. Writes the value to the specified set of GPIO pins. Disables given pins under the Global Enable register Sets the direction of the given pins. See page .

2 All GPIO APIs have changed with the addition of the handle passed as an input parameter. In addition. 11-4 . Note that most functions apply to enabled pins only. there are symbol constants that may be used for the field values.7. it is strongly recommended to update the APIs using the handle−based methodology described in section 1.1. GPIO_enablePins() must be called before using any other functions on these pins.h> to avoid any changes to the user’s code. you must first allocate a device using GPIO_open().1 to CSL 2. Important note for C64x users: Migration CSL 2. Although it is possible to include the header file <csl_legacy.1. there are GPIO_<REG>_RMK (make) macros that construct register value based on field values. To assist in creating register values.Overview 11. Using CSL Handles. In order to enable the pins.1 Using GPIO To use the GPIO pins. and then configure the Global Control register to determine the peripheral mode by using the configuration structure to GPIO_config() or by passing register value to the GPIO_configArgs() function.

Table 11−3 lists the GPIO macros that access registers and fields.<REG>.2 Macros There are two types of GPIO macros: those that access registers and fields.<FIELD>.x) GPIO_FGETA(addr.<SYM>) GPIO_RGETA(addr.<REG>) GPIO_RGETH(h.<FIELD>.fieldval) GPIO_FSETS(<REG>. <SYM>) GPIO_ADDRH(h. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 GPIO Module 11-5 .<FIELD>) GPIO_FSET(<REG>. The GPIO module includes handle-based macros.<REG>. and Table 11−4 lists the GPIO macros that construct register and field values.<FIELD>) GPIO_FSETA(addr.<REG>) GPIO_RSETA(addr. Using the HAL Macros.<FIELD>.x) GPIO_FGET(<REG>.<FIELD>.<FIELD>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address Returns the address of a memory-mapped register for a given handle Returns the value of a register for a given handle Sets the register value to x for a given handle Returns the value of the field for a given handle See page . Table 11−3.<REG>) GPIO_RSETH(h. and those that construct register and field values.Macros 11.<REG>.<REG>.x) GPIO_FGETH(h. GPIO Macros that Access Registers and Fields Macro GPIO_ADDR(<REG>) GPIO_RGET(<REG>) GPIO_RSET(<REG>.<REG>..<REG>. fieldval) GPIO_FSETSA(addr.. The macros themselves are found in Chapter 28.

<REG>. fieldval) GPIO_FSETSH(h.<FIELD>..... GPIO Macros that Access Registers and Fields (Continued) Macro GPIO_FSETH(h.. 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 11-6 . GPIO Macros that Construct Register and Field Values Macro GPIO_<REG>_DEFAULT GPIO_<REG>_RMK() GPIO_<REG>_OF() GPIO_<REG>_<FIELD>_DEFAULT GPIO_FMK() GPIO_FMKS() GPIO_<REG>_<FIELD>_OF() GPIO_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of ..<FIELD>. Table 11−4. <SYM>) Description/Purpose Sets the field value to x for a given handle Sets field for a given address See page . Field default value Field make Field make symbolically Field value of .<REG>.. Field symbolic value See page ..Macros Table 11−3.

GPIO_Config MyConfig = { 0x00000031. /* gphm */ 0x00000000. . /* gpen */ 0x00000070. /* gplm */ 0x00000030 /* gppol */ }.. GPIO_config(hGpio.GPIO_Config 11. /* gdir */ 0x00000082. Example GPIO Module 11-7 .&MyConfig). /* gpval */ 0x00000000. You can use literal values or the _RMK macros to create the structure register value. then pass its address to the GPIO_config() function.3 Configuration Structure GPIO_Config Structure Members GPIO configuration structure used to set up GPIO registers GPIO_Config Uint32 gpgc Uint32 gpen Uint32 gpdir Uint32 gpval Uint32 gphm Uint32 gplm Uint32 gppol GPIO Global control register value GPIO Enable register value GPIO Direction register value GPIO Value register value GPIO High Mask register value GPIO Low Mask register value GPIO Interrupt Polarity register value Description This is the GPIO configuration structure used to set up the GPIO registers. /* gpgc */ 0x000000F9.. You create and initialize this structure.

4.1 Primary GPIO Functions GPIO_close Function Closes GPIO channel previously opened via GPIO_open() void GPIO_close( GPIO_Handle hGpio ). /* gpgc */ GPIO_GPEN_RMK(0x000000F9). /* gdir */ 0x00000082. /* gplm */ 0x00000030 /* gppol */ }.GPIO_close 11. /* gpval */ 0x00000000. See also GPIO_configArgs() and GPIO_Config. hGpio none This function closes a GPIO channel previously opened via GPIO_open(). see GPIO_open() Pointer to an initialized configuration structure Arguments Return Value Description none Sets up the GPIO mode using the configuration structure. The values of the structure are written to the GPIO Global control register. see GPIO_open() Arguments Return Value Description Example GPIO_config Function Sets up GPIO modes using a configuration structure void GPIO_config( GPIO_Handle hGpio. /* gpen */ 0x00000070. GPIO_Config *config ). Example 11-8 . hGpio config Handle to GPIO device. GPIO_close(hGpio). Handle to GPIO device. GPIO_Config MyConfig = { 0x00000031.4 Functions 11. This function accepts the following device handle: From GPIO_open(). … GPIO_config(hGpio. /* gphm */ 0x00000000.&MyConfig).

Uint32 gpen. /* gpen */ 0x00000070. See also GPIO_config().GPIO_configArgs GPIO_configArgs Function Sets up GPIO mode using register value passed in void GPIO_configArgs( GPIO_Handle hGpio. Uint32 gppol ). /* gphm */ 0x00000000. see GPIO_open() Global control register value GPIO Enable register value GPIO Direction register value GPIO Value register value GPIO High Mask register value GPIO Low Mask register value GPIO Interrupt Polarity register value Arguments Return Value Description Example GPIO_configArgs(hGpio. Uint32 gphm. You may use literal values for the arguments or for readability. hGpio gpgc gpen gpdir gpval gphm gplm gppol none Sets up the GPIO mode using the register value passed in. /* gpgc */ 0x000000F9. Handle to GPIO device. Uint32 gpdir. The register value is written to the GPIO Global Control register. Uint32 gplm. Uint32 gpval. Uint32 gpgc. /* gpval */ 0x00000000. /* gplm */ 0x00000030 /* gppol */ ). 0x00000031. You may use the _RMK macros to create the register values based on field values. GPIO Module 11-9 . /* gdir */ 0x00000082.

. 11-10 . which may be cleared using the GPIO_clear() function. it cannot be opened again until closed.. Example GPIO_Handle hGpio. . See GPIO_close().. Arguments Return Value Description Example GPIO_open Function Opens GPIO device GPIO_Handle GPIO_open( int chaNum. see GPIO_open() GPIO channel to open: . with the exceptions of the Delta High and Delta Low registers.GPIO_OPEN_RESET Arguments Return Value Description Device Handle Returns a device handle to be used by other GPIO API function calls Before a GPIO device can be used. hGpio Device handle obtained by GPIO_open() none Resets the given GPIO channel. hGpio = GPIO_open(GPIO_DEV0.GPIO_OPEN_RESET). GPIO_reset(hGpio). . hGpio chaNum flags Handle to GPIO device. The registers are set to their default values. the GPIO channel is reset. Once opened. If the device cannot be opened. INV is returned. may be logical OR of any of the following: . the channel interrupt is disabled and cleared. If the open fails. The return value is a unique device handle that is used in subsequent GPIO API calls.GPIO_DEV0 Open flags.GPIO_reset GPIO_reset Function Resets a given GPIO channel void GPIO_reset( GPIO_Handle hGpio ). If the GPIO_OPEN_RESET is specified. INV is returned. it must first be opened by this function.. Uint32 flags ).

PinID).GPIO_PIN2). hGpio none This function clears the GPIO Delta Low (GPDL) and Delta High (GPDH) registers by writing 1 to every bit in these registers. GPIO_deltaLowClear (hGpio. see GPIO_open() Pin ID to the associated pin to be cleared GPIO Module 11-11 .GPIO_clear 11.4. Uint32 pinId ). see GPIO_open() Arguments Return Value Description Example GPIO_deltaLowClear Clears bits of given input pins in Delta Low Register Function void GPIO_deltaLowClear( GPIO_Handle hGpio. /* Clears one pin */ GPIO_deltaLowClear (hGpio. Arguments Handle to GPIO device. /* Clears several pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3. Handle to GPIO device. GPIO_clear(hGpio). hGpio pinId Return Value Description Example none This function clears the bits of given pins register in Delta Low Register.2 Auxiliary GPIO Functions and Constants GPIO_clear Function Clears GPIO Delta registers void GPIO_clear( GPIO_Handle hGpio ).

Uint32 detectionHL. detectionHL = GPIO_deltaLowGet (hGpio. hGpio pinId Return Value Description 11-12 Arguments Handle to GPIO device. see GPIO_open() Pin ID to the associated pin to be cleared Returns the transition detection status of pinID. Returns the status of the transition detection for the pins associated with the pinId.GPIO_PIN2). Uint32 pinId ).GPIO_deltaLowGet GPIO_deltaLowGet Returns high-to-low transition detection status for given input pins Function Uint32 GPIO_deltaLowGet( GPIO_Handle hGpio. /* Get transition Detection Status for several pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3. see GPIO_open() Pin ID to the associated pin to be cleared none This function clears the bits of given pin register in Delta High Register. /* Get transition Detection Status for pin2 */ Uint32 detectionHL.PinID). Uint32 pinId ). . detectionHL = GPIO_deltaLowGet (hGpio. Arguments This function indicates if a given input pin has undergone a high-to-low transition. hGpio pinId Return Value Description status Handle to GPIO device. /* detectionHL can take the following values : */ /* 0x00000000 : No high-low transition detected */ /* 0x00000004 : transition detected for GP2 */ /* 0x00000008 : transition detected for GP3 */ /* 0x0000000C : transitions detected for GP2 and GP3 */ Example GPIO_deltaHighClear Clears bits of given input pins in Delta High Register Function void GPIO_deltaHighClear( GPIO_Handle hGpio.

/* detectionLH can take the following values : */ /* 0x00000000 : no high-low transitions detected*/ /* 0x00000004 : transition detected for GP2 */ /* 0x00000008 : transition detected for GP3 */ /* 0x0000000C : transitions detected for GP2 and GP3 */ Example GPIO_getConfig Function Reads the current GPIO Configuration Structure void GPIO_getConfig( GPIO_Handle hGpio. see GPIO_open() Pointer to a configuration structure. hGpio pinId Handle to GPIO device. /* Clears several pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3. /* Get transition Detection Status for pin2 */ Uint32 detectionLH.GPIO_PIN2). detectionLH = GPIO_deltaHighGet (hGpio. Uint32 detectionLH. hGpio Config Handle to GPIO device. Uint32 pinId ). GPIO Module 11-13 Arguments . detectionLH = GPIO_deltaHighGet (hGpio. GPIO_deltaHighGet Function Returns low-to-high transition detection status for given input pins Uint32 GPIO_deltaHighGet( GPIO_Handle hGpio. GPIO_Config *Config ).GPIO_PIN2). GPIO_deltaHighClear (hGpio. Returns the status of the transition detection for the pins associated to the pinId. Arguments Return Value Description status This function indicates if a given input pin has undergone a low-to-high transition. /* Get transition Detection Status for several pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3.PinID).GPIO_deltaHighGet Example /* Clears one pin */ GPIO_deltaHighClear (hGpio.PinID). see GPIO_open() Pin ID to the associated pin to be cleared Returns the transition detection status of pinID.

5. Uint32 signal.7} Set of constants that takes the value of the masks of the associated interrupt/event pins. GPIO_intPolarity Function Sets the polarity of the GPINTx interrupt/even signals void GPIO_intPolarity( GPIO_Handle hGpio. hGpio signal polarity Handle to GPIO device. see GPIO_open() The interrupt/event signal to be configured Polarity of the given signal . 2 constants are predefined .4.&GPIOCfg).GPIO_RISING .6. GPIO_GPINTx Constant Description Compiler constant dedicated to identify GPIO interrupt/event pins GPIO_GPINTx with x={0. GPIO_getConfig(hGpio. Bits of several pins can be set simultaneously by using the logic OR between the masks. Example GPIO_intPolarity(GPIO_GPINT7.GPIO_RISING). These constants are used by the GPIO functions that use signal as the input parameter. See GPIO_intPolarity().GPIO_GPINTx Return Value Description Example none Get GPIO current configuration value GPIO_config GPIOCfg. GPIO_intPolarity(GPIO_GPINT8. Uint32 polarity ).GPIO_FALLING).GPIO_FALLING Arguments Return Value none 11-14 .

GPIO_maskLowClear (hGpio. See also GPIO_maskLowSet() function. hGpio pinId Return Value Description none This function sets the bits of given pins to generate an interrupt/event based on corresponding GPxDL or inverted GPxVAL values. /* Sets several pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3.PinID). Arguments Handle to GPIO device.GPIO_maskLowClear GPIO_maskLowClear Clears bits which cause a CPU interrupt or EDMA event Function void GPIO_maskLowClear( GPIO_Handle hGpio. GPIO_maskLowSet (hGpio. /* Clears one pin mask */ GPIO_maskLowClear (hGpio. hGpio pinId Return Value Description Example none This function clears the bits of given pins in Mask Low Register. see GPIO_open() Pin ID to the associated pin to be set Example . /* Clears several pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3.GPIO_PIN2). See also the GPIO_maskLowClear() function. Uint32 pinId ).GPIO_PIN2). see GPIO_open() Pin ID to the associated pin to be cleared GPIO_maskLowSet Sets bits which cause a CPU interrupt or EDMA event Function void GPIO_maskLowSet( GPIO_Handle hGpio. GPIO Module 11-15 Arguments Handle to GPIO device.PinID). /* Sets one pin mask */ GPIO_maskLowSet (hGpio. Uint32 pinId ).

Uint32 pinId ). GPIO_maskHighSet (hGpio. see GPIO_open() Pin ID to the associated pin to be cleared GPIO_maskHighSet Sets bits which cause a CPU interrupt or EDMA event Function void GPIO_maskHighSet( GPIO_Handle hGpio.GPIO_PIN2). see GPIO_open() Pin ID to the associated pin to be set Example 11-16 .GPIO_PIN2). hGpio pinId Return Value Description Example none This function clears the bits of given pins in Mask High Register. hGpio pinId Return Value Description none This function sets the bits of given pins to generate an interrupt/event based on corresponding GPxDH or GPxVAL values. Arguments Handle to GPIO device. See also GPIO_maskHighSet() function. /* Clears several pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3.GPIO_maskHighClear GPIO_maskHighClear Clears bits which cause a CPU interrupt or EDMA event Function void GPIO_maskHighClear( GPIO_Handle hGpio. See also the GPIO_maskHighClear() function. /* Clears one pin mask */ GPIO_maskHighClear (hGpio.PinID). GPIO_maskHighClear (hGpio. Uint32 pinId ). Arguments Handle to GPIO device. /* Sets several pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3. /* Sets one pin mask */ GPIO_maskHighSet (hGpio.PinID).

see GPIO_open() Pin ID to the associated pin to be cleared Determines the direction of the given pins. This function is used after having enabled some pins. hGpio pinId direction Handle to GPIO device. Example GPIO_pinDirection Sets the direction of the given pins as input or output Function Uint32 GPIO_pinDirection( GPIO_Handle hGpio. See also the GPIO_pinEnable() function. see GPIO_open() pin ID to the associated pin to be cleared Arguments Return Value Description none This function disables the given GPIO pins by setting the associated bits to 0 under the GPEN register. GPIO Module 11-17 .GPIO_OUTPUT Returns the current pin direction setting Arguments Return Value Description CurrentSet This function sets the associated direction bits of given pins as input or output. 2 constants are predefined: .GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3). /* Enables Pins */ GPIO_pinEnable(hGpio.GPIO_pinDisable GPIO_pinDisable Function Disables the General Purpose Input/Output pins void GPIO_pinDisable ( GPIO_Handle hGpio. Applies only if the given are enabled previously.GPIO_INPUT . hGpio pinId Handle to GPIO device.GPIO_PIN1). Uint32 pinId ). Uint32 pinId ). … /* Disable GP1 pin */ GPIO_pinDisable(hGpio.

GPIO_INPUT). see GPIO_open() Pin ID to the associated pin to be set 0 or 1 Arguments Return Value Description val If the specified pin has been previously configured as an input. hGpio pinId Handle to GPIO device. this function returns the value to be driven on the pin.GPIO_pinEnable Example Uint32 Current_dir. Uint32 pinId ). see GPIO_open() Pin ID to the associated pin to be cleared Arguments Return Value Description none This function enables the given GPIO pins by setting the associated bits to 1 under the GPEN register. 11-18 . See also the GPIO_pinDisable() function. Example GPIO_pinRead Function Gets value of given pins Uint32 GPIO_pinRead( GPIO_Handle hGpio. GPIO_pinEnable Function Enables the General Purpose Input/Output pins void GPIO_pinEnable( GPIO_Handle hGpio.GPIO_PIN1. Current_dir = GPIO_ pinDirection(hGpio. Uint32 pinId ). /* Sets GP1 as input pin */ Current_dir = GPIO_pinDirection(hGpio.GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3). /* Enables Pins */ GPIO_pinEnable(hGpio. /* Sets GP2 and GP3 as output pins */ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3. hGpio pinId Handle to GPIO device. this function returns the value “0” or “1”.GPIO_OUTPUT). If the specified pin has been configured as an output pin.PinID. This function is used after using the given pins as GPIO pins.

GPIO Module 11-19 . /* Sets values of several pins to 0*/ Uint32 PinID= GPIO_PIN2 | GPIO_PIN3. /* returns value of pin #2 */ val = GPIO_pinRead (hGpio. Bits of several pins can be set simultaneously by using the logic OR between the masks. GPIO_ pinWrite(hGpio. hGpio pinId val Handle to GPIO device. These constants are used by the GPIO functions that use pinID as the input parameter.GPIO_PIN2 | GPIO_PIN3). GPIO_pinWrite Function Writes value of given output pins void GPIO_pinWrite( GPIO_Handle hGpio. 1) /* Sets one pin mask */ GPIO_maskHighSet (hGpio. see GPIO_open() Pin ID to the associated pin to be set Value to be driven on the given output pin: 0 or 1 Arguments Return Value Description Example none This function sets the value 0 or 1 to be driven on given output pins. Example /* Enables pins */ GPIO_pinEnable (hGpio.0). /* Sets value of one pin to 1*/ GPIO_pinWrite(hGpio.GPIO_PIN3.GPIO_PIN2. Uint32 pinId.PinID.GPIO_pinWrite Example Uint32 val. GPIO_PINx Constant Description Compile constant dedicated to identify each GPIO pin GPIO_PINx with x from 0 to 15 Set of constants that takes the value of the masks of the associated pins.1). Uint32 val ). /* Sets Pin3 as an output pin */ Current_dir = GPIO_pinDirection(hGpio. Uint32 val.GPIO_PIN2).GPIO_PIN2).

See also GPIO_write(). GPIO_pinWrite() and GPIO_pinRead(). Uint32 pinMask. You are not required to use this constant. pinVal = GPIO_read(hGpio. GPIO_SUPPORT Constant Description Compile-time constant GPIO_SUPPORT Compile-time constant that has a value of 1 if the device supports the GPIO module and 0 otherwise. hGpio pinMask Handle to GPIO device. . See also GPIO_read(). #if (GPIO_SUPPORT) /* user GPIO configuration / #endif Example GPIO_write Function Writes the value to the specified set of GPIO pins void GPIO_write( GPIO_Handle hGpio.GPIO_PIN8|GPIO_PIN7|GPIO_PIN6). GPIO_ write(hGpio. see GPIO_open() GPIO pin mask for a set of pins Returns the value read on the pins for the pinMask Arguments Return Value Description Example Uint32 This function reads data from a set of pins passed on as a pinmask to the function. Uint32 val ).GPIO_read GPIO_read Function Reads data from a set of pins Uint32 GPIO_read( GPIO_Handle hGpio. hGpio pinMask val Handle to GPIO device. see GPIO_open() GPIO pin mask bit value Arguments Return Value Description Example 11-20 none This function writes the value to a set of GPIO pins. Uint32 pinMask ). Note: The GPIO module is not supported on devices without the GPIO peripheral.0x4).GPIO_PIN2|GPIO_PIN3.

. . . . . . . . . . . . 12-3 12. . . . . . . . . . . . . . Topic Page 12. . . . . .2 Macros . . . . . . . . . . . . . . . . .1 Overview . . . . . . . . . . . . . . . and provides an HPI API reference section. . . . 12-5 12-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12. . . . . . . . . . . . . . . . . . . . . . . . .Chapter 12 HPI Module This chapter describes the HPI module. . . . . .3 Functions . . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Returns the value of the HINT bit of the HPIC register Returns the value of the HRDY bit of the HPIC register Returns the value of the HWOB bit of the HPIC register Returns the Read memory address (HPIAR C64x only) Returns the Write memory address (HPIAW C64x only) Writes the value to the DSPINT field of the HPIC register Writes the value to the HINT field of the HPIC register Sets the Read memory address (HPIAR C64x only) Sets the Write memory address (HPIAW C64x only) A compile-time constant whose value is 1 if the device supports the HPI module See page .1 Overview The HPI module has a simple API for configuring the HPI registers. Table 12−1.Overview 12. 12-5 12-5 12-5 12-6 12-6 12-6 12-6 12-7 12-7 12-7 12-8 12-8 12-8 12-2 . HPI APIs Syntax HPI_getDspint HPI_getEventId HPI_getFetch HPI_getHint HPI_getHrdy HPI_getHwob HPI_getReadAddr HPI_getWriteAddr HPI_setDspint HPI_setHint HPI_setReadAddr HPI_setWriteAddr HPI_SUPPORT Note: F = Function. Table 12−1 shows the API functions within the HPI module.. Functions are provided for reading HPI status bits and setting interrupt events. write and Read memory addresses can be accessed. For C64x™ devices. C = Constant Type Description F F F F F F F F F F F F C Reads the DSPINT bit from the HPIC register Obtain the IRQ event associated with the HPI device Reads the FETCH flag from the HPIC register and returns its value..

<REG>. and those that construct register and field values.<FIELD>) HPI_FSET(<REG>. Table 12−2 lists the HPI macros that access registers and fields. The macros themselves are found in Chapter 28. and Table 12−3 lists the HPI macros that construct register and field values.fieldval) HPI_FSETS(<REG>.<SYM>) HPI_RGETA(addr. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page ..x) HPI_FGET(<REG>.<FIELD>. HPI macros are not handle-based. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 HPI Module 12-3 . Table 12−2. fieldval) HPI_FSETSA(addr.2 Macros There are two types of HPI macros: those that access registers and fields.<REG>) HPI_RSETA(addr.<REG>.<FIELD>.<FIELD>.<REG>..x) HPI_FGETA(addr.Macros 12.<REG>. Using the HAL Macros. HPI Macros that Access Registers and Fields Macro HPI_ADDR(<REG>) HPI_RGET(<REG>) HPI_RSET(<REG>.<FIELD>) HPI_FSETA(addr.<FIELD>.

.Macros Table 12−3. HPI Macros that Construct Register and Field Values Macro HPI_<REG>_DEFAULT HPI_<REG>_RMK() HPI_<REG>_OF() HPI_<REG>_<FIELD>_DEFAULT HPI_FMK() HPI_FMKS() HPI_<REG>_<FIELD>_OF() HPI_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of .. Field default value Field make Field make symbolically Field value of . 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 12-4 . Field symbolic value See page .....

0 or 1 This function reads the DSPINT bit from the HPIC register. none DSPINT Returns the value of the DSPINT bit.3 Functions HPI_getDspint Function Arguments Return Value Description Example Reads DSPINT bit from HPIC register Uint32 HPI_getDspint(). if (HPI_getDspint()) { } HPI_getEventId Function Arguments Return Value Description Example Obtains IRQ event associated with HPI device Uint32 HPI_getEventId(). HpiEventId = HPI_getEventId(). none Event ID Returns the IRQ event for the HPI device Use this function to obtain the IRQ event associated with the HPI device. HPI Module 12-5 . none FETCH Returns the value 0 (always read at 0) This function reads the FETCH flag from the HPIC register and returns its value.HPI_getDspint 12. flag = HPI_getFetch(). Currently this is IRQ_EVT_DSPINT. HPI_getFetch Function Arguments Return Value Description Example Reads FETCH flag from HPIC register and returns its value Uint32 HPI_getFetch().

none HINT Returns the value of the HINT bit.HPI_getHint HPI_getHint Function Arguments Return Value Description Example Returns value of HINT bit of HPIC register Uint32 HPI_getHint(). none HWOB Returns the value of the HWOB bit. addR = HPI_getReadAddr(). 12-6 . hrdy = HPI_getHrdy(). 0 or 1 This function returns the value of the HRDY bit of the HPIC register. 0 or 1 This function returns the value of the HWOB bit of the HPIC register. hint = HPI_getHint(). HPI_getReadAddr Returns the Read memory address (HPIAR C64x devices only) Function Arguments Return Value Description Example Uint32 HPI_getReadAddr(). hwob = HPI_getHwob(). none HPIAR Read Memory Address This function returns the read memory address set under the HPIAR register (supported by C64x devices only) Uint32 addR. 0 or 1 This function returns the value of the HINT bit of the HPIC register. HPI_getHrdy Function Arguments Return Value Description Example Returns value of HRDY bit of HPIC register Uint32 HPI_getHrdy(). HPI_getHwob Function Arguments Return Value Description Example Returns value of HWOB bit of HPIC register Uint32 HPI_getHwob(). none HRDY Returns the value of the HRDY bit.

HPI_setDspint(1). none HPIAW Write Memory Address This function returns the write memory address set under the HPIAW register (supported by C64x devices only) Uint32 addW. addW = HPI_getWriteAddr(). Val none This function writes the value to the DSPINT file of the HPIC register HPI_setDspint(0). HPI Module 12-7 Arguments Return Value Description Example Value to write to HINT: 0 or 1 .HPI_getWriteAddr HPI_getWriteAddr Returns the Write memory address (HPIAW C64x devices only) Function Arguments Return Value Description Example Uint32 HPI_getWriteAddr(). Arguments Return Value Description Example Value to write to DSPINT: 1 (writing 0 has no effect) HPI_setHint Function Writes value to HINT field of HPIC register void HPI_setHint( Uint32 Val ). HPI_setHint(1). HPI_setDspint Function Writes value to DSPINT field of HPIC register void HPI_setDspint( Uint32 Val ). Val none This function writes the value to the HINT file of the HPIC register HPI_setHint(0).

HPI_setReadAddr HPI_setReadAddr
Function

Sets the Read memory address (HPIAR C64x devices only)
void HPI_setReadAddr( Uint32 address; ); address none This function sets the read memory address in the HPIAR register (supported by C64x devices only)
Uint32 addR = 0x80000400; HPI_setReadAddr(addR);

Arguments Return Value Description Example

Read Memory Address to be set

HPI_setWriteAddr Sets the Write memory address (HPIAW C64x devices only)
Function void HPI_setWriteAddr( Uint32 address; ); address none This function sets the write memory address in the HPIAW register (supported by C64x devices only)
Uint32 addW = 0x80000000; HPI_setWriteAddr(addW);

Arguments Return Value Description Example

Write Memory Address to be set

HPI_SUPPORT
Constant Description Example

Compile-time constant
HPI_SUPPORT Compile time constant that has a value of 1 if the device supports the HPI module and 0 otherwise. You are not required to use this constant.
#if (HPI_SUPPORT) /* user HPI configuration / #endif

12-8

Chapter 13

I2C Module
This chapter describes the I2C module, lists the API functions and macros within the module, and provides an I2C API reference section.

Topic

Page

13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

13-1

Overview

13.1 Overview
The inter-integrated circuit (I2C) module provides an interface between a TMS320c6000 DSP and other devices compliant with Phillips Semiconductors Inter−IC bus (I2C−bus) Specification version 2.1 and connected by way of an I2C−bus. Refer to TMS320c6000 DSP Inter−Integrated Circuit (I2C) Module Reference Guide (SPRU175) for more details. Table 13−1 lists the configuration structure for use with the I2C functions. Table 13−2 lists the functions and constants available in the CSL I2C module.

Table 13−1. I2C Configuration Structures
Structure I2C_Config Purpose Structure used to configure an I2C interface See page ... 13-7

Table 13−2. I2C APIs
(a) Primary I2C Functions Syntax I2C_close I2C_config I2C_configArgs I2C_open I2C_reset I2C_resetAll I2C_sendStop I2C_start Type Description F F F F F F F F Closes a previously opened I2C device Configures an I2C using the configuration structure Configures an I2C using register values Opens an I2C device for use Resets an I2C device Resets all I2C device registers Generates a stop condition Generates a start condition See page ... 13-8 13-8 13-9 13-10 13-11 13-12 13-12 13-13

(b) Secondary I2C Functions and Constants Syntax I2C_bb I2C_getConfig I2C_getEventId I2C_getRcvAddr Type Description F F F F Returns the bus−busy status Reads the current I2C configuration values Obtains the event ID for the specified I2C devices Returns the data receive register address See page ... 13-13 13-14 13-14 13-15

13-2

Overview

Table 13−2. I2C APIs
Syntax I2C_getXmtAddr I2C_getPins † I2C_setPins † I2C_clearPins † I2C_getExtMode † I2C_setMstAck † I2C_setDxrCpy † I2C_intClear I2C_intClearAll I2C_intEvtDisable I2C_intEvtEnable I2C_OPEN_RESET I2C_outOfReset I2C_readByte I2C_rfull I2C_rrdy I2C_SUPPORT I2C_writeByte I2C_xempty I2C_xrdy Type Description F F F F F F F F F F F C F F F F C F F F Returns the data transmit register address Returns value of I2CPDIN register Sets value of I2CPDSET register Sets value of I2CPDCLR register Returns status of transmit data receive ready mode Sets the transmit data receive ready mode to MSTACK Sets the transmit data receive ready mode to DXRCPY Clears the highest priority interrupt flag Clears all interrupt flags Disables the specified I2C interrupt Enables the specified I2C interrupt I2C reset flag, used while opening De−asserts the I2C device from reset Performs an 8−bit data read Returns the overrun status of the receiver Returns the receive data ready interrupt flag value Compile time constant whose value is 1 if the device supports the I2C module Writes and 8−bit value to the I2C data transmit register Returns the transmitter underflow status Returns the data transmit ready status See page ... 13-15 13-23 13-23 13-24 13-24 13-25 13-25 13-16 13-16 13-17 13-18 13-18 13-19 13-19 13-20 13-20 13-19 13-21 13-21 13-22

Note: F = Function; C = Constant; † Only in C6410, C6413, and C6418 devices.

13.1.1 Using an I2C Device
To use an I2C device, the user must first open it and obtain a device handle using I2C_open(). Once opened, the device handle is used to call the other APIs.
I2C Module 13-3

Overview

The I2C device can be configured by passing an I2C_Config structure to I2C_config() or by passing register values to the I2C_configArgs() function. To assist in creating register values, the _RMK(make) macros construct register values based on field values. In addition, the symbol constants may be used for the field values. Once the I2C is used and is no longer needed, it should be closed by passing the corresponding handle to I2C_close().

13-4

Macros

13.2 Macros
There are two types of I2C macros: those that access registers and fields, and those that construct register and field values. Table 13−3 lists the I2C macros that access registers and fields, and Table 13−4 lists the I2C macros that construct register and field values. The macros themselves are found in Chapter 28, Using the HAL Macros. I2C macros are handle-based.

Table 13−3. I2C Macros that Access Registers and Fields
Macro I2C_ADDR(<REG>) I2C_RGET(<REG>) I2C_RSET(<REG>,x) I2C_FGET(<REG>,<FIELD>) I2C_FSET(<REG>,<FIELD>,fieldval) I2C_FSETS(<REG>,<FIELD>,<SYM>) I2C_RGETA(addr,<REG>) I2C_RSETA(addr,<REG>,x) I2C_FGETA(addr,<REG>,<FIELD>) I2C_FSETA(addr,<REG>,<FIELD>, fieldval) I2C_FSETSA(addr,<REG>,<FIELD>, <SYM>) I2C_ADDRH(h,<REG>) I2C_RGETH(h,<REG>) I2C_RSETH(h,<REG>,x) I2C_FGETH(h,<REG>,<FIELD>) I2C_FSETH(h,<REG>,<FIELD>, fieldval) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address Returns the address of a memory-mapped register for a given handle Returns the value of a register for a given handle Sets the register value to x for a given handle Returns the value of the field for a given handle Sets the field value to x for a given handle See page ... 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 28-12 28-19 28-21 28-14 28-16

I2C Module

13-5

Macros

Table 13−4. I2C Macros that Construct Register and Field Values
Macro I2C_<REG>_DEFAULT I2C_<REG>_RMK() I2C_<REG>_OF() I2C_<REG>_<FIELD>_DEFAULT I2C_FMK() I2C_FMKS() I2C_<REG>_<FIELD>_OF() I2C_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of ... Field default value Field make Field make symbolically Field value of ... Field symbolic value See page... 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24

13-6

I2C_Config

13.3 Configuration Structure

I2C_Config
Structure Members

Structure used to configure an I2C interface
I2C_Config; Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32

i2coar i2cimr i2cclkl i2cclkh i2ccnt i2csar i2cmdr i2cpsc i2cemdr† i2cpfunc† i2cpdir†

Own address register Interrupt mask register Clock control low register Clock control high register Data count register Slave address register Mode register Prescalar register Extended mode register Pin function register Pin direction register

Additional configuration entries for C6410, C6413, and C6418 devices.

Description

This is the configuration structure used to dynamically configure the I2C device. The user should create and initialize this structure before passing its address to the I2C_config() function.

I2C Module

13-7

I2C_close

13.4 Functions
13.4.1 Primary Functions I2C_close
Function

Closes a previously opened I2C device
void I2C_close( I2C_Handle hI2c ); hI2c none This function closes a previously opened I2C device. The following tasks are performed: 1) The I2C event is disabled and cleared. 2) The I2C registers are set to their default values
I2C_Handle hI2c; ... I2C_close(hI2c);

Arguments Return Value Description

Device handle; see I2C_open()

Example

I2C_config
Function

Configures I2C using the configuration structure
void I2C_config( I2C_Handle hI2c, I2C_Config *myConfig ); hI2c myConfig Device handle; see I2C_open() Pointer to an initialized configuration structure

Arguments

Return Value Description

none This function configures the I2C device using the configuration structure which contains members corresponding to each of the I2C registers. These values are directly written to the corresponding I2C device registers.
I2C_Handle hI2c I2C_Config myConfig ... I2C_config(hI2c,&myConfig);

Example

13-8

I2C_configArgs I2C_configArgs Configures I2C using register values
For C6410, C6413, and C6418 Function void I2C_configArgs( I2C_Handle hI2c Uint32 i2coar, Uint32 i2cimr, Uint32 i2cclkl, Uint32 i2cclkh, Uint32 i2ccnt, Uint32 i2csar, Uint32 i2cmdr, Uint32 i2cpsc Uint32 icemdr Uint32 i2cpfunc Uint32 i2cpdir ); hI2c i2coar i2cimr i2cclkl i2cclkh i2ccnt i2csar i2cmdr i2cpsc i2cemdr i2cpfunc i2cpdir none This function configures the I2C module using the register values passed in as arguments.
I2C_Handle hI2c; ... IRQ_configArgs(hI2c,0x10,0x00,0x08,0x10,0x05,0x10,0x6E0,0x19, 0x1, 0x2); I2C Module 13-9

Arguments

Device handle; see I2C_open() Own address register Interrupt mask register Clock control low register Clock control high register Data count register Slave address register Mode register Prescalar register Extended mode register Pin function register Pin direction register

Return Value Description

Example

I2C_open
For other devices Function void I2C_configArgs( I2C_Handle hI2c Uint32 i2coar, Uint32 i2cimr, Uint32 i2cclkl, Uint32 i2cclkh, Uint32 i2ccnt, Uint32 i2csar, Uint32 i2cmdr, Uint32 i2cpsc ); hI2c i2coar i2cimr i2cclkl i2cclkh i2ccnt i2csar i2cmdr i2cpsc none This function configures the I2C module using the register values passed in as arguments.
I2C_Handle hI2c; ... IRQ_configArgs(hI2c,0x10,0x00,0x08,0x10,0x05,0x10,0x6E0,0x19);

Arguments

Device handle; see I2C_open() Own address register Interrupt mask register Clock control low register Clock control high register Data count register Slave address register Mode register Prescalar register

Return Value Description Example

I2C_open
Function

Opens and I2C device for use
I2C_Handle I2C_open( Uint16 devNum Uint16 flags ); devNum flags Specifies the device to be opened Open flags
- I2C_OPEN_RESET: resets the I2C

Arguments

13-10

I2C_reset
Return Value I2C_Handle Device handle INV: open failed Description Before the I2C device can be used, it must be opened using this function. Once opened, it cannot be opened again until it is closed. (See I2C_close().) The return value is a unique device handle that is used in subsequent I2C API calls. If the open fails, ’INV’ is returned.
I2C_Handle hI2c; ... hI2c = I2C_open(OPEN_RESET);

Example

I2C_reset
Function

Resets an I2C device
void I2C_reset( I2C_Handle hI2c ); hI2c none This function resets the I2C device specified by the handle.
I2C_Handle hI2c; ... I2C_reset(hI2c);

Arguments Return Value Description Example

Device handle; see I2C_open()

I2C Module

13-11

I2C_resetAll I2C_resetAll
Function

Resets all I2C device registers
void I2C_resetAll( void ); none none This function resets all I2C device registers.
I2C_resetAll();

Arguments Return Value Description Example

I2C_sendStop
Function

Generates a stop condition
void I2C_sendStop( I2C_Handle hI2c ); hI2c none This function sets the STP bit in the I2CMDR register, which generates stop conditions.
I2C_Handle hI2c; ... I2C_sendStop(hI2c);

Arguments Return Value Description Example

Device handle; see I2C_open()

13-12

I2C_start I2C_start
Function

Generates a start condition
void I2C_start( I2C_Handle hI2c ); hI2c none This function sets the STP bit in the I2CMDR register, which generates data transmission/reception start condition. It is reset to ’0’ by the hardware after the start condition has been generated.
I2C_Handle hI2c; ... I2C_start(hI2c);

Arguments Return Value Description

Device handle; see I2C_open()

Example

13.4.2 Auxiliary Functions and Constants

I2C_bb
Function

Returns the bus−busy status
Uint32 I2C_bb( I2C_Handle hI2c ); hI2c Uint32 Device handle; see I2C_open() bus status
- 0 − free - 1 − busy

Arguments Return Value

Description Example

This function returns the state of the serial bus.
I2C_Handle hI2c; ... if(I2C_bb(hI2c)){ ... ; I2C Module 13-13

I2C_getConfig I2C_getConfig
Function

Reads the current I2C configuration values
void I2C_getConfig( I2C_Handle hI2c, I2C_Config *myConfig ); hI2c myConfig Device handle; see I2C_open() Pointer to the configuration structure

Arguments

Return Value Description Example

none This function gets the current I2C configuration values.
I2C_Handle hI2c; I2C_Config i2cCfg; ... I2C_getConfig(hI2c, &i2cCfg);

I2C_getEventId
Function

Obtains the event ID for the specified I2C device
Uint32 I2C_getEventId( I2C_Handle hI2c ); hI2c Uint32 Device handle; see I2C_open() Event ID

Arguments Return Value Description Example

This function returns the event ID of the interrupt associated with the I2C device.
I2C_Handle hI2c; Uint16 evt; ... evt = I2C_getEventId(hI2c); IRQ_enable(evt);

13-14

I2C_getRcvAddr I2C_getRcvAddr
Function

Returns data receive register address
Uint32 I2C_getRcvAddr( I2C_Handle hI2c ); hI2c Uint32 Device handle; see I2C_open() Data receive register address

Arguments Return Value Description Example

This function returns the data receive register address.
I2C_Handle hI2c; Uint32 val; ... val = I2C_getRcvAddr(hI2c);

I2C_getXmtAddr
Function

Returns the data transmit register address
Uint32 I2C_getXmtAddr( I2C_Handle hI2c ); hI2c Uint32 Device handle; see I2C_open() Data transmit register address

Arguments Return Value Description Example

This function returns the data transmit register address.
I2C_Handle hI2c; Uint32 val; ... val = I2C_getXmtAddr(hI2c);

I2C Module

13-15

I2C_intClear I2C_intClear
Function

Clears the highest priority interrupt flag
Uint32 I2C_intClear( I2C_Handle hI2c ); hI2c Uint32 Device handle; see I2C_open() Interrupt vector register content

Arguments Return Value Description

This function clears the interrupt flag. If there is more than one interrupt flag, it clears the highest priority flag and returns the content of the interrupt vector register (I2CIVR).
I2C_Handle hI2c; Uint32 val; ... val = I2C_intClear(hI2c);

Example

I2C_intClearAll
Function

Clears all interrupt flags
void I2C_intClearAll( I2C_Handle hI2c ); hI2c none This function clears all the interrupt flags.
I2C_Handle hI2c; Uint32 val; ... val = I2C_intClearAll(hI2c);

Arguments Return Value Description Example

Device handle; see I2C_open()

13-16

I2C_intEvtDisable I2C_intEvtDisable
Function

Disables the specified I2C interrupt
void I2C_intEvtDisable( I2C_Handle hI2c, Uint32 maskFlag ); hI2c maskFlag Device handle; see I2C_open() Interrupt mask

Arguments

Return Value Description

none This function disables the I2C interrupt specified by the maskFlag. maskFlag can be an OR−ed combination of one or more of the following: I2C_EVT_AL − Arbitration Lost Interrupt Enable I2C_EVT_NACK − No Acknowledgement Interrupt Enable I2C_EVT_ARDY − Register Access Ready Interrupt I2C_EVT_RRDY − Data Receive Ready Interrupt I2C_EVT_XRDY − Data Transmit Ready Interrupt

Example

I2C_Handle hI2c; Uint32 maskFlag = I2C_EVT_AL|I2C_EVT_RRDY; ... I2C_intEvtDisable(hI2c, maskFlag);

I2C Module

13-17

I2C_intEvtEnable I2C_intEvtEnable
Function

Enables the specified I2C interrupt
void I2C_intEvtEnable( I2C_Handle hI2c, Uint32 maskFlag ); hI2c maskFlag Device handle; see I2C_open() Interrupt mask

Arguments

Return Value Description

none This function enables the I2C interrupt specified by the maskFlag. maskFlag can be an OR−ed combination of one or more of the following: I2C_EVT_AL − Arbitration Lost Interrupt Enable I2C_EVT_NACK − No Acknowledgement Interrupt Enable I2C_EVT_ARDY − Register Access Ready Interrupt I2C_EVT_RRDY − Data Receive Ready Interrupt I2C_EVT_XRDY − Data Transmit Ready Interrupt

Example

I2C_Handle hI2c; Uint32 maskFlag = I2C_EVT_AL|I2C_EVT_RRDY; ... I2C_intEvtEnable(hI2c, maskFlag);

I2C_OPEN_RESET I2C reset flag, used while opening
Constant Description Example I2C_OPEN_RESET This flag is used while opening and I2C device. To open with reset, use I2C_OPEN_RESET. Otherwise, use 0. See I2C_open()

13-18

I2C_outOfReset I2C_outOfReset
Function

De−asserts the I2C device from reset
void I2C_outOfReset( I2C_Handle hI2c ); hI2c none I2C comes out out reset by setting the IRS field of the I2CMDR register.
I2C_Handle hI2c; ... I2C_outOfReset(hI2c);

Arguments Return Value Description Example

Device handle; see I2C_open()

I2C_SUPPORT
Constant Description

Compile time constant
I2C_SUPPORT Compile time constant that has a value of 1 if the device supports the I2C module and 0 otherwise. You are not required to use this constant. Currently, only the C6713 device supports this module.
#if (I2C_SUPPORT) /* user I2C configuration */ #endif

Example

I2C_readByte
Function

Performs an 8−bit data read
Uint8 I2C_readByte( I2C_Handle hI2c ); hI2c Uint8 Device handle; see I2C_open() Received data

Arguments Return Value Description

This function performs a direct 8−bit read from the data receive register (I2CDRR). This function does not check the receive ready status. To check the receive ready status, use I2C_rrdy().
I2C_Handle hI2c; Uint8 data; ... data = I2C_readByte(hI2c); I2C Module 13-19

Example

I2C_rfull I2C_rfull
Function

Returns the overrun status of the receiver
Uint32 I2C_rfull( I2C_Handle hI2c ); hI2c Uint32 Device handle; see I2C_open() Overrun status
- 0 − Normal - 1 − Overrun

Arguments Return Value

Description Example

This function returns the overrun status of the receive shift register. This field is cleared by reading the data receive register or resetting the I2C.
I2C_Handle hI2c; ... if(I2C_rfull(hI2c)){ ... }

I2C_rrdy
Function

Returns the receive data ready interrupt flag value
Uint32 I2C_rrdy( I2C_Handle hI2c ); hI2c Uint32 Device handle; see I2C_open() Interrupt flag value
- 0 − Receive Data Not Ready - 1 − Receive Data Ready

Arguments Return Value

Description Example

This function returns the receive data ready interrupt flag value. The bit is cleared to ’0’ when I2CDRR is read.
I2C_Handle hI2c; ... if(I2C_rrdy(hI2c)){ ... }

13-20

I2C_writeByte I2C_writeByte
Function

Writes an 8−bit value to the I2C data transmit register
void I2C_writeByte( I2C_Handle hI2c, Uint8 val ); hI2c val Device handle; see I2C_open() 8−bit data to send

Arguments

Return Value Description

none This function writes an 8−bit value to the I2C data transmit register. This function does not check the transfer ready status. To check the transfer ready status, use I2C_xrdy().
I2C_Handle hI2c; ... I2C_writeByte(hI2c, 0x34);

Example

I2C_xempty
Function

Returns the transmitter underflow status
Uint32 I2C_xempty( I2C_Handle hI2c ); hI2c Uint32 Device handle; see I2C_open() Underflow status
- 0 − Underflow

Arguments Return Value

Description Example

This function returns the transmitter underflow status. The value is ’0’ when underflow occurs.
I2C_Handle hI2c; ... if(I2C_xempty(hI2c)){ ... }

I2C Module

13-21

I2C_Handle hI2c... C6413 and C6418 The SDA and SCL pins of the I2C can be used for GPIO. .4.. hI2c Uint32 Device handle. see I2C_open() Interrupt flag value . Some DSPs may require pullups on the SDA and SCL pins in order to use GPIO mode. To use the GPIO mode of the I2C pins: .. } 13.3 Auxiliary Functions Defined for C6410. . Please refer to the device specific data manual to determine if this is the case for the DSP being used. if(I2C_xrdy(hI2c)){ .0 − Transmit Data Not Ready .Place the I2C in reset by setting IRS = ’0’ in I2CMDR. 13-22 .1 − Transmit Data Ready Arguments Return Value Description Example This function returns the transmit data ready interrupt flag value.Enable GPIO mode by setting GPMODE = ’1’ in I2CPFUNC.I2C_xrdy I2C_xrdy Function Returns the data transmit ready status Uint32 I2C_xrdy( I2C_Handle hI2c ).

Uint32 pinStatus..0x3). Return Value Description Example I2C Module 13-23 . A value of 1 indicates that the logic level corresponding to HIGH is present on the SDA pin.. A write of 0 has no effect.. This drives the SDA and SCL pins HIGH. Uint32 Value of I2CPDIN register Indicates the logic level present on the SDA and SCL pins. I2C_Handle hI2C. When 1 is written to either of these bits. None This bit sets the value of the I2CPDOUT by setting the SDAOUT and SCLOUT bits of the I2CPDSET register. If a value of 0 is read for SDAIN. I2C_Handle hI2C.I2C_getPins I2C_getPins Function Returns value of I2CPDIN register Uint32 I2C_getPins( I2C_Handle hI2C ). it indicates that the logic level corresponding to LOW is present on the SDA pin. Uint32 pins ).. I2C_setPins(hI2C. . the corresponding bit in I2COUT is set to 1. The SCLIN similarly indicates the status of the SCL pin. pinStatus = I2C_getPins(hI2C): Return Value Description Example I2C_setPins Function Sets value of SDA and SCL pins when they are configured as output void I2C_setPins( I2C_Handle hI2C. .

I2C_Handle hI2C. Return Value Description Example I2C_getExtMode Function Returns status of transmit data receive ready mode Uint32 I2C_getExtMode( I2C_Handle hI2C ). This has an effect only when the I2C is operating as a slave-transmitter. Return Value Description The XRDYM bit of the I2CEMDR register determines which condition generates a transmit-data-receive interrupt.0x3). Example 13-24 . Uint32 pins ). Uint32 Returns status of transmit data receive ready mode. A write of 0 has no effect. Uint32 emdrStat. . This drives the SDA and SCL pins LOW.I2C_clearPins I2C_clearPins Function Clears the value of SDA and SCL pins where they are configured as output void I2C_clearPins( I2C_Handle hI2C. emdrStat = I2C_getExtMode(hI2C). I2C_Handle hI2C. .. A value of 0 indicates that the transmit-data-ready interrupt is generated when the master requests more data by sending an acknowledge signal after the transmission of the last data. None This bit sets the value of the I2CPDOUT by setting the SDAOUT and SCLOUT bits of the I2CPDCLR register. When 1 is written to either of these bits. the corresponding bit in I2COUT is cleared to 0.. I2C_clearPins(hI2C...

). None The XRDYM bit of the I2CEMDR register determines which condition generates a transmit-data-receive interrupt. This function sets the transmit-data-ready interrupt to be generated when the master requests more data by sending an acknowledge signal after the transmission of the last data. This has an effect only when the I2C is operating as a slave-transmitter. ). Return Value Description I2C_setDxrCpy Function Sets the transmit data receive ready mode to MSTACK void I2C_setDxrCpy( I2C_Handle hI2C. This has an effect only when the I2C is operating as a slave-transmitter. This function sets the transmit-data-ready interrupt to be generated when the data in I2CDXR is copied to the I2CXSR.I2C_setMstAck I2C_setMstAck Function Sets the transmit data receive ready mode to MSTACK void I2C_setMstAck( I2C_Handle hI2C. Return Value Description I2C Module 13-25 . None The XRDYM bit of the I2CEMDR register determines which condition generates a transmit-data-receive interrupt.

. . . . . . . .3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14-1 . . . . . . 14-6 14. . . . . . . . . . . . . . . . and provides an IRQ API reference section. . . . .2 Macros . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . . . 14-2 14. . . . . . . . . . . . . . . . . . 14-4 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Overview . . . . . . . . .4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Chapter 14 IRQ Module This chapter describes the IRQ module. . . . . . . Topic Page 14. . . . . . . . . . . .

Table 14−1 lists the configuration structure for use with the IRQ functions.. 14-6 Table 14−2.. Table 14−2 lists the functions and constants available in the CSL IRQ module. IRQ APIs (a) Primary IRQ Functions Syntax IRQ_clear IRQ_config IRQ_configArgs IRQ_disable IRQ_enable IRQ_globalDisable IRQ_globalEnable IRQ_globalRestore IRQ_reset IRQ_restore IRQ_setVecs IRQ_test Type Description F F F F F F F F F F F F Clears the event flag from the IFR register Dynamically configures an entry in the interrupt dispatcher table Dynamically configures an entry in the interrupt dispatcher table Disables the specified event Enables the specified event Globally disables interrupts Globally enables interrupts Restores the global interrupt enable state Resets an event by disabling and then clearing it Restores an event enable state Sets the base address of the interrupt vectors Allows testing of an event to see if its flag is set in the IFR register See page ..1 Overview The IRQ module is used to manage CPU interrupts.. IRQ Configuration Structure Structure IRQ_Config Purpose Interrupt dispatcher configuration structure See page . Table 14−1.Overview 14. 14-9 14-9 14-10 14-11 14-11 14-12 14-12 14-12 14-13 14-13 14-14 14-14 14-2 .

IRQ Module 14-3 .Overview Table 14−2. IRQ APIs (Continued) Syntax (b) Auxiliary IRQ Functions IRQ_EVT_NNNN IRQ_getArg IRQ_getConfig IRQ_map IRQ_nmiDisable IRQ_nmiEnable IRQ_resetAll IRQ_set IRQ_setArg IRQ_SUPPORT C F F F F F F F F C These are the IRQ events Reads the user-defined interrupt service routine argument Returns the current IRQ set-up using configuration structure Maps an event to a physical interrupt number by configuring the interrupt selector MUX registers Disables the nmi interrupt event Enables the nmi interrupt event Resets all interrupt events by setting the GIE bit to 0 and then disabling and clearing them Sets specified event by writing to appropriate ISR register Sets the user-defined interrupt service routine argument A compile time constant whose value is 1 if the device supports the IRQ module 14-15 14-17 14-18 14-19 14-19 14-19 14-20 14-20 14-21 14-21 Type Description See page .. Note: F = Function.. C = Constant.

<REG>.2 Macros There are two types of IRQ macros: those that access registers and fields. and Table 14−4 lists the IRQ macros that construct register and field values.<FIELD>. The macros themselves are found in Chapter 28.fieldval) IRQ_FSETS(<REG>..<REG>.x) IRQ_FGETA(addr. IRQ macros are not handle-based.<FIELD>) IRQ_FSET(<REG>.<FIELD>) IRQ_FSETA(addr.Macros 14.<FIELD>.x) IRQ_FGET(<REG>. Table 14−3 lists the IRQ macros that access registers and fields. and those that construct register and field values..<REG>.<FIELD>. IRQ Macros that Access Registers and Fields Macro IRQ_ADDR(<REG>) IRQ_RGET(<REG>) IRQ_RSET(<REG>. Table 14−3. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page .<REG>.<FIELD>.<REG>) IRQ_RSETA(addr. Using the HAL Macros. fieldval) IRQ_FSETSA(addr. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 14-4 .<SYM>) IRQ_RGETA(addr.

.... IRQ Macros that Construct Register and Field Values Macro IRQ_<REG>_DEFAULT IRQ_<REG>_RMK() IRQ_<REG>_OF() IRQ_<REG>_<FIELD>_DEFAULT IRQ_FMK() IRQ_FMKS() IRQ_<REG>_<FIELD>_OF() IRQ_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of . 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 IRQ Module 14-5 .. Field default value Field make Field make symbolically Field value of . Field symbolic value See page..Macros Table 14−4.

Members funcArg – user defined argument eventId – the ID of the event that caused the interrupt funcArg This is an arbitrary user-defined argument that gets passed to the interrupt service routine. The following list shows valid values for ccMask: (a) IRQ_CCMASK_NONE (b) IRQ_CCMASK_DEFAULT 14-6 ccMask . the cache settings are restored back to their original state.IRQ_Config 14. This function must be C-callable and must NOT be declared using the interrupt keyword. Uint32 funcArg. Cache control mask: determines how the DSP/BIOS dispatcher handles the cache settings when calling an interrupt service routine (ISR). This argument is also accessible using IRQ_getArg() and IRQ_setArg(). the dispatcher modifies the cache settings based on this argument before calling the ISR. The prototype has the form: void myIsr( Uint32 funcArg. Uint32 ccMask.3 Configuration Structure IRQ_Config Structure Interrupt dispatcher configuration structure typedef struct { void *funcAddr. Then when the ISR exits and control is returned back to the dispatcher. Uint32 ieMask. When an interrupt occurs and that event is being handled by the dispatcher. funcAddr This is the address of the interrupt service routine to be called when the interrupt happens. This is useful when the application code wants to pass information to an ISR without using global variables. } IRQ_Config. Uint32 eventId ).

IRQ_IEMASK_SELF . The DSP/BIOS interrupt dispatcher allows nested interrupts such that interrupts of higher priority may preempt those of lower priority (priority here is determined by hardware). If neither (a) nor (b) is used. the dispatcher restores IER back to its original state. likewise for (b). In other words.IRQ_Config (c) (d) (e) (f) (g) (h) (i) (j) IRQ_CCMASK_PCC_MAPPED IRQ_CCMASK_PCC_ENABLE IRQ_CCMASK_PCC_FREEZE IRQ_CCMASK_PCC_BYPASS IRQ_CCMASK_DCC_MAPPED IRQ_CCMASK_DCC_ENABLE IRQ_CCMASK_DCC_FREEZE IRQ_CCMASK_DCC_BYPASS Only certain combinations of the above values are valid: (a) and (b) are mutually exclusive with all others. IRQ_CCMASK_DEFAULT has the same meaning.IRQ_IEMASK_DEFAULT Use IRQ_IEMASK_ALL to mask out all interrupts including self. A “1” bit in ieMask means disable the corresponding interrupt. The user may specify a numeric value for the mask or use one of the following predefined symbols: . IRQ_CCMASK_NONE means do not touch the cache at all. Each bit in ieMask corresponds to bits in the interrupt enable register (IER). choose one value for the PCC control and one value for the DCC control. IRQ Module 14-7 .IRQ_IEMASK_ALL . This means that if (a) is used. then one value from (c) through (f) bitwise OR’ed with a value from (g) through (j) may be used. it is used by itself. The ieMask argument determines which interrupts to mask out during processing. It is possible to use a PCC value without a DCC value and vise-versa. ieMask Interrupt enable mask: determines how interrupts are masked during the processing of the event. When processing the interrupt service routine is complete.

IRQ_configArgs(). IRQ_config(eventId. Example 1 IRQ_Config myConfig = { myIsr.&myConfig).. .. and IRQ_getConfig(). . Uint32 eventId) { .. 0x00000000..&myConfig). 0x00000000.. The DSP/BIOS dispatcher uses a lookup table to gather information for each interrupt. IRQ_IEMASK_DEFAULT }. } Example 2 14-8 . These functions allow the user to dynamically hook new interrupt service routines at runtime... The interrupt dispatcher may be statically configured using the configuration tool and also dynamically configured using the CSL functions IRQ_config(). } IRQ_Config myConfig = { myIsr. Uint32 eventId) { . void myIsr(Uint32 funcArg. . IRQ_config(eventId. Description This is the configuration structure used to dynamically configure the DSP/BIOS interrupt dispatcher... . Each entry of this built-in table contains the same members as this configuration structure.. IRQ_CCMASK_DEFAULT. or use the default which is the same as IRQ_IEMASK_SELF. void myIsr(Uint32 funcArg. IRQ_IEMASK_ALL }. Calling IRQ_config() simply copies the configuration structure members into the appropriate locations in the dispatch table. IRQ_CCMASK_PCC_ENABLE | IRQ_CCMASK_DCC_MAPPED..IRQ_Config use IRQ_IEMASK_SELF to mask self (prevent an ISR from preempting itself)..

4. See IRQ_Config for a complete description of this structure.cdb must be defined. Arguments Return Value Description none This function dynamically configures an entry in the interrupt dispatcher table with the information contained in the configuration structure. IRQ_clear(IRQ_EVT_TINT0). If the event is not mapped to an interrupt. See IRQ_EVT_NNNN for a complete list of events. To use this function. Pointer to a configuration structure that contains the new configuration information.IRQ_clear 14. IRQ_config Function Dynamically configures an entry in the interrupt dispatcher table void IRQ_config( Uint32 eventId. eventId none Clears the event flag from the interrupt flag register (IFR). See IRQ_EVT_NNNN for a complete list of events. Arguments Return Value Description Example Event ID. a DSP/BIOS configuration .1 Primary IRQ Functions IRQ_clear Function Clears event flag void IRQ_clear( Uint32 eventId ). then no action is taken. eventId config Event ID. IRQ_Config *config ).4 Functions 14. Two constraints must be met before this function has any effect: 1) The event must be mapped to an interrupt 2) The interrupt this event is mapped to must be using the dispatcher IRQ Module 14-9 .

Uint32 ieMask ). Example IRQ_Config myConfig = { myIsr. See the IRQ_Config structure definition for more details. Uint32 funcArg. It does the same thing as IRQ_config() except this function takes the information as arguments rather than passed in a configuration structure. See IRQ_EVT_NNNN for a complete list of events. Interrupt enable mask. IRQ_configArgs Function Dynamically configures an entry in the interrupt dispatcher table void IRQ_configArgs( Uint32 eventId. Arguments funcArg ccMask ieMask Return Value Description none This function dynamically configures an entry in the interrupt dispatcher table. eventId funcAddr Event ID. void *funcAddr.. IRQ_config(eventId. Cache control mask. This function dynamically configures an entry in the interrupt dispatcher table with the information passed in the arguments.. Argument that gets passed to the interrupt service routine See the IRQ_Config structure definition for more details. 0x00000000.&myConfig). 14-10 . . Uint32 ccMask. this function will have no effect. See the IRQ_Config structure definition for more details. IRQ_IEMASK_DEFAULT }. Address of the interrupt service routine.IRQ_configArgs If either of the above two conditions are not met. IRQ_CCMASK_DEFAULT. See the IRQ_Config structure definition for more details.

IRQ_CCMASK_DEFAULT. IRQ_disable(IRQ_EVT_TINT0). Two constraints must be met before this function has any effect: 1) The event must be mapped to an interrupt 2) The interrupt this event is mapped to must be using the dispatcher If either of the above two conditions are not met. this function will have no effect.IRQ_disable To use this function. Arguments Return Value Description Disables the interrupt associated with the specified event by modifying the interrupt enable register (IER). If the event is not mapped to an interrupt. IRQ_disable Function Disables specified event Uint32 IRQ_disable( Uint32 eventId ). IRQ_IEMASK_DEFAULT ). myIsr. Example IRQ_enable Function Enables specified event void IRQ_enable( Uint32 eventId ).cdb must be defined. Example IRQ_configArgs( eventId. then no action is taken. . eventId none IRQ Module 14-11 Arguments Return Value Event ID. a DSP/BIOS configuration . Use with IRQ_restore(). See IRQ_EVT_NNNN for a complete list of events. See IRQ_EVT_NNNN for a complete list of events. 0x00000000. Returns the old event state. eventId state Event ID.

See also IRQ_globalDisable(). gie Value to restore the global interrupt enable to. then restoring them back. none gie Returns the old GIE value This function globally disables interrupts by clearing the GIE bit of the CSR register. This is useful for temporarily disabling global interrupts. gie = IRQ_globalDisable(). IRQ_globalEnable(). Uint32 gie. none none This function globally enables interrupts by setting the GIE bit of the CSR register to 1. The old value of GIE is returned. IRQ_enable(IRQ_EVT_TINT0).IRQ_globalDisable Description Example Enables the event by modifying the interrupt enable register (IER). If the event is not mapped to an interrupt.. 1=enable) Arguments 14-12 . Example IRQ_globalRestore Function Restores the global interrupt enable state void IRQ_globalRestore( Uint32 gie ). (0=disable. IRQ_globalRestore(gie). IRQ_enable(IRQ_EVT_TINT1).. Example IRQ_globalEnable Globally enables interrupts Function Arguments Return Value Description void IRQ_globalEnable(). then no action is taken. .This function must be called if the GIE bit is not set before enabling an interrupt event. IRQ_globalDisable Globally disables interrupts Function Arguments Return Value Description Uint32 IRQ_globalDisable().

IRQ Module 14-13 . eventId ie Event ID. 1=enable). . . ie = IRQ_disable(eventId). Uint32 ie. Arguments Return Value Description Example Event ID. Uint32 gie. IRQ_restore(ie). See IRQ_EVT_NNNN for a complete list of events. IRQ_restore Function Restores an event-enable state void IRQ_restore( Uint32 eventId. This is useful for temporarily disabling an event. See IRQ_EVT_NNNN for a complete list of events. IRQ_reset(eventId). eventId = DMA_getEventId(hDma).. This is useful for temporarily disabling global interrupts. State to restore the event to (0=disable. then restoring them back. Arguments Return Value Description Example none This function restores the enable state of the event to the value passed in.IRQ_reset Return Value Description none This function restores the global interrupt enable state to the value passed in by writing to the GIE bit of the CSR register.. IRQ_globalRestore(gie).. then restoring it back. gie = IRQ_globalDisable().. Uint32 ie ). Example IRQ_reset Function Resets an event by disabling then clearing it void IRQ_reset( Uint32 eventId ). eventId none This function serves as a shortcut method of performing IRQ_disable(eventId) followed by IRQ_clear(eventId).

IRQ_test Function Allows testing event to see if its flag is set in IFR register Uint IRQ_test( Uint32 eventId ). eventId flag Event ID. Returns event flag. CAUTION: Changing the interrupt vector table base can have adverse effects on your system because you will be effectively eliminating all interrupt settings that were there previously. Example IRQ_setVecs((void*)0x800000000). while (!IRQ_test(IRQ_EVT_TINT0)). Example 14-14 . See IRQ_EVT_NNNN for a complete list of events. The DSP/BIOS kernel and RTDX will more than likely fail if care is not taken when using this function. 0 or 1 Arguments Return Value Description Use this function to test an event to see if its flag is set in the interrupt flag register (IFR). then no action is taken and this function returns 0. If the event is not mapped to an interrupt. vecs oldVecs Pointer to the interrupt vector table Returns a pointer to the old vector table Arguments Return Value Description Use this function to set the base address of the interrupt vector table.IRQ_setVecs IRQ_setVecs Function Sets the base address of the interrupt vectors void *IRQ_setVecs( void *vecs ).

4.IRQ_EVT_NNNN 14.2 Auxiliary IRQ Functions and Constants IRQ events (For C6410. DM641 and DM640) IRQ_EVT_DSPINT IRQ_EVT_TINT0 IRQ_EVT_TINT1 IRQ_EVT_SDINTA IRQ_EVT_EXTINT4 IRQ Module 14-15 IRQ_EVT_NNNN Constant . C6413 and C6418 devices) IRQ_EVT_DSPINT IRQ_EVT_TINT0 IRQ_EVT_TINT1 IRQ_EVT_SDINTA IRQ_EVT_EXTINT4 IRQ_EVT_GPINT4 IRQ_EVT_EXTINT5 IRQ_EVT_GPINT5 IRQ_EVT_EXTINT6 IRQ_EVT_GPINT6 IRQ_EVT_EXTINT7 IRQ_EVT_GPINT7 IRQ_EVT_EDMAINT IRQ_EVT_EMUDTDMA IRQ_EVT_EMURTDXRX IRQ_EVT_EMURTDXTX IRQ_EVT_XINT0 IRQ_EVT_RINT0 IRQ_EVT_XINT1 IRQ_EVT_RINT1 IRQ_EVT_GPINT0 IRQ_EVT_TINT2 IRQ_EVT_I2CINT0 IRQ_EVT_I2CINT1 IRQ_EVT_AXINT1 IRQ_EVT_ARINT1 IRQ_EVT_AXINT0 IRQ_EVT_ARINT0 IRQ_EVT_VCPINT# #Defined only for C6418 (For DM642.

IRQ_EVT_NNNN IRQ_EVT_GPINT4 IRQ_EVT_EXTINT5 IRQ_EVT_GPINT5 IRQ_EVT_EXTINT6 IRQ_EVT_GPINT6 IRQ_EVT_EXTINT7 IRQ_EVT_GPINT7 IRQ_EVT_EDMAINT IRQ_EVT_EMUDTDMA IRQ_EVT_EMURTDXRX IRQ_EVT_EMURTDXTX IRQ_EVT_XINT0 IRQ_EVT_RINT0 IRQ_EVT_XINT1 IRQ_EVT_RINT1 IRQ_EVT_GPINT0 IRQ_EVT_TINT2 IRQ_EVT_I2CINT0 IRQ_EVT_MACINT IRQ_EVT_VINT0 IRQ_EVT_VINT1 IRQ_EVT_VINT2# # Only for DM642 IRQ_EVT_AXINT0 IRQ_EVT_ARINT0 (For other devices) IRQ_EVT_DSPINT IRQ_EVT_TINT0 IRQ_EVT_TINT1 IRQ_EVT_TINT2 C64x only IRQ_EVT_SDINT IRQ_EVT_SDINTA C64x only IRQ_EVT_SDINTB C64x only IRQ_EVT_GPINT0 C64x only IRQ_EVT_GPINT4 C64x only IRQ_EVT_GPINT5 C64x only IRQ_EVT_GPINT6 C64x only IRQ_EVT_GPINT7 C64x only IRQ_EVT_EXTINT4 IRQ_EVT_EXTINT5 IRQ_EVT_EXTINT6 IRQ_EVT_EXTINT7 14-16 .

IRQ_getArg Function Reads the user defined interrupt service routine argument Uint32 IRQ_getArg( Uint32 eventId ). For more details.IRQ_getArg IRQ_EVT_DMAINT0 IRQ_EVT_DMAINT1 IRQ_EVT_DMAINT2 IRQ_EVT_DMAINT3 IRQ_EVT_EDMAINT IRQ_EVT_XINT0 IRQ_EVT_RINT0 IRQ_EVT_XINT1 IRQ_EVT_RINT1 IRQ_EVT_XINT2 IRQ_EVT_RINT2 IRQ_EVT_PCIWAKE IRQ_EVT_UINTC64x only Description These are the IRQ events. Two constraints must be met before this function has any effect: 1) The event must be mapped to an interrupt 2) The interrupt this event is mapped to must be using the dispatcher If either of the above two conditions are not met. Refer to the TMS320C6000 Peripherals Reference Guide (SPRU190) for more details regarding these events. this function will have no effect. Example Uint32 a = IRQ_getArg(eventId). Arguments Return Value Description This function reads the user defined argument from the interrupt dispatcher table and returns it to the user. eventId funcArg Event ID. IRQ Module 14-17 . Current value of the interrupt service routine argument. see the IRQ_Config structure definition. See IRQ_EVT_NNNN for a complete list of events.

eventId config Event ID. . 2) The interrupt this event is mapped to must be using the dispatcher. this function will have no effect. Two constraints must be met before this function has any effect: 1) The event must be mapped to an interrupt.&myConfig). See IRQ_EVT_NNNN for a complete list of events. IRQ_Config *config ). 14-18 . See IRQ_Config for a complete description of this structure. Example IRQ_Config myConfig.. If either of the above two conditions are not met.. Pointer to a configuration structure that will be filled in with information from the dispatcher table. Arguments Return Value Description none This function reads information from the interrupt dispatcher table and stores it in the configuration structure. IRQ_getConfig(eventId.IRQ_getConfig IRQ_getConfig Function Returns the current IRQ set-up using configuration structure void IRQ_getConfig( Uint32 eventId.

Note: When using the DSP/BIOS tool. IRQ_nmiDisable(). IRQ_nmiEnable Function Arguments Return Value Description Enables the NMI interrupt event void IRQ_nmiEnable(). none none This function disables the NMI interrupt by setting the corresponding bit in IER register to 0. none none This function enables the NMI interrupt by setting the corresponding bit in IER register to 1.IRQ_map IRQ_map Function Maps event to physical interrupt number void IRQ_map( Uint32 eventId. Example IRQ_nmiDisable Function Arguments Return Value Description Example Disables the NMI interrupt event void IRQ_nmiDisable(). the default map is sufficient and does not need to be changed. int intNumber ). See IRQ_EVT_NNNN for a complete list of events. For most cases. Arguments intNumber Interrupt number. IRQ_map(IRQ_EVT_TINT0.12). eventId Event ID. IRQ Module 14-19 Example . NMIE interrupt is enabled automatically. IRQ_nmiEnable(). 4 to 15 Return Value Description none This function maps an event to a physical interrupt number by configuring the interrupt selector MUX registers.

IRQ_resetAll(). Example 14-20 . eventId none Sets the specified event by writing to the appropriate bit in the interrupt set register (ISR). respectively.IRQ_resetAll IRQ_resetAll Function Arguments Return Value Description Resets all interrupts events supported by the chip device void IRQ_resetAll(). See IRQ_EVT_NNNN for a complete list of events. If the event is not mapped to an interrupt. Arguments Return Value Description Event ID. This basically allows software triggering of events. Example IRQ_set Function Sets specified event by writing to appropriate ISR register void IRQ_set( Uint32 eventId ). then no action is taken. none none Resets all the interrupt events supported by the chip device by disabling the global interrupt enable bit (GIE) and then disabling and clearing all the interrupt bits of IER and IFR. IRQ_set(IRQ_EVT_TINT0).

eventId funcArg Event ID. this function will have no effect. See the IRQ_Config structure definition for more details. Currently. Arguments Return Value Description none This function sets the user-defined argument in the interrupt dispatcher table. Example IRQ_setArg(eventId. #if (IRQ_SUPPORT) /* user IRQ configuration */ #endif Example IRQ Module 14-21 .0x12345678). You are not required to use this constant. See IRQ_EVT_NNNN for a complete list of events. New value for the interrupt service routine argument.IRQ_setArg IRQ_setArg Function Sets the user-defined interrupt service routine argument void IRQ_setArg( Uint32 eventId. all devices support this module. IRQ_SUPPORT Constant Description Compile time constant IRQ_SUPPORT Compile time constant that has a value of 1 if the device supports the IRQ module and 0 otherwise. Two constraints must be met before this function has any effect: 1) The event must be mapped to an interrupt 2) The interrupt this event is mapped to must be using the dispatcher If either of the above two conditions are not met. Uint32 funcArg ).

IRQ_SUPPORT 14-22 .

. . . . . . . . and provides a McASP API reference section. . . . . . . . . . . . . . discusses using a McASP device. . . . . . Topic Page 15. . . . . . . . . . . . . . . . . . . 15-10 15-1 . . . . . . . .2 Macros . . . . . . . . . . . . . . . . . . . . 15-7 15. 15-2 15. lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15. . . . . . . . . . . . . . . .1 Overview . . . . . . . . . . . . . . .4 Functions . . . . .Chapter 15 McASP Module This chapter describes the McASP module. . . . . . . . . . .

. Table 15−1 lists the configuration structure for use with the McASP functions. Table 15−2 lists the functions and constants available in the CSL McASP module. McASP Configuration Structures Syntax MCASP_Config MCASP_ConfigGbl MCASP_ConfigRcv MCASP_ConfigSrctl MCASP_ConfigXmt Type Description S S S S S Used to configure a McASP device Used to configure McASP global receive registers Used to configure McASP receive registers Used to configure McASP serial control Used to configure McASP transmit registers See page . McASP APIs (a) Primary Functions Syntax MCASP_close MCASP_config MCASP_open MCASP_read32 MCASP_reset MCASP_write32 Type Description F F F F F F Closes a McASP device previously opened via MCASP_open() Configures the McASP device using the configuration structure Opens a McASP device for use Reads data when the receiver is configured to receive from the data bus Resets McASP registers to their default values Writes data when the transmitter is configured to transmit by the data bus See page . Table 15−1.. 15-10 15-10 15-11 15-12 15-12 15-13 (b) Parameters and Constants Syntax MCASP_DEVICE_CNT MCASP_OPEN_RESET Note: Type Description C C McASP device count McASP open reset flag See page .1 Overview The McASP module contains a set of API functions for configuring the McASP registers. T = Typedef. C = Constant 15-2 .Overview 15. F = Function... 15-7 15-7 15-8 15-8 15-9 Table 15−2... 15-14 15-14 S = Structure.

C = Constant McASP Module 15-3 . XTDM. depending on direction Enables transmit or receive serializers. F = Function.. depending on direction Enables frame sync if receiver has internal frame sync Wakes up transmit and or receive high clock. McASP APIs (Continued) Syntax MCASP_SetupClk MCASP_SetupFormat MCASP_SetupFsync MCASP_SetupHclk MCASP_SUPPORT Type Description T T T T C Parameters for McASP transmit and receive clock registers Parameters for data stream format: XFMT−RFMT Parameters for frame synchronization control: AFSXCTL−AFSRCTL Parameters for McASP transmit and receive high registers Compile time constant whose value is 1 if the device supports the McASP module See page . depending on direction Wakes up transmit and or receive state machine.. 15-14 15-15 15-16 15-16 15-17 (c)Auxiliary Functions Syntax MCASP_clearPins MCASP_configDit MCASP_configGbl MCASP_configRcv MCASP_configSrctl MCASP_configXmt MCASP_enableClk MCASP_enableFsync MCASP_enableHclk MCASP_enableSers MCASP_enableSm MCASP_getConfig MCASP_getGblctl Note: Type Description F F F F F F F F F F F F F Clears pins which are enabled as GPIO and output Configures XMASK.Overview Table 15−2. and AFSXCTL registers for DIT transmission Configures McASP device global registers Configures McASP device receive registers Configures McASP device serial control registers Configures McASP device transmit registers Wakes up transmit and/or receive clock. T = Typedef.. depending on direction Reads the current McASP configuration values Reads the GBLCTL register.. depending on direction See page . 15-17 15-18 15-18 15-19 15-19 15-20 15-20 15-21 15-22 15-23 15-24 15-25 15-25 S = Structure.

.1 Using a McASP Device To use a McASP device. 15-4 . The McASP device can be configured by passing a MCASP_Config structure to MCASP_config(). McASP APIs (Continued) Syntax MCASP_read32Cfg MCASP_resetRcv MCASP_resetXmt MCASP_setPins MCASP_setupClk MCASP_setupFormat MCASP_setupFsync MCASP_setupHclk MCASP_write32Cfg (c) Interrupt Control Functions Syntax MCASP_getRcvEventId MCASP_getXmtEventId Note: Type Description F F F F F F F F F Reads the data from rbufNum Resets the receiver fields in the Global Control register Resets the transmitter fields in the Global Control register Sets pins which are enabled as GPIO and output Sets up McASP transmit and receive clock registers Sets up McASP transmit and receive format registers Sets up McASP transmit and receive frame sync registers Sets up McASP transmit and receive high clock registers Writes the val into rbufNum See page . it should be closed by passing the corresponding handle to MCASP_close(). Once opened. F = Function.. the device handle should then be passed to other APIs along with other arguments.1.Overview Table 15−2. T = Typedef. C = Constant 15. Once the McASP device is no longer needed. the MCASP_RMK (make) macros construct register values based on field values.. the user must first open it and obtain a device handle using MCASP_open(). 15-26 15-26 15-27 15-27 15-28 15-28 15-29 15-29 15-30 Type Description F F Retrieves the receive event ID for the given device Retrieves the transmit event ID for the given device See page . 15-30 15-31 S = Structure.. To assist in creating register values.

<REG>.x) MCASP_FGETH(h.<REG>.<REG>.<FIELD>) MCASP_FSET(<REG>.Macros 15. and those that construct register and field values.<FIELD>. Table 15−3.<REG>. Table 15−3 lists the McASP macros that access registers and fields.<FIELD>.<REG>) MCASP_RSETH(h. Using the HAL Macros.fieldval) MCASP_FSETS(<REG>. The macros themselves are found in Chapter 28.x) MCASP_FGET(<REG>. McASP Macros that Access Registers and Fields Macro MCASP_ADDR(<REG>) MCASP_RGET(<REG>) MCASP_RSET(<REG>.2 Macros There are two types of McASP macros: those that access registers and fields.<REG>.<FIELD>.<REG>) MCASP_RGETH(h.<FIELD>.<REG>. fieldval) MCASP_FSETSA(addr.<FIELD>.<REG>) MCASP_RSETA(addr.<REG>.. and Table 15−4 lists the McASP macros that construct register and field values. fieldval) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address Returns the address of a memory-mapped register for a given handle Returns the value of a register for a given handle Sets the register value to x for a given handle Returns the value of the field for a given handle Sets the field value to x for a given handle See page . 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 28-12 28-19 28-21 28-14 28-16 McASP Module 15-5 .x) MCASP_FGETA(addr. <SYM>) MCASP_RGETA(addr.<FIELD>) MCASP_FSETH(h. <SYM>) MCASP_ADDRH(h. The McASP module includes handle-based macros..<FIELD>) MCASP_FSETA(addr.

28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 15-6 ....Macros Table 15−4. Field default value Field make Field make symbolically Field value of .. McASP Macros that Construct Register and Field Values Macro MCASP_<REG>_DEFAULT MCASP_<REG>_RMK() MCASP_<REG>_OF() MCASP_<REG>_<FIELD>_DEFAULT MCASP_FMK() MCASP_FMKS() MCASP_<REG>_<FIELD>_OF() MCASP_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of . Field symbolic value See page ...

The user can create and initialize this structure and then pass its address to the MCASP_config() function. Specifies the direction of pins as input/output.3 Configuration Structure MCASP_Config Structure Members Structure used to configure a McASP device MCASP_Config MCASP_ConfigGbl MCASP_ConfigRcv MCASP_ConfigXmt MCASP_ConfigSrctl *global *receive *transmit *srctl Global registers Receive registers Transmit registers Serial control registers Description This is the McASP configuration structure used to set up a McASP device.MCASP_Config 15. Default is 0 = input. MCASP_ConfigGbl Structure used to configure McASP global registers Structure Members MCASP_ConfigGbl Uint32 Uint32 Uint32 Uint32 pfunc pdir ditctl dlbctl Specifies if the McASP pins are McASP or GPIO pins. Specifies the loopback mode and kind loopback (odd serializers (receiver) to even serializers(receivers) or vice versa). Default is 0 = McASP. Specifies the DIT configuration. Uint32 Description amute This is the McASP configuration structure used to configure McASP device global registers. McASP Module 15-7 . Specifies the AMUTE register configuration. The user can create and initialize this structure and then pass its address to the MCASP_configGbl() function.

C6713 and DA610 ! Only for DA610 15-8 . Specifies the receive high clock configuration. C6413. MCASP_ConfigSrctl Structure used to configure McASP serial control registers Structure Members MCASP_ConfigSrctl Uint32 srctl0 Configures the serial control for pin 0 Uint32 srctl1 Configures the serial control for pin 1 Uint32 srctl2 Configures the serial control for pin 2 Uint32 srctl3 Configures the serial control for pin 3 Uint32 srctl4@ Configures the serial control for pin 4 Uint32 srctl5@ Configures the serial control for pin 5 Uint32 srctl6# Configures the serial control for pin 6 Uint32 srctl7# Configures the serial control for pin 7 Uint32 srctl8! Configures the serial control for pin 8 Uint32 srctl9! Configures the serial control for pin 9 Uint32 srctl10! Configures the serial control for pin 10 Uint32 srctl11! Configures the serial control for pin 11 Uint32 srctl12! Configures the serial control for pin 12 Uint32 srctl13! Configures the serial control for pin 13 Uint32 srctl14! Configures the serial control for pin 14 Uint32 srctl15! Configures the serial control for pin 15 @ Only for DM642. Specifies the active events for receive. Specifies the receive serial clock configuration. Specifies the receive frame sync configuration. Specifies the format for receive data. C6418. C6713 and DA610 # Only for DM642. Specifies the active receive tdm slots. The user can create and initialize this structure and then pass its address to the MCASP_configRcv() function. Specifies the receive serial clock control configuration. Description This is the McASP configuration structure used to configure McASP device receive registers. C6410.MCASP_ConfigRcv MCASP_ConfigRcv Structure used to configure McASP receive registers Structure Members MCASP_ConfigRcv Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 rmask rfmt afsrctl aclkrctl ahclkrctl rtdm rintct rclkchk Specifies the mask value for receive data.

McASP Module 15-9 . The user can create and initialize this structure and then pass its address to the MCASP_configSrctl() function. Specifies the transmit frame sync configuration. Description This is the McASP configuration structure used to configure McASP device transmit registers.MCASP_ConfigXmt Description This is the McASP configuration structure used to configure McASP device serial control registers. Specifies the format for transmit data. Specifies the transmit high clock configuration. Specifies the transmit serial clock configuration. Specifies the transmit serial clock control configuration. MCASP_ConfigXmt Structure used to configure McASP transmit registers Structure Members MCASP_ConfigXmt Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 xmask xfmt afsxctl aclkxctl ahclkxctl xtdm xintct xclkchk Specifies the mask value for transmit data. Specifies the active transmit tdm slots. The user can create and initialize this structure and then pass its address to the MCASP_configXmt() function. Specifies the active events for transmit.

MCASP_Config MyConfig = { … MCASP_config(hMcasp. MCASP_close(hMcasp). MCASP_configRcv(). hMcasp myConfig Handle to McASP device. MCASP_configXmt(). MCASP_Config *myConfig ). This structure is passed on to the MCASP_config() functions. See also MCASP_getConfig().1 Primary Functions MCASP_close Function Closes a McASP device previously opened via MCASP_open() void MCASP_close( MCASP_Handle hMcasp ).&MyConfig). The values of the structure members are written to the McASP registers.4. hMcasp none This function closes a McASP device previously opened via MCASP_open(). The following tasks are performed: the registers for the McASP device are set to their defaults. MCASP_configGbl(). See MCASP_open() Pointer to an initialized configuration structure Arguments Return Value Description none This function configures the McASP device using the configuration structure. see MCASP_open() Example MCASP_config Function Configures the McASP device using the configuration structure void MCASP_config( MCASP_Handle hMcasp. and the McASP handle is closed.4 Functions 15. and MCASP_configSrctl(). Example 15-10 .MCASP_close 15. Arguments Return Value Description Handle to McASP device.

MCASP_DEV1 Open flags . the McASP device registers are set to their power-on defaults. If the MCASP_OPEN_RESET is specified. Uint32 flags ). ’INV’ is returned. See MCASP_close().MCASP_OPEN_RESET: resets the McASP Arguments flags Return Value Description Device Handle Returns a device handle Before a McASP device can be used.MCASP_DEV0 . or hMcasp = MCASP_open(MCASP_DEV1.MCASP_open MCASP_open Function Opens a McASP device MCASP_Handle MCASP_open( int devNum.MCASP_OPEN_RESET).The return value is a unique device handle that is used in subsequent McASP API calls. it cannot be opened again until it is closed. McASP Module 15-11 . If the open fails. devNum McASP device to be opened: . it must first be opened by this function. … hMcasp = MCASP_open(MCASP_DEV0. Once opened. 0). Example MCASP_Handle hMcasp.

MCASP_Handle hMcasp. MCASP_reset(hMcasp). . Arguments Return Value Description Example Handle to McASP device. hMcasp Uint32 Handle to McASP port.i < 8. i++) { val = MCASP_read32(hMcasp). . MCASP_Handle hMcasp. Uint32 i.. See MCASP_open() 15-12 .MCASP_read32 MCASP_read32 Function Reads data when the receiver is configured to receive from data bus Uint32 MCASP_read32( MCASP_Handle hMcasp ). extern far dstBuf[8]. for (i = 0. val = MCASP_read32(hMcasp). See MCASP_open() Returns the data received by McASP Arguments Return Value Description This function reads data when the receiver is configured to receive from the peripheral data bus... .. //Reads data } Example MCASP_reset Function Resets McASP registers to their default values void MCASP_reset( MCASP_Handle hMcasp ).. hMcasp none This function resets the McASP registers to their default values.// Read data from the Address space for the McASP MCASP_Handle hMcasp..

val = 30.i < 8. See MCASP_open() Value to be transmitted Arguments Return Value Description Example none This function writes data when the transmitter is configured to transmit to the peripheral data bus. MCASP_write32(hMcasp). Uint32 val. // Writes data through the peripheral data bus for McASP } McASP Module 15-13 .. Uint32 i. hMcasp val Handle to McASP port.. MCASP_Handle hMcasp.MCASP_write32 MCASP_write32 Function Writes data when the transmitter is configured to transmit by data bus void MCASP_write32( MCASP_Handle hMcasp. for (i = 0. Uint32 val ). . i++) { MCASP_write32(hMcasp. .i).// Writes data into the Address space for the McASP MCASP_Handle hMcasp...

15-14 .4. The user can create and initialize this structure and then pass its address to the MCASP_setupClk() function. Constant Description Example MCASP_SetupClk Parameters for McASP transmit and receive clock registers Structure Members MCASP_SetupClk Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 syncmodeTransmit and receive clock synchronous flag xclksrc Transmit clock source xclkpol Transmit clock polarity xclkdiv Transmit clock div rclksrc Receive clock source rclkpol Receive clock polarity rclkdiv Receive clock div Description This is the clock configuration structure used to set up transmit and receive clocks for the McASP device.MCASP_DEVICE_CNT 15. See MCASP_open().2 Parameters and Constants MCASP_DEVICE_CNT McASP device count MCASP_DEVICE_CNT Compile-time constant that holds the number of McASP devices present on the current device. Constant Description MCASP_OPEN_RESET McASP open reset flag MCASP_OPEN_RESET Compile-time constant that holds the number of McASP devices present on the current device.

McASP Module 15-15 .MCASP_SetupFormat MCASP_SetupFormat Parameters for data streams format: XFMT−RFMT Structure Members MCASP_SetupFormat Uint32 MCASP_Dsprep Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 MCASP_Dsprep Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 xbusel xdsprep xslotsize xwordsize xalign xpad xpbit xorder xdelay rbusel rdsprep rslotsize rwordsize ralign rpad rpbit rorder rdelay Selects peripheral config/data bus for transmit DSP representation:Q31/Integer 8−32 bits XSSZ field − XFMT register Rotation right Left/right aligned Pad value for extra bits Which bit to pad the extra bits MSB/LSB XRVRS field − XFMT register Bit delay − XFMT register Selects peripheral config/data bus for receive DSP representation:Q31/Integer 8−32 bits RSSZ field − RFMT register Rotation right Left/right aligned Pad value for extra bits Which bit to pad the extra bits MSB/LSB XRVRS field − RFMT register FSXDLY Bit delay − RFMT register Description This is the format configuration structure used to set up transmit and receive formats for the McASP device. The user can create and initialize this structure and then pass its address to the MCASP_setupFormat() function.

15-16 . The user can create and initialize this structure and then pass its address to the MCASP_setupHclk() function. MCASP_SetupHclk Parameters for McASP transmit and receive high clock registers Structure Members MCASP_SetupHclk Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 xhclksrc xhclkpol xhclkdiv rhclksrc rhclkpol rhclkdiv Transmit high clock source Transmit high clock polarity Transmit high clock div Receive high clock source Receive high clock polarity Receive high clock div Description This is the high clock configuration structure used to set up transmit and receive high clocks for the McASP device.MCASP_SetupFsync MCASP_SetupFsync Parameters for frame sync control: AFSXCTL − AFSRCTL Structure Members MCASP_SetupFsync Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 xmode xslotsize xfssrc xfspol fxwid rmode rslotsize rfssrc rfspol rxwid TDM−BURST: FSXMOD − AFSXCTL register Number of slots for TDM: FSXMOD − AFSXCTL register Internal/external AFSXE − AFSXCTL register Transmit clock polarity FSXPOL − AFSXCTL register Transmit frame duration FXWID − AFSXCTL register TDM−BURST: FSRMOD − AFSRCTL register Number of slots for TDM: FSRMOD − AFSRCTL register Receive internal/external AFSRE − AFSRCTL register Receive clock polarity FSRPOL − AFSRCTL register Receive frame duration FRWID − AFSRCTL register Description This is the frame sync configuration structure used to set up transmit and receive frame sync for the McASP device. The user can create and initialize this structure and then pass its address to the MCASP_setupFsync() function.

4. Uint32 pins ) hMcasp pins none This function sets the the PDCLR register with the mask value pins specified in ’pins’.4 in PDOUT Arguments Return Value Description Handle to McASP device..MCASP_SUPPORT MCASP_SUPPORT Compile time constant Constant Description MCASP_SUPPORT Compile-time constant that has a value of 1 if the device supports the McASP module and 0 otherwise. MCASP_Handle hMcasp. The PDCLR register is an alias of the PDOUT register. Example #if (MCASP_SUPPORT) /* user MCASP configuration / #endif 15. 0x101). See MCASP_open() Mask value for the pins Example McASP Module 15-17 . Writing a 0 leaves it unchanged. . MCASP_clearPins(hMcasp. This function is used for those McASP pins which are configured as GPIO and are in output direction. You are not required to use this constant. the C6713 device supports this module.. Currently.// Clears bits 0. Writing a 1 clears the corresponding bit in PDOUT as 1.3 Auxiliary Functions MCASP_clearPins Clear pins which are enabled as GPIO and output Function void MCASP_clearPins( MCASP_Handle hMcasp.

Dsprep dpsrep. See MCASP_open() Q31/Integer 16−24 bits MCASP_configGbl Configures McASP device global registers Function void MCASP_configGbl( MCASP_Handle hMcasp. See MCASP_open() Pointer to the configuration structure Arguments 15-18 . See also MCASP_getConfig(). MCASP_configDit(hMcasp. 20). 0. XTDM and AFSXCTL registers depending on the representation MCASP_Dsprep and datalen.//Set up DIT transmission for Q31 24−bit data type MCASP_configDit(hMcasp.MCASP_configDit MCASP_configDit Configures XMASK/XTDM/AFSXCTL registers for DIT transmission Function void MCASP_configDit( MCASP_Handle hMcasp. MCASP_Handle hMcasp. .. 1. Handle to McASP device.. 24). MCASP_configXmt().//Set up DIT transmission for Int 20−bit data type Arguments Handle to McASP device. MCASP_ConfigGbl *myConfigGbl ) hMcasp myConfigGbl Return Value Description none This function configures McASP device global registers using the configuration structure MCASP_ConfigGbl. MCASP_configRcv(). The values of the structure−members are written to McASP registers. MCASP_config(). and MCASP_configSrctl(). Uint32 datalen ) hMcasp dsprep datalen Return Value Description Example none This function sets up XMAS.

&MyConfigRcv).. See also MCASP_getConfig(). The values of the structure−members are written to McASP registers.. See MCASP_open() Pointer to the configuration structure Example MCASP_configSrctl Configures McASP device serial control registers Function void MCASP_configSrctl( MCASP_Handle hMcasp. MCASP_configGbl(hMcasp.MCASP_configRcv Example MCASP_ConfigGbl MyConfigGbl. MCASP_configRcv Configures McASP device receive registers Function void MCASP_configRcv( MCASP_Handle hMcasp. MCASP_configXmt(). McASP Module 15-19 Arguments Handle to McASP device. MCASP_config(). MCASP_configGbl(). See also MCASP_getConfig().. The values of the structure−members are written to McASP registers. See MCASP_open() Pointer to the configuration structure . MCASP_config(). and MCASP_configSrctl(). &MyConfigGbl). . and MCASP_configRcv(). . Arguments Handle to McASP device. MCASP_ConfigRcv *myConfigRcv ) hMcasp myConfigRcv Return Value Description none This function configures McASP device receive registers using the configuration structure MCASP_ConfigRcv. MCASP_ConfigSrctl *myConfigSrctl ) hMcasp myConfigSrctl Return Value Description none This function configures McASP device serial control registers using the configuration structure MCASP_ConfigSrctl. MCASP_ConfigRcv MyConfigRcv. MCASP_configRcv(hMcasp.. MCASP_configGbl(). MCASP_configXmt().

MCASP_configXmt Configures McASP device transmit registers Function void MCASP_configXmt( MCASP_Handle hMcasp.. MCASP_configSrctl(hMcasp. MCASP_configSrctl(). See MCASP_open() direction of the clock Arguments ..MCASP_configXmt Example MCASP_ConfigSrctl MyConfigSrctl. &MyConfigSrctl).MCASP_XMT . MCASP_configGbl(). .MCASP_XMTRCV 15-20 . See MCASP_open() Pointer to the configuration structure Example MCASP_enableClk Wakes up transmit and/or receive clock. MCASP_ConfigXmt *myConfigXmt ) hMcasp myConfigXmt Return Value Description none This function configures McASP device transmit registers using the configuration structure MCASP_ConfigXmt. MCASP_config()... Arguments Handle to McASP device. Uint32 direction ) hMcasp direction Handle to McASP device. and MCASP_configRcv().MCASP_RCV . See also MCASP_getConfig(). depending on direction Function void MCASP_enableClk( MCASP_Handle hMcasp. The values of the structure−members are written to McASP registers. MCASP_configXmt(hMcasp. MCASP_ConfigXmt MyConfigXmt. . &MyConfigXmt).MCASP_RCVXMT .

See MCASP_open() direction of frame sync . //Wakes up transmit and receive clock MCASP_enableClk(hMcasp.MCASP_XMT . MCASP_Handle hMcasp. . MCASP_RCVXMT). //Wakes up transmit clock MCASP_enableClk(hMcasp.MCASP_enableFsync Return Value Description none This function wakes up the transmit or receive (or both) clock out of reset by writing into RCLKRST and XCLKRST of GBLCTL. MCASP_enableClk(hMcasp. //Wakes up receive clock MCASP_enableClk(hMcasp. This function should only be used when the corresponding clock is internal. MCASP_RCV). Uint32 direction ) hMcasp direction Handle to McASP device.MCASP_XMTRCV Arguments Return Value Description none This function wakes up the transmit or recieve (or both) frame sync out of reset by writing into RFSRST and XFSRST of GBLCTL..MCASP_RCVXMT . MCASP_XMTRCV). MCASP_XMT). //Wakes up receive and transmit clock Example MCASP_enableFsync Enables frame sync if receiver has internal frame sync Function void MCASP_enableFsync( MCASP_Handle hMcasp. McASP Module 15-21 . This function should only be used when the corresponding frame sync is internal.MCASP_RCV ..

MCASP_Handle hMcasp. //Wakes up transmit high clock MCASP_enableHclk(hMcasp. This function should only be used when the corresponding high clock is internal.. MCASP_XMT). depending on direction Function void MCASP_enableHclk( MCASP_Handle hMcasp. MCASP_XMT).MCASP_enableHclk Example MCASP_Handle hMcasp. MCASP_RCVXMT). See MCASP_open() direction of the high clock MCASP_RCV MCASP_XMT MCASP_RCVXMT MCASP_XMTRCV Return Value Description none This function wakes up the transmit or recieve (or both) high clock out of reset by writing into RHCLKRST and XHCLKRST of GBLCTL. MCASP_RCV).. Uint32 direction ) hMcasp direction - Arguments Handle to McASP device. //Wakes up transmit and receive frame sync MCASP_enableFsync(hMcasp. //Wakes up receive frame sync MCASP_enableFsync(hMcasp. . MCASP_enableFsync(hMcasp. //Wakes up transmit and receive high clock MCASP_enableHclk(hMcasp. MCASP_XMTRCV). MCASP_enableHclk(hMcasp.. //Wakes up receive high clock MCASP_enableHclk(hMcasp. MCASP_XMTRCV). //Wakes up transmit frame sync MCASP_enableFsync(hMcasp. MCASP_RCVXMT).. //Wakes up receive and transmit frame sync MCASP_enableHclk Wakes up transmit and/or receive high clock. . //Wakes up receive and transmit high clock Example 15-22 . MCASP_RCV).

See MCASP_open() direction of the serializers MCASP_RCV MCASP_XMT MCASP_RCVXMT MCASP_XMTRCV Return Value Description Example none This function wakes up the transmit or recieve (or both) serializers out of reset by writing into RSRCRL and XSRCLR of GBLCTL. //Receive serializers are made active MCASP_enableSers(hMcasp. MCASP_RCVXMT).MCASP_enableSers MCASP_enableSers Enables transmit and/or receive serializers. //Transmit serializers are made active MCASP_enableSers(hMcasp. MCASP_Handle hMcasp. MCASP_XMT).. depending on direction Function void MCASP_enableSers( MCASP_Handle hMcasp. //Transmit and receive serializers are made active MCASP_enableSers(hMcasp. MCASP_enableSers(hMcasp. . MCASP_XMTRCV). Uint32 direction ) hMcasp direction - Arguments Handle to McASP device.. //Receive and transmit serializers are made active McASP Module 15-23 . MCASP_RCV).

. MCASP_RCVXMT). MCASP_Handle hMcasp. MCASP_XMT). //Wakes up transmit and receive state machine MCASP_enableSm(hMcasp. Uint32 direction ) hMcasp direction - Arguments Handle to McASP device. depending on direction Function void MCASP_enableSm( MCASP_Handle hMcasp. //Wakes up receive state machine MCASP_enableSm(hMcasp. MCASP_RCV). MCASP_XMTRCV)..MCASP_enableSm MCASP_enableSm Wakes up transmit and/or receive state machine. //Wakes up receive and transmit state machine 15-24 . See MCASP_open() direction of the state machine MCASP_RCV MCASP_XMT MCASP_RCVXMT MCASP_XMTRCV Return Value Description Example none This function wakes up the transmit or recieve (or both) serializers out of reset by writing into RSMRST and XSMRST of GBLCTL. . //Wakes up transmit state machine MCASP_enableSm(hMcasp. MCASP_enableSm(hMcasp.

See MCASP_config(). MCASP_XMTRCV). and the RGBLCTL value for MCASP_RCV direction. gblVal = MCASP_getGblctl(hMcasp. Receive. Uint32 gblVal.. MCASP_Handle hMcasp. See MCASP_open() direction MCASP_RCV MCASP_XMT MCASP_RCVXMT MCASP_XMTRCV Returns GBCTL. and Serial Control registers. //RGBLCTL gblVal = MCASP_getGblctl(hMcasp.MCASP_getConfig MCASP_getConfig Reads the current McASP configuration values Function void MCASP_getConfig( MCASP_Handle hMcasp. Arguments Handle to McASP device. hMcasp = MCASP_open(MCASP_DEV0. See MCASP_open() Pointer to the source configuration structure Example MCASP_getGblctl Reads GBLCTL register. MCASP_Config mcaspCfg. //XGBLCTL gblVal = MCASP_getGblctl(hMcasp.. MCASP_RCV). MCASP_Config *config ) hMcasp config Return Value Description none This function gets the current McASP configuration values.. . depending on the direction Function Uint32 MCASP_getGblctl( MCASP_Handle hMcasp. MCASP_XMT). as configured in the Global. &mcaspCfg). //GBLCTL McASP Module 15-25 Example . MCASP_OPEN_RESET).. Transmit. depending on direction Return Value Description Uint32 This function returns the XGBLCTL value for MCASP_XMT direction. It returns GBLCTL otherwise. MCASP_getConfig(hMcasp. . Uint32 direction ) hMcasp direction - Arguments Handle to McASP device.

9). RFRST. which is configured as receiver Example MCASP_resetRcv Function Resets the receiver fields in the Global Control register Uint32void MCASP_resetRcv( MCASP_Handle hMcasp ). Uint32 rbufNum ). That is. Note: It takes 32 receive clock cycles for GBLCTL to update. RCLKRST.MCASP_read32Cfg MCASP_read32Cfg Reads the data from rbufNum Function Uint32 MCASP_read32Cfg( MCASP_Handle hMcasp. Handle to McASP device. RSMRST. 15-26 . and RHCLKRST in GBLCTL. ... MCASP_Handle hMcasp. MCASP_resetRcv(hMcasp). See MCASP_open() Arguments Return Value Description Example MCASP_Handle hMcasp. and resets clocks for the receiver. MCASP_OPEN_RESET). clears the serial buffer. Uint32 val. . it clears the RSRCLR.// Read data from RBUF9. hMcasp rbufNum Uint32 Handle to McASP device. hMcasp = MCASP_open(MCASP_DEV0. val = MCASP_read32Cfg(hMcasp.. It should be used only when the corresponding AXR[0:15] is configured as a receiver and the receiver uses the peripheral configuration bus. resets the frame synchronization generator.. hMcasp none This function resets the state machine. See MCASP_open() RBUF[0:15] Returns data in RBUF[rbufNum] Arguments Return Value Description This function reads data from RBUF[0:15].

. MCASP_setPins(hMcasp. and resets clocks for the transmitter. MCASP_Handle hMcasp. XSMRST. resets the frame synchronization generator. MCASP_setPins Function Sets pins which are enabled as GPIO and output void MCASP_setPins( MCASP_Handle hMcasp. .MCASP_resetXmt MCASP_resetXmt Function Resets the transmitter fields in the Global Control register Uint32void MCASP_resetXmt( MCASP_Handle hMcasp ). XFRST. Uint32 pins ) hMcasp pins none This function sets up the the PDSET register with the mask value pins specified in ’pins’. clears the serial buffer.. See MCASP_open() Mask value for the pins Example . That is.. Writing a 1 sets the corresponding bit in PDOUT as 1.4 in PDOUT McASP Module 15-27 Arguments Return Value Description Handle to McASP device. This function is used for those McASP pins which are configured as GPIO and are in output direction. Note: It takes 32 transmit clock cycles for GBLCTL to update. and XHCLKRST in GBLCTL. Writing a 0 leaves it unchanged. See MCASP_open() Arguments Return Value Description Example MCASP_Handle hMcasp. XCLKRST. hMcasp none This function resets the state machine. The PDSET register is an alias of the PDOUT register. it clears the XSRCLR...// Sets bits 0. MCASP_OPEN_RESET). MCASP_resetXmt(hMcasp). hMcasp = MCASP_open(MCASP_DEV0. Handle to McASP device. 0x101).

The values of the structure members are written to McASP transmit and receive clock registers. Arguments Return Value Description Handle to McASP device. See MCASP_open() Pointer to the configuration structure Example 15-28 .. . MCASP_SetupFormat setupformat. MCASP_SetupClk setupclk.. The values of the structure members are written to McASP transmit and receive format registers. See MCASP_open() Pointer to the configuration structure Example MCASP_setupFormat Sets up McASP transmit and receive format registers Function void MCASP_setupFormat( MCASP_Handle hMcasp. MCASP_setupFormat(hMcasp... . Arguments Return Value Description Handle to McASP device. MCASP_SetupClk *setupclk ) hMcasp setupclk none This function configures the McASP device clock registers using the configuration structure MCASP_SetupClk. &setupclk). &setupformat). MCASP_SetupFormat *setupformat ) hMcasp setupformat none This function configures the McASP device format registers using the configuration structure MCASP_SetupFormat.MCASP_setupClk MCASP_setupClk Function Sets up McASP transmit and receive clock registers void MCASP_setupClk( MCASP_Handle hMcasp. MCASP_setupClk(hMcasp.

MCASP_SetupFsync *setupfsync ) hMcasp setupfsync none This function configures the McASP device frame sync registers using the configuration structure MCASP_SetupFsync. MCASP_setupHclk(hMcasp. MCASP_setupFsync(hMcasp. The values of the structure members are written to McASP transmit and receive frame sync registers.. MCASP_SetupFsync setupfsync. MCASP_SetupHclk *setuphclk ) hMcasp setuphclk none This function configures the McASP device high clock registers using the configuration structure MCASP_SetupHclk. See MCASP_open() Pointer to the configuration structure Example McASP Module 15-29 . See MCASP_open() Pointer to the configuration structure Example MCASP_setupHclk Sets up McASP transmit and receive high clock registers Function void MCASP_setupHclk( MCASP_Handle hMcasp. .MCASP_setupFsync MCASP_setupFsync Sets up McASP transmit and receive frame sync registers Function void MCASP_setupFsync( MCASP_Handle hMcasp. Arguments Return Value Description Handle to McASP device. &setupfsync).. .. The values of the structure members are written to McASP transmit and receive high clock registers. &setuphclk). MCASP_SetupHclk setuphclk. Arguments Return Value Description Handle to McASP device..

. Uint32 val ). which is configured as transmitter Arguments Handle to McASP device. MCASP_Handle hMcasp Uint32 eventNo. hMcasp = MCASP_open(MCASP_DEV0.4 Interrupt Control Functions MCASP_getRcvEventId Returns the receive event ID Function Uint32 MCASP_getRcvEventId( MCASP_Handle hMcasp ). hMcasp Uint32 Handle to McASP device. eventNo = MCASP_getRcvEventId(hMcasp).. See MCASP_open() Receiver event ID Arguments Return Value Description Example Retrieves the receive event ID for the given device. It should be used only when the corresponding AXR[0:15] is configured as a transmitter and the transmitter uses the peripheral configuration bus..MCASP_write32Cfg MCASP_write32Cfg Writes the val into xbufNum Function void MCASP_write32Cfg( MCASP_Handle hMcasp. MCASP_Handle hMcasp. 15-30 . See MCASP_open() XBUF[0:15] Value to be transmitted Example 15.4). . MCASP_write32Cfg(hMcasp. hMcasp xbufNum val Return Value Description none This function writes data into XBUF[0:15].// Write data into XBUF4. MCASP_OPEN_RESET). . Uint32 xbufNum.4..

MCASP_Handle hMcasp Uint32 eventNo. MCASP_OPEN_RESET).. McASP Module 15-31 .. See MCASP_open() Transmit event ID Arguments Return Value Description Example Retrieves the transmit event ID for the given device. hMcasp = MCASP_open(MCASP_DEV0. . eventNo = MCASP_getXmtEventId(hMcasp). hMcasp Uint32 Handle to McASP device.MCASP_getXmtEventId MCASP_getXmtEventId Function Returns the transmit event ID Uint32 MCASP_getXmtEventId( MCASP_Handle hMcasp ).

MCASP_getXmtEventId 15-32 .

. . . .4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . discusses using a McBSP port. . . . . . . . Topic Page 16. . . 16-7 16. . . . . . .1 Overview . . . . . . . . . . . . . . .2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16. . . . . . . . and provides a McBSP API reference section. . . . . . . 16-9 16-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16. . . . . lists the API functions and macros within the module.Chapter 16 McBSP Module This chapter describes the McBSP module. . . . . . . . . . . . . . . . .3 Configuration Structure . . .

McBSP APIs (a) Primary Functions Syntax MCBSP_close MCBSP_config MCBSP_configArgs MCBSP_open MCBSP_start Type Description F F F F F Closes a McBSP port previously opened via MCBSP_open() Sets up the McBSP port using the configuration structure Sets up the McBSP port using the register values passed in Opens a McBSP port for use Starts the McBSP device See page . C = Constant Type Description F F F F F F Enables the frame sync generator for the given port Enables the receiver for the given port Enables the sample rate generator for the given port Enables the transmitter for the given port Reads the current McBSP configuration values Reads the values of the port pins when configured as general purpose I/Os See page . Table 16−1.Overview 16. Table 16−1 lists the configuration structure for use with the McBSP functions.1 Overview The McBSP module contains a set of API functions for configuring the McBSP registers.. 16-15 16-15 16-16 16-16 16-16 16-17 16-2 ..... 16-9 16-9 16-11 16-13 16-14 (b) Auxiliary Functions and Constants Syntax MCBSP_enableFsync MCBSP_enableRcv MCBSP_enableSrgr MCBSP_enableXmt MCBSP_getConfig MCBSP_getPins Note: F = Function. McBSP Configuration Structure Syntax MCBSP_Config Type Description S Used to setup a McBSP port See page . Table 16−2 lists the functions and constants available in the CSL McBSP module. 16-7 Table 16−2..

. 16-23 16-24 McBSP Module 16-3 .. McBSP APIs (Continued) Syntax MCBSP_getRcvAddr MCBSP_getXmtAddr MCBSP_PORT_CNT MCBSP_read MCBSP_reset MCBSP_resetAll MCBSP_rfull MCBSP_rrdy MCBSP_rsyncerr MCBSP_setPins MCBSP_SUPPORT MCBSP_write MCBSP_xempty MCBSP_xrdy MCBSP_xsyncerr (c) Interrupt Control Functions Syntax MCBSP_getRcvEventId MCBSP_getXmtEventId Note: F = Function. 16-17 16-18 16-18 16-18 16-19 16-19 16-19 16-20 16-20 16-21 16-21 16-22 16-22 16-22 16-23 Type Description F F Retrieves the receive event ID for the given port Retrieves the transmit event ID for the given port See page . DXR A compile time constant that holds the number of serial ports present on the current device Performs a direct 32-bit read of the data receive register DRR Resets the given serial port Resets all serial ports supported by the device Reads the RFULL bit of the serial port control register Reads the RRDY status bit of the SPCR register Reads the RSYNCERR status bit of the SPCR register Sets the state of the serial port pins when configured as general purpose IO A compile time constant whose value is 1 if the device supports the McBSP module Writes a 32-bit value directly to the serial port data transmit register.Overview Table 16−2. C = Constant Type Description F F C F F F F F F F C F F F F Returns the address of the data receive register (DRR) Returns the address of the data transmit register.. DXR Reads the XEMPTY bit from the SPCR register Reads the XRDY status bit of the SPCR register Reads the XSYNCERR status bit of the SPCR register See page ..

16-4 . MCBSP_getRcvAddr() and MCBSP_getXmtAddr(). use the device handle to call the other API functions. McBSP status bits are easily read using efficient inline functions. the symbol constants may be used for the field values. There are functions for directly reading and writing to the data registers DRR and DXR. To assist in creating register values.Overview 16.1. The port may be configured by passing a MCBSP_Config structure to MCBSP_config() or by passing register values to the MCBSP_configArgs() function. you must first open it and obtain a device handle using MCBSP_open(). the MCBSP_MK (make) macros construct register values based on field values. Once opened. In addition.1 Using a McBSP Port To use a McBSP port. The addresses of the DXR and DRR registers are also obtainable for use with DMA configuration. MCBSP_read() and MCBSP_write().

<FIELD>) MCBSP_FSET(<REG>.x) MCBSP_FGETH(h. and those that construct register and field values.<REG>) MCBSP_RGETH(h.<FIELD>) MCBSP_FSETH(h.<FIELD>.<REG>.fieldval) MCBSP_FSETS(<REG>.<REG>) MCBSP_RSETA(addr..<REG>.2 Macros There are two types of McBSP macros: those that access registers and fields. fieldval) MCBSP_FSETSA(addr.<FIELD>. Using the HAL Macros.<REG>.<REG>. <SYM>) MCBSP_RGETA(addr. McBSP Macros that Access Registers and Fields Macro MCBSP_ADDR(<REG>) MCBSP_RGET(<REG>) MCBSP_RSET(<REG>. The McBSP module includes handle-based macros.<REG>) MCBSP_RSETH(h.<FIELD>) MCBSP_FSETA(addr. fieldval) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address Returns the address of a memory-mapped register for a given handle Returns the value of a register for a given handle Sets the register value to x for a given handle Returns the value of the field for a given handle Sets the field value to x for a given handle See page .x) MCBSP_FGETA(addr.<REG>. <SYM>) MCBSP_ADDRH(h. The macros themselves are found in Chapter 28. and Table 16−4 lists the McBSP macros that construct register and field values.<FIELD>.<FIELD>. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 28-12 28-19 28-21 28-14 28-16 McBSP Module 16-5 .Macros 16.x) MCBSP_FGET(<REG>.<FIELD>.. Table 16−3.<REG>.<REG>. Table 16−3 lists the McBSP macros that access registers and fields.

28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 16-6 . McBSP Macros that Construct Register and Field Values Macro MCBSP_<REG>_DEFAULT MCBSP_<REG>_RMK() MCBSP_<REG>_OF() MCBSP_<REG>_<FIELD>_DEFAULT MCBSP_FMK() MCBSP_FMKS() MCBSP_<REG>_<FIELD>_OF() MCBSP_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of ..Macros Table 16−4...... Field default value Field make Field make symbolically Field value of . Field symbolic value See page .

You can use literal values or the MCBSP_RMK macros to create the structure member values. You create and initialize this structure and then pass its address to the MCBSP_config() function.3 Configuration Structure MCBSP_Config Structure Members Used to setup McBSP port MCBSP_Config Uint32 spcr Uint32 rcr Uint32 xcr Uint32 srgr Uint32 mcr Uint32 rcer Uint32 xcer Uint32 pcr Serial port control register value Receive control register value Transmit control register value Sample rate generator register value Multichannel control register value Receive channel enable register value Transmit channel enable register value Pin control register value Configuration structure for C64x devices only: Uint32 spcr Serial port control register value Uint32 rcr Receive control register value Uint32 xcr Transmit control register value Uint32 srgr Sample rate generator register value Uint32 mcr Multichannel control register value Uint32 rcere0 Enhanced Receive channel enable register 0 value Uint32 rcere1 Enhanced Receive channel enable register 1 value Uint32 rcere2 Enhanced Receive channel enable register 2 value Uint32 rcere3 Enhanced Receive channel enable register 3 value Uint32 xcere0 Enhanced Transmit channel enable register 0 value Uint32 xcere1 Enhanced Transmit channel enable register 1 value Uint32 xcere2 Enhanced Transmit channel enable register 2 value Uint32 xcere3 Enhanced Transmit channel enable register 3 value UInt32 pcr Pin Control register value Description This is the McBSP configuration structure used to set up a McBSP port.MCBSP_Config 16. McBSP Module 16-7 .

/* mcr . 16-8 . /* rcr . /* xcr . /* xcr */ 0x00000000.*/ }. /* xcere0 */ 0x00000000. /* srgr . /* rcere1 */ 0x00000000.*/ 0x00000000..&MyConfig). /* spcr . /* rcere2 */ 0x00000000... /* xcere1 */ 0x00000000.*/ 0x00000000. /* xcere3 */ 0x00000000 /* pcr . /* xcer */ 0x00000000 /* pcr */ }. /* rcer */ 0x00000000. /* spcr */ 0x00010140.&MyConfig)...*/ 0x00010140. /* srgr */ 0x00000000.*/ 0x00010140. /* mcr */ 0x00000000. … MCBSP_config(hMcbsp.MCBSP_Config Example MCBSP_Config MyConfig = { 0x00012001. /* rcere0 */ 0x00000000. /* Configuration structure for C64x devices only */ MCBSP_Config MyConfig = { 0x00012001..*/ 0x00000000. … MCBSP_config(hMcbsp. /* rcr */ 0x00010140. /* xcere2 */ 0x00000000. /* rcere3 */ 0x00000000.

The serial port control register (spcr) is written last.4. MCBSP_close(hMcbsp). hMcbsp none This function closes a McBSP port previously opened via MCBSP_open().4 Functions 16. See MCBSP_open() Pointer to an initialized configuration structure Arguments Return Value Description none Sets up the McBSP port using the configuration structure. MCBSP_Config *Config ). hMcbsp Config Handle to McBSP port. Any associated interrupts are disabled and cleared. The registers for the McBSP port are set to their power-on defaults.MCBSP_close 16. see MCBSP_open() Example MCBSP_config Function Sets up McBSP port using configuration structure void MCBSP_config( MCBSP_Handle hMcbsp.1 Primary Functions MCBSP_close Function Closes McBSP port previously opened via MCBSP_open() void MCBSP_close( MCBSP_Handle hMcbsp ). See also MCBSP_configArgs() and MCBSP_Config. The values of the structure are written to the port registers. McBSP Module 16-9 . Arguments Return Value Description Handle to McBSP port.

/* mcr */ 0x00000000. /* xcere3 */ 0x00000000 /* pcr */ }. /* spcr */ 0x00010140. /* spcr 0x00010140. /* rcere1 */ 0x00000000. /* xcr */ 0x00000000. #else = { */ */ */ */ */ */ */ */ /* Configuration structure for C64x devices only */ MCBSP_Config MyConfig = { 0x00012001. /* rcr 0x00010140. /* rcere0 */ 0x00000000. /* xcer 0x00000000 /* pcr }.&MyConfig). /* xcere0 */ 0x00000000. /* xcere2 */ 0x00000000. /* rcer 0x00000000. /* rcere2 */ 0x00000000. #endif … MCBSP_config(hMcbsp. /* srgr 0x00000000. /* rcere3 */ 0x00000000.MCBSP_config Example #if (!C64_SUPPORT) MCBSP_Config MyConfig 0x00012001. /* xcr 0x00000000. /* xcere1 */ 0x00000000. 16-10 . /* srgr */ 0x00000000. /* mcr 0x00000000. /* rcr */ 0x00010140.

Uint32 pcr ). Uint32 rcer. Uint32 pcr ). Arguments hMcbsp spcr rcr xcr srgr mcr rcer xcer pcr Handle to McBSP port. Uint32 xcere1. Uint32 mcr. Uint32 rcere2. See MCBSP_open() Serial port control register value Receive control register value Transmit control register value Sample rate generator register value Multichannel control register value Receive channel enable register value Transmit channel enable register value Pin control register value McBSP Module 16-11 . Uint32 rcere3. Uint32 spcr. Uint32 xcer. Uint32 rcr. Uint32 srgr. Uint32 rcere0. For C64x devices: void MCBSP_configArgs( MCBSP_Handle hMcbsp. Uint32 rcr. Uint32 xcere3. Uint32 xcere2. Uint32 xcr. Uint32 rcere1. Uint32 xcr. Uint32 spcr. Uint32 mcr.MCBSP_configArgs MCBSP_configArgs Sets up McBSP port using register values passed in Function void MCBSP_configArgs( MCBSP_Handle hMcbsp. Uint32 xcere0. Uint32 srgr.

/* mcr */ 0x00000000. The register values are written to the port registers. /* xcer */ 0x00000000 /* pcr */ ). Example MCBSP_configArgs(hMcbsp. /* xcr */ 0x00000000. /* srgr */ 0x00000000. See also MCBSP_config(). /* spcr */ 0x00010140. The serial port control register (spcr) is written last. /* C64x devices */ 16-12 .MCBSP_configArgs For C64x devices: rcere0 Enhanced Receive channel enable register 0 value rcere1 Enhanced Receive channel enable register 1 value rcere2 Enhanced Receive channel enable register 2 value rcere3 Enhanced Receive channel enable register 3 value xcere0 Enhanced Transmit channel enable register 0 value xcere1 Enhanced Transmit channel enable register 1 value xcere2 Enhanced Transmit channel enable register 2 value xcere3 Enhanced Transmit channel enable register 3 value Return Value Description none Sets up the McBSP port using the register values passed in. You may use literal values for the arguments or for readability. 0x00012001. /* rcr */ 0x00010140. You may use the _RMK macros to create the register values based on field values. /* rcer */ 0x00000000.

may be logical OR of any of the following: . /* rcere3 */ 0x00000000. … hMcbsp = MCBSP_open(MCBSP_DEV0. /* rcr */ 0x00010140. McBSP Module 16-13 .The return value is a unique device handle that you use in subsequent McBSP API calls. devNum McBSP device (port) number: . If the MCBSP_OPEN_RESET is specified. /* xcr */ 0x00000000.MCBSP_open MCBSP_configArgs(hMcbsp. Example MCBSP_Handle hMcbsp. MCBSP_open Function Opens McBSP port for use MCBSP_Handle MCBSP_open( int devNum. /* xcere2 */ 0x00000000. /* rcere2 */ 0x00000000. the McBSP port registers are set to their power-on defaults and any associated interrupts are disabled and cleared. 0x00012001. /* rcere0 */ 0x00000000. /* spcr */ 0x00010140.MCBSP_DEV2 (if supported by the C64x device) Open flags. /* mcr */ 0x00000000. INV is returned. Uint32 flags ). /* xcere3 */ 0x00000000 /* pcr */ ). Once opened. /* xcere1 */ 0x00000000. /* xcere0 */ 0x00000000. /* rcere1 */ 0x00000000. it cannot be opened again until closed. it must first be opened by this function. If the open fails. /* srgr */ 0x00000000.MCBSP_OPEN_RESET Arguments flags Return Value Description Device Handle Returns a device handle Before a McBSP port can be used. See MCBSP_close().MCBSP_DEV1 .MCBSP_DEV0 .MCBSP_OPEN_RESET).

Uint32 startMask. 16-14 . Equivalent to MCBSP_enableXmt(). Value = 2 x SRGR clock period/ 4 x C6x Instruction cycle Default value is 0xFFFFFFFF Return Value Description none Use this function to start a transmit and/or receive operation for a McBSP port by passing the handle and mask. McBSP logic requires two SRGR clock periods after enabling the sample rate generator for itsl logic to stabilize. Use this parameter to provide the appropriate delay. MCBSP_start( hMcbsp. 0x00003000). MCBSP_enableRcv(). MCBSP_RCV_START. hMcbsp startMask Handle to McBSP port.MCBSP_SRGR_FRAMESYNC: Start frame sync.MCBSP_SRGR_START: start Sample rate generator (GRST) . MCBSP_enableSrgr(). Uint32 SampleRateGenDelay ). MCBSP_RCV_START | MCBSP_XMT_START.MCBSP_XMIT_START: start transmit (XRST) .MCBSP_start MCBSP_start Function Starts McBSP device void MCBSP_start( MCBSP_Handle hMcbsp. and MCBSP_enableFsync(). See MCBSP_open() Allows setting of the different start fields using the following macros: .MCBSP_RCV_START: start receive (RRST) . 0x00003000). Example MCBSP_start( hMcbsp. Generation (FRST) Arguments SampleRateGenDelay Sample rate generated delay.

hMcbsp none Use this function to enable the frame sync generator for the given port. See MCBSP_open() MCBSP_enableRcv Function Enables receiver for given port void MCBSP_enableRcv( MCBSP_Handle hMcbsp ).4.MCBSP_enableFsync 16. MCBSP_enableFsync(hMcbsp). MCBSP_enableRcv(hMcbsp). Arguments Return Value Description Example Handle to McBSP port. Arguments Return Value Description Example Handle to McBSP port.2 Auxiliary Functions and Constants MCBSP_enableFsync Function Enables frame sync generator for given port void MCBSP_enableFsync( MCBSP_Handle hMcbsp ). See MCBSP_open() McBSP Module 16-15 . hMcbsp none Use this function to enable the receiver for the given port.

&msbspCfg). Arguments Return Value Description Example Handle to McBSP port. hMcbsp none Use this function to enable the transmitter for the given port. MCBSP_enableXmt(hMcbsp). See MCBSP_open() MCBSP_enableXmt Function Enables transmitter for given port void MCBSP_enableXmt( MCBSP_Handle hMcbsp ). hMcbsp none Use this function to enable the sample rate generator for the given port. Arguments Handle to McBSP port. 16-16 . See MCBSP_open() Pointer to a configuration structure. See MCBSP_open() MCBSP_getConfig Reads the current McBSP configuration values Function void MCBSP_getConfig( MCBSP_Handle hMcbsp. MCBSP_enableSrgr(hMcbsp). hMcbsp config Return Value Description Example none Get McBSP current configuration value MCBSP_config mcbspCfg. MCBSP_Config *config ).MCBSP_enableSrgr MCBSP_enableSrgr Function Enables sample rate generator for given port void MCBSP_enableSrgr( MCBSP_Handle hMcbsp ). MCBSP_getConfig(hMcbsp. Arguments Return Value Description Example Handle to McBSP port.

. hMcbsp Pin Mask Handle to McBSP port. } Example MCBSP_getRcvAddr Returns address of data receive register (DRR) Function Uint32 MCBSP_getRcvAddr( MCBSP_Handle hMcbsp ). Addr = MCBSP_getRcvAddr(hMcbsp). See also MCBSP_getXmtAddr(). PinMask = MCBSP_getPins(hMcbsp).MCBSP_getPins MCBSP_getPins Function Reads values of port pins when configured as general purpose I/Os Uint32 MCBSP_getPins( MCBSP_Handle hMcbsp ). McBSP Module 16-17 Example . See MCBSP_open() - Arguments Return Value Bit-Mask of pin values MCBSP_PIN_CLKX MCBSP_PIN_FSX MCBSP_PIN_DX MCBSP_PIN_CLKR MCBSP_PIN_FSR MCBSP_PIN_DR MCBSP_PIN_CLKS Description This function reads the values of the port pins when configured as general purpose input/outputs. Uint32 PinMask.. .. See MCBSP_open() DRR register address Arguments Return Value Description Returns the address of the data receive register. DRR. if (PinMask & MCBSP_PIN_DR) { . This value is needed when setting up DMA transfers to read from the serial port. hMcbsp Receive Address Handle to McBSP port..

This value is needed when setting up DMA transfers to write to the serial port.MCBSP_getXmtAddr MCBSP_getXmtAddr Returns address of data transmit register. Addr = MCBSP_getXmtAddr(hMcbsp). See MCBSP_open() DXR register address Arguments Return Value Description Transmit Address Returns the address of the data transmit register. DXR Function Uint32 MCBSP_getXmtAddr( MCBSP_Handle hMcbsp ). See MCBSP_open() 16-18 . hMcbsp Handle to McBSP port. #if (MCBSP_PORT_CNT==3) … #endif MCBSP_read Function Performs direct 32-bit read of data receive register DRR Uint32 MCBSP_read( MCBSP_Handle hMcbsp ). Arguments Return Value Description Example Handle to McBSP port. Example MCBSP_PORT_CNT Compile-time constant Constant Description Example MCBSP_PORT_CNT Compile-time constant that holds the number of serial ports present on the current device. Data = MCBSP_read(hMcbsp). hMcbsp Data This function performs a direct 32-bit read of the data receive register DRR. DXR. See also MCBSP_getRcvAddr().

See MCBSP_open() will be reset to the McBSP reset value and not the device reset value .All serial port registers are set to their power-on defaults. hMcbsp Handle to McBSP port.MCBSP_reset MCBSP_reset Function Resets given serial port void MCBSP_reset( MCBSP_Handle hMcbsp ). hMcbsp none Resets the given serial port. See MCBSP_open() McBSP Module 16-19 Arguments . The PCR register Arguments Return Value Description Handle to McBSP port. none none Resets all serial ports supported by the chip device Executed Actions: . MCBSP_rfull Function Reads RFULL bit of serial port control register Uint32 MCBSP_rfull( MCBSP_Handle hMcbsp ). The PCR register will be reset to the McBSP reset value and not the device reset value . Actions Taken: .All serial port registers are set to their power-on defaults. MCBSP_resetAll Function Arguments Return Value Description Resets all serial ports supported by the chip device void MCBSP_resetAll().All associated interrupts are disabled and cleared Example MCBSP_reset(hMcbsp).All associated interrupts are disabled and cleared Example MCBSP_resetAll().

See MCBSP_open() Returns RSYNCERR bit of the SPCR register. if (MCBSP_rrdy(hMcbsp)) { … } MCBSP_rsyncerr Function Reads RSYNCERR status bit of SPCR register Uint32 MCBSP_rsyncerr( MCBSP_Handle hMcbsp ). 0 or 1 Arguments Return Value Description Example Reads the RSYNCERR status bit of the SPCR register. 0 or 1 This function reads the RFULL bit of the serial port control register. hMcbsp RSYNCERR Handle to McBSP port. See MCBSP_open() Returns RRDY status bit of SPCR. hMcbsp RRDY Handle to McBSP port. A 1 indicates a receive shift register full error. A 1 indicates the receiver is ready with data to be read. if (MCBSP_rfull(hMcbsp)) { … } MCBSP_rrdy Function Reads RRDY status bit of SPCR register Uint32 MCBSP_rrdy( MCBSP_Handle hMcbsp ). A 1 indicates a receiver frame sync error. 0 or 1 Arguments Return Value Description Example Reads the RRDY status bit of the SPCR register.MCBSP_rrdy Return Value Description Example RFULL Returns RFULL status bit of SPCR register. if (MCBSP_ rsyncerr(hMcbsp)) { … } 16-20 .

MCBSP_PIN_CLKS Arguments Return Value Description none Use this function to set the state of the serial port pins when configured as general purpose IO. all devices support this module.MCBSP_PIN_CLKR .MCBSP_PIN_DR . Uint32 pins ). You are not required to use this constant.MCBSP_PIN_CLKX .MCBSP_PIN_DX .MCBSP_setPins MCBSP_setPins Function Sets state of serial port pins when configured as general purpose IO void MCBSP_setPins( MCBSP_Handle hMcbsp. Example MCBSP_SUPPORT Constant Description Compile-time constant MCBSP_SUPPORT Compile-time constant that has a value of 1 if the device supports the McBSP module and 0 otherwise. Example #if (MCBSP_SUPPORT) /* user MCBSP configuration / #endif McBSP Module 16-21 .MCBSP_PIN_FSR . Currently. See MCBSP_open() Bit-mask of pin values (logical OR) . MCBSP_setPins(hMcbsp. hMcbsp pins Handle to McBSP port. MCBSP_PIN_FSX | MCBSP_PIN_DX ).MCBSP_PIN_FSX .

hMcbsp val Handle to McBSP port. 0 or 1 Arguments Return Value 16-22 . MCBSP_xempty Function Reads XEMPTY bit from SPCR register Uint32 MCBSP_xempty( MCBSP_Handle hMcbsp ). DXR void MCBSP_write( MCBSP_Handle hMcbsp. Uint32 val ). MCBSP_write(hMcbsp. See MCBSP_open() Returns XEMPTY bit of SPCR register. hMcbsp XRDY Handle to McBSP port. if (MCBSP_xempty(hMcbsp)) { … } MCBSP_xrdy Function Reads XRDY status bit of SPCR register Uint32 MCBSP_xrdy( MCBSP_Handle hMcbsp ). See MCBSP_open() Returns XRDY status bit of SPCR. See MCBSP_open() 32-bit data value Arguments Return Value Description Example none Use this function to directly write a 32-bit value to the serial port data transmit register.MCBSP_write MCBSP_write Function Writes 32-bit value directly to serial port data transmit register. DXR. 0 or 1 Arguments Return Value Description Example Reads the XEMPTY bit from the SPCR register. A 0 indicates the transmit shift (XSR) is empty. hMcbsp XEMPTY Handle to McBSP port.0x12345678).

hMcbsp XSYNCERR Handle to McBSP port. See MCBSP_open() Returns XSYNCERR bit of the SPCR register.4. A 1 indicates the transmitter is ready to be written to. See MCBSP_open() Receiver event ID Arguments Return Value Description Example Retrieves the receive event ID for the given port.MCBSP_xsyncerr Description Example Reads the XRDY status bit of the SPCR register. if (MCBSP_ xsyncerr(hMcbsp)) { … } 16.3 Interrupt Control Functions MCBSP_getRcvEventId Function Retrieves transmit event ID for given port Uint32 MCBSP_getRcvEventId( MCBSP_Handle hMcbsp ). . McBSP Module 16-23 . A 1 indicates a transmitter frame sync error.. hMcbsp Receive Event ID Handle to McBSP port. RecvEventId = MCBSP_getRcvEventId(hMcbsp). IRQ_enable(RecvEventId).. 0 or 1 Arguments Return Value Description Example Reads the XSYNCERR status bit of the SPCR register. Uint32 RecvEventId. if (MCBSP_xrdy(hMcbsp)) { … } MCBSP_xsyncerr Function Reads XSYNCERR status bit of SPCR register Uint32 MCBSP_xsyncerr( MCBSP_Handle hMcbsp ).

.MCBSP_getXmtEventId MCBSP_getXmtEventId Function Retrieves transmit event ID for given port Uint32 MCBSP_getXmtEventId( MCBSP_Handle hMcbsp ). Uint32 XmtEventId. See MCBSP_open() Event ID of transmitter Arguments Return Value Description Example Transmit Event ID Retrieves the transmit event ID for the given port.. XmtEventId = MCBSP_getXmtEventId(hMcbsp). 16-24 . hMcbsp Handle to McBSP port.. IRQ_enable(XmtEventId).

. . .Chapter 17 MDIO Module This chapter describes the MDIO module. . . . . . . . . . . . . . . .3 Functions . . . Topic Page 17. . . . . . . . . . . . . . and provides an MDIO reference section. . . . . . . . . . . . . . . . . . . . . 17-2 17. . . . . . . 17-3 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Macros . . . . . . . . . . . . . . . . . . . . . . . .1 Overview . . 17-4 17-1 . . . . . . . . . . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . .

Table 17−1. The module is designed to allow almost transparent operation of the MDIO interface.Overview 17. MDIO Functions and Constants Syntax MDIO_close MDIO_getStatus MDIO_initPHY MDIO_open MDIO_phyRegRead MDIO_phyRegWrite MDIO_SUPPORT MDIO_timerTick Type Description F F F F F F C F Close the MDIO peripheral and disables further operation Called to get the status of the MDIO/PHY Force a switch to the specified PHY. with very little maintenance from the core processor. When used in a multitasking environment. and start negotiation Opens the MDIO peripheral and starts searching for a PHY device Raw data read of a PHY register Raw data write of a PHY register A compile-time constant whose value is 1 if the device supports the MDIO module Called to signify that approx 100mS have elapsed See page 17-4 17-4 17-5 17-5 17-6 17-6 17-7 17-7 17-2 . It is not necessary for the application to call any MDIO functions directly when the CSL EMAC module is in use. retrieve the negotiation results. In the function descriptions. Table 17−1 lists the functions and constants available in the CSL MDIO module. no MDIO function may be called while another MDIO function is operating on the same device handle in another thread. It is the responsibility of the application to assure adherence to this restriction. uint is defined as unsigned int and Handle as void*. When using the CSL EMAC module. and configure required parameters in the EMAC module for correct operation.1 Overview The management data input/output (MDIO) module implements the 802. the EMAC module makes use of this MDIO module. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus.

and those that construct register and field values. and Table 17−3 lists the MDIO macros that construct register and field values.fieldval) MDIO_FSETS(<REG>.<SYM>) MDIO_<REG>_<FIELD>_DEFAULT MDIO_FMK() MDIO_FMKS() MDIO_<REG>_<FIELD>_<SYM> Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Field default value Field make Field make symbolically Field symbolic value See page Table 17−3. Table 17−2 lists the MDIO macros that access registers and fields.<FIELD>) MDIO_FSET(<REG>. The macros themselves are found in Chapter 28. MDIO Macros that Construct Register and Field Values Macro Description/Purpose See page MDIO Module 17-3 .x) MDIO_FGET(<REG>. Using the HAL Macros. MDIO Macros That Access Registers and Fields Macro MDIO_ADDR(<REG>) MDIO_RGET(<REG>) MDIO_RSET(<REG>.Macros 17.<FIELD>.2 Macros There are two types of MDIO macros: those that access registers and fields.<FIELD>. Table 17−2.

pLinkStatus)... uint *pLinkStatus. Handle hMDIO None Closes the MDIO peripheral and disable further operation. Handle hMDIO uint *pPhy Pointer to store physical address uint *pLinkStatus Pointer to store Link Status None Called to get the status of the MDIO/PHY Handle hMDIO. pPhy... . hMDIO = MDIO_open(0).3 Functions MDIO_close Function Close the MDIO peripheral and disables further operation void MDIO_close( Handle hMDIO ). See MDIO_open for more details Handle hMDIO. uint *pPhy. uint *pPhy. . MDIO_close(hMDIO). MDIO_getStatus(hMDIO. Arguments Return Value Description Example MDIO_getStatus Function Called to get the status of the MDIO/PHY void MDIO_getStatus( Handle hMDIO. Arguments Return Value Description Example 17-4 . uint *pLinkStatus ).MDIO_close 17.

It is assumed that the MDIO module is reset prior to calling this function.. . and start negotiation uint MDIO_initPHY( Handle hMDIO. This call is only used to override the normal PHY detection process. Returns 1 if the PHY selection completed OK. else 0 Handle hMDIO.. retStat = MDIO_initPHY(hMDIO. . Handle hMDIO uint phyAddr uint Force a switch to the specified PHY. Handle hMDIO. hMDIO = MDIO_open(MDIO_MODEFLG_HD10).. 0).MDIO_initPHY MDIO_initPHY Function Force a switch to the specified PHY. uint retStat. and start negotiation. Arguments Return Value Description Example MDIO_open Function Opens the MDIO peripheral and starts searching for a PHY device Handle MDIO_open( uint mdioModeFlags ). Arguments Return Value Description Example MDIO Module 17-5 . uint mdioModeFlags Mode flags for initializing device void* Opens the MDIO peripheral and start searching for a PHY device.. uint phyAddr ).

retStat = MDIO_phyRegRead(0. uint phyIdx PHYADR value uint phyReg REGADR value Uint16 data Data to be written uint Raw data write of a PHY register. 0. Arguments Return Value Description Example 17-6 .. Uint16 *pData. ..MDIO_phyRegRead MDIO_phyRegRead Raw data read of a PHY register Function uint MDIO_phyRegRead( uint phyIdx. uint phyReg. else 0 uint retStat. Uint16 *pData ). Arguments Return Value Description Example MDIO_phyRegWrite Raw data write of a PHY register Function uint MDIO_phyRegWrite( uint phyIdx. . Returns 1 if the PHY ACK’d the read. uint phyReg. 0).. else 0 uint retStat. Returns 1 if the PHY ACK’d the write.. Uint16 data ). uint phyIdx PHYADR value uint phyReg REGADR value Uint16 *pData Pointer to store data read uint Raw data read of a PHY register. 0. retStat = MDIO_phyRegWrite(0. pData).

.. evtCode = MDIO_timerTick(hMDIO). Handle hMDIO uint Called to signify that approx 100 mS have elapsed Returns an MDIO event code (see MDIO Events in csl_mdio. You are not required to use this constant.. uint evtCode. MDIO_timerTick Function Called to signify that approximately 100 mS have elapsed uint MDIO_timerTick( Handle hMDIO ).h) Handle hMDIO.MDIO_SUPPORT MDIO_SUPPORT Constant Description Compile-time constant MDIO_SUPPORT Compile-time constant that has a value of 1 if the device supports the MDIO module and 0 otherwise. Arguments Return Value Description Example MDIO Module 17-7 .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18. . . . . . . . . . . . . .3 Configuration Structure . . . . . . . . . . . .2 Macros . . .1 Overview . . . . . . . . . . and provides a PCI API reference section. . . . . . . . 18-7 18-1 . . . . . . . . . . . discusses the three application domains. 18-4 18. . . . . . . . . . . . . . . . . . . . .4 Functions . . . . . . . . . . . . . . 18-6 18. . . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . Topic Page 18. . . . . . . . . . . . . . . . . . . . . . .Chapter 18 PCI Module This chapter describes the PCI module. . . . . . . . . . . . . . . . . . . . . . .

Table 18−1. PCI Configuration Structure Syntax PCI_ConfigXfr Type Description S PCI configuration structure See page . 18-7 18-7 18-7 18-8 18-8 18-8 18-9 18-9 18-9 18-10 18-10 18-10 Note: F = Function. and erase (starting with the prefix eeprom) .. C = Constant † Not supported by 6415/6416 devices 18-2 .. PCI APIs Syntax PCI_curByteCntGet PCI_curDspAddrGet PCI_curPciAddrGet PCI_dspIntReqClear PCI_dspIntReqSet PCI_eepromErase PCI_eepromEraseAll PCI_eepromIsAutoCfg PCI_eepromRead PCI_eepromSize PCI_eepromTest PCI_eepromWrite Type Description F F F F F F F F F F F F Returns the current number of bytes left (CCNT) Returns the current DSP address (CDSPA) Returns the current PCI address (CPCIA) Clears the DSP-to-PCI interrupt request bit Sets the DSP-to-PCI interrupt request bit Erases the specified EEPROM 16-bit address Erases the whole EEPROM Tests if the PCI reads the configure values from EEPROM Reads a 16-bit data from the EEPROM Returns EEPROM size Tests if EEPROM present Writes a 16-bit data into the EEPROM See page .APIs that are dedicated to EEPROM operations such as write..Overview 18.1 Overview The PCI module APIs cover the following three application domains: .APIs that are dedicated to power management Table 18−1 lists the configuration structure for use with the PCI functions. read. 18-6 Table 18−2. Table 18−2 lists the functions and constants available in the CSL PCI module..APIs that are dedicated to DSP-PCI Master transfers (mainly starting with the prefix xfr) .

18-11 18-11 18-11 18-12 18-12 18-12 18-13 18-13 18-13 18-14 18-14 18-15 18-15 18-16 18-16 18-16 18-17 18-17 Note: F = Function.. PCI APIs (Continued) Syntax PCI_eepromWriteAll PCI_EVT_NNNN PCI_inClear PCI_intDisable PCI_intEnable PCI_intTest PCI_pwrStatTest† PCI_pwrStatUpdate† PCI_SUPPORT PCI_xfrByteCntSet PCI_xfrConfig PCI_xfrConfigArgs PCI_xfrEnable † PCI_xfrFlush PCI_xfrGetConfig PCI_xfrHalt† PCI_xfrStart PCI_xfrTest Type Description F C F F F F F F C F F F F F F F F F Writes a 16-bit data through the whole EEPROM PCI events Clears the specified event flag of PCIIS register Disables the specified PCI event Enables the specified PCI event Tests an event to see if its flag is set in the PCIIS Tests if Current State is equal to Requested State Updates the Power-Management State Compile time constant Sets the number of bytes to be transferred Configures the PCI registers related to the data transfer between the DSP and PCI Configures the PCI registers related to the data transfer between the DSP and PCI Enables the internal transfer request to the auxiliary DMA channel Flushes the current transaction Returns the current PCI register setting related to the transfer between the DSP and PCI Prevents the PCI from performing an auxiliary..Overview Table 18−2. C = Constant † Not supported by 6415/6416 devices PCI Module 18-3 . DMA transfer request Enables the specified transaction Tests if the transaction is complete See page .

<FIELD>.x) PCI_FGET(<REG>.<FIELD>) PCI_FSETA(addr.2 Macros There are two types of PCI macros: those that access registers and fields. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 18-4 .<FIELD>. Table 18−3.x) PCI_FGETA(addr.. PCI macros are not handle-based. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page . Table 18−3 lists the PCI macros that access registers and fields. and those that construct register and field values.<FIELD>) PCI_FSET(<REG>. and Table 18−4 lists the PCI macros that construct register and field values.<REG>.<FIELD>.. PCI Macros that Access Registers and Fields Macro PCI_ADDR(<REG>) PCI_RGET(<REG>) PCI_RSET(<REG>.<REG>.<REG>) PCI_RSETA(addr.fieldval) PCI_FSETS(<REG>.<REG>. The macros themselves are found in Chapter 28.<SYM>) PCI_RGETA(addr.<REG>. fieldval) PCI_FSETSA(addr.Macros 18. Using the HAL Macros.<FIELD>.

Field default value Field make Field make symbolically Field value of ..... PCI Macros that Construct Register and Field Values Macro PCI_<REG>_DEFAULT PCI_<REG>_RMK() PCI_<REG>_OF() PCI_<REG>_<FIELD>_DEFAULT PCI_FMK() PCI_FMKS() PCI_<REG>_<FIELD>_OF() PCI_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of ..Macros Table 18−4. Field symbolic value See page . 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 PCI Module 18-5 ..

/* dspma register Addr to be read*/ 0xFBE80000. You can create and initialize this structure then pass its address to the PCI_xfrConfigA() function. Description Example 18-6 . PCI_ConfigXfr myXfrConfig = { 0x80000000. You can use literal values. PCI_xfrConfig(&myXfrConfig).3 Configuration Structure PCI_ConfigXfr Structure Members Structure that sets up registers related to master transfer PCI_ConfigXfr dspma DSP master address register pcima PCI master address register pcimc PCI master control register (For C64x devices only) trctl PCI transfer request control register This is the PCI configuration structure used to set up the registers related to the master transfer. /* pcima register XBIAS1 CPLD addr*/ 0x00040000 /* pcimc register 4-byte transfer*/ ).PCI_ConfigXfr 18.

none DSP Address Returns the current DSP Address of the master transactions. PCI_curPciAddrGet Function Arguments Return Value Description Example Returns current PCI address Uint32 PCI_curPciAddrGet(). none PCI Address Returns the current PCI Address of the master transactions. Uint32 pciAddr. pciAddr = PCI_curPciAddrGet().PCI_curByteCntGet 18.4 Functions PCI_curByteCntGet Function Arguments Return Value Description Example Returns number of bytes left (CCNT) Uint32 PCI_curByteCntGet(). Uint32 nbBytes. Uint32 dspAddr. PCI_curDspAddrGet Returns current DSP address Function Arguments Return Value Description Example Uint32 PCI_curDspAddrGet(). dspAddr = PCI_curDspAddrGet(). PCI Module 18-7 . none number of bytes Returns number of bytes left on the current master transaction. nbBytes = PCI_curByteCntGet().

18-8 . The “Enable Write EWEN” is performed under this function. PCI_dspIntReqSet(). PCI_dspIntReqClear(). PCI_eepromErase Function Erases specified EEPROM byte Uint32 PCI_eepromErase( Uint32 eeaddr ).PCI_dspIntReqClear PCI_dspIntReqClear Clears DSP-to-PCI interrupt request bit Function Arguments Return Value Description Example void PCI_dspIntReqClear(). Uint32 success. none none Sets the DSP-to-PCI interrupt request bit of the RSTSRC register. success = PCI_eepromErase(0x00000002). eeaddr address of the 16-bit data to be erased Arguments Return Value Description Example 0 or 1 (success) Erases the 16-bit data at the specified address. PCI_dspIntReqSet Sets DSP-to-PCI interrupt request bit Function Arguments Return Value Description Example void PCI_dspIntReqSet(). none none Clears the DSP-to-PCI interrupt request bit of the RSTSRC register.

PCI_eepromEraseAll PCI_eepromEraseAll Erases entire EEPROM Function Arguments Return Value Description Example Uint32 PCI_eepromEraseAll() none address of the 16-bit data to be erased 0 or 1 (success) Erases the full EEPROM. PCI_eepromRead Function Reads 16-bit data from EEPROM Uint16 PCI_eepromRead( Uint32 eeaddr ). Uint32 x. x = PCI_eepromIsAutoCfg(). none 0 or 1 Tests if the PCI reads configure-values from EEPROM. eeaddr Address of the 16-bit data to be read from EEPROM. PCI_eepromIsAutoCfg Function Arguments Return Value Description Example Tests if PCI reads configure-values from EEPROM Uint32 PCI_eepromIsAutoCfg(). Returns value of the EEAI field of EECTL register. Uint16 eepromdata. success = PCI_eepromEraseAll(). eepromdata = PCI_eepromRead(0x00000001). Arguments Return Value Description Example value of the 16-bit data Reads the 16-bit data at the specified address from EEPROM. PCI Module 18-9 . Uint32 success.

eeaddr eedata Address of the byte to read from EEPROM. Example PCI_eepromTest Function Arguments Return Value Description Example Tests if EEPROM is present Uint32 PCI_eepromTest(). none value of the size code Returns the code associated with the size of the EEPROM. eepromSZ = PCI_eepromSize().0x2 :010 2K_EEPROM . . none 0 or 1 Tests if EEPROM is present by reading the code size bits EESZ[2:0] Uint32 eepromIs.0x0 :000 No EEPROM present .PCI_eepromSize PCI_eepromSize Function Arguments Return Value Description Returns EEPROM size Uint32 PCI_eepromSize(). 16-bit data to be written. eepromIs = PCI_eepromTest(). PCI_eepromWrite Function Writes 8-bit data into EEPROM Uint32 PCI_eepromWrite( Uint32 eeaddr.0x4 :100 16K_EEPROM Uint32 eepromSZ. Uint16 eedata ). Arguments Return Value 18-10 0 or 1 .0x1 :001 1K_EEPROM .0x3 :011 4K_EEPROM (6415/6416 devices support the 4K_EEPROM only) .

PCI_eepromWriteAll Writes 16-bit data into entire EEPROM Function Uint32 PCI_eepromWriteAll( Uint16 eedata ). PCI_EVT_NNN Constant PCI events (PCIIEN register) PCI_EVT_DMAHALTED PCI_EVT_PRST PCI_EVT_EERDY PCI_EVT_CFGERR PCI_EVT_CFGDONE PCI_EVT_MASTEROK PCI_EVT_PWRHL PCI_EVT_PWRLH PCI_EVT_HOSTSW PCI_EVT_PCIMASTER PCI_EVT_PCITARGET PCI_EVT_PWRMGMT These are the PCI events. refer to the TMS320C6000 Peripherals Reference Guide (SPRU190). x = PCI_eepromWrite(0x123. The “Enable Write EWEN” is performed under this function. Arguments Return Value Description Example 16-bit data to be written. eventPci See PCI_EVT_NNNN for a complete list of PCI events. eedata 0 or 1 Writes the 16-bit data into the entire EEPROM. For more details regarding these events. PCI Module 18-11 Arguments .0x8888). Description PCI_intClear Function Clears the specified event flag void PCI_intClear( Uint32 eventPci ). Uint16 x.PCI_eepromWriteAll Description Example Writes the 16-bit data into the specified EEPROM address. x = PCI_eepromWriteAll(0x1234). Uint16 x.

Arguments 18-12 . Arguments Return Value Description Example See PCI_EVT_NNNN for a complete list of PCI events. Arguments Return Value Description Example See PCI_EVT_NNNN for a complete list of PCI events. PCI_intDisable(PCI_EVT_MASTEROK). eventPci See PCI_EVT_NNNN for a complete list of PCI events. PCI_intClear(PCI_EVT_MASTEROK).PCI_intDisable Return Value Description Example none Clears the specified event flag of PCIIS register by writing ’1’ to the associated bit. eventPci none Enables the specified PCI event. PCI_intDisable Function Disable specified PCI event void PCI_intDisable( Uint32 eventPci ). PCI_intEnable(PCI_EVT_MASTEROK). PCI_intEnable Function Enables specified PCI event void PCI_intEnable( Uint32 eventPci ). PCI_intTest Function Test if specified PCI event flag is set Uint32 PCI_intTest( Uint32 eventPci ). eventPci none Disables the specified PCI event.

PCI_pwrStatUpdate Updates current state of power management Function Arguments Return Value Description Example void PCI_pwrStatUpdate(). You are not required to use this constant. Uint32 x.PCI_pwrStatTest Return Value Description Example 0 or 1 Tests if the specified event flag was set in the PCIIS register. PCI_SUPPORT Constant Description Compile-time constant PCI_SUPPORT Compile-time constant that has a value of 1 if the device supports the PCI module and 0 otherwise. PCI Module 18-13 . PCI_pwrStatTest(). x = PCI_intTest(PCI_EVT_MASTEROK). none none Updates the current state field of the PWDSRC register with the request state field value (not supported by 64x devices). PCI_pwrStatTest Function Arguments Return Value Tests if DSP has changed state Uint32 PCI_pwrStatTest(). none Returns the following value if state change has occurred: - 0:No State change request 1: Requested State D0/D1 2: Requested State D2 3: Requested State D3 Description Example Tests if the DSP has received an event related to a state change (not supported by 64x devices). PCI_pwrStatUpdate().

all devices support this module. config none Sets up the PCI registers related to the master transfer using the configuration structure. PCI_ConfigXfr myXfrConfig = { 0x80000000. /* pcima reg CPLD XBISA */ 0x0004000 /* pcimc register */ ). See also PCI_xfrConfigArgs() and PCI_ConfigXfr. nbbyte 0 or 1 Sets the number of bytes to transfer. Arguments Return Value Description Pointer to an initialized configuration structure. /* maximum of bytes */ Arguments Return Value Description Example Number of bytes to be transferred for the next transaction. The values of the structure are written to the PCI registers. 1 < nbbyte < 65K max PCI_xfrConfig Function Sets up registers related to master transfer using config structure void PCI_xfrConfig( PCI_ConfigXfr *config ). PCI_xfrConfig(&myXfrConfig).PCI_xfrByteCntSet Currently. Example 18-14 . /* dspma reg location data (src or dst)*/ 0xFBE8000. Example #if (PCI_SUPPORT) /* user PCI configuration */ #endif PCI_xfrByteCntSet Sets number of bytes to be transferred Function void PCI_xfrByteCntSet( Uint16 nbbyte ). PCI_xfrByteCntSet(0xFFFF).

PCI_xfrConfigArgs PCI_xfrConfigArgs Sets up registers related to master transfer using register values Function void PCI_xfrConfigArgs( Uint32 dspma. /* dspma register */ 0xFBE00000. none none Enables the internal transfer request to the auxilliary DMA channel by clearing the HALT bit field of the HALT register (C620x/C670x only. not supported by 64x devices). The register values are written to the PCI registers. PCI_xfrConfigArgs{ 0x80001000. /* pcima register CPLD XBISA DSP reg*/ 0x0100000 /* pcimc register 256-byte transfer*/ ). Uint32 pcima. dspma DSP master address register value pcima PCI master address register value pcimc PCI master control register value For C64x devices only) trctl PCI transfer request control register none Sets up the PCI registers related to the master transfer using the register values passed in. Uint32 pcimc Uint32 trctl (For C64x devices only) ). See also PCI_xfrConfig(). PCI_xfrEnable(). Example PCI Module 18-15 . Arguments Return Value Description Example PCI_xfrEnable Function Arguments Return Value Description Enables internal transfer request to auxiliary DMA channel void PCI_xfrEnable().

none none Halts the internal transfer requests to the auxilliary DMA channel by setting the HALT bit field of the HALT register (C620x/C670x only.PCI_xfrFlush PCI_xfrFlush Function Arguments Return Value Description Example Flushes current transaction void PCI_xfrFlush(). The values of the PCI register are written to the configuration structure. The transfer will stop and the FIFOs will be flushed. PCI_xfrGetConfig(&myXfrConfig). none none Flushes the current transaction. See also PCI_ConfigXfr. Arguments Return Value Description Pointer to the returned configuration structure. not supported by 64x devices). PCI_xfrGetConfig Function Reads configuration by returning values through config structure void PCI_xfrGetConfig( PCI_ConfigXfr *config ). PCI_xfrHalt(). config none Reads the current PCI configuration by returning values through the configuration structure. PCI_ConfigXfr myXfrConfig. Example PCI_xfrHalt Function Arguments Return Value Description Terminates internal transfer requests to auxilliary DMA channel void PCI_xfrHalt(). PCI_xfrFlush(). Example 18-16 .

PCI_PCIMC_START_READPREF: Start a master read transaction to prefetchable memory .PCI_PCIMC_START_CONFIGREAD: Start a configuration read .PCI_PCIMC_START_IOWRITE: Start an I/O write .PCI_xfrStart PCI_xfrStart Function Starts transaction void PCI_xfrStart( Uint32 modeXfr ).PCI_WRITE or 0x1 . PCI_xfrTest Function Arguments Return Value Description Tests if current transaction is complete Uint32 PCI_xfrTest().PCI_PCIMC_START_READNOPREF: Start a master read transaction to nonprefetchable memory . Example PCI Module 18-17 .PCI_PCIMC_START_FLUSH: Transaction not started/flush current transaction . PCI_xfrStart(PCI_WRITE).PCI_PCIMC_START_WRITE: Start a master write transaction .PCI_READ_PREF or 0x2 .PCI_PCIMC_START_CONFIGWRITE: Start a configuration write . modeXfr Specified one of the following transfer modes (macros): .PCI_PCIMC_START_IOREAD: Start an I/O read PCI_xfrTest().PCI_READ_NOPREF or 0x3 Arguments Return Value Description Example none Starts the specified transaction. none 0 to 7 Tests the status of the master transaction and returns one of the following status values: .

. . . . . . . . . . . . . . . . . . 19-7 19-1 . . . . . . . . . and provides a PLL API reference section. . . . . . . . . .1 Overview . . . . . . . . . . . . . . . . . . . . . . .4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Topic Page 19. . . . . . . . . . . . . . . 19-4 19. . . . .2 Macros . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Chapter 19 PLL Module This chapter describes the PLL module. . .3 Configuration Structures . . . . . . . 19-6 19. . . . . . . 19-2 19. . . . . . . . . . . . discusses the three application domains. . . . . . . . . . . . . . . . .

19-7 19-7 19-8 19-8 19-9 19-9 19-9 19-10 19-10 19-11 19-11 19-11 19-12 19-12 19-12 19-13 19-2 . C = Constant Type Description F F F F F F F F F F F F F F F F Sets the PLL in bypass mode Checks and returns the oscillator input stable condition Configures the PLL using the configuration structure Configures the PLL using register fields as arguments Releases the PLL from reset Disables the oscillator divider OD1 Disables the specified divider Enables the PLL Enables the oscillator divider OD1 Enables the specified divider Reads the current PLL controller configuration values Returns the PLL multiplier value Returns the oscillator divide ratio Returns the PLL divide ratio Initializes the PLL using the PLL_Init structure Sets the PLL in operational mode See page . Table 19−1 lists the configuration structure for use with the PLL functions. PLL Configuration Structures Syntax PLL_Config PLL_Init Type Description S S Structure used to configure the PLL controller Structure used to initialize the PLL controller See page .. Table 19−1..Overview 19.. PLL APIs Syntax PLL_bypass PLL_clkTest PLL_config PLL_configArgs PLL_deassert PLL_disableOscDiv PLL_disablePllDiv PLL_enable PLL_enableOscDiv PLL_enablePllDiv PLL_getConfig PLL_getMultiplier PLL_getOscRatio PLL_getPllRatio PLL_init PLL_operational Note: F = Function.1 Overview This module provides functions and macros to configure the PLL controller. 19-6 19-6 Table 19−2.. The PLL controller peripheral is in charge of controlling the DSP clock. Table 19−2 lists the functions and constants available in the CSL PLL module.

The PLL can also be initialized based on parameters by passing a PLL_Init structure to the PLL_init() function. the _RMK(make) macros construct register values based on field values... PLL APIs (Continued) Syntax PLL_pwrdwn PLL_reset PLL_setMultiplier PLL_setOscRatio PLL_setPllRatio PLL_SUPPORT Note: F = Function.1 Using the PLL Controller The PLL controller can be used by passing an initialized PLL_Config structure to PLL_config() or by passing register values to the PLL_configArgs() function. PLL Module 19-3 . To assist in creating register values. the symbol constants may be used for the field values.1.Overview Table 19−2. C = Constant Type Description F F F F F C Sets the PLL in power down state Resets the PLL Sets the PLL multiplier value Sets the oscillator divide ratio (CLKOUT3 divider) Sets the PLL divide ratio A compile time constant whose value is 1 if the device supports PLL See page . 19-13 19-14 19-14 19-14 19-15 19-16 19. In addition.

<SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page .x) PLL_FGET(<REG>. and Table 19−4 lists the PLL macros that construct register and field values.Macros 19.<FIELD>.<FIELD>) PLL_FSETA(addr..<FIELD>.x) PLL_FGETA(addr. The macros themselves are found in Chapter 28. PLL macros are not handle-based.fieldval) PLL_FSETS(<REG>.2 Macros There are two types of PLL macros: those that access registers and fields. Using the HAL Macros. fieldval) PLL_FSETSA(addr.<FIELD>) PLL_FSET(<REG>.<FIELD>. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 19-4 .<FIELD>. PLL Macros that Access Registers and Fields Macro PLL_ADDR(<REG>) PLL_RGET(<REG>) PLL_RSET(<REG>.<SYM>) PLL_RGETA(addr. and those that construct register and field values.<REG>..<REG>) PLL_RSETA(addr.<REG>. Table 19−3. Table 19−3 lists the PLL macros that access registers and fields.<REG>.<REG>.

Macros Table 19−4... Field default value Field make Field make symbolically Field value of .. PLL Macros that Construct Register and Field Values Macro PLL_<REG>_DEFAULT PLL_<REG>_RMK() PLL_<REG>_OF() PLL_<REG>_<FIELD>_DEFAULT PLL_FMK() PLL_FMKS() PLL_<REG>_<FIELD>_OF() PLL_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of .. Field symbolic value See page . 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 PLL Module 19-5 ...

PLL_Config 19.3 Configuration Structures PLL_Config Structure Members Structure used to configure the PLL controller PLL_Config Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 pllcsr PLL control/status register pllm PLL multiplier control register plldiv0 PLL controller divider 0 register plldiv1 PLL controller divider 1 register plldiv2 PLL controller divider 2 register plldiv3 PLL controller divider 3 register oscdiv1 Oscillator divider 1 register Description This is the PLL configuration structure used to configure the PLL controller. The user should create and initialize this structure before passing its address to the PLL_config() function. 19-6 . The user should create and initialize this structure before passing its address to the PLL_init() function. PLL_Init Structure Members Structure used to initialize the PLL controller PLL_Init Uint32 Uint32 Uint32 Uint32 Uint32 Uint32 mdiv d0ratio d1ratio d2ratio d3ratio od1ratio PLL multiplier PLL divider 0 ratio PLL divider 1 ratio PLL divider 2 ratio PLL divider 3 ratio Oscillator divider 1 ratio Description This is the PLL initialization structure used to initialize the PLL controller.

none Uint32 Oscillator condition . none none This function sets the PLL in bypass mode wherein Divider D0 and PLL are bypassed. SYSCLK1 to SYSCLK3 are divided down directly from the input reference clock.0 − Not stable . PLL_bypass(). Arguments Return Value Description Example PLL_clkTest Function Checks and returns the oscillator input stable condition void Uint32 PLL_clkTest( void ). 0 − OSCIN/CLKIN input not yet stable.4 Functions PLL_bypass Function Sets the PLL in bypass mode void PLL_bypass( void ). This is true if the synchronous counter has not finished counting.1 − Stable Arguments Return Value Description This function checks and returns the oscillator input stable condition. 1 − OSCIN/CLKIN input is stable.PLL_bypass 19. PLL Module 19-7 . val = PLL_clkTest(). This is true if any one of the following three cases is true: H Synchronous counter has finished counting the number of OSCIN/CLKIN cycles H Synchronous counter is disabled H Test mode Example Uint32 val.

0x800A. Arguments Return Value Description Pointer to the configuration structure Example PLL_configArgs Function Configures the PLL controller using register fields as arguments void PLL_configArgs( Uint32 pllcsr.0x800D. The values of the structure variables are written to the PLL controller registers.. PLL_configArgs(0x8000.0x800B..PLL_config PLL_config Function Configures the PLL using the configuration structure void PLL_config( PLL_Config *myConfig ). Uint32 plldiv1. Uint32 oscdiv1 ) pllcsr PLL control/status register pllm PLL multiplier control register plldiv0 PLL controller divider 0 register plldiv1 PLL controller divider 1 register plldiv2 PLL controller divider 2 register plldiv3 PLL controller divider 3 register oscdiv1 Oscillator divider 1 register none This function configures the PLL controller as per the register field values given. Uint32 plldiv3.0x0009).0x01. Uint32 plldiv0. PLL_config(&MyConfig). Uint32 pllm. myConfig none This function configures the PLL controller using the configuration structure. Uint32 plldiv2. PLL_Config MyConfig . Arguments Return Value Description Example 19-8 .0x800C.

Arguments Return Value Description Example PLL_disablePllDiv Disables the specified divider Function void PLL_disablePllDiv( Uint32 divId ). PLL_deassert(). divId Divider ID . none none This function releases the PLL from reset.PLL_DIV3 − Divider 3 Arguments Return Value none PLL Module 19-9 .PLL_deassert PLL_deassert Function Releases the PLL from reset void PLL_deassert( void ).PLL_DIV1 − Divider 1 .PLL_DIV0 − Divider 0 . Arguments Return Value Description Example PLL_disableOscDiv Disables the oscillator divider OD1 Function void PLL_disableOscDiv( void ).PLL_DIV2 − Divider 2 . PLL_disableOscDiv(). none none This function disables the oscillator divider OD1.

Note that here divider D0 is not bypassed. Arguments Return Value Description Example PLL_enableOscDiv Enables the oscillator divider OD1 Function void PLL_enableOscDiv( void ). none none This function enables the oscillator divider OD1. none none This function enables the PLL and sets it in ’PLL’ mode. SYSCLK1 to SYSCLK3 are divided down directly from the input reference clock.PLL_enable Description Example This function disables the divider specified by the ’divId’ parameter. PLL_enable(). PLL_enable Function Enables the PLL void PLL_enable( void ). PLL_enableOscDiv(). Arguments Return Value Description Example 19-10 . PLL_disablePllDiv(PLL_DIV0).

. . PLL_getConfig Function Reads the current PLL controller configuration values void PLL_getConfig( PLL_Config *myConfig ).PLL_DIV1 − Divider 1 . PLL_enablePllDiv(PLL_DIV0). myConfig none This function gets the current PLL configuration values.PLL_enablePllDiv PLL_enablePllDiv Function Enables the specified divider void PLL_enablePllDiv( Uint32 divId ). divId Divider ID . none PLL Module 19-11 Arguments . PLL_getConfig(&pllCfg). PLL_Config pllCfg.PLL_DIV0 − Divider 0 .PLL_DIV2 − Divider 2 . Arguments Return Value Description Example Pointer to the configuration structure PLL_getMultiplier Function Returns the PLL multiplier value Uint32 PLL_getMultiplier( void ).PLL_DIV3 − Divider 3 Arguments Return Value Description Example none This function enables the divider specified by the ’divId’ parameter..

see PLL_setPllRatio(). val = PLL_getOscRatio(). Arguments Return Value Description Example This function returns the PLL divide ratio. Arguments 19-12 . PLL_getPllRatio Function Returns the PLL divide ratio Uint32 PLL_getPllcRatio( void ). See PLL_setPllRatio(). val = PLL_getPllRatio(PLL_DIV0). For PLL multiplier values. See PLL_setOscRatio(). PLL_init Function Initialize PLL using PLL_Init structure void PLL_init( PLL_Init *myInit ). This function gets the current PLL multiplier value. see PLL_setMultiplier(). none Uint32 Oscillator divide ratio. Uint32 val. divId Uint32 PLL divider ID. For oscillator divide values. see PLL_setOscRatio(). PLL_getOscRatio Function Returns the oscillator divide ratio Uint32 PLL_getOscRatio( void ). Arguments Return Value Description Example This function returns the oscillator divide ratio. PLL divide ratio. Uint32 val. myInit Pointer to the initialization structure. For PLL divide values. See PLL_setPllRatio(). Uint32 val.PLL_getOscRatio Return Value Description Example Uint32 PLL multiplier value. See PLL_setMultiplier(). val = PLL_getMultiplier().

PLL_init(&myInit). none none This function sets the PLL in operational mode. SYSCLK1 to SYSCLK3 are divided down directly from the input reference clock. Divider D0 and the PLL are bypassed. none none This function sets the PLL in power down state. The values of the structure variables are written to the corresponding PLL controller register fields. See PLL_pwrdwn(). .. This function enables the PLL and Divider 0 path. Example PLL_operational Function Sets PLL in operational mode void PLL_operational( void ). PLL_prwdwn(). PLL_Init myInit. Arguments Return Value Description Example PLL Module 19-13 . Arguments Return Value Description Example PLL_pwrdwn Function Sets the PLL in power down mode void PLL_pwrdwn( void )..PLL_operational Return Value Description none This function initializes the PLL controller using the PLL_Init structure. PLL_operational().

none none This function asserts reset to the PLL. 00011=x12. PLL_reset(). 00011=x8. 00011=x24. 00011=Not Supported Example PLL_setMultiplier(0x04). PLL multiplier select 00000 = x1 00001=x2 00000 = x5 00001=x6 00000 = x9 00001=x10 00000 = x13 00001=x14 00000 = x17 00001=x18 00000 = x21 00001=x22 00000 = x25 00001=x26 00000 = x29 00001=x30 Multiplier select Arguments Return Value Description 00010=x3 00010=x7 00010=x11 00010=x15 00010=x19 00010=x23 00010=x28 00010=x31 00011=x4.PLL_reset PLL_reset Function Resets the PLL device void PLL_reset( void ). PLL_setOscRatio Function Sets the oscillator divide ratio (CLKOUT3 divider) void PLL_setOscRatio( Uint32 val ). 00011=x16 00011=x20. val Divider values Arguments 19-14 . 00011=x28. val none This function sets the PLL multiplier value. Arguments Return Value Description Example PLL_setMultiplier Function Sets the PLL multiplier value void PLL_setMultiplier( Uint32 val ).

Divider values 00000 = /1 00000 = /5 00000 = /9 00000 = /13 00000 = /17 00000 = /21 00000 = /25 00000 = /29 Example 00001=/2 00001=/6 00001=/10 00001=/14 00001=/18 00001=/22 00001=/26 00001=/30 00010=/3 00010=/7 00010=/11 00010=/15 00010=/19 00010=/23 00010=/28 00010=/31 00011=/4. 00011=/24. 00011=/16 00011=/20.PLL_DIV1 − Divider 1 . 00011=/32 PLL_setOscRatio(0x05). divId Divider ID .PLL_DIV2 − Divider 2 . Uint32 val ). PLL Module 19-15 . 00011=/28.PLL_DIV3 − Divider 3 Arguments val Return Value Description none Divider values This function sets the divide ratio for the clock divider specified by the ’divId’ parameter. 00011=/12. 00011=/8. PLL_setPllRatio Function Sets the PLL divide ratio void PLL_setPllDiv( Uint32 divId.PLL_DIV0 − Divider 0 .PLL_setPllRatio Return Value Description none This function sets the oscillator divide ratio (CLKOUT3 divider).

00011=/12. 00011=/28. Divider values 00000 = /1 00000 = /5 00000 = /9 00000 = /13 00000 = /17 00000 = /21 00000 = /25 00000 = /29 Example 00001=/2 00001=/6 00001=/10 00001=/14 00001=/18 00001=/22 00001=/26 00001=/30 00010=/3 00010=/7 00010=/11 00010=/15 00010=/19 00010=/23 00010=/28 00010=/31 00011=/4. 00011=/8. PLL_SUPPORT Constant Description Compile time constant PLL_SUPPORT Compile-time constant that has a value of 1 if the device supports the PLL module and 0 otherwise. 00011=/16 00011=/20. only the C6713 device supports this module. You are not required to use this constant. 00011=/32 PLL_setPllDiv(PLL_DIV0. Example #if (PLL_SUPPORT) /* user PLL configuration */ #endif 19-16 .0x05). Currently.PLL_SUPPORT Description This function sets the divide ratio for the clock divider specified by the ’divId’ parameter. 00011=/24.

. 20-2 20. . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . . . . . Topic Page 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and provides a PWR API reference section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20. . . . . .4 Functions . . . . . . . . 20-5 20. 20-6 20-1 . . .Chapter 20 PWR Module This chapter describes the PWR module.1 Overview . . . .2 Macros . . . . . . . . . . .3 Configuration Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

and to invoke various power-down modes.. 20-6 20-6 20-7 20-7 20-8 20-2 .. PWR APIs Syntax PWR_config PWR_configArgs PWR_getConfig PWR_powerDown PWR_SUPPORT Note: F = Function. PWR Configuration Structure Syntax PWR_Config Purpose Structure used to set up the PWR options See page .1 Overview The PWR module is used to configure the power-down control registers.Overview 20. Table 20−1 lists the configuration structure for use with the PWR functions. Table 20−2 lists the functions and constants available in the CSL PWR module. C = Constant Type Description F F F F C Sets up the PWR register using the configuration structure Sets up the power-down logic using the register value passed in Reads the current PWR configuration values Forces the DSP to enter a power-down state A compile time constant whose value is 1 if the device supports the PWR module See page . if applicable. 20-5 Table 20−2... Table 20−1.

<REG>.<SYM>) PWR_RGETA(addr.<FIELD>) PWR_FSETA(addr. and Table 20−4 lists the PWR macros that construct register and field values..<FIELD>) PWR_FSET(<REG>. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page .<FIELD>. Table 20−3 lists the PWR macros that access registers and fields. fieldval) PWR_FSETSA(addr. PWR Macros that Access Registers and Fields Macro PWR_ADDR(<REG>) PWR_RGET(<REG>) PWR_RSET(<REG>.<REG>.<REG>) PWR_RSETA(addr.<FIELD>..x) PWR_FGETA(addr. PWR macros are not handle-based. and those that construct register and field values.Macros 20. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 PWR Module 20-3 .<REG>. Using the HAL Macros.<FIELD>.2 Macros There are two types of PWR macros: those that access registers and fields.x) PWR_FGET(<REG>.fieldval) PWR_FSETS(<REG>.<REG>.<FIELD>. The macros themselves are found in Chapter 28. Table 20−3.

.Macros Table 20−4. Field symbolic value See page .... PWR Macros that Construct Register and Field Values Macro PWR_<REG>_DEFAULT PWR_<REG>_RMK() PWR_<REG>_OF() PWR_<REG>_<FIELD>_DEFAULT PWR_FMK() PWR_FMKS() PWR_<REG>_<FIELD>_OF() PWR_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of . Field default value Field make Field make symbolically Field value of ... 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 20-4 .

Example PWR Module 20-5 . PWR_Config pwrCfg = { 0x00000000 }.PWR_Config 20.3 Configuration Structure PWR_Config Structure Members Description Structure used to set up the PWR options PWR_Config Uint32 pdctl Power-down control register (6202 and 6203 devices) This is the PWR configuration structure used to set up the PWR option of the 6202 device. You create and initialize this structure and then pass its address to the PWR_config() function. You can use literal values or the _RMK macros to create the structure member values. … PWR_config(&pwrCfg).

pdctl none Sets up the power-down logic using the register value passed in. config none Sets up the PWR register using the configuration structure. PWR_config(&pwrCfg). PWR_Config pwrCfg = { 0x00000000 }. PWR_configArgs Function Sets up power-down logic using register value passed in void PWR_configArgs( Uint32 pdctl ).4 Functions PWR_config Function Sets up the PWR register using the configuration structure void PWR_config( PWR_Config *config ). You may use the PWR_PDCTL_RMK macro to create the register value based on field values.PWR_config 20. 20-6 . Arguments Return Value Description Example Pointer to a configuration structure. Power-down control register value Arguments Return Value Description Example PWR_configArgs(0x00000000). You may use literal values for the argument or for readability.

PWR_getConfig(&pwrCfg).PWR_IDLE Arguments Return Value Description none Calling this function forces the DSP to enter a power-down state.PWR_PD1B . PWR_powerDown Forces DSP to enter power-down state Function void PWR_powerDown( PWR_MODE mode ). Example PWR Module 20-7 . config none Gets PWR current configuration value.PWR_NONE . PWR_powerDown(PWR_PD2).PWR_PD3 . Arguments Return Value Description Example Pointer to a configuration structure. Refer to the TMS320C6000 Peripherals Reference Guide (SPRU190) for a description of the power-down modes. PWR_Config pwrCfg.PWR_getConfig PWR_getConfig Function Reads the current PWR configuration values void PWR_config( PWR_Config *config ).PWR_PD1A .PWR_PD2 . mode Power-down mode: .

Example #if (PWR_SUPPORT) /* user PWR configuration / #endif 20-8 .PWR_SUPPORT PWR_SUPPORT Constant Description Compile-time constant PWR_SUPPORT Compile-time constant that has a value of 1 if the device supports the PWR module and 0 otherwise. all devices support this module. You are not required to use this constant. Currently.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21. . . . . . . . . . . . . . . . .1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . lists the API functions and macros within the module. . 21-2 21. . . . . . . . . . . . . . .Chapter 21 TCP Module This chapter describes the TCP module. . . . . . . . . . . . . .4 Functions . . . . . . . discusses how to use the TCP. . . . . . . . . . . .3 Configuration Structures . . 21-6 21. . . . . . 21-13 21-1 . . . . . . . . .2 Macros . . . . . . . . . . . . . . . . . . . . Topic Page 21. . . . . . . . . . . . . . . . . . . . . . . . . . . and provides a TCP API reference section. . . . . . . . .

. 21-8 21-9 21-10 Table 21−2.. Table 21−1 lists the configuration structures for use with the TCP functions. but the CPU must first configure the TCP control values. Table 21−2 lists the functions and constants available in the CSL TCP module. C = Constant F F F F C 21-14 21-14 21-15 21-15 21-16 21-2 .Overview 21. Table 21−1.1 Overview Currently. The TCP is intended to be serviced using the EDMA for most accesses.. 21-13 21-13 21-13 TCP_calcCountsSP F 21-13 TCP_calculateHd TCP_ceil TCP_deinterleaveExt TCP_demuxInput TCP_END_NATIVE Note: F = Function. TCP APIs Syntax TCP_calcSubBlocksSA TCP_calcSubBlocksSP TCP_calcCountsSA Type Description F F F Calculates the sub-blocks within a frame for standalone mode Calculates the sub-frames and -blocks within a frame for shared processing mode Calculates the number of elements for each data buffer to be transmitted to/from the TCP using the EDMA for standalone mode Calculates the number of elements for each data buffer to be transmitted to/from the TCP using the EDMA for shared processing mode Calculates hard decisions for shared processing mode Ceiling function De-interleaves extrinsics data for shared processing mode Demultiplexes input into two working data sets for shared processing mode Value indicating native endian format See page .. There are also a number of functions available to the CPU to monitor the TCP status and access decision and output parameter data. TCP Configuration Structures Syntax TCP_BaseParams TCP_ConfigIc TCP_Params Type Description S S S Structure used to set basic TCP parameters Structure containing the IC register values Structure containing all channel characteristics See page . there is one TMS320C6000™ device with a turbo coprocessor (TCP): the TMS320C6416.

. TCP APIs (Continued) Syntax TCP_END_PACKED32 TCP_errTest TCP_FLEN_MAX TCP_genIc TCP_genParams TCP_getAccessErr TCP_getAprioriEndian TCP_getExtEndian TCP_getFrameLenErr TCP_getIcConfig TCP_getInterEndian TCP_getInterleaveErr TCP_getLastRelLenErr TCP_getModeErr TCP_getNumIt TCP_getOutParmErr TCP_getProlLenErr TCP_getRateErr TCP_getRelLenErr TCP_getSubFrameErr TCP_getSysParEndian TCP_icConfig TCP_icConfigArgs Note: F = Function.Overview Table 21−2. 21-16 21-16 21-17 21-17 21-17 21-18 21-18 21-19 21-19 21-19 21-20 21-20 21-21 21-21 21-22 21-22 21-22 21-23 21-23 21-23 21-24 21-24 21-25 TCP Module 21-3 .. C = Constant Type Description C F F F F F F F C F F F F F F F F F F F F F F Value indicating little endian format within packed 32-bit words Returns the error bit of ERR register Maximum frame length Generates the TCP_ConfigIc struct based on the TCP parameters provided by the TCP_Params struct Function used to set basic TCP parameters Returns access error flag Returns Apriori data endian configuration Returns the Extrinsics data endian configuration Returns the frame length error status Returns the IC values already programmed into the TCP Returns the Interleaver Table data endian configuration Returns the interleaver table error status Returns the error status for a bad reliability length Returns the error status for a bad TCP mode Returns the number of iterations performed by the TCP Returns the output parameters error status Returns the error status for an invalid prolog length Returns the error status for an invalid rate Returns the error status for an invalid reliability length Returns the error status indicating an invalid number of sub frames Returns the Systematics and Parities data endian configuration Stores the IC values into the TCP Stores the IC values into the TCP using arguments See page .

.. TCP APIs (Continued) Syntax TCP_interleaveExt TCP_makeTailArgs TCP_MAP_MAP1A TCP_MAP_MAP1B TCP_MAP_MAP2 TCP_MODE_SA TCP_MODE_SP TCP_normalCeil TCP_pause TCP_RATE_1_2 TCP_RATE_1_3 TCP_RATE_1_4 TCP_RLEN_MAX TCP_setAprioriEndian TCP_setExtEndian TCP_setInterEndian TCP_setNativeEndian TCP_setPacked32Endian TCP_setParams TCP_setSysParEndian TCP_STANDARD_3GPP TCP_STANDARD_IS2000 TCP_start TCP_statError Note: F = Function. 21-26 21-27 21-27 21-27 21-27 21-28 21-28 21-28 21-28 21-28 21-29 21-29 21-29 21-29 21-30 21-30 21-31 21-31 21-31 21-32 21-32 21-32 21-33 21-33 21-4 .Overview Table 21−2. C = Constant Type Description F F C C C C C F F C C C C F F F F F F F C C F F Interleaves extrinsics data for shared processing mode Builds the Tail values used for IC6–IC11 Value indicating that the first iteration of a MAP1 decoding Value indicating a MAP1 decoding (any iteration after the first) Value indicating a MAP2 decoding Value indicating standalone processing mode Value indicating shared processing mode Normalized ceiling function Pauses the TCP Value indicating a rate of 1/2 Value indicating a rate of 1/3 Value indicating a rate of 1/4 Maximum reliability length Sets the Apriori data endian configuration Sets the Extrinsics data endian configuration Sets the Interleaver Table data endian configuration Sets all data formats to be native (not packed data) Sets all data formats to be packed data Generates IC0–IC5 based on the channel parameters Sets the Systematics and Parities data endian configuration Value indicating the 3GPP standard Value indicating the IS2000 standard Starts the TCP Returns the error status See page .

the configuration function can be bypassed and the user can generate each IC value independently.. the symbol constants may be used for the field values.. 21-33 21-34 21-34 21-34 21-35 21-35 21-35 21-36 21-36 21-37 21-38 21-39 21-40 21. the data will all be of the same format.Overview Table 21−2. that will be sent via the EDMA to program its operation. you must first configure the control values. TCP_Params contains all of the channel characteristics and TCP_XabData is a pointer to the tail data located at the end of the received channel data. or IC values. using several TCP_RMK (make) macros that construct register values based on field values.1 Using the TCP To use the TCP. This is accomplished by programming the TCP Endian register (TCP_END). C = Constant Type Description F F F F F F F F F F F F F Returns the pause status Returns the run status Returns the Apriori data status Returns the Extrinsics data status Returns the Hard Decisions status Returns the IC values status Returns the Interleaver Table status Returns the Output Parameters status Returns the Systematics and Parities data status Generates IC6–IC11 by calling either TCP_tailConfig3GPP or TCP_tailConfigIS2000 Generates tail values for 3GPP channel data Generates tail values for IS2000 channel data Unpauses the TCP See page . This configuration function returns a pointer to the IC values that are to be sent using the EDMA. Typically. If desired. To do this. the CPU must configure the format of all the data to be transferred to and from the TCP. TCP APIs (Continued) Syntax TCP_statPause TCP_statRun TCP_statWaitApriori TCP_statWaitExt TCP_statWaitHardDec TCP_statWaitIc TCP_statWaitInter TCP_statWaitOutParm TCP_statWaitSysPar TCP_tailConfig TCP_tailConfig3GPP TCP_tailConfigIs2000 TCP_unpause Note: F = Function. When operating in big endian mode.1. the TCP_Params structure and TCP_XabData pointer are passed to TCP_icConfig(). either following the native element size (either 8-bit or TCP Module 21-5 . In addition.

The TCP module includes handle-based macros. These are not required as all TCP configuring and monitoring can be done through the provided functions. the endian mode values can be set using a single function call to either TCP_setNativeEndian() or TCP_setPacked32Endian().2 Macros There are two types of TCP macros: those that access registers and fields.Macros 16−bit) or being packed into a 32-bit word. 21-6 . These TCP functions make use of a number of macros. Table 21−4 lists the TCP macros that construct register and field values. the data format of individual data types can be programmed with independent functions. Alternatively. Using the HAL Macros. This being the case. and those that construct register and field values. Table 21−3 lists the TCP macros that access registers and fields. The macros themselves are found in Chapter 28. The user can monitor the status of the TCP during operation and also monitor error flags if there is a problem. 21.

.<FIELD>.<FIELD>) TCP_FSETA(addr.. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 Table 21−4.<REG>.<FIELD>.<REG>) TCP_RSETA(addr.fieldval) TCP_FSETS(<REG>. fieldval) TCP_FSETSA(addr. 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 TCP Module 21-7 .Macros Table 21−3..<REG>.x) TCP_FGETA(addr. Field symbolic value See page ..<FIELD>) TCP_FSET(<REG>.. TCP Macros that Access Registers and Fields Macro TCP_ADDR(<REG>) TCP_RGET(<REG>) TCP_RSET(<REG>.<FIELD>. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page ...<REG>. Field default value Field make Field make symbolically Field value of .<SYM>) TCP_RGETA(addr.<FIELD>.x) TCP_FGET(<REG>. TCP Macros that Construct Register and Field Values Macro TCP_<REG>_DEFAULT TCP_<REG>_RMK() TCP_<REG>_OF() TCP_<REG>_<FIELD>_DEFAULT TCP_FMK() TCP_FMKS() TCP_<REG>_<FIELD>_OF() TCP_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of .<REG>..

/*Interleaver Write Flag */ 1 /*Output Parameters Read Flag */ }. Maximum Iteration snr. /* Rate */ 40. Code rate frameLen. Interleaver flag outParmFlag Output Parameter read flag Description This is the TCP base parameters structure used to set up the TCP programmable parameters. &tcpParam0). /* Decoder Standard */ TCP_RATE_1_3. TCP_BaseParams tcpBaseParam0 = { TCP_STANDARD_3GPP.TCP_BaseParams 21.3 Configuration Structures TCP_BaseParams Structure used to set basic TCP Parameters Structure Members TCP_BaseParams TCP_Standard TCP_Rate Uint16 Uint8 Uint8 Uint8 Uint8 Uint8 standard. You create the object and pass it to the TCP_genParams() function which returns the TCP_Params structure. SNR Threshold intFlag. /*Max of Iterations (MAXIT−SA mode only)*/ 0. /*Prolog Size (P: 24 to 48) */ 8. /*Frame Length (FL: 40 to 20730)*/ 24. Example 21-8 . TCP Decoded Standard3GPP/IS2000 rate. Frame Length prologSize. … TCP_genParams(&tcpBaseParam0. Prolog Size maxIter. /*SNR Threshold (SNR − SA mode only) */ 1.

TCP_ConfigIc TCP_ConfigIc Structure Structure containing the IC register values typedef struct { Uint32 ic0. Uint32 ic7.. Uint32 ic8.. Uint32 ic1. . Uint32 ic11. Though using the EDMA is highly recommended. TCP_ConfigIc *config.. TCP_genIc(params. Uint32 ic3. Uint32 ic9. Uint32 ic10. Uint32 ic4. extern TCP_UserData *xabData.. config). . Uint32 ic5. extern TCP_Params *params. Uint32 ic6. the values can be written to the TCP using the CPU with the TCP_icConfig() function. } TCP_ConfigIc. xabData. Uint32 ic2. ic0 ic1 ic2 ic3 ic4 ic5 ic6 ic7 ic8 ic9 ic10 ic11 Input Configuration word 0 value Input Configuration word 1 value Input Configuration word 2 value Input Configuration word 3 value Input Configuration word 4 value Input Configuration word 5 value Input Configuration word 6 value Input Configuration word 7 value Input Configuration word 8 value Input Configuration word 9 value Input Configuration word 10 value Input Configuration word 11 value Members Description This is the TCP input configuration structure that holds all of the configuration values that are to be transferred to the TCP via the EDMA. TCP Module 21-9 Example .

Uint32 numExt.TCP_Params TCP_Params Structure Structure containing all channel characteristics typedef struct { TCP_Standard standard. } TCP_Params. 21-10 . Uint32 snr. Uint32 frameLen. Uint32 maxIter. TCP_Rate rate. Uint32 subFrameLen. TCP_Map map. Uint32 relLenLast. Uint32 numSubBlockLast. Uint32 outParmFlag. Uint32 intFlag. Uint32 numInter. Uint32 prologSize. Uint32 numSubBlock. Uint32 relLen. Uint32 numApriori. TCP_Mode mode. Uint32 numSysPar. Uint32 numHd.

TCP_RATE_1_3 .TCP_MAP_MAP2 The rate: 1/2.TCP_MAP_MAP1A .TCP_Params Members standard The 3G standard used: 3GPP or IS2000 The available constants are: .TCP_MODE_SP The map mode constants are: .TCP_MAP_MAP1B .1/4 The rate constants are: .TCP_RATE_1_2 .TCP_STANDARD_IS2000 The processing mode: Shared or Standalone The available constants are: .TCP_RATE_1_4 Interleaver write flag Output parameters flag Number of symbols in the frame to be decoded The number of symbols in a sub-frame Reliability length Reliability length of the last sub-frame Prolog Size Number of sub-blocks Number of sub-blocks in the last sub-frame Maximum number of iterations Signal to noise ratio threshold Number of interleaver words per event Number of systematics and parities words per event Number of apriori words per event Number of extrinsics per event Number of hard decisions words per event TCP Module 21-11 mode map rate intFlag outParmFlag frameLen subFrameLen relLen relLenLast prologSize numSubBlock numSubBlockLast maxIter snr numInter numSysPar numApriori numExt numHd . 1/3.TCP_STANDARD_3GPP .TCP_MODE_SA .

TCP_Params Description This is the TCP parameters structure that holds all of the information concerning the user channel. xabData. TCP_genIc(params.. . .. These values are used to generate the appropriate input configuration values for the TCP and to program the EDMA. Example 21-12 .. extern TCP_Params *params.. TCP_ConfigIc *config. config). extern TCP_UserData *xabData.

NumSubFrames = TCP_calcSubBlocksSP(configParms). Configuration parameters Calculates sub-blocks for shared processing Uint32 TCP_calcSubBlocksSP(TCP_Params *configParms. ConfigParms numSubFrames Configuration parameters Number of sub-frames Divides the data frames into sub-frames and sub-blocks for shared processing mode. TCP_calcSubBlocksSA(configParms). Uint32 numSubFrames. Example TCP_calcCountsSA Calculates the count values for standalone processing Function Arguments Return Value Description Void TCP_calcCountsSA(TCP_Params *configParms). TCP_calcCountsSA(configParms). ConfigParms none Divides the data frames into sub-blocks for standalone processing mode. This function is for standalone processing mode. configParms none This function calculates all of the count values required to transfer all data to/from the TCP using the EDMA.TCP_calcSubBlocksSA 21.4 Functions TCP_calcSubBlocksSA Function Arguments Return Value Description Example TCP_calcSubBlocksSP Function Arguments Return Value Description Calculates sub-blocks for standalone processing void TCP_calcSubBlocksSA(TCP_Params *configParms). Configuration parameters Example TCP_calcCountsSP Calculates the count values for shared processing Function Arguments Void TCP_calcCountsSP(TCP_Params *configParms). The number of subframes into which the data frame was divided is returned. configParms Configuration parameters TCP Module 21-13 .

apriori. Uint16 numExt. val pwr2 ceilVal Value to be augmented The power of two by which val must be divisible The smallest number which when multiplied by 2^pwr2 is greater than val.. hardDecisions. channel_data. rate). TCP_calculateHd Function Calculate hard decisions void TCP_calculateHd( const TCP_ExtrinsicData *restrict extrinsicsMap1.. Uint32 pwr2).. extrinsicsMap1 apriori channel_data harddecisions numext rate none This function calculates the hard decisions following multiple MAP decodings in shared processing mode. This function is for shared processing mode. numExt. Uint8 rate). pwr2).. <. const TCP_UserData *restrict channel_data. 21-14 . This function calculates the ceiling for a given value and a power of 2. Arguments Extrinsics data following MAP1 decode Apriori data following MAP2 decode Input channel data Hard decisions Number of extrinsics Channel rate Return Value Description Example TCP_ceil Function Arguments Return Value Description Ceiling function Uint32 TCP_ceil(Uint32 val. The arguments follow the formula: ceilVal * 2^pwr2 = ceiling(val.TCP_calculateHd Return Value Description Example none This function calculates all of the count values required to transfer all data to/from the TCP using the EDMA.Iterate through MAP1 and MAP2 decodes. TCP_calcCountsSP(configParms).> void TCP_calculateHd(extrinsicsMap1. const TCP_ExtrinsicData *restrict apriori. Uint32 *restrict hardDecisions.

> Arguments Apriori data for MAP1 decode Extrinsics data following MAP2 decode Interleaver data table Number of Extrinsics TCP_demuxInput Function Demultiplexes the input data Void TCP_demuxInput(Uint32 rate. const TCP_UserData *restrict input.MAP 1 decode.. const Uint16 *restrict interleaver. extrinsicsMap1. <. This function is for use in performing shared processing..TCP_deinterleaveExt Example numSysPar = TCP_ceil((frameLen * rate). const Uint16 *restrict interleaverTable.. TCP_ExtrinsicData *restrict nonInterleaved...> TCP_deinterleaveExt(aprioriMap2. 4). numExt).MAP 2 decode. TCP_deinterleaveExt De-interleave extrinsics data Function Void TCP_deinterleaveExt( TCP_ExtrinsicData *restrict aprioriMap1.. <. Uint32 numExt).. Uint32 frameLen. const TCP_ExtrinsicData *restrict extrinsicsMap2. TCP_ExtrinsicData *restrict interleaved). aprioriMap1 extrinsicsMap2 interleaverTable numExt Return Value Description Example none This function de-interleaves the MAP2 extrinsics data to generate apriori data for the MAP1 decode. interleaverTable. rate frameLen input interleaver nonInterleaved interleaved Channel rate Frame length Input channel data Interleaver data table Non-interleaved input data Interleaved input data TCP Module 21-15 Arguments ..

TCP_END_PACKED32 Constant Description Value indicating little endian format within packed 32-bit words TCP_END_PACKED32 This constant allows selection of the packed 32-bit format for data transferred to and from the TCP. This function is used in shared processing mode. That is to say that all data is contiguous in memory with incrementing addresses. interleaver. The other contains the interleaved input data and is used with the MAP2 decoding. input. none Error code Code error value Returns an ERR bit indicating what TCP error has occurred. interleaved). } /* end if */ 21-16 . frameLen. nonInterleaved. That is to say that all data is packed into 32-bit words in little endian format and these words are contiguous in memory.TCP_END_NATIVE Return Value Description none This function splits the input data into two working sets. One set contains the non-interleaved input data and is used with the MAP 1 decoding. TCP_errTest Function Arguments Return Value Description Example Returns the error code Uint32 TCP_errTest(). Example TCP_END_NATIVE Value indicating native endian format Constant Description TCP_END_NATIVE This constant allows selection of the native format for all data transferred to and from the TCP. /* check whether an error has occurred */ if (TCP_errorStat()){ error = TCP_ErrGet(). TCP_demuxInput(rate.

Arguments Pointer to Channel parameters structure Pointer to tail values at the end of the channel data Pointer to Input Configuration structure Return Value Description Example TCP_genParams Function Sets basic TCP Parameters Uint32 TCP_genParams( TCP_BaseParams *configBase. TCP_Params *configParams ) configBase configParams Pointer to TCP_BaseParams structure Output TCP_Params structure pointer Arguments Return Value Description number of sub-blocks Copies the basic parameters under the output TCP_Params parameters structure and returns the number of sub-blocks... TCP_ConfigIc *config. . extern TCP_UserData *xabData. config). . TCP Module 21-17 .TCP_FLEN_MAX TCP_FLEN_MAX Constant Description Maximum frame length TCP_FLEN_MAX This constant equals the maximum frame length programmable into the TCP. TCP_UserData *restrict xabData. TCP_ConfigIc *restrict configIc ) configParms xabData configIc none Generates the required input configuration values needed to program the TCP based on the parameters provided by configParms. xabData.. extern TCP_Params *params. TCP_genIc Function Generates the TCP_ConfigIc structure void TCP_genIc( TCP_Params *restrict configParms.. TCP_genIc(params.

TCP_interEndianGet. numSubblk = TCP_genParams(&tcpBaseParam0. TCP_ConfigIc *config. } /* end if */ 21-18 . Example If (TCP_getAprioriEndian()){ . TCP_extEndianGet. } /* end if */ TCP_getAprioriEndian Returns Apriori data endian configuration Function Arguments Return Value Description Uint32 TCP_getAprioriEndian(). none Endian Endian setting for apriori data Returns the value programmed into the TCP_END register for the apriori data indicating whether the data is in its native 8-bit format (‘1’) or consists of values packed in little endian format into 32-bit words (‘0’). TCP_packed32EndianSet. TCP_getAccessErr Returns access error flag Function Arguments Return Value Description Example Uint32 TCP_getAccessErr(). TCP_sysParEndianGet. TCP_nativeEndianSet.. none Error value of access error bit Returns the ACC bit value indicating whether an invalid access has been made to the TCP during operation. TCP_Params tcpParam0. TCP_extEndianSet.TCP_getAccessErr Example Uint32 numSubblk.. &tcpParam0). TCP_interEndianSet. TCP_sysParEndianSet.. /* check whether an invalid access has been made */ if (TCP_getAccessErr()){ .. This should always be ‘0’ for little endian operation. See also TCP_aprioriEndianSet.

TCP_setInterEndian. Example If (TCP_getExtEndian()){ . See also TCP_setExtEndian..TCP_getExtEndian TCP_getExtEndian Returns the Extrinsics data endian configuration Function Arguments Return Value Description Uint32 TCP_getExtEndian(). } /* end if */ TCP_getFrameLenErr Returns the frame length error status Function Arguments Return Value Description Example Uint32 TCP_getFrameLenErr(). none Error flag Boolean indication of frame length error Returns a Boolean value indicating whether an invalid frame length has been programmed in the TCP during operation. none Endian Endian setting for extrinsics data Returns the value programmed into the TCP_END register for the extrinsics data indicating whether the data is in its native 8-bit format (‘1’) or consists of values packed in little endian format into 32-bit words (‘0’). This should always be ‘0’ for little endian operation. TCP_setNativeEndian. TCP_getInterEndian. TCP_getAprioriEndian. TCP_getSysParEndian.. /* check whether an invalid access has been made */ if (TCP_getFrameLenErr()){ . TCP_setSysParEndian.. TCP_setPacked32Endian. TCP_setAprioriEndian. } /* end if */ TCP_getIcConfig Function Arguments Returns the IC values already programmed into the TCP void TCP_getIcConfig(TCP_ConfigIc *config) config Pointer to Input Configuration structure TCP Module 21-19 ..

TCP_getInterEndian Return Value Description Example none Reads the input configuration values currently programmed into the TCP. } /* end if */ TCP_getInterleaveErr Returns the interleaver table error status Function Arguments Return Value Description Uint32 TCP_getInterleaveErr(). TCP_getInterEndian Returns the interleaver table data endian Function Arguments Return Value Description Uint32 TCP_getInterEndian(). TCP_ConfigIc *config. TCP_getIcConfig(config)... none Endian Endian setting for interleaver table data Returns the value programmed into the TCP_END register for the interleaver table data indicating whether the data is in its native 8-bit format (‘1’) or consists of values packed in little endian format into 32-bit words (‘0’). Example If (TCP_getInterEndian()){ . 21-20 .. TCP_setSysParEndian. TCP_getExtEndian. . An interleaver table can only be sent when operating in standalone mode.. See also TCP_setExtEndian. TCP_setAprioriEndian. TCP_setNativeEndian. TCP_getSysParEndian. . TCP_setInterEndian. none Error flag value of interleaver table error bit Returns an INTER value bit indicating whether the TCP was incorrectly programmed to receive an interleaver table. This should always be ‘0’ for little endian operation. TCP_getAprioriEndian. TCP_setPacked32Endian... This bit indicates if an interleaver table was sent when in shared processing mode.

. */ if (TCP_getInterleaveErr()){ ... } /* end if */ Example TCP_getModeErr Function Arguments Return Value Description Example Returns the error status for a bad TCP mode Uint32 TCP_getModeErr(). /* check whether the TCP was programmed using an invalid mode.TCP_getLastRelLenErr Example /* check whether the TCP was programmed to receive an interleaver table when in shared processing mode. and 7 are valid. 5. } /* end if */ TCP Module 21-21 . none Error flag Value of mode error bit Returns the MODE bit value indicating whether an invalid MAP mode was programmed into the TCP... none Error flag value of an error for the reliability length of the last subframe (LR bit) Returns the LR bit value indicating whether the TCP was programmed with a bad reliability length for the last subframe. } /* end if */ TCP_getLastRelLenErr Function Arguments Return Value Description Returns the error status for a bad reliability length Uint32 TCP_getLastRelLenErr(). /* check whether the TCP was programmed with a bad reliability length for the last frame. */ if (TCP_getModeErr()){ . */ if (TCP_getLastRelLenErr()){ . Only values of 4. The reliability length must be greater than or equal to 40 to be valid..

TCP_getNumIt TCP_getNumIt Function Arguments Return Value Description Returns the number of iterations performed by the TCP Uint32 TCP_getNumit().. Alternatively. the EDMA can be used to transfer the output parameters following the hard decisions (recommended). numIter = TCP_getNumit(). /* check whether the TCP was programmed to provide output parameters when in Shared Processing mode. none iterations The number of iterations performed by the TCP Returns the number of iterations executed by the TCP in standalone processing mode. */ if (TCP_getOutParmErr()){ . none Error flag value of output parameters error Returns the OP bit value indicating whether the TCP was programmed to transfer output parameters in shared processing mode. */ if (TCP_getProlLenErr()){ . Example TCP_getOutParmErr Returns the output parameter Function Arguments Return Value Description Uint32 TCP_getOutParmErr(). The output parameters are only valid when operating in standalone mode. This function reads the output parameters register.. none Error flag Value of Prolog Length error Returns the P bit value indicating whether an invalid prolog length has been programmed into the TCP... /* check whether an invalid prolog length has been programmed. } /* end if */ Example TCP_getProlLenErr Returns the error status for an invalid prolog length Function Arguments Return Value Description Example Uint32 TCP_getProlLenErr(). } /* end if */ 21-22 .

/* check whether an invalid reliability length has been programmed. } /* end if */ TCP_getRelLenErr Returns the error status for and invalid reliability length Function Arguments Return Value Description Example Uint32 TCP_getRelLenErr().. none Error flag Value of rate error Returns the RATE bit value indicating whether an invalid rate has been programmed into the TCP..TCP_getRateErr TCP_getRateErr Function Arguments Return Value Description Example Returns the error status for an invalid rate Uint32 TCP_getRateErr(). */ if (TCP_getSubFrameErr()){ . */ if (TCP_getRelLenErrG()){ . /* check whether an invalid sub-frame length has been programmed... none Error flag Value of reliability length error Returns the R bit value indicating whether an invalid reliability length has been programmed into the TCP.. /* check whether an invalid rate has been programmed */ if (TCP_getRateErr()){ . none Error flag Boolean indication of sub-frame error Returns a Boolean value indicating whether the sub-frame length programmed into the TCP is invalid.. } /* end if */ TCP_getSubFrameErr Returns sub-frame error flag Function Arguments Return Value Description Example Uint32 TCP_getSubFrameErr(). } /* end if */ TCP Module 21-23 .

. TCP_genIc(params.. TCP_ConfigIc *config. Pointer to Input Configuration structure Example 21-24 ... This is not the recommended means by which to program the TCP. See also TCP_setSysParEndian. xabData. . TCP_setPacked32Endian. extern TCP_UserData *xabData. but can be used in test code. indicating whether the data is in its native 8-bit format (‘1’) or consists of values packed in little endian format into 32-bit words (‘0’). } /* end if */ TCP_icConfig Function Arguments Return Value Description Stores the IC values into the TCP void TCP_icConfig(TCP_ConfigIc *config) Config none Stores the input configuration values currently programmed into the TCP.TCP_getSysParEndian TCP_getSysParEndian Returns Systematics and Parities data endian configuration Function Arguments Return Value Description Uint32 TCP_getSysParEndian().. TCP_setNativeEndian. config). TCP_icConfig(config). extern TCP_Params *params. . none Endian Endian setting for systematics and parities data Returns the value programmed into the TCP_END register for the systematics and parities data. This should always be ‘0’ for little endian operation. Example If (TCP_getSysParEndian()){ . as it is more efficient to transfer the IC values using the EDMA..

Uint32 ic11 ) ic0 ic1 ic2 ic3 ic4 ic5 ic6 ic7 ic8 ic9 ic10 ic11 none Stores the input configuration values currently programmed into the TCP. Uint32 ic2. Uint32 ic10. Uint32 ic7. Uint32 ic1. Uint32 ic3. Uint32 ic9. Uint32 ic4. Uint32 ic6. This is not the recommended means by which to program the TCP. as it is more efficient to transfer the IC values using the EDMA. Uint32 ic8. Input Configuration word 0 value Input Configuration word 1 value Input Configuration word 2 value Input Configuration word 3 value Input Configuration word 4 value Input Configuration word 5 value Input Configuration word 6 value Input Configuration word 7 value Input Configuration word 8 value Input Configuration word 9 value Input Configuration word 10 value Input Configuration word 11 value Arguments Return Value Description TCP Module 21-25 .TCP_icConfigArgs TCP_icConfigArgs Stores the IC values into the TCP using arguments Function Void TCP_icConfigArgs( Uint32 ic0. but can be used in test code. Uint32 ic5.

This function is for use in performing shared processing.. aprioriMap2 extrinsicsMap1 interleaverTable NumExt none This function interleaves the MAP1 extrinsics data to generate apriori data for the MAP2 decode.. /* /* /* /* /* /* /* /* /* /* /* /* IC0 IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 */ */ */ */ */ */ */ */ */ */ */ */ TCP_interleaveExt Interleaves extrinsics data Function Void TCP_interleaveExt( TCP_ExtrinsicData *restrict aprioriMap2.. InterleaverTable.. <.MAP 1 decode.MAP 2 decode..TCP_interleaveExt Example TCP_icConfigArgs( 0x00283200 0x00270000 0x00080118 0x001E0014 0x00000000 0x00000002 0x00E3E6F2 0x00E40512 0x00000000 0x00F5FA1E 0x00F00912 0x00000000 ). numExt). extrinsicsMap1. const Uint16 *restrict interleaverTable.> Arguments Apriori data for MAP2 decode Extrinsics data following MAP1 decode Interleaver data table Number of Extrinsics Return Value Description Example 21-26 .. Uint32 numExt)..> TCP_interleaveExt(aprioriMap2. <. const TCP_ExtrinsicData *restrict extrinsicsMap1..

Uint8 byte7_0 ) byte31_24 byte23_16 byte15_8 byte7_0 none Formats individual bytes into a 32-bit word tail1 = TCP_makeTailArgs(0 . xabData[10]. xabData[6]). xabData[8]. TCP Module 21-27 . Uint8 byte15_8. TCP_MAP_MAP1B Value indicating a MAP1 decoding (any iteration after the first) Constant Description TCP_MAP_MAP1B This constant allows selection of the Map 1decoding mode used when operating in shared processing mode on any but the first iteration through the data. Uint8 byte23_16. The first iteration through the Map 1 decoding is unique in that no apriori data is set to the TCP. The first iteration through the Map 1 decoding is unique in that no apriori data is set to the TCP. TCP_MAP_MAP2 Constant Description Value indicating a MAP2 decoding TCP_MAP_MAP2 This constant allows selection of the Map 2decoding mode used when operating in shared processing mode. Arguments Byte to be placed in bits 31−24 of the 32-bit value Byte to be placed in bits 23−16 of the 32-bit value Byte to be placed in bits 15−8 of the 32-bit value Byte to be placed in bits 7−0 of the 32-bit value Return Value Description Example TCP_MAP_MAP1A Value indicating the first iteration of a MAP1 decoding Constant Description TCP_MAP_MAP1A This constant allows selection of the Map 1 decoding mode used when operating in shared processing mode on the first iteration through the data.TCP_makeTailArgs TCP_makeTailArgs Function Generates the Tail values used for ICCIC11 Uint32 TCP_makeTailArgs( Uint8 byte31_24.

TCP_MODE_SA TCP_MODE_SA Constant Description Value indicating standalone processing TCP_MODE_SA This constant allows selection of standalone processing mode. TCP_pause(). TCP_pause Function Arguments Return Value Description Example Pauses the TCP by writing a ‘1’ to the pause bit in TCP_EXE void TCP_pause(). . val1 val2 ceilVal Value to be augmented Value by which val1 must be divisible The smallest number greater than or equal to val1 that is divisible by val2. numSlidingWindow). Uint32 val2) . TCP_MODE_SP Constant Description Value indicating shared processing mode TCP_MODE_SP This constant allows selection of shared processing mode. TCP_normalCeil Function Arguments Return Value Description Example Normalized ceiling function Uint32 TCP_normalCeil(Uint32 val1. See also TCP_start() and TCP_unpause(). none none This function pauses the TCP by writing a ‘1’ to the PAUSE field of the TCP_EXE register. TCP_RATE_1_2 Constant Description 21-28 Value indicating a rate of 1/2 TCP_RATE_1_2 This constant allows selection of a rate of 1/2. winSize = TCP_normalCeil(winSize. Returns the smallest number greater than or equal to val1 that is divisible by val2.

TCP_RATE_1_4 Constant Description Value indicating a rate of 1/4 TCP_RATE_1_4 This constant allows selection of a rate of 1/4. TCP_getInterEndian. Endian none This function programs TCP to view the format of the apriori data as either native 8-bit format (‘1’) or values packed into 32-bit words in little endian format (‘0’). TCP_setInterEndian. TCP_setNativeEndian. TCP_RLEN_MAX Constant Description Maximum reliability length TCP_RLEN_MAX This constant equals the maximum reliability length programmable into the TCP. TCP Module 21-29 . Endian setting for apriori data Example TCP_setAprioriEndian(TCP_END_PACKED32). TCP_setAprioriEndian Function Arguments Return Value Description Sets Apriori data endian configuration Void TCP_setAprioriEndian(Uint32 endianMode). TCP_getExtEndian. TCP_setExtEndian. TCP_setSysParEndian.TCP_RATE_1_3 TCP_RATE_1_3 Constant Description Value indicating a rate of 1/3 TCP_RATE_1_3 This constant allows selection of a rate of 1/3. TCP_getSysParEndian. TCP_setPacked32Endian. This should always be ‘0’ for little endian operation. See also TCP_getAprioriEndian.

TCP_getExtEndian. See also TCP_getExtEndian. TCP_getAprioriEndian. TCP_getSysParEndian. Endian Endian setting for interleaver table data The following constants can be used: . TCP_setNativeEndian. TCP_setNativeEndian. TCP_getSysParEndian. TCP_setPacked32Endian. TCP_setAprioriEndian. TCP_setExtEndian.TCP_setExtEndian TCP_setExtEndian Sets the Extrinsics data endian configuration Function Arguments Return Value Description Void TCP_setExtEndian(Uint32 endianMode). . TCP_getInterEndian. Endian none This function programs TCP to view the format of the extrinsics data as either native 8-bit format (‘1’) or values packed into 32-bit words in little endian format (‘0’). Example TCP_setAprioriEndian(TCP_END_PACKED32). TCP_setSysParEndian. TCP_getAprioriEndian. This should always be ‘0’ for little endian operation. TCP_setInterEndian.TCP_END_NATIVE or 1 Return Value Description none This function programs TCP to view the format of the interleaver table data as either native 8-bit format (‘1’) or values packed into 32-bit words in little endian format (‘0’). TCP_setPacked32Endian. TCP_setSysParEndian.TCP_END_PACKED32 or 0 . Example 21-30 TCP_setInterEndian(TCP_END_PACKED32). See also TCP_getInterEndian. TCP_setAprioriEndian. Endian setting for extrinsics data TCP_setInterEndian Sets the interleaver table data endian Function Arguments Void TCP_setInterEndian(Uint32 endianMode). This should always be ‘0’ for little endian operation.

This should always be used when running in little endian mode and should be used in big endian mode only if the CPU is formatting the data. none none This function programs the TCP to view the format of all data as packed data in 32-bit words. TCP_getSysParEndian. TCP_setPacked32Endian Sets all data formats to packed data Function Arguments Return Value Description void TCP_setPacked32Endian(). TCP_getSysParEndian. TCP_setAprioriEndian. TCP_setInterEndian. Example TCP_setNativeEndian(). TCP_setExtEndian. TCP_getExtEndian. TCP_getExtEndian.TCP_setNativeEndian TCP_setNativeEndian Sets all data formats to be native (not packed) Function Arguments Return Value Description void TCP_setNativeEndian(). See also TCP_setNativeEndian. Example TCP_setPacked32Endian(). configParms configIc Pointer to the user channel parameters structure Pointer to the IC values structure TCP Module 21-31 Arguments . TCP_getAprioriEndian. This should only be used when running in big endian mode. TCP_getAprioriEndian. TCP_setPacked32Endian. TCP_setSysParEndian. none none This function programs the TCP to view the format of all data as native 8-/16-bit format. TCP_setAprioriEndian. TCP_setParams Function Generates IC0–C5 based on channel parameters void TCP_setParams( TCP_Params *configParms. TCP_setInterEndian. See also TCP_setExtEndian. TCP_setSysParEndian. TCP_ConfigIc *configIc ).

This should always be ‘0’ for little endian operation. Endian setting for systematics and parities data Example TCP_setSysParEndian(TCP_END_PACKED32). TCP_STANDARD_3GPP Value indicating the 3GPP standard Constant Description TCP_STANDARD_3GPP This constant allows selection of the 3GPP standard. extern TCP_Params *configParms. TCP_setPacked32Endian. TCP_setSysParEndian Function Arguments Return Value Description Sets Systematics and Parities data endian configuration Void TCP_setSysParEndian(Uint32 endianMode). TCP_setNativeEndian.. TCP_setParams(configParms. . configIc). .TCP_setSysParEndian Return Value Description Example none This function generates the input control values IC0–IC5 based on the user channel parameters contained in the configParms structure. TCP_ConfigIc *configIC. TCP_STANDARD_IS2000 Constant Description 21-32 Value indicating the IS2000 standard TCP_STANDARD_IS2000 This constant allows selection of the IS2000 standard. See also TCP_getSysParEndian. Endian none This function programs the TCP to view the format of the systematics and parities data as either native 8-bit format (‘1’) or values packed into 32-bit words in little endian format (‘0’)..

TCP_statError Function Arguments Return Value Description Example Returns the error status Uint32 TCP_statError().. /* pause the TCP */ TCP_pause(). TCP Module 21-33 . none Status Boolean status Returns a Boolean status indicating whether the TCP is paused or not. TCP_start(). See also TCP_pause() and TCP_unpause(). } /* end if */ TCP_statPause Function Arguments Return Value Description Example Returns the pause status Uint32 TCP_statPause().TCP_start TCP_start Function Arguments Return Value Description Example Starts the TCP by writing a ’1’ to the start bit in TCP_EXE void TCP_start(). none Error status Value of error bit Returns the ERR bit value indicating whether any TCP error has occurred. none none This function starts the TCP by writing a ‘1’ to the START field of the TCP_EXE register. /* check whether an error has occurred */ if (TCP_statError()){ . /* wait for pause to take place */ while (!TCP_statPause())..

/* check that the TCP is running */ while (!TCP_statRun())... none Status Boolean REXTstatus Returns the REXT bit status indicating whether the TCP is waiting for extrinsic data to be read. TCP_statWaitApriori Function Arguments Return Value Description Example Returns the apriori data status Uint32 TCP_statWaitApriori(). } /* end if */ 21-34 . none Status Boolean WAP status Returns the WAP bit status indicating whether the TCP is waiting to receive apriori data.. none Status Boolean status Returns a Boolean status indicating whether the TCP is running /* start the TCP */ TCP_start(). } /* end if */ TCP_statWaitExt Function Arguments Return Value Description Example Returns the extrinsics data Uint32 TCP_statWaitExt()..TCP_statRun TCP_statRun Function Arguments Return Value Description Example Returns the run status Uint32 TCP_statRun(). /* check if TCP is waiting on apriori data */ if (TCP_statWaitApriori()){ . /* check if TCP has extrinsic data pending */ if (TCP_statWaitExt()){ .

. none Status WINT status Returns the WINT status indicating whether the TCP is waiting to receive interleaver table data. /* check if TCP is waiting on new IC values */ if (TCP_statWaitIc()){ . } /* end if */ TCP Module 21-35 .... /* check if TCP has hard decisions data pending*/ if (TCP_statWaitHardDec()){ ..TCP_statWaitHardDec TCP_statWaitHardDec Function Arguments Return Value Description Example Returns the hard decisions data status Uint32 TCP_statWaitHardDec(). } /* end if */ TCP_statWaitInter Returns the interleaver table data status Function Arguments Return Value Description Example Uint32 TCP_statWaitInter(). /* check if TCP is waiting on interleaver data */ if (TCP_statWaitInter()){ . none Status RHD status Returns the RHD bit status indicating whether the TCP is waiting for the hard decisions data to be read.. none Status WIC status Returns the WIC bit status indicating whether the TCP is waiting to receive new IC values. } /* end if */ TCP_statWaitIc Function Arguments Return Value Description Example Returns the IC data status Uint32 TCP_statWaitIc().

/* check if TCP is waiting on systematic and parity data */ if (TCP_statWaitSysPar()){ . } /* end if */ TCP_statWaitSysPar Function Arguments Return Value Description Example Returns the systematics and parities data status Uint32 TCP_statWaitSysPar(). /* check if TCP has output parameters data pending */ if (TCP_statWaitOutParm()){ .TCP_statWaitOutParm TCP_statWaitOutParm Function Arguments Return Value Description Example Returns the output parameters data status Uint32 TCP_statWaitOutParm().. } /* end if */ 21-36 . none Status ROP status Returns the ROP bit status indicating whether the TCP is waiting for the output parameters to be read... none Status WSP status Returns the WSP bit status indicating whether the TCP is waiting to receive systematic and parity data..

TCP_Mode mode = configParms–>mode. TCP_Rate rate = configParms−>rate. 3G standard Processing mode Map mode for shared processing Rate Pointer to the tail data Pointer to the IC values structure Arguments Return Value Description Example extern TCP_Params *configParms. TCP_ConfigIc *configIC. configIc). TCP_Rate rate. standard mode map rate xabData configIc none This function generates the input control values IC6−IC11 based on the processing to be performed by the TCP. Uint16 index = configParms−>frameLen * rate. This function actually calls specific tail generation functions depending on the standard followed: TCP_tailConfig3GPP or TCP_tailConfigIS2000.TCP_tailConfig TCP_tailConfig Function Generates IC6–IC11 tail values void TCP_tailConfig( TCP_Standard standard. TCP_ConfigIc *configIc ). TCP Module 21-37 . TCP_Map map. extern TCP_UserData *userData. xabData. rate. .. map. mode.. TCP_UserData *xabData = &userData[index]. TCP_Map map = configParms–>map. TCP_Mode mode. These values consist of the tail data following the systematics and parities data. TCP_UserData *xabData. TCP_setParams(standard. TCP_Standard standard = configParms–>standard.

See also: TCP_tailConfig and TCP_tailConfigIS2000. TCP_setParams(mode. map.TCP_tailConfig3GPP TCP_tailConfig3GPP Function Generates IC6−IC11 tail values for G3PP channels void TCP_tailConfig3GPP( TCP_Mode mode. TCP_Map map. TCP_Map map = configParms−>map. Processing mode Map mode for shared processing Pointer to the tail data Pointer to the IC values structure Arguments Return Value Description Example extern TCP_Params *configParms. configIc). TCP_UserData *xabData.. 21-38 . Uint16 index = configParms−>frameLen * rate. This function is called from the generic TCP_tailConfig function. TCP_ConfigIc *configIC.. . TCP_Mode mode = configParms−>mode. mode map xabData configIc none This function generates the input control values IC6–IC11 for 3GPP channels. xabData. extern TCP_UserData *userData. TCP_UserData *xabData = &userData[index]. TCP_ConfigIc *configIc ). These values consist of the tail data following the systematics and parities data.

Mode Map Rate XabData configIc Return Value Description none This function generates the input control values IC6 – IC11 for IS2000 channels. TCP_ConfigIc *configIC. Uint16 index = configParms−>frameLen rate. xabData.TCP_UserData *xabData = &userData[index]. This function is called from the generic TCP_tailConfig function.. Example extern TCP_Params *configParms. TCP_Map map. configIc). mode.. TCP_ConfigIc *configIc ). .TCP_tailConfigIS2000 TCP_tailConfigIS2000 Generates IC6–IC11 tail values for IS2000 channels Function Void TCP_tailConfigIS2000( TCP_Mode mode. TCP_UserData *xabData. rate. These values consist of the tail data following the systematic and parity data. map. TCP_Rate rate = configParms−>rate. TCP_Map map = configParms−>map. See also: TCP_tailConfig and TCP_tailConfig3GPP. TCP_Rate rate. TCP_Mode mode = configParms−>mode. extern TCP_UserData *userData. Arguments Processing mode Map mode for shared processing Rate Pointer to the tail data Pointer to the IC values structure * TCP Module 21-39 . TCP_setParams(standard.

TCP_unpause()... 21-40 . See also TCP_start() and TCP_pause(). TCP_pause(). . none none This function un-pauses the TCP by writing a ‘1’ to the UNPAUSE field of the TCP_EXE register.TCP_unpause TCP_unpause Function Arguments Return Value Description Example Unpauses the TCP by writing a ’1’ to the unpause bit in TCP_EXE void TCP_unpause().

. . .3 Configuration Structure . . . . . . Topic Page 22. . . 22-2 22. . . . . . . . . . . . . . . . 22-7 22-1 . . . . . . . . . . . . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22. . . . . . . . . . . . . . . . . . . . 22-4 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Functions . . . . . . . . . . . . . . . .1 Overview . .Chapter 22 TIMER Module This chapter describes the TIMER module. . . . . . . . .2 Macros . and provides a TIMER API reference section. . . . . . . . . . . . . . . . . . . . discusses how to use a TIMER device. . . . . . . . . . . . . . . . . . .

..Overview 22. 22-11 22-11 22-11 22-12 22-12 22-12 22-2 .. Table 22−1. 22-6 Table 22−2. 22-7 22-7 22-8 22-9 22-9 22-10 22-10 22-10 (b) Auxiliary Functions and Constants Syntax TIMER_DEVICE_CNT TIMER_getConfig TIMER_getCount TIMER_getDatIn TIMER_getEventId TIMER_getPeriod Note: F = Function. TIMER Configuration Structure Syntax TIMER_Config Type Description S Structure used to set up a timer device See page . C = Constant Type Description C F F F F F A compile time constant. Table 22−1 lists the configuration structure for use with the TIMER functions.. Table 22−2 lists the functions and constants available in the CSL TIMER module. number of timer devices present Reads the current Timer configuration values Returns the current timer count value Reads the value of the TINP pin Obtains the event ID for the timer device Returns the period of the timer device See page . TIMER APIs (a) Primary Functions Syntax TIMER_close TIMER_config TIMER_configArgs TIMER_open TIMER_pause TIMER_reset TIMER_resume TIMER_start Type Description F F F F F F F F Closes a previously opened timer device Configure timer using configuration structure Sets up the timer using the register values passed in Opens a TIMER device for use Pauses the timer Resets the timer device associated to the handle Resumes the timer after a pause Starts the timer device running See page ...1 Overview The TIMER module has a simple API for configuring the timer registers.

use the device handle to call the other API functions.. C = Constant 22. value of timer output Resets all timer devices Sets the count value of the timer Sets the data output value Sets the timer period A compile time constant whose value is 1 if the device supports the TIMER module See page .. you must first open it and obtain a device handle using TIMER_open(). To assist in creating register values. the symbol constants may be used for the field values. In addition. 22-13 22-13 22-13 22-14 22-14 22-14 F = Function. TIMER Module 22-3 .1. The timer device may be configured by passing a TIMER_Config structure to TIMER_config() or by passing register values to the TIMER_configArgs() function.Overview Syntax TIMER_getTStat TIMER_resetAll TIMER_setCount TIMER_setDatOut TIMER_setPeriod TIMER_SUPPORT Note: Type Description F F F F F C Reads the timer status.1 Using a TIMER Device To use a TIMER device. Once opened. there are TIMER_RMK (make) macros that construct register values based on field values.

fieldval) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address Returns the address of a memory-mapped register for a given handle Returns the value of a register for a given handle Sets the register value to x for a given handle Returns the value of the field for a given handle Sets the field value to x for a given handle See page .<REG>.<FIELD>.<REG>.<REG>) TIMER_RSETA(addr.. fieldval) TIMER_FSETSA(addr. and those that construct register and field values.<FIELD>.<FIELD>) TIMER_FSETH(h.<FIELD>) TIMER_FSET(<REG>.x) TIMER_FGETH(h..Macros 22. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 28-12 28-19 28-21 28-14 28-16 22-4 . Using the HAL Macros. Table 22−3 lists the TIMER macros that access registers and fields.<REG>.<REG>. and Table 22−4 lists the TIMER macros that construct register and field values.<FIELD>. <SYM>) TIMER_ADDRH(h.<REG>. Table 22−3.2 Macros There are two types of TIMER macros: those that access registers and fields.<REG>) TIMER_RGETH(h.<REG>) TIMER_RSETH(h.<FIELD>. TIMER Macros that Access Registers and Fields Macro TIMER_ADDR(<REG>) TIMER_RGET(<REG>) TIMER_RSET(<REG>. The TIMER module includes handle-based macros.<REG>.<REG>.<FIELD>) TIMER_FSETA(addr.<FIELD>. The macros themselves are found in Chapter 28.fieldval) TIMER_FSETS(<REG>.<SYM>) TIMER_RGETA(addr.x) TIMER_FGETA(addr.x) TIMER_FGET(<REG>.

. Field default value Field make Field make symbolically Field value of . 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 TIMER Module 22-5 ..Macros Table 22−4. TIMER Macros that Construct Register and Field Values Macro TIMER_<REG>_DEFAULT TIMER_<REG>_RMK() TIMER_<REG>_OF() TIMER_<REG>_<FIELD>_DEFAULT TIMER_FMK() TIMER_FMKS() TIMER_<REG>_<FIELD>_OF() TIMER_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of ..... Field symbolic value See page .

3 Configuration Structure TIMER_Config Structure Members Structure used to setup timer device TIMER_Config Uint32 ctl Control register value Uint32 prd Period register value Uint32 cnt Count register value This is the TIMER configuration structure used to set up a timer device. TIMER_Config MyConfig = { 0x000002C0. You create and initialize this structure and then pass its address to the TIMER_config() function. /* prd */ 0x00000000 /* cnt */ }.&MyConfig). … TIMER_config(hTimer. Description Example 22-6 .TIMER_Config 22. You can use literal values or the _RMK macros to create the structure member values. /* ctl */ 0x00010000.

The timer registers are set to their default values Arguments Return Value Description Device handle. The timer control register (CTL) is written last. /* ctl */ 0x00010000. Pointer to initialize configuration structure.TIMER_close 22. See TIMER_open().&MyConfig).4. TIMER_config Function Configure timer using configuration structure void TIMER_config( TIMER_Handle hTimer. hTimer none This function closes a previously opened timer device.The timer event is disabled and cleared . … TIMER_config(hTimer. See TIMER_configArgs() and TIMER_Config. See TIMER_open().1 Primary Functions TIMER_close Function Closes previously opened timer device void TIMER_close( TIMER_Handle hTimer ). Example TIMER_close(hTimer). hTimer config none This function sets up the timer device using the configuration structure. TIMER Module 22-7 Arguments Return Value Description Device handle. TIMER_Config MyConfig = { 0x000002C0. The following tasks are performed: . The values of the structure are written to the TIMER registers. TIMER_Config *config ).4 Functions 22. /* prd */ 0x00000000 /* cnt */ }. See TIMER_open(). Example .

See TIMER_open().TIMER_configArgs TIMER_configArgs Sets up timer using register values passed in Function void TIMER_configArgs( TIMER_Handle hTimer. The register values are written to the timer registers. You may use literal values for the arguments or for readability. Arguments Device handle. Uint32 ctl. Uint32 prd. 0x000002C0. You may use the _RMK macros to create the register values based on field values. Uint32 cnt ). The timer control register (ctl) is written last. Control register value Period register value Count register value Return Value Description 22-8 . 0x00010000. 0x00000000). hTimer ctl prd cnt none This function sets up the timer using the register values passed in. See also TIMER_config(). Example TIMER_configArgs (LTimer.

The return value is a unique device handle that is used in subsequent TIMER API calls. If the TIMER_OPEN_RESET is specified. May be restarted using TIMER_resume().TIMER_DEVANY . See TIMER_open(). the timer device registers are set to their power-on defaults and any associated interrupts are disabled and cleared.TIMER_DEV2 Open flags. Example TIMER_Handle hTimer. … TIMER_resume(hTimer). TIMER Module 22-9 Arguments Return Value Description Example Device handle.TIMER_DEV0 . Once opened. hTimer none This function pauses the timer.TIMER_open TIMER_open Function Opens timer device for use TIMER_Handle TIMER_open( int devNum. devNum Device Number: . logical OR of any of the following: TIMER_OPEN_RESET Arguments flags Return Value Description Device Handle Device handle Before a TIMER device can be used. … hTimer = TIMER_open(TIMER_DEV0. it cannot be opened again until closed. . TIMER_pause Function Pauses timer void TIMER_pause( TIMER_Handle hTimer ). Uint32 flags ). INV is returned. If the open fails.TIMER_DEV1 .0). it must first be opened by this function. TIMER_pause(hTimer). See TIMER_close().

hTimer none This function resets the timer device. TIMER_resume Function Resumes timer after pause void TIMER_resume( TIMER_Handle hTimer ). TIMER_start(hTimer). Disables and clears the interrupt event and sets the timer registers to default values. See TIMER_open(). See TIMER_open(). … TIMER_resume(hTimer). See TIMER_open(). TIMER_reset(hTimer).TIMER_reset TIMER_reset Function Resets timer device associated to the Timer handle void TIMER_reset( TIMER_Handle hTimer ). TIMER_pause(hTimer). Arguments Return Value Description Example 22-10 Device handle. See TIMER_pause(). hTimer none This function starts the timer device running. hTimer none This function resumes the timer after a pause. TIMER_start Function Starts timer device running void TIMER_start( TIMER_Handle hTimer ). HLD of the CTL control register is released and the GO bit field is set. Arguments Return Value Description Example Device handle. Arguments Return Value Description Example Device handle. .

TIMER_getConfig(hTimer.2 Auxiliary Functions and Constants TIMER_DEVICE_CNT Compile time constant Constant Description TIMER_DEVICE_CNT Compile-time constant. TIMER_getConfig Function Reads the current TIMER configuration values void TIMER_getConfig( TIMER_Handle hTimer. See TIMER_open() Pointer to a configuration structure. hTimer config Device handle. TIMER_getCount Function Returns current timer count value Uint32 TIMER_getCount( TIMER_Handle hTimer ). cnt = TIMER_getCount(hTimer).&timerCfg). hTimer Device handle. Arguments Return Value Description Example Count Value This function returns the current timer count value. Arguments Return Value Description Example none This function reads the TIMER current configuration value TIMER_Config timerCfg. See TIMER_open().4.TIMER_DEVICE_CNT 22. number of timer devices present. TIMER_Config *config ). TIMER Module 22-11 .

hTimer DATIN Device handle. See TIMER_open().TIMER_getDatIn TIMER_getDatIn Function Reads value of TINP pin int TIMER_getDatIn( TIMER_Handle hTimer ). TIMER_getPeriod Function Returns period of timer device Uint32 TIMER_getPeriod( TIMER_Handle hTimer ). hTimer Event ID Device handle. TIMER_getEventId Obtains event ID for timer device Function Uint32 TIMER_getEventId( TIMER_Handle hTimer ). hTimer Period Value Device handle. p = TIMER_getPeriod(hTimer). IRQ Event ID for the timer device Arguments Return Value Description Example Use this function to obtain the event ID for the timer device. Timer period Arguments Return Value Description Example 22-12 This function returns the period of the timer device. See TIMER_open(). TimerEventId = TIMER_getEventId(hTimer). . tinp = TIMER_getDatIn(hTimer). IRQ_enable(TimerEventId). See TIMER_open(). Returns DATIN. value on TINP pin. 0 or 1 Arguments Return Value Description Example This function reads the value of the TINP pin.

0 or 1 Arguments Return Value Description Example This function reads the timer status. Timer status. status = TIMER_getTstat(hTimer).TIMER_getTstat TIMER_getTstat Function Reads timer status. value of timer output int TIMER_getTstat( TIMER_Handle hTimer ). Count value Arguments Return Value Description Example none This function sets the count value of the timer. The timer is not paused during the update. TIMER Module 22-13 . Example TIMER_setCount Function Sets count value of timer void TIMER_setCount( TIMER_Handle hTimer. TIMER_setCount(hTimer. See also TIMER_reset() function. TIMER_resetAll Function Arguments Return Value Description Resets all timer devices supported by the chip device void TIMER_resetAll(). hTimer count Device handle.0x00000000). See TIMER_open(). none none This function resets all timer devices supported by the chip device by clearing and disabling the interrupt event and setting the default timer register values for each timer device. See TIMER_open(). hTimer TSTAT Device handle. TIMER_resetAll(). Uint32 count ). value of timer output.

Example #if (TIMER_SUPPORT) /* user TIMER configuration / #endif 22-14 . Arguments Return Value Description Example Device handle.0x00010000). hTimer val none This function sets the data output value.TIMER_setDatOut TIMER_setDatOut Function Sets data output value void TIMER_setDatOut( TIMER_Handle hTimer. all devices support this module. hTimer period none This function sets the timer period. You are not required to use this constant. TIMER_setPeriod(hTimer. See TIMER_open(). Arguments Return Value Description Example Device handle. TIMER_setDatOut(hTimer. Period value TIMER_SUPPORT Compile time constant Constant Description TIMER_SUPPORT Compile-time constant that has a value of 1 if the device supports the TIMER module and 0 otherwise. The timer is not paused during the update. Currently. See TIMER_open().0). 0 or 1 TIMER_setPeriod Function Sets timer period void TIMER_setPeriod( TIMER_Handle hTimer. Uint32 period ). int val ).

. . . . . . 23-7 23-1 . . . . . . . . . . .1 Overview . . .4 Functions . . . . . . . . . . . . .Chapter 23 UTOPIA Module This chapter describes the UTOPIA module. . . . . . . . . . . .3 Configuration Structure . . . . . . . .2 Macros . . . . . . . . and provides a UTOP API reference section. . Topic Page 23. . . . . . . . . . . . . . discusses how to set the UTOPIA interface. . . . . . . . . 23-4 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23. . . . . . . . . . . . . . lists the API functions and macros within the module. . . . . . . . . . . 23-6 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23-7 23-7 23-8 23-8 23-8 23-9 23-9 23-10 23-10 23-11 23-11 23-11 23-2 . Table 23−1 lists the configuration structure for use with the UTOP functions. Table 23−1. The properties and functionalities of each interface can be set and controlled by using the CSL APIs dedicated to the UTOPIA interface. 23-6 Table 23−2... Tests an error bit event Reads the current UTOPIA configuration structure Returns the CPU interrupt event number dedicated to the UTOPIA interface Returns the Slave Receive Queue Address.. See page . the UTOPIA consists of a transmit interface and a receive interface. UTOPIA Configuration Structure Syntax UTOP_Config Type Description S The UTOPIA configuration structure used to set the control register and the Clock Detect register See page . UTOPIA APIs Syntax UTOP_config UTOP_configArgs UTOP_enableRcv UTOP_enableXmt UTOP_errClear UTOP_errDisable UTOP_errEnable UTOP_errReset UTOP_errTest UTOP_getConfig UTOP_getEventId UTOP_getRcvAddr Type Description F F F F F F F F F F F F Sets up the UTOPIA interface using the configuration structure Sets up the UTOPIA control register and Clock detect register using the register values passed in Enables the receiver interface Enables the transmitter interface Clears a pending error bit Disables an error bit event Enables an error bit event Reset an error bit event by clearing and disabling the corresponding bits under EIPR and EIER respectively. Both interfaces are configurable via the configuration registers. Table 23−2 lists the functions and constants available in the CSL UTOPIA module.1 Overview For TMS320C64x™ devices.Overview 23..

UTOPIA APIs (Continued) Syntax UTOP_getXmtAddr UTOP_intClear UTOP_intDisable UTOP_intEnable UTOP_intReset UTOP_intTest UTOP_read UTOP_SUPPORT UTOP_write Note: F = Function. Clears the relevant interrupt pending queue bit of the UTOPIA queue interfaces. Disables the relevant interrupt queue bit of the UTOPIA queue interfaces.1 Using UTOPIA APIs To use the UTOPIA interfaces. C = Constant Type Description F F F F F F F C F Returns the Slave Transmit Queue Address. To assist in creating a register value. Clears and disables the interrupt queue event of the UTOPIA queue interfaces. Enables the relevant interrupt queue event of the UTOPIA queue interfaces.Overview Table 23−2. you must first configure the Control register and the Clock Detect register by using the configuration structure to UTOP_config() or by passing register values to the UTOP_configArgs() function. there is the UTOP_<REG>_RMK (make) macro that builds register value based on field values.. the symbol constants may be used for the field setting. 23-12 23-12 23-12 23-13 23-13 23-14 23-14 23-14 23-15 23. In addition.1. Tests a queue event interrupt Reads from the slave receive queue A compile time constant whose value is 1 if the device supports the UTOPIA module Writes into the slave transmit queue See page . UTOPIA Module 23-3 ..

<FIELD>. and those that construct register and field values.<REG>. Using the HAL Macros. Table 23−3 lists the UTOP macros that access registers and fields.<REG>.. and Table 23−4 lists the UTOP macros that construct register and field values. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 23-4 .<FIELD>) UTOP_FSETA(addr.<REG>..fieldval) UTOP_FSETS(<REG>.x) UTOP_FGETA(addr.<FIELD>. The UTOPIA module includes handle-based macros.<FIELD>) UTOP_FSET(<REG>.x) UTOP_FGET(<REG>.<SYM>) UTOP_RGETA(addr. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page . The macros themselves are found in Chapter 28. fieldval) UTOP_FSETSA(addr.<REG>) UTOP_RSETA(addr.2 Macros There are two types of UTOP macros: those that access registers and fields.Macros 23.<FIELD>.<FIELD>.<REG>. Table 23−3. UTOP Macros that Access Registers and Fields Macro UTOP_ADDR(<REG>) UTOP_RGET(<REG>) UTOP_RSET(<REG>.

..... UTOP Macros that Construct Register and Field Values Macro UTOP_<REG>_DEFAULT UTOP_<REG>_RMK() UTOP_<REG>_OF() UTOP_<REG>_<FIELD>_DEFAULT UTOP_FMK() UTOP_FMKS() UTOP_<REG>_<FIELD>_OF() UTOP_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of . Field default value Field make Field make symbolically Field value of . 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 UTOPIA Module 23-5 .. Field symbolic value See page .Macros Table 23−4.

UTOP_Config MyConfig = { 0x00010001.3 Configuration Structure UTOP_Config Structure Members UTOP configuration structure UTOP_Config Uint32 ucr Uint32 cdr UTOP control register value UTOP Clock Detect register value Description This is the UTOP configuration structure used to set up the UTOPIA registers. Example 23-6 . … UTOP_config(MyConfig). /* cdr */ }. /* ucr */ 0x00FF00FF.UTOP_Config 23. You create and initialize this structure then pass its address to the UTOP_config() function. You can use literal values or the _RMK macros to create the structure register value.

4 Functions UTOP_config Function Sets up UTOP modes using a configuration structure void UTOP_config( UTOP_Config *config ). /* ucr */ 0x00FF00FF. Example UTOP_configArgs( 0x00010000. You may use literal values for the arguments or for readability.UTOP_config 23. /* cdr */ ). The register value is written to the associated registers. See also UTOP_configArgs() and UTOP_Config. /* ucr */ 0x00FF00FF. You may use the _RMK macros to create the register values based on field values. config none Sets up the UTOPIA using the configuration structure. Arguments Return Value Description Pointer to an initialized configuration structure Example UTOP_configArgs Function Sets up UTOP mode using register value passed in Void UTOP_configArgs( Uint32 ucr. See also UTOP_config(). /* cdr */ }. UTOPIA Module 23-7 . … UTOP_config(&MyConfig). ucr cdr Control register value Clock Detect value Arguments Return Value Description none Sets up the UTOP mode using the register value passed in. The values of the structure are written to the UTOP associated register. Uint32 cdr ). UTOP_Config MyConfig = { 0x00010000.

/*ucr*/ 0x00FF00FF /*cdr*/| ). /*ucr*/ 0x00FF00FF /*cdr*/ ).UTOP_ERR_RQS .UTOP_ERR_XCP Arguments 23-8 .UTOP_enableRcv UTOP_enableRcv Function Arguments Return Value Description Example Enables UTOPIA receiver interface void UTOP_enableRcv(). UTOP_errClear Function Clears error condition bit void UTOP_errClear( Uint32 errNum ).UTOP_ERR_RCP . /* Enables Receiver port */ UTOP_enableRcv(). none none This function enables the UTOPIA receiver port.UTOP_ERR_XQS .UTOP_ERR_RCF . UTOP_enableXmt Function Arguments Return Value Description Example Enables the UTOPIA transmitter interface void UTOP_enableXmt(). /* Configures UTOPIA */ UTOP_configArgs( 0x00040004. /* Enables Transmitter port */ UTOP_enableXmt(). none none This function enables the UTOPIA transmitter port. errNum Error condition ID from the following constant list: .UTOP_ERR_XCF . /* Configures UTOPIA*/ UTOP_configArgs( 0x00040004.

UTOP_ERR_RCF .UTOP_ERR_XQS .UTOP_ERR_RQS . errNum Error condition ID from the following constant list: . /* Clears bit error condition*/ UTOP_errClear(UTOP_ERR_RCF).UTOP_ERR_RQS .UTOP_ERR_XQS .UTOP_ERR_RCP .UTOP_ERR_RCF .UTOP_ERR_XCF .UTOP_ERR_XCP Arguments Return Value none UTOPIA Module 23-9 .UTOP_ERR_XCP Arguments Return Value Description Example none This function disables the error interrupt event /* Disables error condition interrupt*/ UTOP_errDisable(UTOP_ERR_RCF).UTOP_ERR_RCP . UTOP_errEnable Function Enables the error interrupt bit void UTOP_errEnable( Uint32 errNum ). UTOP_errDisable Function Disables the error interrupt bit void UTOP_errDisable( Uint32 errNum ).UTOP_ERR_XCF .UTOP_errDisable Return Value Description Example none This function clears the bit of given error condition ID of EIPR. errNum Error condition ID from the following constant list: .

UTOP_ERR_RQS .UTOP_ERR_RQS .UTOP_ERR_XCP Arguments Return Value Description Example none This function resets the error interrupt event by disabling and clearing the error interrupt bit associated to the error condition. UTOP_errTest Function Tests the error interrupt event bit Uint32 UTOP_errTest( Uint32 errNum ).UTOP_ERR_RCP .UTOP_ERR_XCP Equals to 1 if Error event has occurred and 0 otherwise Arguments Return Value Description 23-10 val This function tests the error interrupt event by returning the bit status.UTOP_ERR_XQS .UTOP_errReset Description Example This function enables the error interrupt event.UTOP_ERR_XCF . /* Enables error condition interrupt */ UTOP_errEnable(UTOP_ERR_RCF).UTOP_ERR_XQS . errNum Error condition ID from the following constant list: .UTOP_ERR_RCF .UTOP_ERR_RCF . UTOP_errReset Function Resets the error interrupt event bit void UTOP_errReset( Uint32 errNum ). errNum Error condition ID from the following constant list: .UTOP_ERR_XCF .UTOP_ERR_RCP . . /* Resets error condition interrupt */ UTOP_errReset(UTOP_ERR_RCF).

UTOP_getConfig(&UTOPCfg). Arguments Return Value Description Example Pointer to a configuration structure. none val UTOPIA Event ID UTOPIA Module 23-11 . UTOP_getRcvAddr Function Arguments Return Value Returns the Receiver Queue address Uint32 UTOP_getRcvAddr().UTOP_getConfig Example /* Enables error condition interrupt */ Uint32 errDetect. UTOP_errEnable(UTOP_ERR_RCF). UtopEventId = UTOP_getEventId(). UTOP_getEventId Function Arguments Return Value Description Example Returns the UTOPIA interrupt Event ID Uint32 UTOP_getEventId(). See also UTOP_config() and UTOP_configArgs() functions. Config none Get UTOP current configuration value. none val UTOPIA Event ID This function returns the event ID associated to the UTOPIA CPU-interrupt. UTOP_config UTOPCfg. errDetect = UTOP_errTest(UTOP_ERR_RCF) UTOP_getConfig Function Reads the current UTOP configuration structure Uint32 UTOP_getConfig( UTOP_Config *Config ). See also IRQ_EVT_NNNN (IRQ Chapter 13) Uint32 UtopEventId.

UTOP_INT_RQ Arguments Return Value Description Example none Clears the associated bit to the interrupt ID of the utopia interrupt pending register (UIPR). none val UTOPIA Event ID This function returns the address of the Transmit Queue. Uint32 UtopXmtAddr. UTOP_intDisable Function Disables the interrupt to the CPU void UTOP_intDisable( Uint32 intNum ). UtopXmtAddr = UTOP_getXmtAddr(). This address is needed when you read from the Receiver Port. UTOP_intClear Function Clears the interrupt bit related to Receive and Transmit Queues void UTOP_intClear( Uint32 intNum ). intNum The interrupt ID from the following list: . intNum The interrupt ID from the following list: .UTOP_INT_XQ .UTOP_INT_RQ Arguments 23-12 . This address is needed when you write to the Transmit Port. Uint32 UtopRcvAddr. /* Clears the flag of the receive event */ UTOP_intClear(UTOP_INT_RQ). UTOP_getXmtAddr Function Arguments Return Value Description Example Returns the Transmit Queue address Uint32 UTOP_getXmtAddr().UTOP_INT_XQ .UTOP_getXmtAddr Description Example This function returns the address of the Receiver Queue. UtopRcvAddr = UTOP_getRcvAddr().

UTOP_INT_RQ Arguments Return Value Description none Enables the interrupt to the CPU by setting the bit to 1. /* Disables the interrupt of the receive event */ UTOP_intDisable(UTOP_INT_RQ). No interrupts are sent if the corresponding event occurs. The interrupt event is sent to the CPU selector. The CPU interrupt is generated only if the relevant bit is set under UIER register.UTOP_INT_XQ . /* Resets the interrupt of the receive event */ UTOP_intReset(UTOP_INT_RQ). Example UTOP_intReset Function Resets the interrupt to the CPU void UTOP_intReset( Uint32 intNum ).UTOP_intEnable Return Value Description Example none Disables the interrupt bit to the CPU. intNum The interrupt ID from the following list: .UTOP_INT_RQ Arguments Return Value Description Example none Resets the interrupt to the CPU by disabling the interrupt bit uner UIER and clearing the pending bit of UIPR. UTOP_intEnable Function Enables the interrupt to the CPU void UTOP_intEnable( Uint32 intNum ). /* Enables the interrupt of the receive event */ UTOP_intEnable(UTOP_INT_RQ). UTOPIA Module 23-13 . intNum The interrupt ID from the following list: . IRQ_enable(IRQ_EVT_UINT).UTOP_INT_XQ .

UTOP_INT_XQ . UTOP_SUPPORT Constant Description Compile-time constant UTOP_SUPPORT Compile-time constant that has a value of 1 if the device supports the UTOP module and 0 otherwise. /* Reads data from the receive queue */ UtopData = UTOP_read(). Example #if (UTOP_SUPPORT) /* user UTOP configuration / #endif 23-14 . You are not required to use this constant. Uint32 UtopData.UTOP_INT_RQ Equal to 1 if the event has occurred and 0 otherwise Arguments Return Value Description Example val Tests the interrupt to the CPU has occurred by reading the corresponding flag of UIPR register.UTOP_intTest UTOP_intTest Function Tests the interrupt event Uint32 UTOP_intReset( Uint32 intNum ). Note: The UTOP module is not supported on devices that do not have the UTOP peripheral. intNum The interrupt ID from the following list: . none val Value from the receive queue Reads data from the receive queue. UTOP_read Function Arguments Return Value Description Example Reads the UTOPIA receive queue Uint32 UTOP_read(). Uint32 UtopEvent. /* Tests the interrupt of the receive event */ UtopEvent = UTOP_intTest(UTOP_INT_RQ).

UTOP_write UTOP_write Function Writes to the UTOPIA transmit queue void UTOP_write( Uint32 val ). Arguments Return Value Description Example Value to be written into transmit queue UTOPIA Module 23-15 . Uint32 UtopData = 0x1111FFFF. /* Writes data into the transmit queue */ UTOP_write(UtopData). val none Writes data into the transmit queue.

.3 Configuration Structures . . . . . . . . .2 Macros . . . . . . . . . . . . and provides a VCP API reference section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . discusses how to use the VCP. . . . . . . 24-7 24. . . . . . . . . . . . . . . . . . . 24-5 24. . . . . . . . . . . . . . . . . . . . . . . 24-2 24. . . . . . . . . . . . . . . . . . . . . . . . Topic Page 24. . . . . . . .1 Overview . . .4 Functions . . . . . . . . . . . . . . . . . . .Chapter 24 VCP Module This chapter describes the VCP module. . . . . . . . lists the API functions and macros within the module. . . . . . . . . . 24-11 24-1 . . . . . . . . . .

Table 24−1 lists the configuration structures for use with the VCP functions.1 Overview The Viterbi co-processor is supported only on TMS320C6416.. Table 24−2 lists the functions and constants available in the CSL VCP module. C = Constant F F 24-13 24-14 24-2 .. The VCP should be serviced using the EDMA for most accesses.. Table 24−1.Overview 24.. VCP APIs Syntax VCP_ceil VCP_DECISION_HARD VCP_DECISION_SOFT VCP_END_NATIVE VCP_END_PACKED32 VCP_errTest VCP_genIc Type Description F C C C C F F Ceiling function Value indicating hard decisions output Value indicating soft decisions output Value indicating native data format Value indicating packed data format Returns the error code Generates the VCP_ConfigIc struct based on the VCP parameters provided by the VCP_Params struct Function used to set basic VCP Parameters Returns branch metrics data endian configuration See page . 24-7 24-8 24-9 Table 24−2. 24-11 24-11 24-11 24-11 24-12 24-12 24-12 VCP_genParams VCP_getBmEndian Note: F = Function. but the CPU must first configure the VCP control values. VCP Configuration Structures Syntax VCP_BaseParams VCP_ConfigIc VCP_Params Type Description S S S Structure used to set basic VCP Parameters Structure containing the IC register values Structure containing all channel characteristics See page . There are also a number of functions available to the CPU to monitor the VCP status and access decision and output parameter data.

VCP APIs (Continued) Syntax VCP_getIcConfig VCP_getMaxSm VCP_getMinSm VCP_getNumInFifo VCP_getNumOutFifo VCP_getSdEndian VCP_getYamBit VCP_icConfig VCP_icConfigArgs VCP_normalCeil VCP_pause VCP_RATE_1_2 VCP_RATE_1_3 VCP_RATE_1_4 VCP_reset VCP_setBmEndian VCP_setNativeEndian VCP_setPacked32Endian VCP_setSdEndian VCP_start VCP_statError VCP_statInFifo Note: F = Function.Overview Table 24−2. C = Constant Type Description F F F F F F F F F F F C C C F F F F F F F F Returns the IC values already programmed into the VCP Returns the final maximum state metric Returns the final minimum state metric Returns the number of symbols in the input FIFO Returns the number of symbols in the output FIFO Returns the soft decisions data configuration Returns the Yamamoto bit result Stores the IC values into the VCP Stores the IC values into the VCP using arguments Normalized ceiling function Pauses the VCP Value indicating a rate of 1/2 Value indicating a rate of 1/3 Value indicating a rate of 1/4 Resets the VCP Sets the branch metrics data endian configuration Sets all data formats to be native (not packed data) Sets all data formats to be packed data Sets the soft decisions data configuration Starts the VCP Returns the error status Returns the input FIFO status See page .. 24-14 24-15 24-15 24-15 24-16 24-16 24-16 24-17 24-18 24-18 24-19 24-19 24-19 24-19 24-19 24-20 24-20 24-21 24-21 24-21 24-22 24-22 VCP Module 24-3 ..

1 Using the VCP To use the VCP. the configuration function can be bypassed and the user can generate each IC value independently using several VCP_RMK (make) macros that construct register values based on field values. When operating in big endian mode the CPU must configure the format of all the data to be transferred to and from the VCP. the symbol constants may be used for the field values. or IC values. the data will all be of the same format. If desired.Overview Table 24−2.1. 24-22 24-23 24-23 24-23 24-24 24-24 24-24 24-24 24-25 24-25 24. VCP_Params contains all of the channel characteristics required to configure the VCP. you must first configure the control values.. Alternatively. C = Constant Type Description F F F F F F C C C F Returns the output FIFO status Returns the pause status Returns the run status Returns the Number of Symbols processed status bit Returns the input control status Stops the VCP Value indicating convergent traceback mode Value indicating mixed traceback mode Value indicating tailed traceback mode Unpauses the VCP See page . the values can be set using a single function call to either VCP_nativeEndianSet() or VCP_packed32EndianSet(). This configuration function returns a pointer to the IC values that are to be sent using the EDMA. Typically. This is accomplished by programming the VCP Endian register (VCP_END). To do this. In addition. The user can monitor the status of the VCP during operation and also monitor error flags if there is a problem. either following the native element size (either 8-bit or 16-bit) or packed into a 32-bit word. VCP APIs (Continued) Syntax VCP_statOutFifo VCP_statPause VCP_statRun VCP_statSymProc VCP_statWaitIc VCP_stop VCP_TRACEBACK_CONVERGENT VCP_TRACEBACK_MIXED VCP_TRACEBACK_TAILED VCP_unpause Note: F = Function. This being the case. the VCP_Params structure is passed to VCP_icConfig(). the data format of individual data types can be programmed with independent functions. that will be sent via the EDMA to program its operation. 24-4 ..

The macros themselves are found in Chapter 28. VCP Macros that Access Registers and Fields Macro VCP_ADDR(<REG>) VCP_RGET(<REG>) VCP_RSET(<REG>.2 Macros There are two types of VCP macros: those that access registers and fields. These VCP functions make use of a number of macros. Using the HAL Macros..<FIELD>) VCP_FSETA(addr.<FIELD>. These are not required as all VCP configuring and monitoring can be done through the provided functions.<FIELD>.<REG>. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page . Table 24−3.x) VCP_FGETA(addr. and Table 24−4 lists the VCP macros that construct register and field values.<REG>.<REG>) VCP_RSETA(addr.. The VCP module includes handle-based macros.<REG>.x) VCP_FGET(<REG>. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 VCP Module 24-5 . and those that construct register and field values.<REG>.<FIELD>. Table 24−3 lists the VCP macros that access registers and fields.fieldval) VCP_FSETS(<REG>. fieldval) VCP_FSETSA(addr.<FIELD>.Macros 24.<FIELD>) VCP_FSET(<REG>.<SYM>) VCP_RGETA(addr.

Macros Table 24−4. Field symbolic value See page . 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 24-6 . Field default value Field make Field make symbolically Field value of .... VCP Macros that Construct Register and Field Values Macro VCP_<REG>_DEFAULT VCP_<REG>_RMK() VCP_<REG>_OF() VCP_<REG>_<FIELD>_DEFAULT VCP_FMK() VCP_FMKS() VCP_<REG>_<FIELD>_OF() VCP_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of ....

Example VCP Module 24-7 .8.3 Configuration Structure VCP_BaseParams Structure used to set basic TCP parameters Structure Members VCP_BaseParams VCP_Rate Uint8 Uint16 Uint16 Uint8 Uint8 Uint8 rate. /*Stat Index to set to IMAXS (IMAXI) */ 0. Code rate Code rate Frame Length Yamamoto Threshold State Index Hard/soft Decision Output Parameter Read flag Description This is the VCP base parameters structure used to set up the VCP programmable parameters. /*Constraint Length (K=5. readFlag. &vcpParam0). constLen. yamTh.VCP_BaseParams 24. … VCP_genParams(&vcpBaseParam0. /*Frame Length (FL) */ 0.7. stateNum. /*Yamamoto Threshold (YAMT)*/ 0. VCP_BaseParams vcpBaseParam0 = { 3. frameLen. OR 9)*/ 81. decision. You create the object and pass it to the VCP_genParams() function which returns the VCP_Params structure.6. /* Rate */ 9. /*Output Hard Decision Type */ 0 /*Output Parameters Read Flag */ }. See the VCP_genParams() function.

VCP_ConfigIc *config. Uint32 ic4. config). Example 24-8 . Uint32 ic5. the values can be written to the VCP using the CPU with the VCP_icConfig() function.. ic0 ic1 ic2 ic3 ic4 ic5 Input Configuration word 0 value Input Configuration word 1 value Input Configuration word 2 value Input Configuration word 3 value Input Configuration word 4 value Input Configuration word 5 value Members Description This is the VCP input configuration structure that holds all of the configuration values that are to be transferred to the VCP via the EDMA. Though using the EDMA is highly recommended. .VCP_ConfigIc VCP_ConfigIc Structure Structure containing the IC register values typedef struct { Uint32 ic0.. VCP_genIc(params. Uint32 ic1. Uint32 ic2. extern VCP_Params *params. } VCP_ConfigIc. Uint32 ic3.

Uint32 constLen. Uint32 bmBuffLen. Uint32 poly1. Uint32 decBuffLen. Uint32 readFlag. } VCP_Params. Uint32 frameLen. Uint32 numDecisions. Uint32 poly0. Uint32 decision. 1/3. Uint32 maxSm. rate The rate: 1/2. Uint32 poly3. 1/4 The available constants are: .VCP_RATE_1_2 . Uint32 minSm.VCP_RATE_1_4 Constraint length Polynomial 0 Polynomial 1 Polynomial 2 Polynomial 3 Yamamoto Threshold value The number of symbols in a frame Reliability length Convergence distance Maximum initial state metric Minimum initial state metric State index set to the maximum initial state metric VCP Module 24-9 Members constLen poly0 poly1 poly2 poly3 yamTh frameLen relLen convDist maxSm minSm stateNum . Uint32 relLen. Uint32 convDist. Uint32 poly2. Uint32 stateNum. Uint32 numBranchMetrics.VCP_Params VCP_Params Structure Structure containing all channel characteristics typedef struct { VCP_Rate rate. Uint32 yamTh.VCP_RATE_1_3 . Uint32 traceBack.

VCP_TRACEBACK_NONE .VCP_TRACEBACK_TAILED .VCP_TRACEBACK_MIXED . config)..VCP_Params Branch metrics buffer length in input FIFO Decisions buffer length in output FIFO Traceback mode The available constants are: . bmBuffLen decBuffLen traceBack Example 24-10 . VCP_ConfigIc *config.VCP_TRACEBACK_CONVERGENT readFlag Output parameters read flag decision Decision selection: hard or soft The following constants are available: . . extern VCP_Params *params...VCP_DECISION_HARD .VCP_DECISION_SOFT numBranchMetrics Number of branch metrics per event numDecisions Number of decisions words per event Description This is the VCP parameters structure that holds all of the information concerning the user channel. . VCP_genIc(params.. These values are used to generate the appropriate input configuration values for the VCP and to program the EDMA.

pwr2). VCP_DECISION_HARD Constant Description Value indicating hard decisions output VCP_DECISION_HARD This constant allows selection of hard decisions output from the VCP. VCP_END_NATIVE Value indicating native endian format Constant Description VCP_END_NATIVE This constant allows selection of the native format for all data transferred to and from the VCP.VCP_ceil 24. numSysPar = VCP_ceil((frameLen * rate). That is to say that all data is contiguous in memory with incrementing addresses. VCP Module 24-11 . This function calculates the ceiling for a given value and a power of 2. VCP_DECISION_SOFT Constant Description Value indicating soft decisions output VCP_DECISION_SOFT This constant allows selection of soft decisions output from the VCP.4 Functions VCP_ceil Function Arguments Return Value Description Example Ceiling function Uint32 VCP_ceil(Uint32 val. Uint32 pwr2). val pwr2 ceilVal Value to be augmented The power of two by which val must be divisible The smallest number which when multiplied by 2^pwr2 is greater than val. The arguments follow the formula: ceilVal * 2^pwr2 = ceiling(val. 4).

.. . VCP_ConfigIc *config. .VCP_END_PACKED32 VCP_END_PACKED32 Constant Description Value indicating little endian format within packed 32-bit words VCP_END_PACKED32 This constant allows selection of the packed 32-bit format for data transferred to and from the VCP. Arguments Return Value Description Example Pointer to Channel parameters structure Pointer to Input Configuration structure 24-12 . /* check whether an error has occurred */ if (VCP_errTest()){ } /* end if */ VCP_genIc Function Generates the VCP_ConfigIc struct void VCP_genIc( VCP_Params *restrict configParms. VCP_errTest Function Arguments Return Value Description Example Returns the error code Uint32 VCP_errTest().. That is to say that all data is packed into 32-bit words in little endian format and these words are contiguous in memory. config). VCP_ConfigIc *restrict configIc ) configParms configIc None This function generates the required input configuration values needed to program the VCP based on the parameters provided by configParms. extern VCP_Params *params.. VCP_genIc(params. None Error code Code error value This function returns an ERR bit indicating what VCP error has occurred.

VCP_genParams(&vcpBaseParam0.VCP_genParams VCP_genParams Function Sets basic VCP Parameters void VCP_genParams( VCP_BaseParams *configBase. VCP Module 24-13 . VCP_Params *configParams ) configBase configParams None This function calculates the TCP parameters based on the input VCP_BaseParams object values and set the values to the output VCP_Params parameters structure. &vcpParam0). The calculated parameters are: Polynomial constants: - Arguments Return Value Description Pointer to VCP_BaseParams structure Output VCP_Params structure pointer G0-G3 (POLY1-POLY3) Traceback (TB) Convergence Distance (CD) Reliability Length (R) Decision Buffer Length (SYMR +1) Branch Metric Buffer Length (SYMX +1) Max Initial Metric State (IMAXS) Min Initial Metric State (IMINS) Example VCP_Params vcpParam0.

..VCP_getBmEndian VCP_getBmEndian Returns branch metrics data endian configuration Function Arguments Return Value Description Uint32 VCP_getBmEndian().. } /* end if */ VCP_getIcConfig Function Arguments Return Value Description Example Returns the IC values already programmed into the VCP void VCP_getIcConfig(VCP_ConfigIc *config) config None This function reads the input configuration values currently programmed into the VCP. Pointer to Input Configuration structure 24-14 .. None Endian Endian setting for branch metrics data This function returns the value programmed into the END register for the branch metrics data indicating whether the data is in its native 8-bit format (‘1’) or consists of values packed in little endian format into 32-bit words (‘0’). VCP_ConfigIc *config. . VCP_setPacked32Endian. VCP_setSdEndian. Example If (VCP_getBmEndian()){ . .. See also VCP_setBmEndian. VCP_getIcConfig(config). VCP_getSdEndian. VCP_setNativeEndian.. This should always be ‘0’ for little endian operation.

numSym = VCP_getNumInFifo(). None State Metric Final maximum state metric This function returns the final maximum state metric after the VCP has completed its decoding. VCP_getMinSm Function Arguments Return Value Description Returns the final minimum state metric Uint32 VCP_getMinSm(). VCP_getNumInFifo Returns the number of symbols in the input FIFO Function Arguments Return Value Description Example Uint32 VCP_getNumInFifo(). MinSm = VCP_getMinSm(). Example Uint32 minSm. MaxSm = VCP_getMaxSm(). None count The number of symbols currently in the input FIFO this function returns the number of symbols currently in the input FIFO. See also VCP_getMaxSm. Example Uint32 maxSm. VCP Module 24-15 .VCP_getMaxSm VCP_getMaxSm Function Arguments Return Value Description Returns the final maximum state metric Uint32 VCP_getMaxSm(). None State Metric Final minimum state metric This function returns the final minimum state metric after the VCP has completed its decoding. See also VCP_getMinSm.

24-16 . See also VCP_setSdEndian. VCP_setPacked32Endian.. VCP_getSdEndian Returns soft decision data endian configuration Function Arguments Return Value Description Uint32 VCP_getSdEndian(). YamBit = VCP_getYamBit(). Uint32 yamBit. None Endian Endian setting for soft decision data This function returns the value programmed into the VCP_END register for the soft decision data indicating whether the data is in its native 16-bit format (‘1’) or consists of values packed in little endian format into 32-bit words (‘0’). None bit Yamamoto bit result Returns the value of the Yamamoto bit after the VCP decoding. numSym = VCP_getNumOutFifo().VCP_getNumOutFifo VCP_getNumOutFifo Returns the number of symbols in the output FIFO Function Arguments Return Value Description Example Uint32 VCP_getNumOutFifo(). } /* end if */ VCP_getYamBit Function Arguments Return Value Description Example Returns the Yamamoto bit result Uint32 VCP_getYamBit(). VCP_setNativeEndian. Example If (VCP_getBmEndian()){ . This should always be ‘0’ for little endian operation. None count The number of symbols currently in the output FIFO this function returns the number of symbols currently in the output FIFO..

. . VCP_genIc(params.. This is not the recommended means by which to program the VCP.. as it is more efficient to transfer the IC values using the EDMA.. extern VCP_Params *params.VCP_icConfig VCP_icConfig Function Arguments Return Value Description Stores the IC values into the VCP void VCP_icConfig(VCP_ConfigIc *config) Config None This function stores the input configuration values currently programmed into the VCP. but can be used in test code.. VCP_ConfigIc *config. VCP_icConfig(config). config). Pointer to Input Configuration structure Example VCP Module 24-17 .

VCP_icConfigArgs VCP_icConfigArgs Stores the IC values into the VCP using arguments Function void VCP_icConfigArgs( Uint32 ic0. winSize = VCP_normalCeil(winSize. Uint32 ic2. Uint32 ic4. as it is more efficient to transfer the IC values using the EDMA. Uint32 ic1. Arguments Input Configuration word 0 value Input Configuration word 1 value Input Configuration word 2 value Input Configuration word 3 value Input Configuration word 4 value Input Configuration word 5 value Return Value Description Example /* /* /* /* /* /* IC0 IC1 IC2 IC3 IC4 IC5 */ */ */ */ */ */ VCP_normalCeil Function Arguments Return Value Description Example 24-18 Normalized ceiling function Uint32 VCP_normalCeil(Uint32 val1. . Uint32 ic3. val1 val2 ceilVal Value to be augmented Value by which val1 must be divisible The smallest number greater than or equal to val1 that is divisible by val2. numSlidingWindow). VCP_icConfigArgs( 0x00283200 0x00270000 0x00080118 0x001E0014 0x00000000 0x00000002 ). Uint32 val2) . Uint32 ic5 ) ic0 ic1 ic2 ic3 ic4 ic5 None This function stores the input configuration values currently programmed into the VCP. This is not the recommended means by which to program the VCP. but can be used in test code. This function returns the smallest number greater than or equal to val1 that is divisible by val2.

VCP Module 24-19 . See also VCP_start(). None None This function pauses the VCP by writing a pause command in the VCP_EXE register. VCP_RATE_1_4 Constant Description Value indicating a rate of 1/4 VCP_RATE_1_4 This constant allows selection of a rate of 1/4.VCP_pause VCP_pause Function Arguments Return Value Description Example Pauses VCP by writing a pause command in VCP_EXE void VCP_pause(). VCP_reset Function Arguments Return Value Description Example Resets VCP registers to default values Uint32 VCP_reset(). VCP_RATE_1_2 Constant Description Value indicating a rate of 1/2 VCP_RATE_1_2 This constant allows selection of a rate of 1/2. VCP_RATE_1_3 Constant Description Value indicating a rate of 1/3 VCP_RATE_1_3 This constant allows selection of a rate of 1/3. VCP_unpause(). and VCP_stop(). VCP_pause(). VCP_reset(). None None This function sets all of the VCP control registers to their default values.

None None This function programs the VCP to view the format of all data as native 8-/16-bit format. Example VCP_setNativeEndian(). See also VCP_setPacked32Endian. VCP_getBmEndian.VCP_setBmEndian VCP_setBmEndian Sets the branch metrics data endian configuration Function Void VCP_setBmEndian( Uint32 bmEnd ).VCP_END_PACKED32 Arguments Return Value Description None This function programs the VCP to view the format of the branch metrics data as either native 8-bit format (‘1’) or values packed into 32-bit words in little endian format (‘0’). VCP_setBmEndian.VCP_END_NATIVE . bmEnd Endian setting for branch metrics data The following constants can be used: . VCP_setSdEndian. VCP_setNativeEndian Sets all data formats to native (not packed data) Function Arguments Return Value Description void VCP_setNativeEndian(). 24-20 . This should always be ‘0’ for little endian operation. Example VCP_setBmEndian(VCP_END_PACKED32). VCP_setNativeEndian. VCP_getSdEndian. VCP_setPacked32Endian. This should only be used when running in big endian mode. See also VCP_getBmEndian.

Starts VCP by writing a start command in VCP_EXE void VCP_start(). VCP_setSdEndian. VCP_getSdEndian. SdEnd Endian setting for soft decision data The following constants can be used: . See also VCP_setNativeEndian. This should always be used when running in little endian mode and should be used in big endian mode only if the CPU is formatting the data. Example VCP_setPacked32Endian(). See also VCP_getSdEndian. and VCP_stop(). VCP Module 24-21 .VCP_END_PACKED32 Arguments Return Value Description None This function programs the VCP to view the format of the soft decision data as either native 8-bit format (‘1’) or values packed into 32-bit words in little endian format (‘0’). VCP_getBmEndian. VCP_setBmEndian. None None This function programs the VCP to view the format of all data as packed data in 32-bit words. Example VCP_start Function Arguments Return Value Description Example VCP_setSdEndian(VCP_END_PACKED32). VCP_setNativeEndian. VCP_setSdEndian Sets soft decision data endian configuration Function Void VCP_setSdEndian (Uint32 sdEnd ). VCP_start().VCP_setPacked32Endian VCP_setPacked32Endian Sets all data formats to packed data Function Arguments Return Value Description void VCP_setPacked32Endian(). VCP_setPacked32Endian.VCP_END_NATIVE . VCP_unpause(). None None This function starts the VCP by writing a start command to the VCP_EXE register. This should always be ‘0’ for little endian operation. See also VCP_pause().

None Empty Flag Flag indicating FIFO empty This function returns the input FIFO’s empty status flag. A ‘1’ indicates that the output FIFO is full and a ‘1’ indicates it is not full.VCP_statError VCP_statError Function Arguments Return Value Description Example Returns the error status Uint32 VCP_statError(). } /* end if */ 24-22 . } /* end if */ VCP_statInFifo Function Arguments Return Value Description Example Returns the input FIFO status Uint32 VCP_statInFifo().. If (VCP_statOutFifo()){ ... None Error status Boolean indication of any error This function returns a Boolean value indicating whether any VCP error has occurred.. If (VCP_statInFifo()){ . } /* end if */ VCP_statOutFifo Function Arguments Return Value Description Example Returns the output FIFO status Uint32 VCP_statOutFifo(). None Empty Flag Flag indicating FIFO full This function returns the output FIFO’s full status flag. A ‘1’ indicates that the input FIFO is empty and a ‘0’ indicates it is not empty. /* check whether an error has occurred */ if (VCP_statError()){ error = VCP_errTest().

/* start the VCP */ VCP_start(). /* wait for pause to take place */ while (!VCP_statPause()).VCP_statPause VCP_statPause Function Arguments Return Value Description Example Returns pause status Uint32 VCP_statPause(). /* check that the VCP is running */ while (!VCP_statRun()). None Status Boolean status This function returns the PAUSE bit status indicating whether the VCP is paused or not. numSym = VCP_statSymProc(). /* pause the VCP */ VCP_pause(). VCP_statRun Function Arguments Return Value Description Example Returns the run status Uint32 VCP_statRun(). None count The number of symbols processed This function returns the NSYMPROC status bit of the VCP. None Status Boolean status This function returns the RUN bit status indicating whether the VCP is running. VCP_statSymProc Returns number of symbols processed Function Arguments Return Value Description Example Uint32 VCP_statSymProc(). VCP Module 24-23 .

VCP_statWaitIc VCP_statWaitIc Function Arguments Return Value Description Example Returns input control status Uint32 VCP_statWaitIc(). VCP_unpause().. and VCP_start(). If (statWaitIc()){ . VCP_stop(). None Status Boolean status This function returns the WIC bit status indicating whether the VCP is waiting to receive new IC values. 24-24 .. } /* end if */ VCP_stop Function Arguments Return Value Description Example Stops the VCP by writing a stop command in VCP_EXE void VCP_stop(). See also VCP_pause(). VCP_TRACEBACK_MIXED Value indicating mixed traceback mode Constant Description VCP_TRACEBACK_MIXED This constant allows selection of mixed traceback mode. None None This function stops the VCP by writing a stop command to the VCP_EXE register. VCP_TRACEBACK_CONVERGENT Constant Description Value indicating convergent tracebackmode VCP_TRACEBACK_CONVERGENT This constant allows selection of convergent traceback mode.

Example VCP Module 24-25 . and VCP_stop(). See also VCP_pause(). None None This function un-pauses the VCP by writing an un-pause command to the VCP_EXE register. VCP_unpause().VCP_TRACEBACK_TAILED VCP_TRACEBACK_TAILED Constant Description Value indicating tailed traceback mode VCP_TRACEBACK_TAILED This constant allows selection of tailed traceback mode. VCP_start(). VCP_unpause Function Arguments Return Value Description Un-pauses the VCP by writing an unpause command in VCP_EXE void VCP_unpause().

. . . . . . . . . . 25-3 25. . . . . . . . . . . . . . 25-2 25. . . . . and provides a VIC reference section. . . . . . . . . . . . . . . . . . . . .2 Macros . . . . . .1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . Topic Page 25. . . . . . . . . . . . . . . . . . . . . . . . . . .Chapter 25 VIC Module Describes the VIC module. . . . . . . . . . . . . . 25-4 25-1 . . . . . . . . . . . . . . . . . . . . . . . lists the API functions and macros within the module. . . . . .3 Functions . . . . . . . .

Table 25−1 lists the functions and constants available in the CSL VIC module. and DM640 devices.1 Overview The VCXO interpolated control (VIC) port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. VIC Functions and Constants Syntax VIC_getPrecision VIC_getGo VIC_getInputBits VIC_getClkDivider VIC_setPrecision VIC_setGo VIC_setInputBits VIC_setClkDivider Type Description F F F F F F F F Gets the resolution of the interpolation Gets the value of the GO bit of the VICCTL register Gets the value written by the DSP Gets the clock divider for the interpolation frequency Sets the resolution of the interpolation Sets the value of the GO bit of the VICCTL register Writes to the VICIN register Sets the clock divider for the interpolation frequency See page 25-4 25-4 25-5 25-5 25-6 25-6 25-7 25-7 25-2 . DM641.Overview 25. The VIC module is currently supported only on the DM642. The frequency of interpolation is dependent on the resolution needed. Table 25−1.

2 Macros There are two types of VIC macros: those that access registers and fields.<REG>.x) VIC_FGET(<REG>. VIC Macros That Access Registers and Fields Macro VIC_ADDR(<REG>) VIC_RGET(<REG>) VIC_RSET(<REG>.<FIELD>. Table 25−2.<REG>) VIC_RSETA(addr. and those that construct register and field values.<REG>..<FIELD>) VIC_FSETA(addr..Overview 25. Using the HAL Macros..<FIELD>) VIC_FSET(<REG>..<REG>.fieldval) VIC_FSETS(<REG>. and Table 25−3 lists the VIC macros that construct register and field values.<FIELD>. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Returns the value of the specified field in the peripheral register Register set Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 Table 25−3. Table 25−2 lists the VIC macros that access registers and fields. The macros themselves are found in Chapter 28.<FIELD>.x) VIC_FGETA(addr.<REG>. fieldval) VIC_FSETSA(addr.<SYM>) VIC_RGETA(addr.<FIELD>. VIC Macros That Construct Register and Field Values Macro VIC_<REG>_DEFAULT VIC_<REG>_RMK() VIC_<REG>_OF() VIC_<REG>_<FIELD>_DEFAULT VIC_FMK() VIC_FMKS() VIC_<REG>_<FIELD>_OF() VIC_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of . Field default value Field make Field make symbolically Field value of . Field symbolic value See page 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 VIC Module 25-3 .

A GO bit value of 1 disallows writes to these registers. Uint32 getGoStatus. 25-4 . precision = VIC_getPrecision(). None Uint32 Returns the precision of resolution of the interpolation Precision bits determine the resolution of the interpolation. . VIC_getGo Function Arguments Return Value Description Example Gets the value of the GO bit of the VICCTL register Uint32 VIC_getGo(). If this is 0..3 Functions VIC_getPrecision Function Arguments Return Value Description Example Gets the value of the precision bits Uint32 VIC_getPrecision().. writes to the VICCTL and VICDIV registers are permitted. . getGoStatus = VIC_getGo().VIC_getPrecision 25. Uint32 precision. None Uint32 Returns precision of resolution of the interpolation Gets the status of the GO bit...

VIC_getInputBits VIC_getInputBits Function Arguments Return Value Description Gets the value written by the DSP Uint32 VIC_getInputBits None Uint32 Returns value written by DSP to the VICIN register The DSP writes the input bits for VCXO interpolated control in the VIC input register (VICIN).. VIC Module 25-5 . .. getInputBits = VIC_getInputBits(). Example Uint32 getInputBits. The DSP can write to VICIN only when the GO bit in the VIC control register (VICCTL) is set to 1.. This API returns the value written by the DSP to the VICINBITS field of the VICIN register. getClkDivider = VIC_getClkDivider(). This API returns this value. . VIC_getClkDivider Gets the clock divider for the interpolation frequency Function Arguments Return Value Description Example Uint32 VIC_getClkDivider None Uint32 Returns value of the VICCLKDIV field of the VICDIV register The VIC clock divider register (VICDIV) defines the clock divider for the VIC interpolation frequency. Uint32 getClkDivider..

If the GO bit is 0. If the GO bit is 1. disallowing any further changes to the VICCTL and VICDIV registers. a write to the PRECISION bits does not change the bits. VIC_setPrecision(VIC_VICCTL_PRECISION_16BITS). The PRECISION bits can only be written when the GO bit is cleared to 0. the VICDIV and VICCTL (except for the GO bit) registers cannot be written. The VIC port is in its normal working mode in this state. it results in GO = 0 while keeping the rest of the VICCTL bits unchanged. Example VIC_setGo(VIC_VICCTL_GO_0). Example VIC_setGo Function Arguments Return Value Description Sets the value of the GO bit of the VICCTL register void VIC_setGo Uint32 Value None The GO bit can be written to at any time. If a write is performed to the VICDIV or VICCTL registers when the GO bit is set.VIC_setPrecision VIC_setPrecision Function Arguments Return Value Description Sets the resolution of the interpolation void VIC_setPrecision Uint32 Precision value None Precision bits determine the resolution of the interpolation. If a write is performed that clears the GO bit to 0 and changes the values of other VICCTL bits. This bit controls whether writes to VICDIV and VICCTL registers are permitted or are invalid. 25-6 . A write to VICCTL programs the VICCTL register and sets the GO bit to 1. If the GO bit is set to 1. the values of these registers remain unchanged. these registers can be updated.

VIC_setClkDivider Sets the clock divider for the interpolation frequency Function Arguments Return Value Description Example VIC_setClkDivider Uint32 Value None Sets the value of the clock divider for the interpolation frequency VIC_setClkDivider(0x00000001). VIC Module 25-7 .VIC_setInputBits VIC_setInputBits Function Arguments Return Value Description Example Writes to the VICIN register VIC_setInputBits Uint32 Value None Sets the given value to the VICINBITS of the VICIN register VIC_setInputBits(0x00000001).

. 26-2 26. . . . . . . . . . . Topic Page 26. . . . . . . . . . . . . . . . 26-4 26. . . . . . . . . . . . . . . . . . .2 Configuration Structures . . . . . . . . . . . . . . .Chapter 26 VP Module This chapter describes the VP module. . . . . . . . . . . . . . . . . . . . . .3 Functions and Constants . . . . . . . . .1 Overview . . . . 26-9 26-1 . lists the API functions and macros within the module. . . . . . . . . . . . and provides a VP reference section. . . . . . . . . . . . . . . . . . . .

or transport stream interface (TSI) capture port. Table 26−1 lists the configuration structures available in the CSL VP module.1 Overview The video port peripheral can operate as a video capture port. Table 26−2 lists the functions and constants available in the CSL VP module. VP APIs and Constants Syntax VP_OPEN_RESET VP_clearPins VP_close VP_config VP_configCapture VP_configCaptureChA VP_configCaptureChB# Type Description C F F F F F F VP reset flag used while opening Writes value to PDCLR Closes previously opened VP device Configure VP using configuration structure Configures capture mode of video port Configures capture mode of Channel A of video port Configures capture mode of Channel B of video port See page 26-9 26-9 26-9 26-10 26-10 26-11 26-11 26-2 . Configuration Structures (Macros) Syntax VP_Config VP_ConfigCapture VP_ConfigCaptureChA VP_ConfigCaptureChB# VP_ConfigCaptureTSI VP_ConfigDisplay VP_ConfigGpio VP_ConfigPort # Defined only for DM642 Type Description T T T T T T T T Structure used to configure video port peripherals Structure used to configure video capture mode Structure used to configure the Channel A video capture mode Structure used to configure the Channel B video capture mode Structure used to configurethe transport stream interface (TSI) capture mode Structure used to configure video display mode Structure used to enable use of VP pins for GPIO Structure used to configure video port control and interrupt registers See page 26-4 26-4 26-5 26-5 26-6 26-7 26-8 26-8 Table 26−2. video display port. refer to the TMS320C64x DSP Video Port Reference Guide (SPRU629). Table 26−1. For more information about the peripheral.Overview 26.

This reflects the state of the video port pins.Overview Syntax VP_configCaptureTSI VP_configDisplay VP_configGpio VP_configPort VP_getCbdstAddr VP_getCbsrcaAddr VP_getCbsrcbAddr# VP_getConfig VP_getCrdstAddr VP_getCrsrcaAddr VP_getCrsrcbAddr# VP_getEventId VP_getPins VP_getYdstaAddr VP_getYdstbAddr VP_getYsrcaAddr VP_getYsrcbAddr# VP_open VP_reset VP_resetAll VP_resetCaptureChA VP_resetCaptureChB# VP_resetDisplay VP_setPins # Defined only for DM642 Type Description F F F F F F F F F F F F F F F F F F F F F F F F Configures transfer stream interface (TSI) mode of video port Sets display characteristics for video port Enables pins to be used as GPIO pins Configures port characteristics of VP Gets the address of the Cb FIFO Destination Register Gets the address of the Cb FIFO Source Register A Gets the address of the Cb FIFO Source Register B Reads the VP configuration values Gets the address of the Cr FIFO Destination Register Gets the address of the Cr FIFO Source Register A Gets the address of the Cr FIFO Source Register B Gets event id specified in device handle Returns value of PDIN. Gets the address of the Y FIFO Destination Register A Gets the address of the Y FIFO Destination Register B Gets the address of the Y FIFO Source Register A Gets the address of the Y FIFO Source Register B Opens VP device for use Resets the VP device Resets all video ports Resets the Capture Channel A and disables all its interrupts Resets the Capture Channel B and disables all its interrupts Resets the video display module and disables all its interrupts Writes value to PDSET See page 26-12 26-12 26-13 26-13 26-14 26-14 26-14 26-15 26-15 26-16 26-16 26-17 26-17 26-18 26-18 26-19 26-19 26-20 26-20 26-21 26-21 26-21 26-22 26-22 VP Module 26-3 .

VP_ConfigCapture Display code at selected address Members Uint32 vcactl Video Capture Channel A Control Register Uint32 vcastrt1 Video Capture Channel A Field 1 Start Register Uint32 vcastop1 Video Capture Channel A Field 1 Stop Register Uint32 vcastrt2 Video Capture Channel A Field 2 Start Register Uint32 vcastop2 Video Capture Channel A Field 2 Stop Register Uint32 vcavint Video Capture Channel A Vertical Interrupt Register Uint32 vcathrld Video Capture Channel A Threshold Register Uint32 vcaevtct Video Capture Channel A Event Count Register Uint32 vcbctl# Video Capture Channel B Control Register Uint32 vcbstrt1# Video Capture Channel B Field 1 Start Register Uint32 vcbstop1# Video Capture Channel B Field 1 Stop Register Uint32 vcbstrt2# Video Capture Channel B Field 2 Start Register Uint32 vcbstop2# Video Capture Channel B Field 2 Stop Register Uint32 vcbvint# Video Capture Channel B Vertical Interrupt Register Uint32 vcbthrld# Video Capture Channel B Threshold Register Uint32 vcbevtct# Video Capture Channel B Event Count Register # Defined only for DM642 Uint32 tsictl TSI Capture Control Register Uint32 tsiclkinitl TSI Clock Initialization LSB Register Uint32 tsiclkinitm TSI Clock Initialization MSB Register Uint32 tsistcmpl TSI System Time Clock Compare LSB Register Uint32 tsistcmpm TSI System Time Clock Compare MSB Register Uint32 tsistmskl TSI System Time Clock Compare Mask LSB Register Uint32 tsistmskm TSI System Time Clock Compare Mask MSB Register Uint32 tsiticks TSI System Time Clock Ticks Interrupt Register 26-4 .2 Configuration Structures VP_Config Members Structure used to configure video port peripheral VP_ConfigPort VP_ConfigCapture VP_ConfigDisplay VP_ConfigGpio *port Port Address *capture Video Capture Mode Configuration *display Video Display Mode Configuration *gpio Configures pins used for GPIO Description This is the VP configuration structure used to configure Video Port(s). You create and initialize this structure and then pass its address to the VP_config function.VP_Config 26.

#Defined only for DM642 VP Module 26-5 . This is used as a parameter in VP_Config. VP_ConfigCaptureChB Structure used to configure the channel B video capture mode# Members Uint32 vcbctl Uint32 vcbstrt1 Uint32 vcbstop1 Uint32 vcbstrt2 Uint32 vcbstop2 Uint32 vcbvint Uint32 vcbthrld Uint32 vcbevtct Video Capture Channel B Control Register Video Capture Channel B Field 1 Start Register Video Capture Channel B Field 1 Stop Register Video Capture Channel B Field 2 Start Register Video Capture Channel B Field 2 Stop Register Video Capture Channel B Vertical Interrupt Register Video Capture Channel B Threshold Register Video Capture Channel B Event Count Register Description This structure is used to configure the channel B video capture mode VP_ConfigCaptureChB#. VP_ConfigCaptureChA Structure used to configure the channel A video capture mode Members Uint32 vcactl Uint32 vcastrt1 Uint32 vcastop1 Uint32 vcastrt2 Uint32 vcastop2 Uint32 vcavint Uint32 vcathrld Uint32 vcaevtct Video Capture Channel A Control Register Video Capture Channel A Field 1 Start Register Video Capture Channel A Field 1 Stop Register Video Capture Channel A Field 2 Start Register Video Capture Channel A Field 2 Stop Register Video Capture Channel A Vertical Interrupt Register Video Capture Channel A Threshold Register Video Capture Channel A Event Count Register Description This structure is used to configure the Channel A Video Port Capture Mode.VP_ConfigCaptureChA Description This structure is used to configure the Video Port Capture Mode.

VP_ConfigCaptureTSI VP_ConfigCaptureTSI Structure used to configure the transport stream interface mode (TSI) capture mode Members Uint32 vcactl Uint32 tsictl Uint32 tsiclkinitl Uint32 tsiclkinitm Uint32 tsistcmpl Uint32 tsistcmpm Uint32 tsistmskl Uint32 tsistmskm Uint32 tsiticks Video Capture Channel A Control Register TSI Capture Control Register TSI Clock Initialization LSB Register TSI Clock Initialization MSB Register TSI System Time Clock Compare LSB Register TSI System Time Clock Compare MSB Register TSI System Time Clock Compare Mask LSB Register TSI System Time Clock Compare Mask MSB Register TSI System Time Clock Ticks Interrupt Register Description This structure is used to configure the transport stream interface mode (TSI) port capture mode. 26-6 .

VP_ConfigDisplay VP_ConfigDisplay Structure used to configure video display mode Members Uint32 vdctl Uint32 vdfrmsz Uint32 vdhblnk Uint32 vdvblks1 Uint32 vdvblke1 Uint32 vdvblks2 Uint32 vdvblke2 Uint32 vdimoff1 Uint32 vdimgsz1 Uint32 vdimoff2 Uint32 vdimgsz2 Uint32 vdfldt1 Uint32 vdfldt2 Uint32 vdthrld Uint32 vdhsync Uint32 vdvsyns1 Uint32 vdvsyne1 Uint32 vdvsyns2 Uint32 vdvsyne2 Uint32 vdreload Uint32 vddispevt Uint32 vdclip Uint32 vddefval Uint32 vdvint Uint32 vdfbit Uint32 vdvbit1 Uint32 vdvbit2 Video Display Control Register Video Display Frame Size Register Video Display Horizontal Blanking Register Video Display Field 1 Vertical Blanking Start Register Video Display Field 1 Vertical Blanking End Register Video Display Field 2 Vertical Blanking Start Register Video Display Field 2 Vertical Blanking End Register Video Display Field 1 Image Offset Register Video Display Field 1 Image Size Register Video Display Field 2 Image Offset Register Video Display Field 2 Image Size Register Video Display Field 1 Timing Register Video Display Field 2 Timing Register Video Display Threshold Register Video Display Horizontal Sync Register Video Display Field 1 Vertical Sync Start Register Video Display Field 1 Vertical Sync End Register Video Display Field 2 Vertical Sync Start Register Video Display Field 2 Vertical Sync End Register Video Display Counter Reload Register Video Display Display Event Register Video Display Clipping Register Video Display Default Display Value Register Video Display Vertical Interrupt Register Video Display Field Bit Register Video Display Field 1 Vertical Blanking Bit Register Video Display Field 2 Vertical Blanking Bit Register Description This structure is used to configure the Video Display Mode. This is used as a parameter in VP_Config. VP Module 26-7 .

This is used as a parameter in VP_Config. VP_ConfigPort Members Structure used to configure video port control and interrupt registers Uint32 vpctl Uint32 vpie Uint32 vpis Video Port Control Register Video Port Interrupt Enable Register Video Port Interrupt Status Register Description This structure is used to configure the video port control and interrupt registers. The GPIO register set includes registers to set for using pins in GPIO mode. This structure is used as a parameter in VP_Config. 26-8 .VP_ConfigGpio VP_ConfigGpio Members Structure used to enable use of VP pins for GPIO Uint32 pfunc Uint32 pdir Uint32 pdout Uint32 pdset Uint32 pdclr Uint32 pien Uint32 pipol Uint32 piclr Video Port Pin Function Register Video Port GPIO Direction Control Register Video Port GPIO Data Output Register Video Port GPIO Data Set Register Video Port GPIO Data Clear Register Video Port GPIO Interrupt Enable Register Video Port GPIO Interrupt Polarity Register Video Port GPIO Interrupt Clear Regsiter Description Signals not used for Video display and capture can be used as GPIO pins.

VP Module 26-9 Arguments Return Value Description Example . Arguments Return Value Description Example VP_close Function Closes previously opened VP device void VP_close( VP_Handle hVP ) hVP Device handle. The following tasks are performed: The VP event is disabled and cleared The VP registers are set to their default values VP_close(hVP). val). otherwise use 0 See VP_open VP_clearPins Function Writes value to PDCLR void VP_clearPins( VP_Handle hVP. see VP_open val Value to be written to PDCLR None Writes value to PDCLR. Uint32 val ) hVP Device Handle. VP_Handle hVP. .VP_OPEN_RESET 26. VP_clearPins(hVP.used while opening Description Example This flag is used while opening VP device To open with reset. see VP_open None Closes a previously opened VP device (see VP_open). Uint32 val. Writing a 1 to a bit of PDCLR clears the corresponding bit in PDOUT.. Writing a 0 has no effect.3 Functions and Constants VP_OPEN_RESET VP reset flag. use VP_OPEN_RESET..

. Arguments Return Value Description Example VP_configCapture Configures capture mode of video port Function void VP_configCapture( VP_Handle hVP.. VP_config(hVP.. &myConfig).VP_config VP_config Function Configure VP using configuration structure void VP_config( VP_Handle hVP.. see VP_Config None Configure the Video Port VP_Config myConfig. see VP_ConfigCapture None Used to configure the Capture mode of Video Port... . VP_Handle hVP. see VP_open myConfig. VP_Config *myConfig ) hVP Device Handle. VP_ConfigCapture *myPort ) hVP Device Handle. see VP_open myPort. VP_configCapture(hVP. Arguments Return Value Description Example 26-10 . VP_ConfigCapture myCapture. VP_Handle hVP..&myCapture).

Arguments Return Value Description Example # Defined only for DM642 VP Module 26-11 .. VP_Handle hVP. see VP_ConfigCaptureChB None Used to configure the capture mode of Channel B of video port VP_ConfigCaptureChB myCaptureChB.. ..&myCaptureChA). see VP_open myCaptureChA. VP_configCaptureChB(hVP.VP_configCaptureChA VP_configCaptureChA Configures capture mode of channel A of video port Function void VP_configCaptureChA( VP_Handle hVP... see VP_open myCaptureChB. VP_ConfigCaptureChB *myCaptureChB ) hVP Device Handle. Arguments Return Value Description Example VP_configCaptureChB Configures capture mode of channel B of video port# Function void VP_configCaptureChB( VP_Handle hVP. VP_Handle hVP.&myCaptureChB). .. VP_ConfigCaptureChA *myCaptureChA ) hVP Device Handle. see VP_ConfigCaptureChA None Used to configure the capture mode of Channel A of video port VP_ConfigCaptureChA myCaptureChA. VP_configCaptureChA(hVP.

VP_Handle hVP.. Arguments Return Value Description Example VP_configDisplay Function Sets display characteristics for video port void VP_configDisplay( VP_Handle hVP. see VP_ConfigDisplay None Used to configure the display settings of video port VP_ConfigDisplay myDisplay. VP_ConfigDisplay *myDisplay ) hVP Device Handle. Arguments Return Value Description Example 26-12 ... VP_configCaptureTSI(hVP..&myDisplay).&myCaptureTSI). VP_Handle hVP. VP_configDisplay(hVP.. see VP_ConfigCaptureTSI None Used to configure the transfer stream interface (TSI) mode of video port VP_ConfigCaptureTSI myCaptureTSI..VP_configCaptureTSI VP_configCaptureTSI Configures Transfer stream interface (TSI) mode of video port Function void VP_configCaptureTSI( VP_Handle hVP. . VP_ConfigCaptureTSI *myCaptureTSI ) hVP Device Handle. see VP_open myCaptureTSI. see VP_open myDisplay. .

.. Arguments Return Value Description Example VP_configPort Function Configures port characteristics of VP void VP_configPort( VP_Handle hVP. .. VP_ConfigPort *myPort ) hVP Device Handle...&myGpio).. Arguments Return Value Description Example Example VP Module 26-13 . VP_ConfigGpio *myGpio ) hVP Device Handle. VP_configGpio(hVP. see VP_open myPort. see VP_ConfigGpio None Enables pins to be used as GPIO pins VP_ConfigGpio myGpio. VP_Handle hVP. VP_configPort(hVP. VP_Handle hVP. see VP_open myGpio.&myPort).VP_configGpio VP_configGpio Function Enables pins to be Used as GPIO pins void VP_configGpio( VP_Handle hVP. . see VP_ConfigPort None Used to configure the port characteristics of video port VP_ConfigPort myPort.

see VP_open Uint32 Gets the address of the Cb FIFO source Register B VP_Handle hVP. Uint32 getVal. see VP_open Uint32 Gets the address of the Cb FIFO source Register A VP_Handle hVP. Arguments Return Value Description Example # Defined only for DM642 26-14 . getVal = VP_getCbsrcaAddr(hVP). getVal = VP_getCbdstAddr(hVP). Arguments Return Value Description Example VP_getCbsrcaAddr Gets the address of the Cb FIFO source register A Function Uint32 VP_getCbsrcaAddr( VP_Handle hVP ) hVP Device Handle. Uint32 getVal. see VP_open Uint32 Gets the address of the Cb FIFO destination register VP_Handle hVP.VP_getCbdstAddr VP_getCbdstAddr Gets the address of the Cb FIFO destination register Function Uint32 VP_getCbdstAddr( VP_Handle hVP ) hVP Device Handle. Arguments Return Value Description Example VP_getCbsrcbAddr Gets the address of the Cb FIFO source register B# Function Uint32 VP_getCbsrcbAddr( VP_Handle hVP ) hVP Device Handle. Uint32 getVal. getVal = VP_getCbsrcbAddr(hVP).

VP_getConfig VP_getConfig Function Reads the VP configuration values void VP_getConfig( VP_Handle hVP. see VP_open Uint32 Gets the address of the Cr FIFO destination register VP_Handle hVP. see VP_open myConfig. Uint32 getVal. VP_getConfig(hVP. Arguments Return Value Description Example VP Module 26-15 . &vpCfg). VP_Config *myConfig ) hVP Device Handle. getVal = VP_getCrdstAddr(hVP). see VP_Config None Gets the current VP configuration values VP_Config vpCfg. Arguments Return Value Description Example VP_getCrdstAddr Function Gets the address of the Cr FIFO destination register Uint32 VP_getCrdstAddr( VP_Handle hVP ) hVP Device Handle.

Arguments Return Value Description Example # Defined only for DM642 26-16 . Uint32 getVal. Uint32 getVal.VP_getCrsrcaAddr VP_getCrsrcaAddr Gets the address of the Cr FIFO source register A Function Uint32 VP_getCrsrcaAddr( VP_Handle hVP ) hVP Device Handle. getVal = VP_getCrsrcaAddr(hVP). see VP_open Uint32 Gets the address of the Cr FIFO source Register A VP_Handle hVP. see VP_open Uint32 Gets the address of the Cr FIFO source Register B VP_Handle hVP. getVal = VP_getCrsrcbAddr(hVP). Arguments Return Value Description Example VP_getCrsrcbAddr Gets the address of the Cr FIFO source register B# Function Uint32 VP_getCrsrcbAddr( VP_Handle hVP ) hVP Device Handle.

This reflects the state of the video port pins Uint32 VP_getPins( VP_Handle hVP ) hVP Device Handle.VP_getEventID VP_getEventID Function Gets event id specified in device handle Uint32 VP_getEventId( VP_Handle hVP ) hVP Device Handle. Arguments Return Value Description Example VP_getPins Function Returns value of PDIN. Arguments Return Value Description Example VP Module 26-17 . VP_Handle hVP. This reflects the state of the video port pins. Uint32 getVal. Uint32 evtId. see VP_open Uint32 Returns value of PDIN. getVal = VP_getPins(hVP). see VP_open Uint32 Gets event id specified in device handle VP_Handle hVP. evtId = VP_getEventId(hVP).

VP_getYdstaAddr VP_getYdstaAddr Function Gets the address of the Y FIFO destination register A Uint32 VP_getYdstaAddr( VP_Handle hVP ) hVP Device Handle. getVal = VP_getYdstbAddr(hVP). getVal = VP_getYdstaAddr(hVP). Arguments Return Value Description Example VP_getYdstbAddr Gets the address of the Y FIFO destination register B# Function Uint32 VP_getYdstbAddr( VP_Handle hVP ) hVP Device Handle. see VP_open Uint32 Gets the address of the Y FIFO destination Register B VP_Handle hVP. see VP_open Uint32 Gets the address of the Y FIFO destination Register A VP_Handle hVP. Arguments Return Value Description Example #Defined only for DM642 26-18 . Uint32 getVal. Uint32 getVal.

Arguments Return Value Description Example #Defined only for DM642 VP Module 26-19 . Arguments Return Value Description Example VP_getYsrcbAddr Gets the address of the Y FIFO source register B# Function Uint32 VP_getYsrcbAddr( VP_Handle hVP ) hVP Device Handle.VP_getYsrcaAddr VP_getYsrcaAddr Function Gets the address of the Y FIFO source register A Uint32 VP_getYsrcaAddr( VP_Handle hVP ) hVP Device Handle. Uint32 getVal. getVal = VP_getYsrcaAddr(hVP). see VP_open Uint32 Gets the address of the Y FIFO source Register A VP_Handle hVP. getVal = VP_getYsrcbAddr(hVP). Uint32 getVal. see VP_open Uint32 Gets the address of the Y FIFO source Register B VP_Handle hVP.

it must be ’opened’ using this function. the VP module registers are set to their power−on defaults and any associated interrupts are disabled and cleared.. see VP_open None Sets the VP registers to their default values VP_Handle hVP. hVP = VP_open(OPEN_RESET). Example VP_reset Function Resets the VP device void VP_reset( VP_Handle hVP ) hVP Device Handle. Uint16 flags ) devNum specifies the device to be opened flags Open flags Arguments OPEN_RESET : resets the VP Return Value Description VP_Handle Device Handle INV : open failed Before the VP device can be used... Arguments Return Value Description Example 26-20 . Handle hVP. VP_reset(hVP). If the OPEN_RESET flag is specified. If the open fails. ’INV’ is returned. .VP_open VP_open Function Opens VP device for use VP_Handle VP_open( Uint16 devNum.. Once opened it cannot be opened again until it is ’closed’ (see VP_close).. The return value is a unique device handle that is used in subsequent VP API calls. .

see VP_open None Resets the channel bit in VCBCTL. VP_Handle hVP. Arguments Return Value Description Example VP_resetCaptureChB Resets the capture channel B and disables all its interrupts# Function void VP_resetCaptureChB( VP_Handle hVP ) hVP Device Handle. VP_resetCaptureChA Resets the capture channel A and disables all its interrupts Function void VP_resetCaptureChA( VP_Handle hVP ) hVP Device Handle. All further DMA event generation is blocked and the FIFO is flushed upon completion of pending DMA events. All further DMA event generation is blocked and the FIFO is flushed upon completion of pending DMA events. disables interrupts for this channel and clears status bits in VPIS set for this channel. VP_Handle hVP. VP_resetCaptureChB(hVP). Arguments Return Value Description Example #Defined only for DM642 VP Module 26-21 . see VP_open None Resets the channel bit in VCACTL. VP_resetCaptureChA(hVP). disables interrupts for this channel and clears status bits in VPIS set for this channel.VP_resetAll VP_resetAll Function Return Value Description Example Resets all video ports void VP_resetAll( ) None Resets all video ports VP_resetAll().

.VP_resetDisplay VP_resetDisplay Function Resets the video display module and disables all its interrupts void VP_resetDisplay( VP_Handle hVP ) hVP Device Handle. see VP_open val Value to be written to PDSET None Writes value to PDSET. Writing a 0 has no effect. see VP_open None Resets the video display module and sets its registers to their initial values. VP_Handle hVP. All related interrupts are disabled and the status bits set in VPIS are cleared VP_Handle hVP. VP_resetDisplay(hVP). VP_setPins(hVP.. Uint32 val. Arguments Return Value Description Example 26-22 . val). Uint32 val ) hVP Device Handle.. Writing a 1 to a bit of PDSET sets the corresponding bit in PDOUT. Arguments Return Value Description Example VP_setPins Function Writes value to PDSET void VP_setPins( VP_Handle hVP.

4 Functions . . . . . . . . lists the API functions and macros within the module. . . . . . . . .3 Configuration Structure . .Chapter 27 XBUS Module This chapter describes the XBUS module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Topic Page 27. . . . . . . . . . . . . . . . . discusses how to use the XBUS device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and provides an XBUS API reference section. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Macros . . . . . . . . . 27-2 27. . . . . 27-4 27. . . . 27-5 27-1 . 27-2 27. . . . . . . . . . . . . . . . . . . . . . . . . . .1 Overview . . .

Table 27−1. The macros themselves are found in Chapter 28.Overview 27. Table 27−3 lists the XBUS macros that access registers and fields. 27-5 27-5 27-6 27-7 27.. XBUS APIs Syntax XBUS_config XBUS_configArgs XBUS_getConfig XBUS_SUPPORT Note: F = Function. 27-2 ...2 Macros There are two types of XBUS macros: those that access registers and fields. 27-4 Table 27−2.1 Overview This module has a simple API for configuring the XBUS registers. and those that construct register and field values. and Table 27−4 lists the XBUS macros that construct register and field values.. C = Constant Type Description F F F C Configures entry for XBUS configuration structure Configures entry for XBUS registers Returns the current XBUS configuration structure Compile time constant See page . XBUS macros are not handle-based. Table 27−1 lists the configuration structure for use with the XBUS functions. Table 27−2 lists the functions and constants available in the CSL DMA module. Using the HAL Macros. XBUS Configuration Structure Syntax XBUS_Config Type Description S XBUS configuration structure See page . The XBUS may be configured by passing an XBUS_CONFIG structure to XBUS_Config() or by passing register values to the XBUS_ConfigArgs() function.

<FIELD>.. <SYM>) Description/Purpose Register address Returns the value in the peripheral register Register set Returns the value of the specified field in the peripheral register Writes fieldval to the specified field in the peripheral register Writes the symbol value to the specified field in the peripheral Gets register for a given address Sets register for a given address Gets field for a given address Sets field for a given address Sets field symbolically for a given address See page . XBUS Macros that Access Registers and Fields Macro XBUS_ADDR(<REG>) XBUS_RGET(<REG>) XBUS_RSET(<REG>.Macros Table 27−3. 28-12 28-18 28-20 28-13 28-15 28-17 28-19 28-20 28-13 28-16 28-17 Table 27−4.<REG>) XBUS_RSETA(addr...<REG>.<REG>.x) XBUS_FGETA(addr. XBUS Macros that Construct Register and Field Values Macro XBUS_<REG>_DEFAULT XBUS_<REG>_RMK() XBUS_<REG>_OF() XBUS_<REG>_<FIELD>_DEFAULT XBUS_FMK() XBUS_FMKS() XBUS_<REG>_<FIELD>_OF() XBUS_<REG>_<FIELD>_<SYM> Description/Purpose Register default value Register make Register value of .<FIELD>.<FIELD>.<FIELD>.<SYM>) XBUS_RGETA(addr. fieldval) XBUS_FSETSA(addr..fieldval) XBUS_FSETS(<REG>. 28-21 28-23 28-22 28-24 28-14 28-15 28-24 28-24 XBUS Module 27-3 .<REG>.<FIELD>) XBUS_FSET(<REG>..<FIELD>) XBUS_FSETA(addr.. Field default value Field make Field make symbolically Field value of .. Field symbolic value See page ..<REG>.x) XBUS_FGET(<REG>.

Example */ */ */ */ */ 27-4 .3 Configuration Structure XBUS_Config Structure Members XBUS configuration structure XBUS_Config Uint32 xbgc Uint32 xce0ctl Uint32 xce1ctl Uint32 xce2ctl Uint32 xce3ctl Uint32 xbhc Uint32 xbima Uint32 xbea Expansion Bus global control register value XCE0 space control register value XCE1 space control register value XCE2 space control register value XCE3 space control register value Expansion Bus host port interface control register value Expansion Bus internal master address register value Expansion Bus external address register value Description This is the XBUS configuration structure used to set up an XBUS configuration.XBUS_Config 27. . /* XBUS Internal Master Address Register(XBIMA) */ 0x00000000 /* XBUS External Address Register(XBEA) }. /* XCE3 Space Control Register(XCE3CTL) 0x00000000. . XBUS_Config xbusCfg = { 0x00000000. XBUS_config(&xbusCfg). /* XCE1 Space Control Register(XCE1CTL) 0xFFFF3F23. You create and initialize this structure then pass its address to the XBUS_config() function. /* XCE0 Space Control Register(XCE0CTL) 0xFFFF3F23. /* Global Control Register(XBGC) */ 0xFFFF3F23. /* XBUS HPI Control Register(XBHC) */ 0x00000000. /* XCE2 Space Control Register(XCE2CTL) 0xFFFF3F23.

Uint32 xce0ctl.4 Functions XBUS_config Function Establishes XBUS configuration structure void XBUS_config( XBUS_Config *config ). /* XCE2 Space Control Register(XCE2CTL) 0xFFFF3F23. /* XCE0 Space Control Register(XCE0CTL) 0xFFFF3F23. config none Sets up the XBUS using the configuration structure. XBUS Module 27-5 . /* XBUS Internal Master Address Register(XBIMA) */ 0x00000000 /* XBUS External Address Register(XBEA) }. XBUS_Config xbusCfg = { 0x00000000. Uint32 xce3ctl. Uint32 xbhc. The values of the structure are written to the XBUS registers. Uint32 xbima. Arguments Return Value Description Example Pointer to an initialized configuration structure */ */ */ */ */ XBUS_configArgs Establishes XBUS register value Function void XBUS_configArgs( Uint32 xbgc. XBUS_config(&xbusCfg). Uint32 xbea ). /* Global Control Register(XBGC) */ 0xFFFF3F23. Uint32 xce1ctl. Uint32 xce2ctl. /* XCE3 Space Control Register(XCE3CTL) 0x00000000.XBUS_config 27. /* XBUS HPI Control Register(XBHC) */ 0x00000000. /* XCE1 Space Control Register(XCE1CTL) 0xFFFF3F23.

XBUS_configArgs( xbgc. xbhc. xbhc = 0x00000000. Pointer to a configuration structure Arguments Return Value Description 27-6 . config none Get XBUS current configuration value. xbea = 0x00000000. xce0ctl. xce0ctl = 0xFFFF3F23. xce2ctl = 0xFFFF3F23. xce3ctl. xbgc = 0x00000000. xce2ctl.XBUS_getConfig Arguments xbgc xce0ctl xce1ctl xce2ctl xce3ctl xbhc xbima xbea none Sets up the XBUS using the register values passed in. xce3ctl = 0xFFFF3F23. xbima = 0x00000000. xce1ctl. xbima. The register values are written to the XBUS registers. Expansion Bus global control register value XCE0 space control register value XCE1 space control register value XCE2 space control register value XCE3 space control register value Expansion Bus host port interface control register value Expansion Bus internal master address register value Expansion Bus external address register value Return Value Description Example XBUS_getConfig Function Gets XBUS current configuration value void XBUS_getConfig( XBUS_Config *config ). xbea ). xce1ctl = 0xFFFF3F23.

XBUS_SUPPORT Constant Description Example Compile time constant XBUS_SUPPORT The compile time constant has a value of 1 if the device supports the XBUS module. #if (XBUS_SUPPORT) /* user XBUS configuration */ #endif XBUS Module 27-7 . You are not required to use this constant. XBUS_getConfig(&xbusCfg).XBUS_SUPPORT Example XBUS_config xbusCfg. and 0 otherwise.

. . . . . .3 General Comments Regarding HAL Macros . gives a summary of the HAL macros. .Chapter 28 Using the HAL Macros This chapter describes the hardware abstraction layer (HAL). . . 28-12 28-1 . . . . . . . . . . and provides a HAL macro reference section. . . . . . . . . . . . . . . . . .4 HAL Macro Reference . . 28-6 28. . . . . . . . . . . . . . . . . . . Topic Page 28. . . . . . . . . . . . . . . . . . . .1 Introduction . . . . . . . discusses RMK macros and macro token pasting. . . . . . . . . . . . . . . . . . 28-2 28. . . . . . . . . . . . . . . . . . . . . . 28-4 28. .2 Generic Macro Notation and Table of Macros . .

TI has generated a set of HAL macros and made it available to all users in order to make peripheral configuration easy. The HAL is made up of a set of header files that define an orthogonal set of C macros and constants which abstract registers and bit-fields into symbols. Devices other than 6211/6711 cannot access the abstract macros related to the SDEXT register. which will indirectly include csl_dmahal. this is reflected in the HAL macros.Introduction 28. that process generated a large development time for programmers. which indirectly includes the HAL file.2 HAL Header Files The HAL macros are defined in the HAL header file (e. more importantly.) The user does not directly include these files. HAL usually refers to a set of functions that completely abstract hardware.h. and access macros for reading/writing registers and individual bit-fields. Users would go through and add many symbols (#defines) to map registers.h. and they would define bit-field positions and values.1.. In other high-level OS environments. Consequently. In the context of the CSL.h). For example. instead. For example. the result will be that zero CSL library code gets linked in. 28. register bit-field mask and shift values.1. For example. The HAL is nothing more than a large set of C macros.g. if a bit-field changes width from one chip to another. In an application where only the HAL gets used. The service layer contains the API functions.1 Introduction The chip support library (CSL) has two layers: the service layer and the hardware abstraction layer (HAL). the memory-mapped register SDEXT (EMIF register) is supported only by 6211 and 6711 devices. csl_mcbsphal. etc. and the register description is set for these devices with a condition access.h. the abstraction is limited to processor-dependent changes of register/bit-field definitions. the register is described in the HAL file with a condition.1 HAL Macro Symbols These HAL macro symbols define memory-mapped register addresses. symbolic names for bit-field values. If a memory-mapped register is specific to a chip. The HAL macros add a level of compatibility and standardization and. 28-2 . all with their own HAL macros and no standardization. the service layer header file is included. With the development of the CSL. data types. include csl_dma. almost all application programmers found themselves defining a HAL in one form or another. if the DMA HAL file is needed (csl_dmahal. csl_dmahal. and constants as defined in the various chapters of this reference guide. reduce development time. Prior to the HAL definition.h. 28. there is no compiled C code involved.

Macros that construct register and field values.Macros that access registers and fields (set.3 HAL Macro Summary TMS320C6000™ CSL macros can be divided into two functionality groups: . These macros are register-specific and implemented for each value. get). They include: J J J J J Macro constant for the default value of a register Macro that constructs register values based on field values Macro constant for the default value of a register field Macro that constructs a field value Macro that constructs a field value given a symbolic constant Using the HAL Macros 28-3 . These macros are implemented at the beginning of the HAL files and include: J J J J J J J J Macro for reading a register Macro for writing to a register Macro that returns the address of a memory-mapped register Macro for inserting a field value into a register Macro for extracting a field value from a register Macro for inserting a field value into a register using a symbolic name Variations of the above for handle-based registers Variations of the above for given register addresses .1.Introduction 28.

etc. etc. MCBSP_SPCR_GRST_D EFAULT.<REG> = placeholder for a register name: PRICTL. STATUS. AUXCTL. etc. <PER> represents a placeholder for the peripheral (module) name. MCBSP_SPCR_DEFAULT. XEMPTY. etc. . whenever <REG> is used. MCBSP_ADDR(…).e. In this case it represents a set of macros including: DMA_PRICTL_PRI_DEFAULT. etc. MCBSP. When the table lists something like <PER>_ADDR. MCBSP. TIMER_CTL_DEFA ULT. it is a placeholder for a register name.<PER> = placeholder for peripheral (module) name: DMA.Generic Macro Notation and Table of Macros 28. SPCR. . 28-4 . For example..<SYM> = placeholder for a value name: ENABLE. IRQ. etc. it actually represents a whole set of macros defined in the different modules: DMA_ADDR(…).2 Generic Macro Notation and Table of Macros Table 28−1 lists the macros defined in the HAL using the following generic notation: .<FIELD> = placeholder for a field name: PRI. HIGH. etc. . There are also field name place holders such as in the macro <PER>_<REG>_<FIELD>_DEFAULT. YES. i. etc. Likewise. DMA. <PER>_<REG>_DEFAULT represents a set of macros including DMA_AUXCTL_DEFAULT.

. CSL HAL Macros HAL Macro Type <PER>_ADDR <PER>_ADDRH <PER>_CRGET <PER>_CRSET <PER>_FGET <PER>_FGETA <PER>_FGETH <PER>_FMK <PER>_FMKS <PER>_FSET <PER>_FSETA <PER>_FSETH <PER>_FSETS <PER>_FSETSA <PER>_FSETSH <PER>_RGET <PER>_RGETA <PER>_RGETH <PER>_RSET <PER>_RSETA <PER>_RSETH <PER>_<REG>_DEFAULT <PER>_<REG>_OF <PER>_<REG>_RMK <PER>_<REG>_<FIELD>_DEFAULT <PER>_<REG>_<FIELD>_OF <PER>_<REG>_<FIELD>_<SYM> Purpose Register Address Register Address For Given Handle Gets the Value of CPU Register Sets the Value of CPU Register Field Get Field Get Given Address Field Get For Given Handle Field Make Field Make Symbolically Field Set Field Set Given Address Field Set For Given Handle Field Set Symbolically Field Set Symbolically For Given Address Field Set Symbolically For Given Handle Register Get Register Get Given Address Register Get For Given Handle Register Set Register Set Given Address Register Set For Given Handle Register Default Value Register Value Of … Register Make Field Default Value Field Value Of … Field Symbolic Value See page .. 28-12 28-12 28-12 28-13 28-13 28-13 28-14 28-14 28-15 28-15 28-16 28-16 28-17 28-17 28-18 28-18 28-19 28-19 28-20 28-20 28-21 28-21 28-22 28-23 28-24 28-24 28-24 Using the HAL Macros 28-5 .Generic Macro Notation and Table of Macros Table 28−1.

To illustrate. x) macro that accepts a right-justified field value and inserts it into the register. Also assume that this field can take on three valid values. We would also have the MYPER_FSET(MYREG. and 11111b = V3. you would first left-shift it by 17 bits then mask it with 0x003E0000. you would first mask the register value with 0x003E0000 then right-shift it by 17 bits. they are always right-justified. 01011b = V2. The FMK and RMK macros also deal with right-justified field values. All of the FGET type of macros return the right-justified field value and all of the FSET type of macros take a right-justified field value as an argument. 28.3 General Comments Regarding HAL Macros This section contains some general comments of interest regarding the HAL macros. MYFIELD) macro that would return the MYFIELD value right-justified. consider the following: Assume that you have a register (MYREG) in a peripheral named MYPER with a field that spans bits 17 to 21 − a 5-bit field named (MYFIELD).3. then we would have a MYPER_FGET(MYREG. MYFIELD. If you start with the right justified field value and want to create the in-place field value. If we had HAL macros for this hypothetical register.1 Right-Justified Fields Whenever field values are referenced.General Comments Regarding HAL Macros 28. It will look like this: MYREG: 31 21 MYFIELD 17 0 If you wanted to extract this field. This would give the right-justified field value. 00000b = V1. This makes it easier to deal with them and it also adds some processor independence. 28-6 .

2 _OF Macros The HAL defines a set of value-of macros for registers and fields: <PER>_<REG>_OF(x) <PER>_<REG>_<FIELD>_OF(x) These macros serve the following two purposes: . Consider the following example where a DMA configuration structure is being statically initialized with hard-coded values. Also notice that the _OF() macros help out by eliminating the need to do manual typecasts. Using the HAL Macros 28-7 . 0x00000080. When you are assigning a value to a register or field.3. (Uint32)buffa. Making Code More Readable The second purpose of these macros is to make code more readable. using the _OF() macros. if you enclose the value with an _OF() macro. you could pass just about anything as an argument and it will get typecasted into a Uint32. #define <PER>_<REG>_OF(x) ((Uint32)(x)) So. However. The above code and the below code both do the same thing.They typecast the argument . (Uint32)buffb. then it becomes perfectly clear what the value is. /* create a config structure using hard coded values */ DMA_Config cfg = { 0x10002050. 0x00010008 ). the code now becomes clear. You can see from the example that it is not very clear what the values mean. However.They make code readable Typecasting the Argument The macros do nothing more than return the original argument but with a typecast. it may not be clear what you are assigning to.General Comments Regarding HAL Macros 28.

DMA_SECCTL_OF(0x00000080).DMA_AUXCTL_CHPRI_OF(x) . It basically shifts and masks all of the field values then ORs them together bit-wise to form a value.General Comments Regarding HAL Macros /* create a config structure using the _OF() macros */ DMA_Config cfg = { DMA_PRICTL_OF(0x10002050).3. The RMK macros take an argument for each writable field and they are passed in the order of most significant field first down to the least-significant field.etc… The same principle applies for field values. 28-8 .MCBSP_SPCR_DLB_OF(x) . Every register has an _OF() macro: . However. No writes are actually performed.etc… The field _OF() macros are generally used with the RMK macros. 28.DMA_PRICTL_PRI_OF(x) .DMA_PRICTL_OF(x) .DMA_PRICTL_ESIZE_OF(x) . DMA_XFRCNT_OF(0x00010008) ).MCBSP_SPCR_OF(x) . DMA_DST_OF(buffb).3 RMK Macros This set of macros allows you to create or make a value suitable for a particular register by specifying its individual field values.TIMER_PRD_OF(x) .DMA_AUXCTL_OF(x) . DMA_SRC_OF(buffa). Every field has an _OF() macro defined for it: . only a value is returned. they are also useful when a field is very wide and it is not practical to #define a symbol for every value the field could take on.

we will pick a register that does not have too many fields. or MCR.rmcm) Using the HAL Macros 28-9 .xpablk. Here is the MCR register comment header pulled directly from the MCBSP HAL file: /********************************************************\ * _____________________ * | * | * * MCR0 * MCR1 * MCR2 * * (1) only supported on devices with three serial ports * * FIELDS (msb −> lsb) * (rw) XPBBLK * (rw) XPABLK * (r) XCBLK * (rw) XMCM * (rw) RPBBLK * (rw) RPABLK * (r) * \********************************************************/ RCBLK * (rw) RMCM − serial port 0 multichannel control register − serial port 1 multichannel control register − serial port 2 multichannel control register (1) M C R | | * |___________________| Out of the eight fields.General Comments Regarding HAL Macros <PER>_<REG>_RMK(field_ms. only six are writable.xmcm. such as the MCBSP multichannel control register.…. hence.rpablk. MCBSP_MCR_RMK(xpbblk.field_ls) For illustrative purposes.rpbblk. the RMK macro takes six arguments.

General Comments Regarding HAL Macros This macro will take each of the field values xpbblk to rmcm and form a 32-bit value.0. MCBSP_MCR_RMCM_CHENABLE ).1). There are several ways you could use this macro each with a differing level of readability. MCBSP_MCR_RPBBLK_SF3.0. You could just hardcode the field values x = MCBSP_MCR_RMK(1.0. MCBSP_MCR_RPBBLK_SF3. in the long run. MCBSP_MCR_RMCM_CHENABLE ). the second method is much easier to understand and. Or you could use the field value symbols x = MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_SF1. MCBSP_MCR_XPABLK_SF0. 28-10 . In the first method. MCBSP_MCR_XPABLK_SF0. MCBSP_MCR_RPBBLK_SF3. in the second method. MCBSP_MCR_RMCM_CHENABLE ). it’s a little unclear what myVar is. will be much easier to maintain. Another consideration is when you use a variable for one of the field value arguments. MCBSP_MCR_XMCM_DISXP. Let’s say that the XMCM argument is based on a variable in your program. however. Now use the field _OF() macro x = MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_SF1. MCBSP_MCR_XMCM_OF(myVar).1. MCBSP_MCR_RPABLK_SF0. Just like before. MCBSP_MCR_RPABLK_SF0. but with the variable x = MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_SF1. MCBSP_MCR_XPABLK_SF0. MCBSP_MCR_RPABLK_SF0. myVar. it’s very clear because of the _OF() macro. As you can see.

4 Macro Token Pasting The HAL macros rely heavily on token pasting. For example. the argument of a macro is used to form identifiers. One option is to look inside the HAL header files where it is fairly easy to determine the register names. Where. then the whole macro resolves down to a single integer from the compilers standpoint. #define DMA_RGET(REG) REG) _PER_RGET(_DMA_##REG##_ADDR. As a matter of fact.5 Peripheral Register Data Sheet It is beyond the scope of this document to list every register name and every bit-field name.3. and field values. in static initializers. The RMK macros may be used anywhere in your code.PER. 28. there is the possibility of side effects if you define macros that match the token names. then it resolves into MYMAC0() which can be a totally different macro definition. it is anticipated that you will have all applicable supplemental documentation available when working with this user’s guide. 28. Basically. field names.General Comments Regarding HAL Macros One thing that needs to be re-emphasized is the fact that the RMK macros do not write to anything. The HAL uses this in many instances. if you used all symbolic constants for the field values. they simply return a value. function arguments.REG) (*(volatileUint32*)(addr)) Because of this token pasting. arguments to other macros. a feature of the C language. #define _PER_RGET(addr. consider: #define MYMAC(ARG) MYMAC##ARG##() If you call MYMAC(0).3. Instead. DMA. Using the HAL Macros 28-11 . etc.

regAddr = MCBSP_ADDR(SPCR0). The value returned is right-justified. <PER> is a placeholder for the peripheral name: DMA. hDma = DMA_open(DMA_CHA2.4 HAL Macro Reference <PER>_ADDR Macro Arguments Return Value Description Example Register Address <PER>_ADDR(<REG>) <REG> Uint32 Register name Address Returns the address of a memory mapped register. Uint32 regAddr. IER. MCBSP. regAddr = DMA_ADDR(AUXCTL).) Register value Returns the current value of a CPU register. MCBSP. Uint32 regAddr. SRC). DMA_Handle hDma.e. <PER> is a placeholder for the peripheral name: DMA. ISR. regAddr = DMA_ADDRH(hDma. <PER>_ADDRH Macro Arguments Return Value Description Register Address for a Given Handle <PER>_ADDRH(h. TIMER.<PER>_ADDR 28. regAddr = DMA_ADDRH(hDma. TIMER... Example <PER>_CRGET Macro Arguments Return Value Description Gets the Value of CPU Register <PER>_CRGET(<REG>) <REG> Uint32 CPU register name (i. Uint32 valReg. CSL. if any. valReg = CHIP_CRGET(CSR).<REG>) h <REG> Uint32 Peripheral handle Register name Address Returns the address of the memory-mapped register given a handle. Only registers covered by the handle structure are valid. etc. Example 28-12 . regAddr = DMA_ADDR(PRICTL0). <PER> is a placeholder for the peripheral name (applies to CHIP module only). etc. PRICTL). 0).

MCBSP.<FIELD>) addr <REG> <FIELD> Uint32 Uint32 address Register name Field name Field value. x may be any valid C expression.<REG>. fieldVal = MCBSP_FGET(SPCR0.. XRDY). <PER> is a placeholder for the peripheral name: DMA. TIMER..<FIELD>) <REG> <FIELD> Uint32 Register name Field name Field value. <PER>_FGETA Macro Arguments Gets Field for a Given Address <PER>_FGETA(addr. MCBSP. fieldVal = DMA_FGET(AUXCTL. TIMER. Using the HAL Macros 28-13 .<PER>_CRSET <PER>_CRSET Macro Arguments Return Value Description Sets the Value of CPU Register <PER>_CRSET(<REG>) <REG> x none Writes the value x into the CPU <REG> register. Uint32 fieldVal. This macro is useful in those situations where an arbitrary memory location is treated like a register such as in a configuration structure. <PER> is a placeholder for the peripheral name: DMA.) Uint 32 value to set the register Example <PER>_FGET Macro Arguments Return Value Description Example Gets a Field Value From a Register <PER>_FGET(<REG>. right-justified Return Value Description Returns the value of the field given the address of the memory mapped register. ISR. CHPRI). CSL. The value returned is right-justified. The return value is right-justified. fieldVal = DMA_FGET(PRICTL0. right-justified Returns a field value from a register. INDEX). etc. <PER> is a placeholder for the peripheral name (applies to CHIP module only). CPU register name (i.e. /* set the IER register */ CHIP_CRSET(IER. etc. IER.0x00010001).

prictl). Example 28-14 .<FIELD>) h <REG> <FIELD> Uint32 Peripheral handle Register name Field name Field value. Only registers covered by handles per peripheral are valid. It can be bit-wise OR’ed with other FMK or FMKS macros to form a register value as an alternative to the RMK macro.<REG>. fieldVal = DMA_FGETA(&(cfg. 0). PRICTL . Uint32 x. x = DMA_FMK(AUXCTL.<PER>_FGETH Example Uint32 fieldVal.x) <REG> <FIELD> x Uint32 Register name Field name Field value. PRICTL. TIMER. <PER>_FGETH Macro Arguments Gets Field for a Given Handle <PER>_FGETH(h. <PER> is a placeholder for the peripheral name: DMA. AUXPRI. Uint32 regAddr = 0x01840000. 0) | DMA_FMK(AUXCTL. EMOD). right-justified Return Value Description Returns the value of the field given a handle.<FIELD>. MCBSP. hDma = DMA_open(DMA_CHA1. DMA_Handle hDma. DMA_Config cfg. 0). Uint32 fieldVal. fieldVal = DMA_FGETA(0x01840000. Example <PER>_FMK Macro Arguments Field Make <PER>_FMK(<REG>. AUXCTL. INDEX). fieldVal = DMA_FGETA(regAddr. fieldVal = DMA_FGETH(hDma. PRICTL. PRICTL. PRI). if any. CHPRI). CHPRI. fieldVal = DMA_FGETA(0x01840070. right-justified In-place and masked-field value Return Value Description This macro takes the right-justified field value then shifts it over and masks it to form the in-place field value. ESIZE). etc.

AUXPRI. fieldVal). The value is right-justified. HIGHEST) | DMA_FMKS(AUXCTL. INDEX. <PER> is a placeholder for the peripheral name: DMA.<SYM>) <REG> <FIELD> <SYM> Uint32 Register name Field name Symbolic field value In-place and masked-field value Return Value Description This macro takes the symbolic field value then shifts it over and masks it to form the in-place field value. DMA_FSET(AUXCTL. DMA_FSET(PRICTL0.<FIELD>. Example <PER>_FSET Macro Arguments Field Set <PER>_FSET(<REG>. DMA_FSET(PRICTL0. CPU).<FIELD>. 0). CHPRI. TIMER.x) <REG> <FIELD> x none Sets a field of a register to the specified value. 1). etc. INDEX. It can be bit-wise OR’ed with other FMK or FMKS macros to form a register value as an alternative to the RMK macro. GO. x = DMA_FMKS(AUXCTL. Uint32 fieldVal = 0. CHPRI. MCBSP. Uint32 x.<PER>_FMKS <PER>_FMKS Macro Arguments Field Make Symbolically <PER>_FMKS(<REG>. TIMER_FSET(CTL0. 0). Register name Field name Uint32 right-justified field value Return Value Description Example Using the HAL Macros 28-15 .

DLB.x) h <REG> <FIELD> x none Sets the field value to x given a handle. TIMER. <PER> is a placeholder for the peripheral name: DMA. PRICTL . MCBSP. etc. DMA_FSETA(0x01840000. 3).x) addr <REG> <FIELD> x none Sets the field value to x where x is right-justified.<PER>_FSETA <PER>_FSETA Macro Arguments Sets Field for a Given Address <PER>_FSETA(addr.<FIELD>. Peripheral handle Register name Field name Uint32 field value. DMA_FSETH(hDma. 0). DMA_OPEN_RESET). 1). INDEX.INDEX.<FIELD>. INDEX. 0). fieldVal). Uint32 dummyReg = DMA_PRICTL_DEFAULT. DMA_FSETA(regAddr. DMA_Handle hDma. right-justified Return Value Description Example 28-16 . This macro is useful in those situations where an arbitrary memory location is treated like a register such as in a configuration structure. if any. Uint32 address Register name Field name Uint32 field value.<REG>. DMA_FSETA(&dummyReg. hDma = DMA_open(DMA_CHA2. PRICTL. PRICTL. Uint32 regAddr = 0x01840000. TIMER. Uint32 fieldVal = 0.<REG>. MCBSP_FSETA(0x018C0008. ESIZE. DMA_FSETA(0x01840000. fieldVal). Only registers covered by handles per peripheral are valid. <PER> is a placeholder for the peripheral name: DMA. SPCR. EMOD. MCBSP. PRICTL. right-justified Return Value Description Example <PER>_FSETH Macro Arguments Sets Field for a Given Handle <PER>_FSETH(h. PRICTL. etc.

<FIELD>.INDEX. A). MCBSP_FSETS(SPCR0. This macro is useful in those situations where an arbitrary memory location is treated like a register such as in a configuration structure. Uint32 dummyReg = DMA_PRICTL_DEFAULT.<SYM>) <REG> <FIELD> <SYM> none Sets a register field to the specified symbol value.<REG>. MCBSP_FSETSA(0x018C0008. etc. DMA_FSETSA(&dummyReg. A). The value MUST be one of the predefined symbolic names for that field for that register. DMA_FSETS(PRICTL0. <PER> is a placeholder for the peripheral name: DMA.<PER>_FSETS <PER>_FSETS Macro Arguments Sets a Field Symbolically <PER>_FSETS(<REG>. DLB. <PER> is a placeholder for the peripheral name: DMA. DEFAULT). DMA_FSETS(AUXCTL. INDEX. DMA_FSETSA(0x01840000. MCBSP. Register name Field name Symbolic value name Return Value Description Example <PER>_FSETSA Macro Arguments Sets Field Symbolically for a Given Address <PER>_FSETSA(addr. TIMER. MCBSP. DLB. SPCR. HALT). HIGHEST). OFF). PRICTL . OFF). B). DMA_FSETSA(regAddr. A). MCBSP_FSETS(SPCR1. Using the HAL Macros 28-17 Uint32 address Register name Field name Field value name Return Value Description Example . Uint32 regAddr = 0x01840000. CHPRI. TIMER. INDEX. The value MUST be one of the predefined symbolic names for that field in that register. EMOD. PRICTL. PRICTL. DLB. DMA_FSETSA(0x01840000.<SYM>) addr <REG> <FIELD> <SYM> none Sets a register field to the specified value. etc. PRICTL. INDEX.<FIELD>.

hDma = DMA_open(DMA_CHA0. <PER> is a placeholder for the peripheral name: DMA. DMA_FSETSH(hDma. MCBSP. Peripheral handle Register name Field name Symbolic field value Return Value Description Example <PER>_RGET Macro Arguments Return Value Description Example Gets Register Current Value <PER>_RGET(<REG>) <REG> Uint32 Register name Register value Returns the current value of a register. TIMER. ESIZE. 28-18 . PRICTL. etc. DMA_OPEN_RESET). 32BIT). Only registers covered by handles per peripheral are valid. etc. Uint32 regVal. regVal = TIMER_RGET(CTL0). The value MUST be one of the predefined symbolic names for that field in that register. <PER> is a placeholder for the peripheral name: DMA. MCBSP. if any. DMA_Handle hDma. regVal = DMA_RGET(PRICTL0). regVal = DMA_RGET(AUXCTL).<REG>.<PER>_FSETSH <PER>_FSETSH Macro Arguments Sets Field Symbolically for a Given Handle <PER>_FSETSH(h. TIMER. regVal = MCBSP_RGET(SPCR0).<FIELD>.<SYM>) h <REG> <FIELD> <SYM> none Sets a register field to the specified value given a handle.

DMA_Handle hDma. regVal = DMA_RGETA(0x01840070. MCBSP.<PER>_RGETA <PER>_RGETA Macro Arguments Return Value Description Gets Register Address <PER>_RGETA(addr. Uint32 regVal. Uint32 regVal. MCBSP. TIMER. if any. AUXCTL).<REG>) h <REG> Uint32 Peripheral handle Register name Uint32 register value Returns the value of a register given a handle. Example <PER>_RGETH Macro Arguments Return Value Description Gets Register for a Given Handle <PER>_RGETH(h.prictl). <PER> is a placeholder for the peripheral name: DMA. Example Using the HAL Macros 28-19 . Only registers covered by the handle structure are valid. etc. etc. regVal = DMA_RGETA(&(cfg. <PER> is a placeholder for the peripheral name: DMA. PRICTL). This macro is useful in those situations where an arbitrary memory location is treated like a register such as in a configuration structure. DMA_OPEN_RESET). PRICTL). DMA_Config cfg.<REG>) addr <REG> Uint32 Uint32 address Register name Register value Returns the current value of a register given the address of the register. TIMER. regVal = DMA_RGETH(hDma. regVal = DMA_RGETA(0x01840000. hDma = DMA_open(DMA_CHA2. PRICTL).

<PER> is a placeholder for the peripheral name: DMA. 0x00000000). Register name Uint32 value to set register to Return Value Description Example <PER>_RSETA Macro Arguments Sets Register for a Given Address <PER>_RSETA(addr. MCBSP. regVal).x) <REG> x none Write the value x to the register. DMA_RSET(PRICTL0. DMA_RSET(AUXCTL. DMA_Config cfg. 0x09000101).secctl). 0). AUXCTL. MCBSP_RSET(SPCR0. DMA_RSETA(0x01840000. DMA_RSET(PRICTL0. Uint32 regVal = 0x09000101. etc.x) addr <REG> x none Sets the value of a register given its address. DMA_RGET(PRICTL0)&0xFFFFFFFC). Uint32 regVal = 0x09000101. TIMER. DMA_AUXCTL_DEFAULT). PRICTL. DMA_RSETA(&(cfg. x may be any valid C expression. TIMER. DMA_RSETA(0x01840000. <PER> is a placeholder for the peripheral name: DMA. etc.<PER>_RSET <PER>_RSET Macro Arguments Register Set <PER>_RSET(<REG>. 0). regVal). MCBSP. 0x09000101). This macro is useful in those situations where an arbitrary memory location is treated like a register such as in a configuration structure. DMA_RSETA(0x01840070. Uint32 address Register name Uint32 register value Return Value Description Example 28-20 . DMA_RSET(PRICTL0.<REG>. PRICTL. SECCTL.

<REG>. Uint32 defRegVal.x) h <REG> x none Sets the register value to x given a handle.<PER>_RSETH <PER>_RSETH Macro Arguments Sets Register for a Given Handle <PER>_RSETH(h. <PER> is a placeholder for the peripheral name: DMA.. DMA_Handle hDma. defRegVal = EMIF_GBLCTL_DEFAULT. MCBSP. if any. PRICTL. defRegVal = DMA_PRICTL_DEFAULT. etc. Using the HAL Macros 28-21 . TIMER. DMA_OPEN_RESET). 0x09000101). 0x00000080). SECCTL. DMA_RSETH(hDma. Only registers covered by handles per peripheral are valid. defRegVal = DMA_AUXCTL_DEFAULT. DMA_RSETH(hDma. Peripheral handle Register name Uint32 register value Return Value Description Example <PER>_<REG>_DEFAULT Macro Arguments Return Value Description Example Register Default Value <PER>_<REG>_DEFAULT none Uint32 Register default value Returns the default (power-on) value for the specified register. hDma = DMA_open(DMA_CHA0.

(Uint32)buffa. (Uint32)buffb.<PER>_<REG>_OF <PER>_<REG>_OF Macro Arguments Return Value Description Returns Value Of <PER>_<REG>_OF(x) x Uint32 Register value Returns x casted into a Uint32 This macro simply takes the argument x and returns it. DMA_SECCTL_OF(0x00000080). DMA_SRC_OF(buffa). they can be helpful. You are not required to use these macros. 0x00000080. DMA_XFRCNT_OF(0x00010008) ). however. The examples illustrate this: Example 1 does not use these macros and Example 2 does. 0x00010008 ). The intent is to make code more readable. Notice how Example 2 is easier to follow. /* create a config structure using the OF macros */ DMA_Config cfg = { DMA_PRICTL_OF(0x10002050). Example 1 Example 2 28-22 . DMA_DST_OF(buffb). /* create a config structure using hard coded values */ DMA_Config cfg = { 0x10002050. It is type-casted into a Uint32.

DMA_PRICTL_EMOD_HALT. it just returns a value suitable for this register. right-justified Value suitable for this register Return Value Description This macro constructs (makes) a register value based on individual field values. DMA_PRICTL_CNTRLD_DEFAULT.<PER>_<REG>_RMK <PER>_<REG>_RMK Register Make Macro Arguments <PER>_<REG>_RMK(field_ms. DMA_PRICTL_PRI_CPU. DMA_PRICTL_INDEX_DEFAULT. DMA_PRICTL_SPLIT_DISABLE. DMA_PRICTL_RSYNC_NONE. Only writable fields are specified and they are ordered from most significant to least significant. prictl = DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_NONE. Using the HAL Macros 28-23 . right-justified Intermediate-field values. right-justified Least-significant field value.field_ls) field_ms … field_ls Uint32 Most-significant field value. DMA_PRICTL_FS_DISABLE. DMA_PRICTL_TCINT_DISABLE. Example Uint32 prictl. It does not do any writes. Also. note that this macro may vary from one device to another for the same register. DMA_PRICTL_WSYNC_NONE.…. DMA_PRICTL_START_NORMAL ). DMA_PRICTL_ESIZE_32BIT. DMA_PRICTL_SRCDIR_INC. DMA_PRICTL_SRCRLD_NONE. Use this macro to make your code readable. DMA_PRICTL_DSTDIR_INC.

defRegVal = DMA_PRICTLESIZE_DEFAULT. idx = DMA_PRICTL_INDEX_OF(1). 28-24 . right-justified Returns x casted into a Uint32 This macro simply takes the argument x and returns it. Generally. <PER>_<REG>_<FIELD>_OF Field Value Of Macro Arguments Return Value Description <PER>_<REG>_<FIELD>_OF(x) x Uint32 Field value. Uint32 defFieldVal. Example <PER>_<REG>_<FIELD>_<SYM> Macro Arguments Return Value Description Example none Uint32 Field Symbolic Value <PER>_<REG>_<FIELD>_<SYM> field value Sets the specified value to the bit field MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_FREE. You are not required to use these macros. Uint32 idx. MCBSP_SRGR_CLKGDV_OF(15) ). they can be helpful. MCBSP_SRGR_FPER_OF(63). defRegVal = DMA_AUXCTLCHPRI_DEFAULT.<PER>_<REG>_<FIELD>_DEFAULT <PER>_<REG>_<FIELD>_DEFAULT Field Default Value Macro Arguments Return Value Description Example <PER>_<REG>_<FIELD>_DEFAULT none Uint32 Register default value Returns the default (power-on) value for the specified field.. MCBSP_SRGR_CLKSM_INTERNAL. MCBSP_SRGR_CLKSP_RISING. these macros are used in conjunction with the <PER>_RMK(…) macros. however. MCBSP_SRGR_FWID_OF(31). It serves a similar purpose to the <PER>_<REG>_OF() macros. MCBSP_SRGR_FSGM_DXR2XSR. It is type-casted into a Uint32. The intent is to make code more readable.

. . . . . . . . . A-7 A-1 . . . . . . As GUI−based configuration of the CSL is getting deprecated. . . For 6713 and DA610 CSL. . A-2 Compiling/Linking With CSL Using Code Composer Studio IDE . .Appendix A Appendix A Using CSL APIs Without DSP/BIOS ConfigTool You are not required to use the DSP/BIOS Configuration Tool when working with the CSL library. Topic A. . . . . . . . . . . . . . . the GUI configuration supports only the peripherals already supported in GUI for 6711. . . . . . . . you can choose not to use CSL GUI in the CDB file. . . . . . This appendix provides an example of using CSL independently of the DSP/BIOS kernel. it is recommended to avoid its usage.2 Page Using CSL APIs .1 A. . Note: You can continue to use the CDB file in your application but only for configuring CSL peripherals. .

1 Using CSL APIs Example A−1 illustrates the use of CSL to initialize DMA channel 0 and copy table BuffA to another table BuffB of 1024 bytes (1024/4 elements). #include <csl.1 Using DMA_config() Example A−1 uses the DMA_config() function to initialize the registers. The order of inclusion does not matter. on page 1-3. CSL Modules and Include Files.h> // Example−specific initialization #define BUFFSZ 1024 #define Uint32 BuffA[BUFFSZ/sizeof(Uint32)] #define Uint32 BuffB[BUFFSZ/sizeof(Uint32)] //Step 2: // Define and initialize the DMA channel configuration structure.h include file and the header file of the module/peripheral you will use. The different header files are shown in Table 1−1.h> #include <csl_dma. A. Example A−1. A-2 .1.Using CSL APIs A. Initializing a DMA Channel with DMA_config() // Step 1: // // // // Include the generic csl.

). DMA_PRICTL_SPLIT_DISABLE. DMA_SECCTL_BLOCKIE_ENABLE. DMA_SECCTL_RSYNCSTAT_CLEAR. DMA_PRICTL_FS_DISABLE. DMA_PRICTL_INDEX_NA. DMA_PRICTL_WSYNC_NONE. DMA_PRICTL_TCINT_DISABLE. DMA_PRICTL_PRI_DMA. DMA_SECCTL_WDROPCOND_CLEAR. /* dst */ (Uint32) BuffB. ). DMA_SECCTL_SXCOND_CLEAR. DMA_PRICTL_CNTRLD_NA. DMA_PRICTL_SRCRLD_NONE. DMA_SECCTL_BLOCKCOND_CLEAR. DMA_PRICTL_DSTDIR_INC. DMA_SECCTL_FRAMEIE_DISABLE. DMA_SECCTL_FRAMECOND_CLEAR. DMA_PRICTL_ESIZE_32BIT. /* DMA_SECCTL */ DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA. DMA_PRICTL_START_NORMAL.Using CSL APIs DMA_Config myconfig = { /* DMA_PRICTL */ DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_NONE. DMA_SECCTL_SXIE_DISABLE. DMA_SECCTL_WSYNCCLR_NOTHING. DMA_SECCTL_RSYNCCLR_NOTHING. DMA_PRICTL_EMOD_NOHALT. DMA_SECCTL_LASTIE_DISABLE. DMA_PRICTL_SRCDIR_INC. DMA_PRICTL_STATUS_STOPPED. Using CSL APIs Without DSP/BIOS A-3 . DMA_SECCTL_WDROPIE_DISABLE. DMA_SECCTL_RDROPCOND_CLEAR. /* src */ (Uint32) BuffA. /* xfrcnt */ BUFFSZ/sizeof(Uint32) }. DMA_SECCTL_DMACEN_LOW. DMA_SECCTL_RSPOL_NA. DMA_SECCTL_WSYNCSTAT_CLEAR. DMA_SECCTL_RDROPIE_DISABLE. DMA_SECCTL_LASTCOND_CLEAR. DMA_PRICTL_RSYNC_NONE. DMA_SECCTL_FSIG_NA.

Initializing a DMA Channel with DMA_config() (Continued) //Step 3: // // Define a DMA_Handle pointer. //Step 5: Open. Refer to Table 1−5 for further help on the RMK macro. Also refer to Appendix B for the symbolic constants provided by CSL for registers and bit−fields of any peripherals./*Open Channel(Optional) */ DMA_config(myhDma. } DMA_close(myhDma). &myconfig). } //Step 4: // // One-time only initialization of the CSL library and of the CSL module to be used. This is because it is using symbolic constants provided by CSL for setting fields of the register. Must be done before calling any CSL module API. configure and start the DMA channel. /* Wait for complete */ //Step 7: Close DMA channel after using. void main(void) { // Initialize Buffer tables for (x=0. myhDma = DMA_open(DMA_CHA0. A-4 .0). // To configure the channel you can use the // DMA_config or DMA_configArgs functions.Using CSL APIs Example A−1. /* Close channel (Optional) */ Note: The usage of the RMK macro for configuring registers is recommended as shown above in Step 2. while(DMA_getStatus(myhDma)). DMA_Handle myhDma. /* Init CSL */ CSL_init(). BuffB[x]=0. DMA_open returns a pointer to a DMA_Handle when a DMA channel is opened.x++) { BuffA[x]=x.x<BUFFSZ/sizeof(Uint32). /* Begin Transfer */ //Step 6: (Optional) // Use CSL DMA APIs to track DMA channel status. /* Configure Channel */ DMA_start(myhDma).

2 Using DMA_configArgs() Example A−2 performs the same task as Example A−1 but uses DMA_configArgs() to initialize the registers. DMA_Handle myhDma. /* Init CSL */ CSL_init(). The different header files are shown in Table 1−1.h> #include <csl_dma. #include <csl. // To configure the channel you can use the // DMA_config() or DMA_configArgs() functions. and start the DMA channel. on page 1-3.h> // Example−specific initialization #define BUFFSZ 1024 #define Uint32 BuffA[BUFFSZ/sizeof(Uint32)] #define Uint32 BuffB[BUFFSZ/sizeof(Uint32)] //Step 2: // // Define a DMA_Handle pointer.1.h include file and the header file of the module/peripheral you will use. DMA_open returns a pointer to a DMA_Handle when a DMA channel is opened. void main(void) { // Initialize Buffer tables for (x=0. BuffB[x]=0. configure. CSL Modules and Include Files. The order of inclusion does not matter. } //Step 3: // // One-time only initialization of the CSL library and of the CSL module to be used.x<BUFFSZ/sizeof(Uint32). Example A−2. Using CSL APIs Without DSP/BIOS A-5 .x++) { BuffA[x]=x. Initializing a DMA Channel with DMA_configArgs() // Step 1: // // // // Include the generic csl. //Step 4: Open.Using CSL APIs A. Must be done before calling any CSL module API.

/* Close channel (Optional) */ A-6 . //Step 6: (Optional) // Use CSL DMA APIs to track DMA channel status./*Open Channel(Optional) */ DMA_configArgs(myhDma. /* prictl */ 0x00000080.Using CSL APIs Example A−2. /* Wait for complete */ //Step 7: Close DMA channel after using. /* src */ (Uint32) BuffB. } DMA_close(myhDma). /* Begin Transfer */ }. 0x01000051. Initializing a DMA Channel with DMA_configArgs() (Continued) myhDma = DMA_open(DMA_CHA0. /* secctl */ (Uint32) BuffA. while(DMA_getStatus(myhDma)). DMA_start(myhDma).0). /* dst */ BUFFSZ/sizeof(Uint32) /* xfrcnt */ ).

Using CSL APIs Without DSP/BIOS A-7 . enter one and only one of the compiler symbols in Table 1−10. For example.2.2 Using the Code Composer Studio Project Environment To configure the CCS project environment to work with CSL. CSL Device Support Library Name and Symbol Conventions. CSL Directory Structure This CSL component.. if you are using the 6201™ device. from the menu bar. 2) Select the Compiler tab in the Build Options dialog box (Figure A−1). on page 1-17. Use this information when you set up the compiler and linker search paths.1 CSL Directory Structure Table A−1 lists the locations of the CSL components. enter CHIP_6201.Compiling and Linking With CSL Using Code Composer Studio IDE A. Table A−1.. c:\ti\c6000\bios\lib c:\ti\c6000\bios\src c:\ti\c6000\bios\include c:\ti\examples\dsk6211\csl c:\ti\examples\evm6201\csl Documentation c:\ti\docs A. follow these steps to specify the target device you are using: 1) Select Project→Options. and highlight Symbols in the category list box.2 Compiling and Linking With CSL Using Code Composer Studio IDE A.. Libraries Source library Include files Examples is located in this directory. 4) Click OK.. 3) In the Define Symbols field.2...

Defining the Target Device in the Build Options Dialog Box A-8 .Compiling and Linking With CSL Using Code Composer Studio IDE Figure A−1.

. . .15 B. . . .17 B. . . . . . . .12 B. .1 B. . . . . . . . . . . . . . . . . . .20 B. . . . B-386 VCP Registers . . . . . . . . . . . . . . .23 B. . . . . . . . . . . . . . . .7 B. . . . . . . . . . . . . . . . . . . . . . . B-60 EMAC Module Registers . . . B-284 MDIO Module Registers . . . . . . . . . . . . . . . . . . . . . . . . B-2 Direct Memory Access (DMA) Registers . . . .24 B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-207 Multichannel Buffered Serial Port (McBSP) Registers . . .25 B. . .4 B. . . . .26 Page Cache Registers . . . . . . . . .18 B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64 External Memory Interface (EMIF) Registers . . . . B-359 TCP Registers . . . . . . . . . . . . . . . . . . B-353 Power-Down Control Register . . . . . . . . . . . . .Appendix B Appendix A TMS320C6000 CSL Registers This appendix shows the registers associated with current TMS320C6000 digital signal processor (DSP) devices. . Topic B. . . . . . . . . . . . . . B-427 Video Display Registers . . .21 B. . . . . . . . . . . . . . .10 B. . . . . . . . . .6 B.2 B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . For a list of peripheral reference guides for your device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-360 Timer Registers . . . . . . . . . . . The symbolic constants and registers in the peripheral reference guides are to be used as the latest updates. . . . . . . . . . . . . . . . . . . . . .11 B. . B-159 Inter-Integrated Circuit (I2C) Registers . . . . . . . . . . . . . . B-149 Host Port Interface (HPI) Register . . .16 B. . . B-504 Expansion Bus (XBUS) Registers . . . . . . . . . . . . . . B-203 Multichannel Audio Serial Port (McASP) Registers . . . . . . . . B-31 EMAC Control Module Registers . . B-17 Enhanced DMA (EDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-413 Video Capture Registers . . . B-529 B-1 . . . . . . . . . . . . B-462 Video Port GPIO Registers . . . . . . . . . B-311 Peripheral Component Interconnect (PCI) Registers . . . .14 B. . . . . . . . . . . . . . . . . The individual peripheral reference guides also include the registers and may also have a list of symbolic constants. . . . . . . . . . .3 B. . . . . . . . . . . . . . . . . . . . . . . .5 B. . . . . . . . . . B-409 Video Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TMS320C6000 DSP Peripherals Overview Reference Guide (SPRU190). . . . . . . . . . . B-122 General-Purpose Input/Output (GPIO) Registers .22 B. . . . .19 B. . . . . . . . . . . . . . . . . B-328 Phase-Locked Loop (PLL) Registers . . . . . . . . . . . . . . . B-382 UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . B-168 Interrupt Request (IRQ) Registers . . . . . . . . . . . . . B-396 VIC Port Registers . . . . . . . . . . . .8 B. . . . . . .9 B.13 B. . . . . . .

7 B.12 B.1.5 B.1.14 B. B-2 TMS320C6000 CSL Registers .3 B.1.6 B.2 B.1.4 B.16 B.20 Notes: 1) The names of the registers have been changed.1.1.18 B.1.1.1.15 B.13 B.8 B.1.9 B.10 B.Cache Registers B.1.1. Appendix D contains a comparison table of old versus new names.1 B.1.1.1.1 Cache Registers Table B−1. Cache Registers Acronym CCFG EDMAWEIGHT‡ L2WBAR L2WWC L2WIBAR L2WIWC L2IBAR‡ L2IWC‡ L2ALLOC0− L2ALLOC3‡ L1PIBAR L1PIWC L1DWIBAR L1DWIWC L1DIBAR‡ L1DIWC‡ L2WB L2WBINV MAR0−15† MAR96−111‡ MAR128−191‡ Register Name Cache configuration register L2 EDMA access control register L2 writeback base address register L2 writeback word count L2 writeback− invalidate base address register L2 writeback− invalidate word count L2 invalidate base address register L2 invalidate word count L2 allocation priority queue registers L1P invalidate base address register L1P invalidate word count L1D writeback− invalidate base address register L1D writeback− invalidate word count L1D invalidate base address register L1D invalidate word count L2 writeback all L2 writeback− invalidate all L2 memory attribute registers L2 memory attribute registers for EMIFB only L2 memory attribute registers for EMIFA only Section B.19 B.1.17 B.1.11 B. ‡ For C64x only.1.1.1. † For C621x/C671x only.

The reserved bit location is always read as zero. bit field P is Reserved. Legend: R/W-x = Read/Write-Reset value Table B−2. Cache Configuration Register (CCFG) Field Values Bit 31−29 field† P URGENT HIGH MEDIUM LOW 28−10 9 Reserved IP NORMAL INVALIDATE 8 ID NORMAL INVALIDATE 7−3 † symval† Value Description L2 Requestor Priority (for C64x only. use the notation CACHE_CCFG_field_symval TMS320C6000 CSL Registers B-3 .Cache Registers B. L1P operation − 0 1 Normal L1P operation All L1P lines invalidated Invalidate L1D 0 1 0 Normal L1D operation All L1D lines invalidated Invalidate LIP Reserved. The reserved bit location is always read as zero. A value written to this field has no effect. A value written to this field has no effect. On C621x/C671x.1. R-000b. Cache Configuration Register (CCFG) 31 P{ R/W-000 15 Reserved R-0 † 29 28 Reserved R-0 10 9 IP W-0 8 ID W-0 7 Reserved R-0 3 2 L2MODE R/W-000 16 0 Applicable on C64 only. Reserved − For CSL implementation. reserved for C621x/C671x) 0 1h 2h 3h 0 L2 controller requests are placed on urgent priority level L2 controller requests are placed on high priority level L2 controller requests are placed on medium priority level L2 controller requests are placed on low priority level Reserved.1 Cache Configuration Register (CCFG) Figure B−1.

Cache Configuration Register (CCFG) Field Values (Continued) Bit 2−0 field† L2MODE 0KC 16KC 32KC 32KC 64KC 48KC 128KC − 64KC 256KC † symval† Value Description L2 Operation Mode 0 1h 1h 2h 2h 3h 3h 4h−6h 7h 7h No L2 Cache (All SRAM mode) 1-way cache (16K L2 cache) C621x/C671x only 4-way cache (32K L2 cache) C64x only 2-way cache (32K L2 cache) C621x/C671x only 4-way cache (64K L2 cache) C64x only 3-way cache (48K L2 cache) C621x/C671x only 4-way cache (128K L2 cache) C64x only Reserved 4-way cache (64K L2 cache) C621x/C671x only 4-way cache (256K L2 cache) C64x only For CSL implementation.Cache Registers Table B−2. use the notation CACHE_CCFG_field_symval B-4 TMS320C6000 CSL Registers .

For CSL implementation. use the notation CACHE_L2WBAR_field_symval TMS320C6000 CSL Registers B-5 . The reserved bit location is always read as zero.2 L2 EDMA Access Control Register (C64x) Figure B−2.1. EDMA receives priority after 4 L1D priority cycles. EDMA never receives priority.3 L2 Writeback Base Address Register (L2WBAR) Figure B−3. -n = value after reset 2 1 R/W-1 0 EDMAWEIGHT Table B−3. A value written to this field has no effect.Cache Registers B. L1D access always a higher priority than EDMA access to L2. R/W = Read/Write. L2 Writeback Base Address Register (L2WBAR) Field Values Bit 31−0 † field† LWFBAR symval† OF(value) Value 0−FFFF FFFFh Description L2 Writeback Base Address. B. L2 EDMA Access Control Register (EDMAWEIGHT) 31 Reserved R-0 Legend: R = Read only.1. EDMA receives priority after 1 L1D priority cycle. EDMA weight limits the amount of time L1D blocks EDMA access to L2. EDMA receives priority after 16 L1D priority cycles. L2 EDMA Access Control Register (EDMAWEIGHT) Field Values Bit 31−2 1−0 Field Reserved EDMAWEIGHT 0 1h 2h 3h Value 0 Description Reserved. L2 Writeback Base Address Register (L2WBAR) 31 L2 Writeback Base Address (L2WBAR) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−4.

L2 Writeback Word Count Register (L2WWC) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 15 L2 Writeback Word Count (L2WWC) R/W-0 0 Table B−5. L2 Writeback−Invalidate Base Address Register (L2WIBAR) 31 L2 Writeback−Invalidate Base Address (L2WIBAR) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−6.4 L2 Writeback Word Count Register (L2WWC) Figure B−4.Cache Registers B.5 L2 Writeback−Invalidate Base Address Register (L2WIBAR) Figure B−5. For CSL implementation.1. use the notation CACHE_L2WIBAR_field_symval B-6 TMS320C6000 CSL Registers . L2 Writeback Word Count Register (L2WWC) Field Values Bit 31−16 15−0 † field† Reserved L2WWC symval† − OF(value) Value 0 0−FFFFh Description Reserved. L2 Writeback−Invalidate Base Address Register (L2WIBAR) Field Values Bit 31−0 † field† L2WIBAR symval† OF(value) Value 0−FFFF FFFFh Description L2 Writeback−Invalidate Base Address. A value written to this field has no effect. The reserved bit location is always read as zero.1. For CSL implementation. use the notation CACHE_L2WWC_field_symval B. L2 Writeback Word Count.

use the notation CACHE_L2WIWC_field_symval B. The reserved bit location is always read as zero.6 L2 Writeback−Invalidate Count Register (L2WIWC) Figure B−6. use the notation CACHE_L2IBAR_field_symval TMS320C6000 CSL Registers B-7 .1. L2 Invalidate Base Address Register (L2IBAR) Field Values Bit 31−0 † field† L2IBAR symval† OF(value) Value 0−FFFF FFFFh Description L2 Invalidate Base Address. For CSL implementation.Cache Registers B. L2 Writeback−Invalidate Clean Word Count. For CSL implementation.1. L2 Writeback−Invalidate Word Count Register (L2WIWC) Field Values Bit 31−16 15−0 † field† Reserved L2WIWC symval† − OF(value) Value 0 0−FFFFh Description Reserved. L2 Invalidate Base Address Register (L2IBAR) 31 L2 Invalidate Base Address (L2IBAR) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−8.7 L2 Invalidate Base Address Register (L2IBAR) (C64x only) Figure B−7. L2 Writeback−Invalidate Word Count Register (L2WIWC) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 15 0 L2 Writeback−Invalidate Clean Word Count (L2WIWC) R/W-0 Table B−7. A value written to this field has no effect.

For CSL implementation. The reserved bit location is always read as zero. A value written to this field has no effect. For CSL implementation. A value written to this field has no effect. L2 Invalidate Word Count Register (L2IWC) Field Values Bit 31−16 15−0 † field† Reserved L2IWC symval† − OF(value) Value 0 0−FFFFh Description Reserved. use the notation CACHE_L2IWC_field_symval B. L2 Allocation Registers (L2ALLOC0−L2ALLOC3) 31 Reserved 16 15 Reserved 3 2 QnCNT R/W-0 0 Legend: R/W-x = Read/Write-Reset value Table B−10.1. The reserved bit location is always read as zero. use the notation CACHE_L2ALLOCn_field_symval B-8 TMS320C6000 CSL Registers .9 L2 Allocation Priority Queue Registers (L2ALLOC0−L2ALLOC3) (C64x) Figure B−9.8 L2 Invalidate Count Register (L2IWC) (C64x only) Figure B−8. L2 Writeback−Invalidate Word Count Register (L2IWC) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 15 L2 Invalidate Clean Word Count (L2IWC) R/W-0 0 Table B−9. L2 Invalidate Clean Word Count.Cache Registers B. L2 Allocation Registers (L2ALLOC0−L2ALLOC3) Field Values Bit 31−3 2−0 † field† Reserved QnCNT symval† − OF(value) Value 0 0−7h Description Reserved.1.

1.Cache Registers B. For CSL implementation. The reserved bit location is always read as zero. A value written to this field has no effect. use the notation CACHE_L1PIBAR_field_symval B. L1P Invalidate Base Address Register (L1PIBAR) Field Values Bit 31−0 † field† L1PIBAR symval† OF(value) Value 0−FFFF FFFFh Description L1P Invalidate Base Address. L1P Invalidate Base Address Register (L1PIBAR) 31 L1P Invalidate Base Address (L1PIBAR) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−11. L1P Invalidate Word Count Register (L1PIWC) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 15 L1P Invalidate Word Count (L1PIWC) R/W-x 0 Table B−12. L1P Invalidate Word Count Register (L1PIWC) Field Values Bit 31−16 15−0 † field† Reserved L1PIWC symval† − OF(value) Value 0 0−FFFFh Description Reserved. L1P Invalidate Word Count. use the notation CACHE_L1PIWC_field_symval TMS320C6000 CSL Registers B-9 .11 L1P Invalidate Word Count Register (L1PIWC) Figure B−11. For CSL implementation.1.10 L1P Invalidate Base Address Register (L1PIBAR) Figure B−10.

L1D Writeback−Invalidate Word Count.1. L1D Writeback−Invalidate Base Address Register (L1DWIBAR) Field Values Bit 31−0 † field† L1DWIBAR symval† OF(value) Value 0−FFFF FFFFh Description L1D Writeback−Invalidate Base Address. L1D Writeback−Invalidate Word Count Register (L1DWIWC) Field Values Bit 31−16 15−0 † field† Reserved L1DWIWC symval† − OF(value) Value 0 0−FFFFh Description Reserved.Cache Registers B.1. use the notation CACHE_L1DWIWC_field_symval B-10 TMS320C6000 CSL Registers .13 L1D Writeback−Invalidate Word Count Register (L1DWIWC) Figure B−13. For CSL implementation. A value written to this field has no effect. L1D Writeback−Invalidate Word Count Register (L1DWIWC) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 15 0 L1D Writeback−Invalidate Word Count (L1DWIWC) R/W-0 Table B−14.12 L1D Writeback−Invalidate Base Address Register (L1DWIBAR) Figure B−12. L1D Writeback−Invalidate Base Address Register (L1DWIBAR) 31 L1D Writeback−Invalidate Base Address (L1DWIBAR) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−13. For CSL implementation. The reserved bit location is always read as zero. use the notation CACHE_L1DWIBAR_field_symval B.

For CSL implementation. L1D Invalidate Word Count Register (L1DIWC) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 15 L1D Invalidate Word Count (L1DIWC) R/W-0 0 Table B−16.15 L1D Invalidate Word Count Register (L1DIWC) (C64x only) Figure B−15. use the notation CACHE_L1DIWC_field_symval TMS320C6000 CSL Registers B-11 . L1D Invalidate Base Address Register (L1DIBAR) Field Values Bit 31−0 † field† L1DIBAR symval† OF(value) Value 0−FFFF FFFFh Description L1D Invalidate Base Address. For CSL implementation. L1D Invalidate Word Count.Cache Registers B.1.1. The reserved bit location is always read as zero. L1D Invalidate Word Count Register (L1DIWC) Field Values Bit 31−16 15−0 † field† Reserved L1DIWC symval† − OF(value) Value 0 0−FFFFh Description Reserved. A value written to this field has no effect. L1P Invalidate Base Address Register (L1PIBAR) 31 L1D Invalidate Base Address (L1DIBAR) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−15. use the notation CACHE_L1DIBAR_field_symval B.14 L1D Invalidate Base Address Register (L1DIBAR) (C64x only) Figure B−14.

Figure B−16.1. use the notation CACHE_L2WB_field_symval B-12 TMS320C6000 CSL Registers .Cache Registers B. Writing a 1 to the C bit of L2WB initiates a global writeback of L2. Writeback All L2 0 1 Normal L2 operation All L2 lines writeback all For CSL implementation. L2 Writeback All Register (L2WB) Field Values Bit 31−1 0 field† Reserved C NORMAL FLUSH † symval† − Value 0 Description Reserved. The reserved bit location is always read as zero. Programs can poll to determine when a cache operation is complete. L2 Writeback All Register (L2WB) 31 Reserved R-0 15 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 1 0 C R/W-0 Table B−17.16 L2 Writeback All Register (L2WB) The L2 offers both global writeback and global writeback-invalidate operations. Global cache operations in L2 are initiated by writing a 1 to the C bit in L2WB (Figure B−16). The C bit continues to read as 1 until the cache operation is complete. A value written to this field has no effect.

Programs can poll to determine when a cache operation is complete. use the notation CACHE_L2WBINV_field_symval TMS320C6000 CSL Registers B-13 . The C bit continues to read as 1 until the cache operation is complete. A value written to this field has no effect. L2 Writeback−Invalidate All Register (L2WBINV) 31 Reserved R-0 15 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 1 0 C R/W-0 Table B−18. Clean L2 0 1 Normal L2 operation All L2 lines writeback−invalidate all For CSL implementation. Writing a 1 to the C bit of L2WBINV initiates a global writeback-invalidate of L2.1.Cache Registers B. The reserved bit location is always read as zero. Figure B−17.17 L2 Writeback−Invalidate All Register (L2WBINV) The L2 offers both global writeback and global writeback-invalidate operations. L2 Writeback−Invalidate All Register (L2WBINV) Field Values Bit 31−1 0 field† Reserved C NORMAL CLEAN † symval† − Value 0 Description Reserved. Global cache operations in L2 are initiated by writing a 1 to the C bit in L2WBINV (Figure B−17).

1. No special procedure is necessary. L2 Memory Attribute Registers (MAR0−MAR15) Field Values Bit 31−1 0 field† Reserved CE DISABLE ENABLE † symval† − Value 0 Description Reserved.Cache Registers B. and L2 are allowed to cache the corresponding address range. The reserved bit location is always read as zero. an application should set the CE bit in the appropriate MAR to 1. thereby disabling caching of external memory by default. This is in contrast to L2 SRAM. To enable caching on a particular external address range. use the notation CACHE_MAR_field_symval B-14 TMS320C6000 CSL Registers . Figure B−18. 0 1 Memory range is not cacheable. After reset.18 L2 Memory Attribute Registers (MAR0−MAR15) The cache enable (CE) bit in each MAR determines whether the L1D. the CE bit in each MAR is cleared to 0. L2 Memory Attribute Registers (MAR0−MAR15) 31 Reserved R-0 15 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 1 0 CE R/W-0 Table B−19. Memory range is cacheable. which is always considered cacheable. Cache enable bit. A value written to this field has no effect. Subsequent accesses to the affected address range are cached by the two-level memory system. L1P. For CSL implementation.

A value written to this field has no effect. For CSL implementation.Cache Registers B. the CE bit in each MAR is cleared to 0. an application should set the CE bit in the appropriate MAR to 1. To enable caching on a particular external address range. thereby disabling caching of external memory by default. Figure B−19. which is always considered cacheable.1. 0 1 Memory range is not cacheable. and L2 are allowed to cache the corresponding address range. L2 Memory Attribute Registers (MAR96−MAR111) Field Values Bit 31−1 0 field† Reserved CE DISABLE ENABLE † symval† − Value 0 Description Reserved. use the notation CACHE_MAR_field_symval TMS320C6000 CSL Registers B-15 . After reset. L1P.19 L2 Memory Attribute Registers for EMIFB Only (MAR96−MAR111) The cache enable (CE) bit in each MAR determines whether the L1D. Memory range is cacheable. The reserved bit location is always read as zero. No special procedure is necessary. This is in contrast to L2 SRAM. Cache enable bit. Subsequent accesses to the affected address range are cached by the two-level memory system. L2 Memory Attribute Registers (MAR96−MAR111) 31 Reserved R-0 15 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 1 0 CE R/W-0 Table B−20.

Figure B−20. After reset. which is always considered cacheable. Cache enable bit.1.Cache Registers B. Memory range is cacheable. L2 Memory Attribute Registers (MAR128−MAR191) Field Values Bit 31−1 0 field† Reserved CE DISABLE ENABLE † symval† − Value 0 Description Reserved. L1P.20 L2 Memory Attribute Registers for EMIFA Only (MAR128−MAR191) The cache enable (CE) bit in each MAR determines whether the L1D. L2 Memory Attribute Registers (MAR128−MAR191) 31 Reserved R-0 15 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 1 0 CE R/W-0 Table B−21. thereby disabling caching of external memory by default. the CE bit in each MAR is cleared to 0. No special procedure is necessary. This is in contrast to L2 SRAM. 0 1 Memory range is not cacheable. and L2 are allowed to cache the corresponding address range. A value written to this field has no effect. an application should set the CE bit in the appropriate MAR to 1. The reserved bit location is always read as zero. Subsequent accesses to the affected address range are cached by the two-level memory system. For CSL implementation. use the notation CACHE_MAR_field_symval B-16 TMS320C6000 CSL Registers . To enable caching on a particular external address range.

2.2.2 Direct Memory Access (DMA) Registers Table B−22.5 B.2.2.2.2.2.2 B.2.Direct Memory Access (DMA) Registers B.4 B. DMA Registers Acronym AUXCTL PRICTL SECCTL SRC DST XFRCNT GBLCNT GBLIDX GBLADDR Register Name DMA auxiliary control register DMA channel primary control register DMA channel secondary control register DMA channel source address register DMA channel destination address register DMA channel transfer counter register DMA global count reload register DMA global index register DMA global address reload register Section B.7 B.8 B. DMA Auxiliary Control Register (AUXCTL) 31 Reserved R-0 5 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 4 AUXPRI R/W-0 3 CHPRI R/W-0 0 TMS320C6000 CSL Registers B-17 .3 B.1 DMA Auxiliary Control Register (AUXCTL) Figure B−21.6 B.2.1 B.2.9 B.

DMA Auxiliary Control Register (AUXCTL) Field Values Bit 31−5 4 field† Reserved AUXPRI CPU DMA 3−0 CHPRI 0 1 symval† − Value 0 Description Reserved. use the notation DMA_AUXCTL_field_symval B-18 TMS320C6000 CSL Registers . A value written to this field has no effect.Direct Memory Access (DMA) Registers Table B−23. HIGHEST 2ND 3RD 4TH LOWEST − † 0 1h 2h 3h 4h 5h−Fh Fixed channel priority mode auxiliary channel highest priority Fixed channel priority mode auxiliary channel 2nd-highest priority Fixed channel priority mode auxiliary channel 3rd-highest priority Fixed channel priority mode auxiliary channel 4th-highest priority Fixed channel priority mode auxiliary channel lowest priority Reserved For CSL implementation. In the case when the auxiliary channel is used to service the expansion bus host port operation. CHPRI must be 0000b (auxiliary channel highest priority). The reserved bit location is always read as zero. Auxiliary channel priority mode CPU priority DMA priority DMA channel priority.

Direct Memory Access (DMA) Registers B. use the notation DMA_PRICTL_field_symval TMS320C6000 CSL Registers B-19 . DMA Channel Primary Control Register (PRICTL) Field Values Bit 31−30 field† DSTRLD NONE B C D 29−28 SRCRLD NONE B C D † symval† Value Description Destination address reload for autoinitialization 0 1h 2h 3h Do not reload during autoinitialization Use DMA global address register B as reload Use DMA global address register C as reload Use DMA global address register D as reload Source address reload for autoinitialization 0 1h 2h 3h Do not reload during autoinitialization Use DMA global address register B as reload Use DMA global address register C as reload Use DMA global address register D as reload For CSL implementation. DMA Channel Primary Control Register (PRICTL) 31 DSTRLD R/W-0 23 WSYNC R/W-0 14 RSYNC R/W-0 7 DSTDIR R/W-0 6 5 SRCDIR R/W-0 13 INDEX R/W-0 12 CNTRLD R/W-0 4 3 STATUS R-0 11 SPLIT R/W-0 2 1 START R/W-0 10 9 ESIZE R/W-0 0 30 29 SRCRLD R/W-0 28 27 EMOD R/W-0 19 18 RSYNC R/W-0 8 26 FS R/W-0 25 TCINT R/W-0 24 PRI R/W-0 Legend: R/W-x = Read/Write-Reset value Table B−24.2 DMA Channel Primary Control Register (PRICTL) Figure B−22.2.

use the notation DMA_PRICTL_field_symval B-20 TMS320C6000 CSL Registers .Direct Memory Access (DMA) Registers Table B−24. DMA Channel Primary Control Register (PRICTL) Field Values (Continued) Bit 27 field† EMOD NOHALT HALT 26 FS DISABLE RSYNC 25 TCINT DISABLE ENABLE 24 PRI CPU DMA 23−19 WSYNC NONE TINT0 TINT1 SDINT EXTINT4 EXTINT5 EXTINT6 EXTINT7 DMAINT0 DMAINT1 DMAINT2 † symval† Value Description Emulation mode 0 1 DMA channel keeps running during an emulation halt DMA channel pauses during an emulation halt Frame synchronization 0 1 Disable RSYNC event used to synchronize entire frame Transfer controller interrupt 0 1 Interrupt disabled Interrupt enabled Priority mode: DMA versus CPU 0 1 CPU priority DMA priority Write transfer synchronization 0 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah No synchronization Timer interrupt event 0 Timer interrupt event 1 External interrupt event 4 External interrupt event 5 External interrupt event 6 External interrupt event 7 DMA interrupt event 0 DMA interrupt event 1 DMA interrupt event 2 For CSL implementation.

use the notation DMA_PRICTL_field_symval TMS320C6000 CSL Registers B-21 .Direct Memory Access (DMA) Registers Table B−24. DMA Channel Primary Control Register (PRICTL) Field Values (Continued) Bit field† symval† DMAINT3 XEVT0 REVT0 XEVT1 REVT1 DSPINT XEVT2 REVT2 − 18−14 RSYNC NONE TINT0 TINT1 SDINT EXTINT4 EXTINT5 EXTINT6 EXTINT7 DMAINT0 DMAINT1 DMAINT2 DMAINT3 XEVT0 REVT0 XEVT1 † Value Bh Ch Dh Eh Fh 10h 11h 12h 13h−1Fh Description DMA interrupt event 3 McBSP 0 transmit event 0 McBSP 0 receive event McBSP 1 transmit event McBSP 1 receive event DSP interrupt event McBSP 2 transmit event McBSP 2 receive event Reserved Read synchronization 0 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh No synchronization Timer interrupt event 0 Timer interrupt event 1 External interrupt event 4 External interrupt event 5 External interrupt event 6 External interrupt event 7 DMA interrupt event 0 DMA interrupt event 1 DMA interrupt event 2 DMA interrupt event 3 McBSP 0 transmit event 0 McBSP 0 receive event McBSP 1 transmit event For CSL implementation.

Direct Memory Access (DMA) Registers Table B−24. use the notation DMA_PRICTL_field_symval B-22 TMS320C6000 CSL Registers . use DMA global address register C as split address Element size 0 1h 2h 3h 32-bit 16-bit 8-bit Reserved For CSL implementation. use DMA global address register A as split address Split-channel mode enabled. DMA Channel Primary Control Register (PRICTL) Field Values (Continued) Bit field† symval† REVT1 DSPINT XEVT2 REVT2 1−18 13 INDEX A B 12 CNTRLD A B 11−10 SPLIT DISABLE A B C 9−8 ESIZE 32 BIT 16 BIT 8 BIT − † Value Fh 10h 11h 12h 13−1Fh Description McBSP 1 receive event DSP interrupt event McBSP 2 transmit event McBSP 2 receive event Reserved Selects the DMA global data register to use as a programmable index 0 1 Use DMA global index register A Use DMA global index register B Transfer counter reload for autoinitialization and multiframe transfers 0 1 Reload with DMA global count reload register A Reload with DMA global count reload register B Split channel mode 0 1h 2h 3h Split-channel mode disabled Split-channel mode enabled. use DMA global address register B as split address Split-channel mode enabled.

use the notation DMA_PRICTL_field_symval TMS320C6000 CSL Registers B-23 . DMA Channel Primary Control Register (PRICTL) Field Values (Continued) Bit 7−6 field† DSTDIR NONE INC DEC IDX 5−4 SRCDIR NONE INC DEC IDX 3−2 STATUS STOPPED RUNNING PAUSED AUTORUNNING 1−0 START STOP NORMAL PAUSE AUTOINIT † symval† Value Description Destination address modification after element transfers 0 1h 2h 3h No modification Increment by element size in bytes Decrement by element size in bytes Adjust using DMA global index register selected by INDEX Source address modification after element transfers 0 1h 2h 3h No modification Increment by element size in bytes Decrement by element size in bytes Adjust using DMA global index register selected by INDEX 0 1h 2h 3h Stopped Running without autoinitialization Paused Running with autoinitialization 0 1h 2h 3h Stopped Running without autoinitialization Paused Running with autoinitialization For CSL implementation.Direct Memory Access (DMA) Registers Table B−24.

These bits are R+0 on the C6201 and C6701 devices. The reserved bit location is always read as zero. A value written to this field has no effect. Legend: R/W-x = Read/Write-Reset value Table B−25.3 DMA Channel Secondary Control Register (SECCTL) Figure B−23. DMA Channel Secondary Control Register (SECCTL) 31 Reserved R-0 22 Reserved R-0 15 WSYNCCLR 21 WSPOL† 20 RSPOL† R/W-0 12 19 FSIG† R/W-0 11 WDROPIE 18 DMACEN 10 WDROPCOND 16 14 WSYNCSTAT R/W-0 13 R/W-000 9 RDROPIE 8 RDROPCOND RSYNCCLR RSYNCSTAT R/W-0 7 BLOCKIE R/W-0 6 BLOCKCOND R/W-0 5 LASTIE R/W-0 4 LASTCOND R/W-0 3 FRAMEIE R/W-0 2 FRAMECOND R/W-0 1 SXIE R/W-0 0 SXCOND R/W-1 † R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 These bits are not available on the C6201 and C6701 devices. This field is valid only if EXT_INTx is selected.Direct Memory Access (DMA) Registers B. ACTIVEHIGH ACTIVELOW † 0 1 Active high Active low For CSL implementation.2. Write synchronization event polarity (not applicable for C6201 and C6701 devices). This field is valid only if EXT_INTx is selected. ACTIVEHIGH ACTIVELOW 20 RSPOL 0 1 Active high Active low Read and frame synchronization event polarity (not applicable for C6201 and C6701 devices). use the notation DMA_SECCTL_field_symval B-24 TMS320C6000 CSL Registers . DMA Channel Secondary Control Register (SECCTL) Field Values Bit 31−22 21 field† Reserved WSPOL symval† − Value 0 Description Reserved.

DMAC reflects FRAMECOND. For CSL implementation. 18−16 DMACEN LOW HIGH RSYNCSTAT WSYNCSTAT FRAMECOND BLOCKCOND − 15 WSYNCCLR NOTHING CLEAR 14 WSYNCSTAT CLEAR SET 13 RSYNCCLR NOTHING CLEAR † DMA action complete pins reflect status and condition. DMAC reflects RSYNCSTAT. Reserved Write synchronization status clear bit. Level detect mode (valid only when FS = 1). 0 1 No effect. DMAC reflects BLOCKCOND. Clear write synchronization status. use the notation DMA_SECCTL_field_symval TMS320C6000 CSL Registers B-25 . DMAC reflects WSYNCSTAT. 0 1h 2h 3h 4h 5h 6h−7h DMAC pin is held low. Synchronization is received. Write synchronization status. FSIG must be cleared to 0 for non-frame-synchronized transfers (not applicable for C6201 and C6701 devices).Direct Memory Access (DMA) Registers Table B−25. NORMAL IGNORE 0 1 Edge detect mode (FS = 1 or FS = 0). 0 1 No effect. In level detect mode. Clear read synchronization status. DMAC pin is held high. synchronization inputs received during a frame transfer are ignored unless still set after the frame transfer completes. 0 1 Synchronization is not received. DMA Channel Secondary Control Register (SECCTL) Field Values (Continued) Bit 19 field† FSIG symval† Value Description Level/edge detect mode selection. Read synchronization status clear bit.

Write synchronization dropped interrupt enable. Synchronization is received. Block transfer finished condition. 0 1 RDROP condition does not enable DMA channel interrupt. Write drop condition. 0 1 WDROP condition does not enable DMA channel interrupt. Block transfer finished interrupt enable. use the notation DMA_SECCTL_field_symval B-26 TMS320C6000 CSL Registers . Read drop condition. BLOCK condition is detected. 0 1 RDROP condition is not detected. Read synchronization dropped interrupt enable. RDROP condition enables DMA channel interrupt. 0 1 BLOCK condition does not enable DMA channel interrupt. RDROP condition is detected. 0 1 BLOCK condition is not detected. For CSL implementation. WDROP condition is detected. BLOCK condition enables DMA channel interrupt. 0 1 Synchronization is not received. DMA Channel Secondary Control Register (SECCTL) Field Values (Continued) Bit 12 field† RSYNCSTAT CLEAR SET 11 WDROPIE DISABLE ENABLE 10 WDROPCOND CLEAR SET 9 RDROPIE DISABLE ENABLE 8 RDROPCOND CLEAR SET 7 BLOCKIE DISABLE ENABLE 6 BLOCKCOND CLEAR SET † symval† Value Description Read synchronization status. 0 1 WDROP condition is not detected.Direct Memory Access (DMA) Registers Table B−25. WDROP condition enables DMA channel interrupt.

LAST condition is detected. Frame complete condition. 0 1 LAST condition does not enable DMA channel interrupt. Split transmit overrun receive interrupt enable. 0 1 LAST condition is not detected. FRAME condition enables DMA channel interrupt. DMA Channel Secondary Control Register (SECCTL) Field Values (Continued) Bit 5 field† LASTIE DISABLE ENABLE 4 LASTCOND CLEAR SET 3 FRAMEIE DISABLE ENABLE 2 FRAMECOND CLEAR SET 1 SXIE DISABLE ENABLE 0 SXCOND CLEAR SET † symval† Value Description Last frame finished interrupt enable. 0 1 FRAME condition is not detected.Direct Memory Access (DMA) Registers Table B−25. For CSL implementation. FRAME condition is detected. Frame complete interrupt enable. 0 1 SX condition is not detected. SX condition is detected. SX condition enables DMA channel interrupt. Split transmit condition. LAST condition enables DMA channel interrupt. Last frame finished condition. 0 1 SX condition does not enable DMA channel interrupt. use the notation DMA_SECCTL_field_symval TMS320C6000 CSL Registers B-27 . 0 1 FRAME condition does not enable DMA channel interrupt.

2. DMA Channel Source Address Register (SRC) 31 Source Address (SRC) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−26. DMA Channel Destination Address Register (DST) 31 Destination Address (DST) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−27. use the notation DMA_DST_DST_symval B-28 TMS320C6000 CSL Registers .2.Direct Memory Access (DMA) Registers B. use the notation DMA_SRC_SRC_symval B. DMA Channel Destination Address Register (DST) Field Values Bit 31−0 † Field DST symval† OF(value) Value 0−FFFF FFFFh Description Destination Address For CSL implementation.5 DMA Channel Destination Address Register (DST) Figure B−25.4 DMA Channel Source Address Register (SRC) Figure B−24. DMA Channel Source Address Register (SRC) Field Values Bit 31−0 † Field SRC symval† OF(value) Value 0−FFFF FFFFh Description Source Address For CSL implementation.

DMA Global Count Reload Register (GBLCNT) 31 Frame Count Reload (FRMCNT) R/W-0 Legend: R/W-x = Read/Write-Reset value 16 15 Element Count Reload (ELECNT) R/W-0 0 Table B−29. DMA Global Count Reload Register (GBLCNT) Field Values Bit 31−16 15−0 † field† FRMCNT ELECNT symval† OF(value) OF(value) Value 0−FFFFh 0−FFFFh Description This 16-bit value reloads FRMCNT bits in XFRCNT.Direct Memory Access (DMA) Registers B.6 DMA Channel Transfer Counter Register (XFRCNT) Figure B−26. use the notation DMA_GBLCNT_field_symval TMS320C6000 CSL Registers B-29 .2. This 16-bit value reloads ELECNT bits in XFRCNT. DMA Channel Transfer Counter Register (XFRCNT) 31 Frame Count (FRMCNT) R/W-0 Legend: R/W-x = Read/Write-Reset value 16 15 Element Count (ELECNT) R/W-0 0 Table B−28. For CSL implementation.2.7 DMA Global Count Reload Register (GBLCNT) Figure B−27. use the notation DMA_XFRCNT_field_symval B. DMA Channel Transfer Counter Register (XFRCNT) Field Values Bit 31−16 15−0 † field† FRMCNT ELECNT symval† OF(value) OF(value) Value 0−FFFFh 0−FFFFh Description Frame Count Element Count For CSL implementation.

use the notation DMA_GBLADDR_GBLADDR_symval B-30 TMS320C6000 CSL Registers . DMA Global Index Register (GBLIDX) Field Values Bit 31−16 15−0 † field† FRMIDX ELEIDX symval† OF(value) OF(value) Value 0−FFFFh 0−FFFFh Description Frame Index Element Index For CSL implementation. use the notation DMA_GBLIDX_field_symval B.2.2.Direct Memory Access (DMA) Registers B. DMA Global Index Register (GBLIDX) 31 Frame Index (FRMIDX) R/W-0 Legend: R/W-x = Read/Write-Reset value 16 15 Element Index (ELEIDX) R/W-0 0 Table B−30. DMA Global Address Reload Register (GBLADDR) Field Values Bit 31−0 † Field GBLADDR symval† OF(value) Value 0−FFFF FFFFh Description Global Address Reload For CSL implementation.8 DMA Global Index Register (GBLIDX) Figure B−28.9 DMA Global Address Reload Register (GBLADDR) Figure B−29. DMA Global Address Reload Register (GBLADDR) 31 Global Address Reload (GBLADDR) R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−31.

3.3.3.3.3.3 B.3.14 B.16 B.8 B.7 B.11 B.3.18 B.3.9 B.5 B.3.3.19 B.23 B.3.3.24 B.12 B.3.10 B.17 B.3.3. EDMA Registers Acronym OPT SRC CNT DST IDX RLD ESEL PQAR PQSR PQSR CIPR CIPRL CIPRH CIER CIERL CIERH CCER CCERL CCERH ER ERL ERH EER EERL EERH Register Name EDMA channel options register EDMA channel source address register EDMA channel transfer count register EDMA channel destination address register EDMA channel index register EDMA channel count reload/link register EDMA event selector registers (C621x/C671x) EDMA priority queue allocation registers (C64x) EDMA priority queue status register (C621x/C671x) EDMA priority queue status register (C64x) EDMA channel interrupt pending register (C621x/C671x) EDMA channel interrupt pending low register (C64x) EDMA channel interrupt pending high register (C64x) EDMA channel interrupt enable register (C621x/C671x) EDMA channel interrupt enable low register (C64x) EDMA channel interrupt enable high register (C64x) EDMA channel chain enable register (C621x/C671x) EDMA channel chain enable low register (C64x) EDMA channel chain enable high register (C64x) EDMA event register (C621x/C671x) EDMA event low register (C64x) EDMA event high register (C64x) EDMA event enable register (C621x/C671x) EDMA event enable low register (C64x) EDMA event enable high register (C64x) Section B.3.22 B.3.4 B.15 B.20 B.13 B.2 B.3.25 TMS320C6000 CSL Registers B-31 .3.1 B.3.21 B.Enhanced DMA (EDMA) Registers B.3.3.3 Enhanced DMA (EDMA) Registers Table B−32.3.3.6 B.3.

3. Legend: R/W-x = Read/Write-Reset value B-32 TMS320C6000 CSL Registers .29 B.27 B.3. EDMA Registers (Continued) Acronym ECR ECRL ECRH ESR ESRL ESRH EPRL EPRH Register Name EDMA event clear register (C621x/C671x) EDMA event clear low register (C64x) EDMA event clear high register (C64x) EDMA event set register (C621x/C671x) EDMA event set low register (C64x) EDMA event set high register (C64x) EDMA event polarity low register (C64x) EDMA event set polarity register (C64x) Section B.1 EDMA Channel Options Register (OPT) Figure B−30. On C621x/C671x.30 B.3.3.33 B.26 B.31 B.Enhanced DMA (EDMA) Registers Table B−32.3.32 B.3.3. these bits are Reserved.3. R+0. EDMA Channel Options Register (OPT) 31 PRI R/W-0 23 2DD R/W-0 15 Reserved R-0 14 TCCM{ R/W-00 5 ATCC† R/W-0 † 29 28 ESIZE R/W-0 21 DUM R/W-0 13 20 TCINT R/W-0 12 ATCINT† R/W-0 4 Reserved R-0 11 19 27 26 2DS R/W-0 25 SUM R/W-0 24 22 16 TCC R/W-0 10 ATCC† R/W-0 2 PDTD† R/W-0 1 LINK R/W-0 0 FS R/W-0 Reserved R-0 3 PDTS† R/W-0 Applies to C64x only.28 B.3.

Enhanced DMA (EDMA) Registers Table B−33. Low priority EDMA transfer requests. TMS320C6000 CSL Registers B-33 . EDMA Channel Options Register (OPT) Field Values Bit 31−29 field† PRI symval† Value Description Priority levels for EDMA events For C64x: URGENT HIGH MEDIUM LOW 0 1h 2h 3h Urgent priority. This level is available for CPU and EDMA transfer requests. 2-dimensional source. C67x: HIGH LOW 28−27 ESIZE 32 BIT 16 BIT 8 BIT − 26 2DS NO YES 25−24 SUM NONE INC DEC IDX † 1h 2h This level is reserved only for L2 requests and not valid for EDMA transfer requests. Source address update mode 0 1h 2h 3h Fixed address mode. Medium priority EDMA transfer Low priority EDMA transfer For C62x. use the notation EDMA_OPT_field_symval. Element size 0 1h 2h 3h 32-bit word 16-bit half-word 8-bit byte Reserved Source dimension 0 1 1-dimensional source. For CSL implementation. No source address modification Source address increment depends on 2DS and FS bits Source address decrement depends on 2DS and FS bits Source address modified by the element index/frame index depending on 2DS and FS bits.

Reserved. when the current set is exhausted. B-34 TMS320C6000 CSL Registers .e. For C64x. the 4-bit TCC code is used in conjunction with bit field TCCM for a 6-bit transfer complete code. EDMA Channel Options Register (OPT) Field Values (Continued) Bit 23 field† 2DD NO YES 22−21 DUM NONE INC DEC IDX 20 TCINT NO YES 19−16 TCC OF(value) 0 1 0−Fh 0 1h 2h 3h 0 1 symval† Value Description Destination dimension 1-dimensional destination 2-dimensional destination Destination address update mode Fixed address mode. No destination address modification Destination address increment depends on 2DD and FS bits Destination address decrement depends on 2DD and FS bits Destination address modified by the element index/frame index depending on 2DD and FS bits. 15 14−13 Reserved TCCM − OF(value) 0 0−3h † For CSL implementation. use the notation EDMA_OPT_field_symval. The relevant CIPR bit is set on channel transfer completion. The 6-bit code is used to set the relevant bit in the EDMA channel interrupt pending register (CIPRL or CIPRH) provided TCINT = 1.Enhanced DMA (EDMA) Registers Table B−33. The reserved bit location is always read as zero. Transfer complete interrupt Transfer complete indication disabled. CIPR[TCC] bit) provided. The bit (position) set in the CIPR is the TCC value specified. Transfer complete code 4-bit code is used to set the relevant bit in CIPR (i. This 2-bit value works in conjunction with the TCC bits to provide a 6-bit transfer complete code. CIPR bits are not set upon completion of a transfer. Transfer complete code most-significant bits. A value written to this field has no effect.

After the current set is exhausted.Enhanced DMA (EDMA) Registers Table B−33. The bit (position) set in CIPRL or CIPRH is the ATCC value specified. Alternate transfer complete indication is disabled. Reserved. A value written to this field has no effect. Alternate transfer complete code. The link address must be on a 24-byte boundary and within the EDMA PaRAM. Reserved. the channel entry is reloaded with the parameter set specified by the link address. The EDMA channel interrupt pending register (CIPRL or CIPRH) bit is set upon completion of intermediate transfers in a block. EDMA Channel Options Register (OPT) Field Values (Continued) Bit 12 field† ATCINT NO 0 symval† Value Description Alternate transfer complete interrupt. Entry not reloaded. DISABLE ENABLE 2 PDTD DISABLE ENABLE 1 LINK NO YES 0 1 0 1 0 1 PDT read is disabled. This 6-bit value is used to set the bit in the EDMA channel interrupt pending register (CIPRL or CIPRH) (CIP[ATCC] bit) provided ATCINT = 1. Linking of event parameters enabled. The EDMA channel interrupt pending register (CIPRL or CIPRH) bits are not set upon completion of intermediate transfers in a block. Peripheral device transfer (PDT) mode for destination. Peripheral device transfer (PDT) mode for source. Linking of event parameters enable. Alternate transfer complete indication is enabled. This bit can be used for chaining and interrupt generation. The link address is a 16-bit address offset from the PaRAM base address. The reserved bit location is always read as zero. YES 1 11 Reserved − 0 10−5 ATCC OF(value) 0−3Fh 4 Reserved − 0 3 PDTS † For CSL implementation. PDT write is enabled. PDT write is disabled. The reserved bit location is always read as zero. Linking of event parameters disabled. use the notation EDMA_OPT_field_symval. PDT read is enabled. A value written to this field has no effect. TMS320C6000 CSL Registers B-35 . upon completion of an intermediate transfer in a block.

2 EDMA Channel Source Address Register (SRC) Figure B−31.3. Channel is frame synchronized. The address is modified using the SUM bits in the EDMA channel options parameter (OPT). † For CSL implementation. The relevant event for a given EDMA channel is used to synchronize a frame. EDMA Channel Source Address Register (SRC) Field Values Bit 31−0 Field SRC symval† OF(value) Value 0−FFFF FFFFh Description This 32-bit source address specifies the starting byte address of the source. use the notation EDMA_SRC_SRC_symval. EDMA Channel Options Register (OPT) Field Values (Continued) Bit 0 field† FS NO YES † symval† Value Description Frame synchronization 0 1 Channel is element/array synchronized.Enhanced DMA (EDMA) Registers Table B−33. B. For CSL implementation. B-36 TMS320C6000 CSL Registers . use the notation EDMA_OPT_field_symval. EDMA Channel Source Address Register (SRC) 31 Source Address (SRC) 0 Table B−34.

† For CSL implementation. The address is modified using the DUM bits in the EDMA channel options parameter (OPT). A 16-bit unsigned value that specifies the number of elements in a frame for (1D transfers) or an array (for 2D transfers). B. EDMA Channel Transfer Count Register (CNT) 31 FRMCNT 16 15 ELECNT 0 Table B−35. A 16-bit unsigned value plus 1 that specifies the number of frames in a 1D block or number of arrays in a 2D block.Enhanced DMA (EDMA) Registers B. EDMA Channel Destination Address Register (DST) Field Values Bit 31−0 Field DST symval† OF(value) Value 0−FFFF FFFFh Description This 32-bit destination address specifies the starting byte address of the destination. TMS320C6000 CSL Registers B-37 . EDMA Channel Transfer Count Register (CNT) Field Values Bit 31−16 field† FRMCNT symval† OF(value) Value 0−FFFFh Description Frame/array count.3. Element count.4 EDMA Channel Destination Address Register (DST) Figure B−33. EDMA Channel Destination Address Register (DST) 31 Destination Address (DST) 0 Table B−36.3.3 EDMA Channel Transfer Count Register (CNT) Figure B−32. use the notation EDMA_DST_DST_symval. 15−0 ELECNT OF(value) 1−FFFFh † For CSL implementation. Valid values for the element count: 1−65535. Valid values for the frame/array count: 0−65535. use the notation EDMA_CNT_field_symval.

A 16-bit signed value that specifies the element index used for an address offset to the next element in a frame.Enhanced DMA (EDMA) Registers B. EDMA Channel Index Register (IDX) Field Values Bit 31−16 field† FRMIDX symval† OF(value) Value 0−FFFFh Description Frame/array index. This 16-bit link address specifies the lower 16-bit address in the parameter RAM from which the EDMA loads/reloads the parameters of the next event in the chain. Valid values for the element index: –32768 to 32767. 15−0 LINK OF(value) 0−FFFFh † For CSL implementation. Element index is used only for 1D transfers. This field is used only for a 1D element sync (FS = 0) transfer.5 EDMA Channel Index Register (IDX) Figure B−34. A 16-bit unsigned value used to reload the element count field in the EDMA channel transfer count parameter (CNT) once the last element in a frame is transferred. B-38 TMS320C6000 CSL Registers . This is necessary for multi-frame EDMA transfers where frame count value is greater than 0. EDMA Channel Index Register (IDX) 31 FRMIDX 16 15 ELEIDX 0 Table B−37. B. since the EDMA has to keep track of the next element address using the element count. A 16-bit signed value that specifies the frame/array index used for an address offset to the next frame/ array. use the notation EDMA_IDX_field_symval. 15−0 ELEIDX OF(value) 0−FFFFh † For CSL implementation.3. Element index. EDMA Channel Count Reload/Link Register (RLD) Field Values Bit 31−16 field† ELERLD symval† OF(value) Value 0−FFFFh Description Element count reload. use the notation EDMA_RLD_field_symval. Valid values for the frame/array index: –32768 to 32767. EDMA Channel Count Reload/Link Register (RLD) 31 ELERLD 16 15 LINK 0 Table B−38.3.6 EDMA Channel Count Reload/Link Register (RLD) Figure B−35.

This 6-bit value maps event 0 to any EDMA channel. Reserved. Event selector 0. Reserved. You should always write 0 to this field. Event selector 2. 1. EDMA Event Selector Register 0 (ESEL0) Field Values Bit 31−30 29−24 23−22 21−16 15−14 13−8 7−6 5−0 Field Reserved EVTSEL3 Reserved EVTSEL2 Reserved EVTSEL1 Reserved EVTSEL0 Value 0 0−3Fh 0 0−3Fh 0 0−3Fh 0 0−3Fh Description Reserved. 3) Figure B−36. You should always write 0 to this field. Event selector 3. This 6-bit value maps event 3 to any EDMA channel. This 6-bit value maps event 1 to any EDMA channel.7 EDMA Event Selector Registers (ESEL0. TMS320C6000 CSL Registers B-39 . EDMA Event Selector Register 0 (ESEL0) 31 R-0 15 R-0 14 13 EVTSEL1 R/W-00 0001b 30 29 EVTSEL3 R/W-00 0011b 8 7 R-0 24 23 R-0 6 5 EVTSEL0 R/W-00 0000b 22 21 EVTSEL2 R/W-00 0010b 0 16 Reserved Reserved Reserved Reserved Legend: R = Read only. -n = value after reset Table B−39.3. You should always write 0 to this field. Reserved. R/W = Read/Write. Event selector 1. You should always write 0 to this field. This 6-bit value maps event 2 to any EDMA channel.Enhanced DMA (EDMA) Registers B.

This 6-bit value maps event 4 to any EDMA channel. You should always write 0 to this field. EDMA Event Selector Register 1 (ESEL1) 31 R-0 15 R-0 14 13 EVTSEL5 R/W-00 0101b 30 29 EVTSEL7 R/W-00 0111b 8 7 R-0 24 23 R-0 6 5 EVTSEL4 R/W-00 0100b 22 21 EVTSEL6 R/W-00 0110b 0 16 Reserved Reserved Reserved Reserved Legend: R = Read only. EDMA Event Selector Register 0 (ESEL1) Field Values Bit 31−30 29−24 23−22 21−16 15−14 13−8 7−6 5−0 Field Reserved EVTSEL7 Reserved EVTSEL6 Reserved EVTSEL5 Reserved EVTSEL4 Value 0 0−3Fh 0 0−3Fh 0 0−3Fh 0 0−3Fh Description Reserved. Event selector 6. You should always write 0 to this field. R/W = Read/Write. This 6-bit value maps event 7 to any EDMA channel. You should always write 0 to this field. Reserved. B-40 TMS320C6000 CSL Registers . -n = value after reset Table B−40. You should always write 0 to this field. Reserved. This 6-bit value maps event 6 to any EDMA channel. Event selector 5. Event selector 7.Enhanced DMA (EDMA) Registers Figure B−37. This 6-bit value maps event 5 to any EDMA channel. Reserved. Event selector 4.

Event selector 12. You should always write 0 to this field. Reserved. This 6-bit value maps event 13 to any EDMA channel. This 6-bit value maps event 15 to any EDMA channel. Event selector 14. -n = value after reset Table B−41. TMS320C6000 CSL Registers B-41 . Reserved. You should always write 0 to this field.Enhanced DMA (EDMA) Registers Figure B−38. Reserved. This 6-bit value maps event 12 to any EDMA channel. This 6-bit value maps event 14 to any EDMA channel. Event selector 15. EDMA Event Selector Register 3 (ESEL3) 31 R-0 15 R-0 14 13 EVTSEL13 R/W-00 1101b 30 29 EVTSEL15 R/W-00 1111b 8 7 R-0 24 23 R-0 6 5 EVTSEL12 R/W-00 1100b 22 21 EVTSEL14 R/W-00 1110b 0 16 Reserved Reserved Reserved Reserved Legend: R = Read only. EDMA Event Selector Register 0 (ESEL3) Field Values Bit 31−30 29−24 23−22 21−16 15−14 13−8 7−6 5−0 Field Reserved EVTSEL15 Reserved EVTSEL14 Reserved EVTSEL13 Reserved EVTSEL12 Value 0 0−3Fh 0 0−3Fh 0 0−3Fh 0 0−3Fh Description Reserved. R/W = Read/Write. You should always write 0 to this field. You should always write 0 to this field. Event selector 13.

Priority queue allocation bits determine the queue length available to EDMA requests. You should always write 0 to this field. EDMA_PQAR1_PQA_symval.8 Priority Queue Allocation Registers (PQAR0−3) (C64x) Figure B−39.3. The reserved bit location is always read as 0. If writing to this field. Priority Queue Allocation Register (PQAR) Field Values Bit 31−4 3 2−0 † Field Reserved Reserved PQA symval† − − OF(value) Value 0 0 0−7h Description Reserved. Reserved. -n = value after reset † Always write 0 to the reserved bit. Table B−42. the default value is 010b. the default value is 110b. always write a 0. use the notation EDMA_PQAR0_PQA_symval. ‡ For PQAR0 and PQAR2. R/W = Read/Write. EDMA_PQAR2_PQA_symval. B-42 TMS320C6000 CSL Registers .Enhanced DMA (EDMA) Registers B. Priority Queue Allocation Register (PQAR) 31 Reserved R-0 3 Rsvd† R/W-0 2 PQA2 R-0‡ 1 PQA1 R-1‡ 0 PQA0 R-0‡ Legend: R = Read only. and EDMA_PQAR3_PQA_symval. For CSL implementation. for PQAR1 and PQAR3.

use the notation EDMA_PQSR_PQ_symval. The reserved bit location is always read as zero. Priority Queue Status Register (PQSR) Field Values Bit 31−4 3−0 Field Reserved PQ OF(value) 0−Fh symval Value Description Reserved. † For CSL implementation. You should always write 0 to this field. A 1 in the PQ bit indicates that there are no requests pending in the respective priority level queue. Priority Queue Status Register (PQSR) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 4 3 PQ3 R-1 2 PQ2 R-1 1 PQ1 R-1 0 PQ0 R-1 Table B−44. TMS320C6000 CSL Registers B-43 .10 Priority Queue Status Register (PQSR) (C64x) Figure B−41.9 Priority Queue Status Register (PQSR) (C621x/C671x) Figure B−40.Enhanced DMA (EDMA) Registers B. Priority Queue Status Register (PQSR) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 3 2 PQ2 R-1 1 PQ1 R-1 0 PQ0 R-1 Table B−43. A value written to this field has no effect.3. Priority queue status. use the notation EDMA_PQSR_PQ_symval. B. A 1 in the PQ bit indicates that there are no requests pending in the respective priority level queue. Priority Queue Status Register (PQSR) Field Values Bit 31−3 2−0 † Field Reserved PQ symval† − OF(value) Value 0 0−7h Description Reserved. Priority queue status. For CSL implementation.3.

3. You should always write 0 to this field. B-44 TMS320C6000 CSL Registers . EDMA Channel Interrupt Pending Register (CIPR) 31 Reserved R-0 Legend: R/W-x = Read/Write-Reset value 16 15 CIP R/W-0 0 Table B−45. the EDMA channel controller sets a bit in the CIP field.11 EDMA Channel Interrupt Pending Register (CIPR) (C621x/C671x) Figure B−42. When the TCINT bit in the channel options parameter (OPT) is set to 1 for an EDMA channel and a specific transfer complete code (TCC) is provided by the EDMA transfer controller. Channel interrupt pending. † For CSL implementation. use the notation EDMA_CIPR_CIP_symval.Enhanced DMA (EDMA) Registers B. EDMA Channel Interrupt Pending Register (CIPR) Field Values Bit 31−16 15−0 Field Reserved CIP symval† − OF(value) Value 0 0−FFFFh Description Reserved.

When the TCINT or ATCINT bit in the channel options parameter (OPT) is set to 1 for an EDMA channel and a specific transfer complete code (TCC) or alternate transfer complete code (ATCC) is provided by the EDMA transfer controller. EDMA Channel Interrupt Pending Low Register (CIPRL) 31 CIP R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−46. † For CSL implementation.3. † For CSL implementation.13 EDMA Channel Interrupt Pending High Register (CIPRH) (C64x) Figure B−44.3. EDMA Channel Interrupt Pending High Register (CIPRH) 31 CIP R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−47. B. EDMA Channel Interrupt Pending High Register (CIPRH) Field Values Bit 31−0 Field CIP symval† OF(value) Value 0−FFFF FFFFh Description Channel 32−63 interrupt pending. When the TCINT or ATCINT bit in the channel options parameter (OPT) is set to 1 for an EDMA channel and a specific transfer complete code (TCC) or alternate transfer complete code (ATCC) is provided by the EDMA transfer controller. the EDMA channel controller sets a bit in the CIP field.12 EDMA Channel Interrupt Pending Low Register (CIPRL) (C64x) Figure B−43. EDMA Channel Interrupt Pending Low Register (CIPRL) Field Values Bit 31−0 Field CIP symval† OF(value) Value 0−FFFF FFFFh Description Channel 0−31 interrupt pending. use the notation EDMA_CIPRH_CIP_symval. TMS320C6000 CSL Registers B-45 .Enhanced DMA (EDMA) Registers B. the EDMA channel controller sets a bit in the CIP field. use the notation EDMA_CIPRL_CIP_symval.

C621x/C671x: Channel Interrupt Enable Register (CIER) Field Values Bit 31−16 15−0 Field Reserved CIE symval† − OF(value) Value 0 0−FFFFh Description Reserved. use the notation EDMA_CIER_CIE_symval. † For CSL implementation. B-46 TMS320C6000 CSL Registers . Channel interrupt enable. EDMA Channel Interrupt Enable Register (CIER) 31 Reserved 16 15 CIE R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−48.3.14 EDMA Channel Interrupt Enable Register (CIER) (C621x/C671x) Figure B−45. A 16-bit unsigned value used to disable (bit value = 0) or enable (bit value = 1) an interrupt for an EDMA channel.Enhanced DMA (EDMA) Registers B. You should always write 0 to this field.

EDMA Channel Interrupt Enable Low Register (CIERL) Field Values Bit 31−0 Field CIE symval† OF(value) Value 0−FFFF FFFFh Description Channel 0−31 interrupt enable. EDMA Channel Interrupt Enable High Register (CIERH) Field Values Bit 31−0 Field CIE symval† OF(value) Value 0−FFFF FFFFh Description Channel 32−63 interrupt enable. B.3. † For CSL implementation. A 32-bit unsigned value used to disable (bit value = 0) or enable (bit value = 1) an interrupt for an EDMA channel.16 EDMA Channel Interrupt Enable High Register (CIERH) (C64x) Figure B−47. use the notation EDMA_CIERL_CIE_symval. EDMA Channel Interrupt Enable High Register (CIERH) 31 CIE R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−50.3.Enhanced DMA (EDMA) Registers B.15 EDMA Channel Interrupt Enable Low Register (CIERL) (C64x) Figure B−46. TMS320C6000 CSL Registers B-47 . EDMA Channel Interrupt Enable Low Register (CIERL) 31 CIE R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−49. use the notation EDMA_CIERH_CIE_symval. † For CSL implementation. A 32-bit unsigned value used to disable (bit value = 0) or enable (bit value = 1) an interrupt for an EDMA channel.

17 EDMA Channel Chain Enable Register (CCER) (C621x/C671x) Figure B−48. Additionally. EDMA Channel Chain Enable Register (CCER) 31 Reserved 12 11 Reserved CCE R/W-0 Legend: R/W-x = Read/Write-Reset value 8 7 Reserved 0 Table B−51.3. 7−0 † Reserved − 0 For CSL implementation. use the notation EDMA_CCER_CCE_symval. Reserved. EDMA Channel Chain Enable Register (CCER) Field Values Bit 31−12 11−8 Field Reserved CCE symval† − OF(value) Value 0 0−Fh Description Reserved.Enhanced DMA (EDMA) Registers B. B-48 TMS320C6000 CSL Registers . set the TCINT bit in the channel options parameter (OPT) to 1. You should always write 0 to this field. set the relevant bit in the CCE field to trigger off the next channel transfer specified by TCC. To enable the EDMA controller to chain channels by way of a single event. Channel chain enable. You should always write 0 to this field.

3. EDMA Channel Chain Enable High Register (CCERH) 31 CCE R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−53.18 EDMA Channel Chain Enable Low Register (CCERL) (C64x) Figure B−49. † For CSL implementation. EDMA Channel Chain Enable Low Register (CCERL) 31 CCE R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−52.Enhanced DMA (EDMA) Registers B. To enable the EDMA controller to chain channels by way of a single event. EDMA Channel Chain Enable Low Register (CCERL) Field Values Bit 31−0 Field CCE symval† OF(value) Value 0−FFFF FFFFh Description Channel 0−31 chain enable.3. use the notation EDMA_CCERL_CCE_symval. set the relevant bit in the CCE field to trigger off the next channel transfer specified by the transfer complete code (TCC) or alternate transfer complete code (ATCC). use the notation EDMA_CCERH_CCE_symval. EDMA Channel Chain Enable High Register (CCERH) Field Values Bit 31−0 Field CCE symval† OF(value) Value 0−FFFF FFFFh Description Channel 32−63 chain enable. Additionally. Additionally. To enable the EDMA controller to chain channels by way of a single event. TMS320C6000 CSL Registers B-49 . † For CSL implementation. set the relevant bit in the CCE field to trigger off the next channel transfer specified by the transfer complete code (TCC) or alternate transfer complete code (ATCC). B.19 EDMA Channel Chain Enable High Register (CCERH) (C64x) Figure B−50. set the TCINT or ATCINT bit in the channel options parameter (OPT) to 1. set the TCINT or ATCINT bit in the channel options parameter (OPT) to 1.

For CSL implementation. EDMA Event Register (ER) 31 Reserved 16 15 EVT R-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−54. Event.20 EDMA Event Register (ER) (C621x/C671x) Figure B−51. EDMA Event Register (ER) Field Values Bit 31−16 15−0 † Field Reserved EVT symval† − OF(value) Value 0 0−FFFFh Description Reserved. You should always write 0 to this field. All events that are captured by the EDMA are latched in ER.Enhanced DMA (EDMA) Registers B.3. use the notation EDMA_ER_EVT_symval. even if that event is disabled. B-50 TMS320C6000 CSL Registers .

21 EDMA Event Low Register (ERL) (C64x) Figure B−51. Events 32−63 captured by the EDMA are latched in ERH. use the notation EDMA_ERL_EVT_symval. EDMA Event Low Register (ERL) Field Values Bit 31−0 † Field EVT symval† OF(value) Value 0−FFFF FFFFh Description Event 0−31.3.22 EDMA Event High Register (ERH) (C64x) Figure B−52.Enhanced DMA (EDMA) Registers B. For CSL implementation. EDMA Event High Register (ERH) Field Values Bit 31−0 † Field EVT symval† OF(value) Value 0−FFFF FFFFh Description Event 32−63. even if that event is disabled. even if that event is disabled. EDMA Event Low Register (ERL) 31 EVT R-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−55. TMS320C6000 CSL Registers B-51 .3. use the notation EDMA_ERH_EVT_symval. B. Events 0−31 captured by the EDMA are latched in ERL. For CSL implementation. 1EDMA Event High Register (ERH) 31 EVT R-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−56.

3. † For CSL implementation. Note that bits 11−8 are only available for chaining of EDMA events. B-52 TMS320C6000 CSL Registers . they are enabled in the channel chain enable register (CCER). Any of the event bits can be set to 1 to enable that event or be cleared to 0 to disable that event. Event enable. use the notation EDMA_EER_EE_symval.Enhanced DMA (EDMA) Registers B. Bits 11−8 are reserved and should only be written with 0. EDMA Event Enable Register (EER) 31 Reserved 16 15 EE R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−57. therefore. EDMA Event Enable Register (EER) Field Values Bit 31−16 15−0 Field Reserved EE symval† − OF(value) Value 0 0−FFFFh Description Reserved. You should always write 0 to this field.23 EDMA Event Enable Register (EER) (C621x/C671x) Figure B−53.

use the notation EDMA_EERL_EE_symval. Any of the event bits can be set to 1 to enable that event or be cleared to 0 to disable that event. EDMA Event Enable High Register (EERH) Field Values Bit 31−0 † Field EE symval† OF(value) Value 0−FFFF FFFFh Description Event 32−63 enable. For CSL implementation. B. EDMA Event Enable Low Register (EERL) 31 EE R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−58. Any of the event bits can be set to 1 to enable that event or be cleared to 0 to disable that event.Enhanced DMA (EDMA) Registers B. TMS320C6000 CSL Registers B-53 .3. use the notation EDMA_EERH_EE_symval. For CSL implementation.24 EDMA Event Enable Low Register (EERL) (C64x) Figure B−54. EDMA Event Enable High Register (EERH) 31 EE R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−59. EDMA Event Low Register (EERL) Field Values Bit 31−0 † Field EE symval† OF(value) Value 0−FFFF FFFFh Description Event 0−31 enable.25 EDMA Event Enable High Register (EERH) (C64x) Figure B−55.3.

a write of 0 has no effect. use the notation EDMA_ECR_EC_symval.26 EDMA Event Clear Register (ECR) (C621x/C671x) Figure B−56. You should always write 0 to this field. B-54 TMS320C6000 CSL Registers . For CSL implementation. EDMA Event Clear Register (ECR) 31 Reserved 16 15 EC R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−60.3. Any of the event bits can be set to 1 to clear that event. Event clear. EDMA Event Clear Register (ERC) Field Values Bit 31−16 15−0 † Field Reserved EC symval† − OF(value) Value 0 0−FFFFh Description Reserved.Enhanced DMA (EDMA) Registers B.

For CSL implementation.3. EDMA Event Clear Low Register (ECRL) 31 EC R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−61. Any of the event bits can be set to 1 to clear that event. For CSL implementation. TMS320C6000 CSL Registers B-55 .3. Any of the event bits can be set to 1 to clear that event. EDMA Event Clear High Register (ECRH) 31 EC R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−62.27 EDMA Event Clear Low Register (ECRL) (C64x) Figure B−57. B. EDMA Event Clear High Register (ECRH) Field Values Bit 31−0 † Field EC symval† OF(value) Value 0−FFFF FFFFh Description Event 32−63 clear. use the notation EDMA_ECRL_EC_symval. a write of 0 has no effect.28 EDMA Event Clear High Register (ECRH) (C64x) Figure B−58. a write of 0 has no effect.Enhanced DMA (EDMA) Registers B. EDMA Event Clear Low Register (ERCL) Field Values Bit 31−0 † Field EC symval† OF(value) Value 0−FFFF FFFFh Description Event 0−31 clear. use the notation EDMA_ECRH_EC_symval.

use the notation EDMA_ESR_ES_symval. EDMA Event Set Register (ESR) Field Values Bit 31−16 15−0 Field Reserved ES symval† − OF(value) Value 0 0−FFFFh Description Reserved. B-56 TMS320C6000 CSL Registers . † For CSL implementation.3.Enhanced DMA (EDMA) Registers B. You should always write 0 to this field. Any of the event bits can be set to 1 to set the corresponding bit in the event register (ER). EDMA Event Set Register (ESR) 31 Reserved 16 15 ES R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−63. Event set.29 EDMA Event Set Register (ESR) (C621x/C671x) Figure B−59. a write of 0 has no effect.

Enhanced DMA (EDMA) Registers B.3. Any of the event bits can be set to 1 to set the corresponding bit in the event low register (ERL). † For CSL implementation. † For CSL implementation. EDMA Event Set Low Register (ESRL) 31 ES R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−64. a write of 0 has no effect. B. EDMA Event Set Low Register (ESRL) Field Values Bit 31−0 Field ES symval† OF(value) Value 0−FFFF FFFFh Description Event 0−31 set. Any of the event bits can be set to 1 to set the corresponding bit in the event high register (ERH). use the notation EDMA_ESRH_ES_symval. use the notation EDMA_ESRL_ES_symval. a write of 0 has no effect.3.30 EDMA Event Set Low Register (ESRL) (C64x) Figure B−60.31 EDMA Event Set High Register (ESRH) (C64x) Figure B−61. EDMA Event Set High Register (ESRH) 31 ES R/W-0 Legend: R/W-x = Read/Write-Reset value 0 Table B−65. EDMA Event Set High Register (ESRH) Field Values Bit 31−0 Field ES symval† OF(value) Value 0−FFFF FFFFh Description Event 32−63 set. TMS320C6000 CSL Registers B-57 .

32 EDMA Event Polarity Low Register (EPRL) Figure B−62. † For CSL implementation. use the notation EDMA_EPRL_EP_symval. EDMA Event Polarity Low Register (EPRL) Field Values Bit 31−0 Field EP symval† OF(value) Value 0−FFFF FFFFh Description Event 0−31 polarity. B-58 TMS320C6000 CSL Registers . -n = value after reset Table B−66. EDMA Event Polarity Low Register (EPRL) 31 EP31 R/W-0 23 EP23 R/W-0 15 EP15 R/W-0 7 EP7 R/W-0 30 EP30 R/W-0 22 EP22 R/W-0 14 EP14 R/W-0 6 EP6 R/W-0 29 EP29 R/W-0 21 EP21 R/W-0 13 EP13 R/W-0 5 EP5 R/W-0 28 EP28 R/W-0 20 EP20 R/W-0 12 EP12 R/W-0 4 EP4 R/W-0 27 EP27 R/W-0 19 EP19 R/W-0 11 EP11 R/W-0 3 EP3 R/W-0 26 EP26 R/W-0 18 EP18 R/W-0 10 EP10 R/W-0 2 EP2 R/W-0 25 EP25 R/W-0 17 EP17 R/W-0 9 EP9 R/W-0 1 EP1 R/W-0 24 EP24 R/W-0 16 EP16 R/W-0 8 EP8 R/W-0 0 EP0 R/W-0 Legend: R/W = Read/Write.3.Enhanced DMA (EDMA) Registers B. A 32-bit unsigned value used to select a rising edge (bit value = 0) or falling edge (bit value = 1) to determine when an event is triggered on its input.

3. -n = value after reset Table B−67. EDMA Event Polarity High Register (EPRH) 31 EP63 R/W-0 23 EP55 R/W-0 15 EP47 R/W-0 7 EP39 R/W-0 30 EP62 R/W-0 22 EP54 R/W-0 14 EP46 R/W-0 6 EP38 R/W-0 29 EP61 R/W-0 21 EP53 R/W-0 13 EP45 R/W-0 5 EP37 R/W-0 28 EP60 R/W-0 20 EP52 R/W-0 12 EP44 R/W-0 4 EP36 R/W-0 27 EP59 R/W-0 19 EP51 R/W-0 11 EP43 R/W-0 3 EP35 R/W-0 26 EP58 R/W-0 18 EP50 R/W-0 10 EP42 R/W-0 2 EP34 R/W-0 25 EP57 R/W-0 17 EP49 R/W-0 9 EP41 R/W-0 1 EP33 R/W-0 24 EP56 R/W-0 16 EP48 R/W-0 8 EP40 R/W-0 0 EP32 R/W-0 Legend: R/W = Read/Write. † For CSL implementation. use the notation EDMA_EPRH_EP_symval.Enhanced DMA (EDMA) Registers B. TMS320C6000 CSL Registers B-59 .33 EDMA Event Polarity High Register (EPRH) Figure B−63. EDMA Event Polarity High Register (EPRH) Field Values Bit 31−0 Field EP symval† OF(value) Value 0−FFFF FFFFh Description Event 32−63 polarity. A 32-bit unsigned value used to select a rising edge (bit value = 0) or falling edge (bit value = 1) to determine when an event is triggered on its input.

4.3 B.EMAC Control Module Registers B.1 B.1 EMAC Control Module Transfer Control Register (EWTRCTRL) The EMAC control module transfer control register (EWTRCTRL) is shown in Figure B−64 and described in Table B−69.2 B.4. EWTRCTRL should be written only when the EMAC is idle or when being held in reset using the EWCTL register.4.4 EMAC Control Module Registers Control registers for the EMAC control module are summarized in Table B−68. Table B−68. See the device-specific datasheet for the memory address of these registers.4. -n = value after reset B-60 TMS320C6000 CSL Registers . EMAC Control Module Registers Acronym EWTRCTRL EWCTL EWINTTCNT Register Name EMAC Control Module Transfer Control Register EMAC Control Module Interrupt Control Register EMAC Control Module Interrupt Timer Count Register Section B. EWTRCTRL is used to control the priority and allocation of transfer requests generated by the EMAC. EMAC Control Module Transfer Control Register (EWTRCTRL) 31 Reserved R-0 7 Reserved R-0 6 PRIORITY R/W-2h 4 3 ALLOC R/W-3h 0 8 Legend: R = Read only. Figure B−64. R/W = Read/Write.

EMAC Control Module Transfer Control Register (EWTRCTRL) Field Values Bit 31−7 6−4 field† Reserved PRIORITY symval† − Value 0 0−7h Description Reserved. 0 1h 2h 3h 4h−7h 3−0 ALLOC 0−Fh † For CSL implementation. an allocation amount of 3 is ideal. A value written to this field has no effect. Since the EMAC has only three internal FIFOs. Priority bits specify the relative priority of EMAC packet data transfers relative to other memory operations in the system. Although the default value is medium priority. since the EMAC data transfer is real time (once a packet transfer begins). Urgent priority High priority Medium priority Low priority Reserved Allocation bits specifiy the number of outstanding EMAC requests that can be pending at any given time.EMAC Control Module Registers Table B−69. The reserved bit location is always read as 0. this priority may need to be raised in some system. use the notation EMAC_EWTRCTRL_field_symval TMS320C6000 CSL Registers B-61 .

EMAC and MDIO interrupt enable bit. the software disables the INTEN bit in EWCTL. and generates a new edge that the DSP can recognize. EMAC is held in reset. This ensures that the interrupt line goes back to zero. EMAC Control Module Interrupt Control Register (EWCTL) 31 Reserved R-0 15 R-0 Legend: R = Read only. Figure B−65. 0 1 EMAC and MDIO interrupts are disabled. if the EMAC control module monitors any interrupts still pending. The software reenables the INTEN bit after clearing all the pending interrupts and before leaving the interrupt service routine. The reserved bit location is always read as 0. MDIO is held in reset.EMAC Control Module Registers B.4. EMAC reset bit. -n = value after reset 16 3 2 EMACRST R/W-0 1 MDIORST R/W-0 0 INTEN R/W-0 Table B−70. use the notation EMAC_EWCTL_field_symval B-62 TMS320C6000 CSL Registers . 0 1 MDIO is not in reset. the EMAC and MDIO interrupt is being serviced. For CSL implementation. It is expected that any time. EMAC Control Module Interrupt Control Register (EWCTL) Field Values Bit 31−3 2 field† Reserved EMACRST NO YES 1 MDIORST NO YES 0 INTEN DISABLE ENABLE † symval† − Value 0 Description Reserved.2 EMAC Control Module Interrupt Control Register (EWCTL) The EMAC control module interrupt control register (EWCTL) is shown in Figure B−65 and described in Table B−70. MDIO reset bit. EWCTL is used to enable and disable the central interrupt from the EMAC and MDIO modules and to reset both modules or either module independently. 0 1 EMAC is not in reset. EMAC and MDIO interrupts are enabled. At this point. it reasserts the interrupt line. A value written to this field has no effect. R/W = Read/Write.

A value written to this field has no effect. For CSL implementation. -n = value after reset 17 16 EWINTTCNT R/W-0 0 Table B−71.4. use the notation EMAC_EWINTTCNT_EWINTTCNT_symval TMS320C6000 CSL Registers B-63 . Figure B−66. EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) 31 Reserved R-0 Legend: R = Read only. its maximum value is 1 FFFFh (131 071). EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Values Bit 31−17 16−0 † Field Reserved EWINTTCNT symval† − Value 0 0−1 FFFFh Description Reserved. R/W = Read/Write. Interrupt timer count.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) The EMAC control module interrupt timer count register (EWINTTCNT) is shown in Figure B−66 and described in Table B−71. The counter is decremented at a frequency of CPUclock/4. A second interrupt cannot be generated until this count reaches 0.EMAC Control Module Registers B. The reserved bit location is always read as 0. EWINTTCNT is used to control the generation of back-to-back interrupts from the EMAC and MDIO modules. its default reset count is 0 (inactive). The value of this timer count is loaded into an internal counter every time interrupts are enabled using the EWCTL register.

5.5.5.12 B.18 B.5.5.24 B.5.19 B.17 B.23 B.7 Receive Unicast Set Register Receive Unicast Clear Register Receive Maximum Length Register Receive Buffer Offset Register Receive Filter Low Priority Packets Threshold Register Receive Channel 0−7 Flow Control Threshold Registers Receive Channel 0−7 Free Buffer Count Registers MAC Control Register MAC Status Register Transmit Interrupt Status (Unmasked) Register Transmit Interrupt Status (Masked) Register Transmit Interrupt Mask Set Register Transmit Interrupt Mask Clear Register MAC Input Vector Register Receive Interrupt Status (Unmasked) Register Receive Interrupt Status (Masked) Register Receive Interrupt Mask Set Register Receive Interrupt Mask Clear Register B.5.4 B.21 B.5.5.14 B.9 B.5 B. Table B−72.11 B.22 B.3 B.8 B.5.2 B.5.EMAC Module Registers B. EMAC Module Registers Acronym TXIDVER TXCONTROL TXTEARDOWN RXIDVER RXCONTROL RXTEARDOWN RXMBPENABLE RXUNICASTSET RXUNICASTCLEAR RXMAXLEN RXBUFFEROFFSET RXFILTERLOWTHRESH RXnFLOWTHRESH RXnFREEBUFFER MACCONTROL MACSTATUS TXINTSTATRAW TXINTSTATMASKED TXINTMASKSET TXINTMASKCLEAR MACINVECTOR RXINTSTATRAW RXINTSTATMASKED RXINTMASKSET RXINTMASKCLEAR Register Name Transmit Identification and Version Register Transmit Control Register Transmit Teardown Register Receive Identification and Version Register Receive Control Register Receive Teardown Register Section B.5.5.5.5.10 B.5.5.13 B.16 B.5.25 B-64 TMS320C6000 CSL Registers .6 Receive Multicast/Broadcast/Promiscuous Channel Enable Register B. See the device-specific datasheet for the memory address of these registers.5 EMAC Module Registers Control registers for the EMAC module are summarized in Table B−72.5.5.20 B.15 B.5.5.5.1 B.5.5.

5.5.5.35 B.5.5.5. EMAC Module Registers (Continued) Acronym MACINTSTATRAW MACINTSTATMASKED MACINTMASKSET MACINTMASKCLEAR MACADDRLn MACADDRM MACADDRH MACHASH1 MACHASH2 BOFFTEST TPACETEST RXPAUSE TXPAUSE TXnHDP RXnHDP TXnINTACK RXnINTACK RXGOODFRAMES RXBCASTFRAMES RXMCASTFRAMES RXPAUSEFRAMES RXCRCERRORS RXALIGNCODEERRORS RXOVERSIZED RXJABBER RXUNDERSIZED RXFRAGMENTS RXFILTERED Register Name MAC Interrupt Status (Unmasked) Register MAC Interrupt Status (Masked) Register MAC Interrupt Mask Set Register MAC Interrupt Mask Clear Register MAC Address Channel 0−7 Lower Byte Register MAC Address Middle Byte Register MAC Address High Bytes Register MAC Address Hash 1 Register MAC Address Hash 2 Register Backoff Test Register Transmit Pacing Test Register Receive Pause Timer Register Transmit Pause Timer Register Transmit Channel 0−7 DMA Head Descriptor Pointer Registers Receive Channel 0−7 DMA Head Descriptor Pointer Registers Transmit Channel 0−7 Interrupt Acknowledge Registers Receive Channel 0−7 Interrupt Acknowledge Registers Good Receive Frames Register Broadcast Receive Frames Register Multicast Receive Frames Register Pause Receive Frames Register Receive CRC Errors Register Receive Alignment/Code Errors Register Receive Oversized Frames Register Receive Jabber Frames Register Receive Undersized Frames Register Receive Frame Fragments Register Filtered Receive Frames Register Section B.43 B.5.5.5.5.38 B.43 B.5.5.5.43 B.43 B.27 B.43 B.43 B.39 B.5.30 B.43 B.43 B.5.5.5.31 B.EMAC Module Registers Table B−72.41 B.5.32 B.43 B.28 B.37 B.26 B.33 B.43 TMS320C6000 CSL Registers B-65 .29 B.5.5.5.43 B.5.5.5.5.5.36 B.40 B.5.34 B.5.42 B.

5.43 B.5.43 B.5.43 B.5.43 B.5.5.5.5.5.43 B.5.43 B.5.5.5.43 B. EMAC Module Registers (Continued) Acronym RXQOSFILTERED RXOCTETS RXSOFOVERRUNS RXMOFOVERRUNS RXDMAOVERRUNS TXGOODFRAMES TXBCASTFRAMES TXMCASTFRAMES TXPAUSEFRAMES TXDEFERRED TXCOLLISION TXSINGLECOLL TXMULTICOLL TXEXCESSIVECOLL TXLATECOLL TXUNDERRUN TXCARRIERSLOSS TXOCTETS FRAME64 FRAME65T127 FRAME128T255 FRAME256T511 FRAME512T1023 FRAME1024TUP NETOCTETS Register Name Receive QOS Filtered Frames Register Receive Octet Frames Register Receive Start of Frame Overruns Register Receive Middle of Frame Overruns Register Receive DMA Overruns Register Good Transmit Frames Register Broadcast Transmit Frames Register Multicast Transmit Frames Register Pause Transmit Frames Register Deferred Transmit Frames Register Collision Register Single Collision Transmit Frames Register Multiple Collision Transmit Frames Register Excessive Collisions Register Late Collisions Register Transmit Underrun Register Transmit Carrier Sense Errors Register Transmit Octet Frames Register Transmit and Receive 64 Octet Frames Register Transmit and Receive 65 to 127 Octet Frames Register Transmit and Receive 128 to 255 Octet Frames Register Transmit and Receive 256 to 511 Octet Frames Register Transmit and Receive 512 to 1023 Octet Frames Register Transmit and Receive 1024 or Above Octet Frames Register Network Octet Frames Register Section B.43 B.5.43 B.43 B.5.43 B.5.43 B.43 B.5.43 B.43 B.43 B.5.5.43 B.43 B.5.5.43 B.43 B-66 TMS320C6000 CSL Registers .43 B.EMAC Module Registers Table B−72.5.5.5.43 B.43 B.5.43 B.43 B.

See the device-specific datasheet for the value.1 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure B−67 and described in Table B−73. 16 8 7 TXMINORVER R-x† 0 Table B−73. EMAC Transmit major version value is the major version number.EMAC Module Registers B. Transmit minor version value is the minor version number. Figure B−67. See the device-specific datasheet for the value. use the notation EMAC_TXIDVER_field_symval TMS320C6000 CSL Registers B-67 .5. Transmit Identification and Version Register (TXIDVER) Field Values Bit 31−16 field† TXIDENT 4h 15−8 TXMAJORVER x 7−0 TXMINORVER x † symval† Value Description Transmit identification value bits. For CSL implementation. Transmit Identification and Version Register (TXIDVER) 31 TXIDENT R-0004h 15 TXMAJORVER R-x† Legend: R = Read only. -n = value after reset † See the device-specific datasheet for the default value of this field.

EMAC Module Registers B. Transmit enable bit.5. Transmit Control Register (TXCONTROL) Field Values Bit 31−1 0 Field Reserved TXEN DISABLE ENABLE † symval† − Value 0 Description Reserved. A value written to this field has no effect. For CSL implementation. -n = value after reset 1 0 TXEN R/W-0 Table B−74. 0 1 Transmit is disabled. Transmit Control Register (TXCONTROL) 31 Reserved R-0 Legend: R = Read only. Figure B−68. R/W = Read/Write. Transmit is enabled.2 Transmit Control Register (TXCONTROL) The transmit control register (TXCONTROL) is shown in Figure B−68 and described in Table B−74. The reserved bit location is always read as 0. use the notation EMAC_TXCONTROL_TXEN_symval B-68 TMS320C6000 CSL Registers .

R/W = Read/Write. Teardown transmit channel 3. use the notation EMAC_TXTEARDOWN_TXTDNCH_symval TMS320C6000 CSL Registers B-69 . Transmit Teardown Register (TXTEARDOWN) Field Values Bit 31−3 2−0 Field Reserved TXTDNCH symval† − Value 0 0−7h 0 1h 2h 3h 4h 5h 6h 7h † Description Reserved. Teardown transmit channel 1. A value written to this field has no effect. The reserved bit location is always read as 0. Transmit Teardown Register (TXTEARDOWN) 31 Reserved R-0 Legend: R = Read only.EMAC Module Registers B. Teardown transmit channel 4. Teardown transmit channel 0.5. Figure B−69.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure B−69 and described in Table B−75. Teardown transmit channel 2. For CSL implementation. Transmit teardown channel bits determine the transmit channel to be torn down. The teardown register is read as 0. Teardown transmit channel 7. -n = value after reset 3 2 R/W-0 0 TXTDNCH Table B−75. Teardown transmit channel 6. Teardown transmit channel 5.

4 Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure B−70 and described in Table B−76. 16 8 7 RXMINORVER R-x† 0 Table B−76. For CSL implementation. See the device-specific datasheet for the value. -n = value after reset † See the device-specific datasheet for the default value of this field. Receive Identification and Version Register (RXIDVER) Field Values Bit 31−16 field† RXIDENT 4h 15−8 RXMAJORVER x 7−0 RXMINORVER x † symval† Value Description Receive identification value bits. EMAC Receive major version value is the major version number. Receive Identification and Version Register (RXIDVER) 31 RXIDENT R-0004h 15 RXMAJORVER R-x† Legend: R = Read only.EMAC Module Registers B. Receive minor version value is the minor version number. use the notation EMAC_RXIDVER_field_symval B-70 TMS320C6000 CSL Registers . Figure B−70.5. See the device-specific datasheet for the value.

Receive is enabled. R/W = Read/Write. Receive DMA enable bit. The reserved bit location is always read as 0. 0 1 Receive is disabled. use the notation EMAC_RXCONTROL_RXEN_symval TMS320C6000 CSL Registers B-71 .5 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure B−71 and described in Table B−77.EMAC Module Registers B.5. Receive Control Register (RXCONTROL) Field Values Bit 31−1 0 Field Reserved RXEN DISABLE ENABLE † symval† − Value 0 Description Reserved. -n = value after reset 1 0 RXEN R/W-0 Table B−77. A value written to this field has no effect. Figure B−71. Receive Control Register (RXCONTROL) 31 Reserved R-0 Legend: R = Read only. For CSL implementation.

Teardown receive channel 1. Teardown receive channel 7. Teardown receive channel 4.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure B−72 and described in Table B−78. Receive teardown channel bits determine the receive channel to be torn down. Teardown receive channel 2. -n = value after reset 3 2 R/W-0 0 RXTDNCH Table B−78. use the notation EMAC_RXTEARDOWN_RXTDNCH_symval B-72 TMS320C6000 CSL Registers . Figure B−72.EMAC Module Registers B. The teardown register is read as 0. Teardown receive channel 0. A value written to this field has no effect. The reserved bit location is always read as 0. Teardown receive channel 5. Receive Teardown Register (RXTEARDOWN) 31 Reserved R-0 Legend: R = Read only. Teardown receive channel 3. For CSL implementation. Teardown receive channel 6.5. R/W = Read/Write. Receive Teardown Register (RXTEARDOWN) Field Values Bit 31−3 2−0 Field Reserved RXTDNCH symval† − Value 0 0−7h 0 1h 2h 3h 4h 5h 6h 7h † Description Reserved.

Pass received CRC enable bit. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Values Bit 31 30 field† Reserved RXPASSCRC DISCARD INCLUDE † symval† − Value 0 Description Reserved.EMAC Module Registers B. A value written to this field has no effect. R/W = Read/Write. -n = value after reset Table B−79. use the notation EMAC_RXMBPENABLE_field_symval TMS320C6000 CSL Registers B-73 .7 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure B−73 and described in Table B−79. The reserved bit location is always read as 0. 0 1 Received CRC is discarded for all channels and is not included in the buffer descriptor packet length field. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) 31 Reserved R-0 23 RXCSFEN R/W-0 15 Reserved R-0 7 Reserved R-0 6 30 RXPASSCRC 29 RXQOSEN R/W-0 21 RXCAFEN R/W-0 13 BROADEN R/W-0 5 MULTEN R/W-0 4 12 20 28 RXNOCHAIN 27 Reserved R-0 19 18 25 24 RXCMFEN R/W-0 16 R/W-0 22 RXCEFEN R/W-0 14 R/W-0 Reserved R-0 11 10 Reserved R-0 3 2 Reserved R-0 PROMCH R/W-0 8 BROADCH R/W-0 0 MULTCH R/W-0 Legend: R = Read only. For CSL implementation. Received CRC is transferred to memory for all channels and is included in the buffer descriptor packet length.5. Figure B−73.

Received frames can span multiple buffers. Reserved. All remaining frame data after the first buffer is discarded. Frames transferred to memory due to RXCMFEN will have the control bit set in their EOP buffer descriptor. use the notation EMAC_RXMBPENABLE_field_symval B-74 TMS320C6000 CSL Registers . A value written to this field has no effect. MAC control frames that are pause frames will be acted upon if enabled in MACCONTROL. Fragments are short frames that contain CRC/align/code errors and undersized are short frames without errors. Receive no buffer chaining bit. Receive copy short frames enable bit.EMAC Module Registers Table B−79. For CSL implementation. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Values (Continued) Bit 29 field† RXQOSEN DISABLE ENABLE 28 RXNOCHAIN DISABLE ENABLE 0 1 0 1 symval† Value Description Receive quality of service (QOS) enable bit. MAC control frames are normally acted upon (if enabled). Short frames are transferred to memory. MAC control frames are transferred to memory. Enables frames or fragments shorter than 64 bytes to be copied to memory. regardless of the value of RXCMFEN. Receive QOS is disabled. The reserved bit location is always read as 0. Receive QOS is enabled. Receive copy MAC control frames enable bit. but not copied to memory. Frames transferred to memory due to RXCSFEN will have the fragment or undersized bit set in their EOP buffer descriptor. DISABLE ENABLE 23 RXCSFEN 0 1 MAC control frames are filtered (but acted upon if enabled). Enables MAC control frames to be transferred to memory. DISABLE ENABLE † 27−25 24 Reserved RXCMFEN − 0 0 1 Short frames are filtered. Receive DMA controller transfers each frame into a single buffer regardless of the frame or buffer size.

Reserved. Select channel 6 to receive promiscuous frames. Such frames will be marked with the no_match bit in their EOP buffer descriptor. Enables frames that do not address match (includes multicast frames that do not hash match) to be transferred to the promiscuous channel selected by PROMCH bits. DISABLE ENABLE 21 RXCAFEN 0 1 Frames containing errors are filtered. Reserved. Receive promiscuous channel select bits. The appropriate error bit will be set in the frame EOP buffer descriptor. The reserved bit location is always read as 0. Select channel 4 to receive promiscuous frames. Select channel 5 to receive promiscuous frames. Enables frames containing errors to be transferred to memory. Frames containing errors are transferred to memory. use the notation EMAC_RXMBPENABLE_field_symval TMS320C6000 CSL Registers B-75 . Receive copy all frames enable bit. Select channel 3 to receive promiscuous frames. Select channel 0 to receive promiscuous frames. DISABLE ENABLE 0 1 Frames that do not address match (includes multicast frames that do not hash match) are transferred to the promiscuous channel selected by PROMCH bits. Select channel 1 to receive promiscuous frames. The reserved bit location is always read as 0.EMAC Module Registers Table B−79. A value written to this field has no effect. A value written to this field has no effect. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Values (Continued) Bit 22 field† RXCEFEN symval† Value Description Receive copy error frames enable bit. 20−19 18−16 Reserved PROMCH − 0 0−7h 0 1h 2h 3h 4h 5h 6h 7h 15−14 † Reserved − 0 For CSL implementation. Select channel 2 to receive promiscuous frames. Select channel 7 to receive promiscuous frames.

DISABLE ENABLE † 0 1h 2h 3h 4h 5h 6h 7h 7−6 5 Reserved MULTEN − 0 0 1 Multicast (group addressed) frames are filtered. A value written to this field has no effect.EMAC Module Registers Table B−79. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Values (Continued) Bit 13 field† BROADEN symval† Value Description Receive broadcast enable bit. A value written to this field has no effect. Broadcast frames are copied to the channel selected by BROADCH bits. For CSL implementation. Selects the receive channel for reception of all broadcast frames when enabled by BROADEN bit. Receive broadcast channel select bits. Reserved. Select channel 7 to receive broadcast frames. Receive multicast enable bit. Enable received broadcast frames to be copied to the channel selected by BROADCH bits. Select channel 5 to receive broadcast frames. Enable received hash matching multicast frames to be copied to the channel selected by MULTCH bits. Reserved. Multicast frames are copied to the channel selected by MULTCH bits. Select channel 6 to receive broadcast frames. Select channel 3 to receive broadcast frames. The reserved bit location is always read as 0. Select channel 1 to receive broadcast frames. Select channel 0 to receive broadcast frames. Select channel 2 to receive broadcast frames. The reserved bit location is always read as 0. DISABLE ENABLE 12−11 10−8 Reserved BROADCH − 0 1 0 0−7h Broadcast frames are filtered. Select channel 4 to receive broadcast frames. use the notation EMAC_RXMBPENABLE_field_symval B-76 TMS320C6000 CSL Registers .

Select channel 6 to receive hash matching multicast frames. Select channel 4 to receive hash matching multicast frames. Receive multicast channel select bits selects the receive channel for reception of all hash matching multicast frames when enabled by MULTEN bit. Select channel 5 to receive hash matching multicast frames. use the notation EMAC_RXMBPENABLE_field_symval TMS320C6000 CSL Registers B-77 . Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Values (Continued) Bit 4−3 2−0 field† Reserved MULTCH symval† − Value 0 0−7h Description Reserved. Select channel 2 to receive hash matching multicast frames. Select channel 3 to receive hash matching multicast frames. A value written to this field has no effect.EMAC Module Registers Table B−79. Select channel 1 to receive hash matching multicast frames. Select channel 0 to receive hash matching multicast frames. The reserved bit location is always read as 0. 0 1h 2h 3h 4h 5h 6h 7h † For CSL implementation. Select channel 7 to receive hash matching multicast frames.

regardless of the setting of the corresponding bit in RXUNICASTCLEAR. For CSL implementation. Figure B−74. A value written to this field has no effect. Receive channel 7 unicast enable set bit. a write of 0 has no effect. Receive Unicast Set Register (RXUNICASTSET) Field Values Bit 31−8 7 field† Reserved RXCH7SET 0 1 6 RXCH6SET 0 1 † symval† − Value 0 Description Reserved. Receive channel 6 unicast enable set bit. Write 1 to set the enable. write of 0 has no effect. use the notation EMAC_RXUNICASTSET_field_symval B-78 TMS320C6000 CSL Registers . Each unicast channel is enabled by a write to the MACADDRH. Receive Unicast Set Register (RXUNICASTSET) 31 Reserved R-0 7 RXCH7SET R/WS-0 6 RXCH6SET R/WS-0 5 R/WS-0 4 R/WS-0 3 RXCH3SET R/WS-0 2 RXCH2SET R/WS-0 1 R/WS-0 0 R/WS-0 8 RXCH5SET RXCH4SET RXCH1SET RXCH0SET Legend: R = Read only. No effect. if the corresponding bit in RXUNICASTCLEAR is set. Sets receive channel 6 unicast enable. Reading the RXUNICASTSET address returns the value of the unicast enable register after gating with the MAC address logic.5. WS = Write 1 to set.EMAC Module Registers B. Write 1 to set the enable. Sets receive channel 7 unicast enable. a write of 0 has no effect. No effect.8 Receive Unicast Set Register (RXUNICASTSET) The receive unicast set register (RXUNICASTSET) is shown in Figure B−74 and described in Table B−80. Reading the RXUNICASTCLEAR address returns the actual value of the unicast enable register. Each unicast channel is disabled by a write to the corresponding MACADDRLn. -n = value after reset Table B−80. The reserved bit location is always read as 0.

a write of 0 has no effect. Sets receive channel 3 unicast enable. a write of 0 has no effect. Write 1 to set the enable. No effect. a write of 0 has no effect. No effect. No effect. a write of 0 has no effect. a write of 0 has no effect. Receive Unicast Set Register (RXUNICASTSET) Field Values (Continued) Bit 5 field† RXCH5SET 0 1 4 RXCH4SET 0 1 3 RXCH3SET 0 1 2 RXCH2SET 0 1 1 RXCH1SET 0 1 0 RXCH0SET 0 1 † symval† Value Description Receive channel 5 unicast enable set bit. No effect. Write 1 to set the enable. For CSL implementation. Write 1 to set the enable. Write 1 to set the enable. Sets receive channel 2 unicast enable. Receive channel 0 unicast enable set bit. Sets receive channel 4 unicast enable. Sets receive channel 1 unicast enable. Receive channel 1 unicast enable set bit. use the notation EMAC_RXUNICASTSET_field_symval TMS320C6000 CSL Registers B-79 . Sets receive channel 0 unicast enable.EMAC Module Registers Table B−80. Receive channel 4 unicast enable set bit. Sets receive channel 5 unicast enable. a write of 0 has no effect. No effect. No effect. Write 1 to set the enable. Receive channel 3 unicast enable set bit. Write 1 to set the enable. Receive channel 2 unicast enable set bit.

The reserved bit location is always read as 0. A value written to this field has no effect. Reading the RXUNICASTSET address returns the value of the unicast enable register after gating with the MAC address logic. a write of 0 has no effect. Each unicast channel is disabled by a write to the corresponding MACADDRLn. -n = value after reset Table B−81. Receive channel 7 unicast enable clear bit. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 Reserved R-0 7 R/WC-0 6 R/WC-0 5 R/WC-0 4 R/WC-0 3 R/WC-0 2 R/WC-0 1 R/WC-0 0 R/WC-0 8 RXCH7CLR RXCH6CLR RXCH5CLR RXCH4CLR RXCH3CLR RXCH2CLR RXCH1CLR RXCH0CLR Legend: R = Read only. Reading the RXUNICASTCLEAR address returns the actual value of the unicast enable register. Write 1 to clear the enable. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Values Bit 31−8 7 field† Reserved RXCH7CLR 0 1 6 RXCH6CLR 0 1 † symval† − Value 0 Description Reserved. a write of 0 has no effect. write of 0 has no effect. WC = Write 1 to clear. Clears receive channel 7 unicast enable. No effect. Write 1 to clear the enable.5.EMAC Module Registers B. regardless of the setting of the corresponding bit in RXUNICASTCLEAR. Figure B−75. For CSL implementation. No effect. use the notation EMAC_RXUNICASTCLEAR_field_symval B-80 TMS320C6000 CSL Registers . if the corresponding bit in RXUNICASTCLEAR is set.9 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure B−75 and described in Table B−81. Clears receive channel 6 unicast enable. Receive channel 6 unicast enable clear bit. Each unicast channel is enabled by a write to the MACADDRH.

Clears receive channel 3 unicast enable. Clears receive channel 1 unicast enable. Receive channel 4 unicast enable clear bit.EMAC Module Registers Table B−81. Write 1 to clear the enable. Write 1 to clear the enable. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Values (Continued) Bit 5 field† RXCH5CLR 0 1 4 RXCH4CLR 0 1 3 RXCH3CLR 0 1 2 RXCH2CLR 0 1 1 RXCH1CLR 0 1 0 RXCH0CLR 0 1 † symval† Value Description Receive channel 5 unicast enable clear bit. use the notation EMAC_RXUNICASTCLEAR_field_symval TMS320C6000 CSL Registers B-81 . No effect. No effect. Write 1 to clear the enable. a write of 0 has no effect. No effect. Clears receive channel 2 unicast enable. Clears receive channel 0 unicast enable. a write of 0 has no effect. Clears receive channel 5 unicast enable. No effect. Write 1 to clear the enable. a write of 0 has no effect. Receive channel 1 unicast enable clear bit. a write of 0 has no effect. a write of 0 has no effect. Clears receive channel 4 unicast enable. Receive channel 3 unicast enable clear bit. a write of 0 has no effect. Receive channel 0 unicast enable clear bit. No effect. Receive channel 2 unicast enable clear bit. Write 1 to clear the enable. Write 1 to clear the enable. No effect. For CSL implementation.

use the notation EMAC_RXMAXLEN_RXMAXLEN_symval B-82 TMS320C6000 CSL Registers . Received maximum frame length bits determine the maximum length of a received frame. A value written to this field has no effect. -n = value after reset 16 15 RXMAXLEN R/W-5EEh 0 Table B−82. R/W = Read/Write. Receive Maximum Length Register (RXMAXLEN) 31 Reserved R-0 Legend: R = Read only. Frames with byte counts greater than RXMAXLEN are long frames.5.10 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure B−76 and described in Table B−82. Figure B−76. The reset value is 5EEh (1518). Receive Maximum Length Register (RXMAXLEN) Field Values Bit 31−16 15−0 Field Reserved RXMAXLEN symval† − Value 0 0−FFFFh Description Reserved. Long frames with CRC. code. † For CSL implementation.EMAC Module Registers B. Long frames with no errors are oversized frames. The reserved bit location is always read as 0. or alignment error are jabber frames.

5. R/W = Read/Write. A value of 0 indicates that there are no unused bytes at the beginning of the data and that valid data begins on the first byte of the buffer. Figure B−77. A value of Fh indicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels. Receive Buffer Offset Register (RXBUFFEROFFSET) 31 Reserved R-0 Legend: R = Read only. The reserved bit location is always read as 0. A value written to this field has no effect. Receive buffer offset bits are written by the EMAC into each frame SOP buffer descriptor Buffer Offset field. The frame data begins after the BUFFEROFFSET value of bytes. use the notation EMAC_RXBUFFEROFFSET_BUFFEROFFSET_symval TMS320C6000 CSL Registers B-83 . -n = value after reset 16 15 BUFFEROFFSET R/W-0 0 Table B−83. † For CSL implementation.11 Receive Buffer Offset Register (RXBUFFEROFFSET) The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure B−77 and described in Table B−83. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Values Bit 31−16 15−0 Field Reserved BUFFEROFFSET symval† − Value 0 0−FFFFh Description Reserved.EMAC Module Registers B.

† For CSL implementation.12 Receive Filter Low Priority Packets Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority packets threshold register (RXFILTERLOWTHRESH) is shown in Figure B−78 and described in Table B−84. R/W = Read/Write. 0−FFh Receive filter low threshold bits contain the free buffer count threshold value for filtering low priority incoming frames. A value written to this field has no effect. Receive Filter Low Priority Packets Threshold Register (RXFILTERLOWTHRESH) 31 Reserved R-0 15 Reserved R-0 Legend: R = Read only. The reserved bit location is always read as 0. -n = value after reset 16 8 7 FILTERTHRESH R/W-0 0 Table B−84. This field should remain zero. Figure B−78. if no filtering is desired.5. Receive Filter Low Priority Packets Threshold Register (RXFILTERLOWTHRESH) Field Values Bit 31−8 7−0 Field Reserved FILTERTHRESH symval† − Value 0 Description Reserved.EMAC Module Registers B. use the notation EMAC_RXFILTERLOWTHRESH_FILTERTHRESH_symval B-84 TMS320C6000 CSL Registers .

For CSL implementation.13 Receive Channel 0−7 Flow Control Threshold Registers (RXnFLOWTHRESH) The receive channel n flow control threshold registers (RXnFLOWTHRESH) is shown in Figure B−79 and described in Table B−85. Receive Channel n Flow Control Threshold Registers (RXnFLOWTHRESH) Field Values Bit 31−8 7−0 † Field Reserved FLOWTHRESH symval† − Value 0 Description Reserved.EMAC Module Registers B. use the notation EMAC_RXnFLOWTHRESH_FLOWTHRESH_symval TMS320C6000 CSL Registers B-85 . The reserved bit location is always read as 0. Receive Channel n Flow Control Threshold Registers (RXnFLOWTHRESH) 31 Reserved R-0 15 Reserved R-0 Legend: R = Read only. R/W = Read/Write. A value written to this field has no effect.5. 0−FFh Receive flow threshold bits contain the threshold value for issuing flow control on incoming frames (when enabled). -n = value after reset 16 8 7 FLOWTHRESH R/W-0 0 Table B−85. Figure B−79.

The reserved bit location is always read as 0. R/W = Read/Write. The host must write this field with the number of buffers that have been freed due to host processing. The RXnFLOWTHRESH value is compared with this field to determine if receive flow control should be issued against incoming packets (if enabled). Receive Channel n Free Buffer Count Registers (RXnFREEBUFFER) 31 Reserved R-0 Legend: R = Read only. the host must initialize this field to the number of available buffers (one register per channel). The EMAC decrements (by the number of buffers in the received frame) the associated channel register for each received frame. If hardware flow control or QOS is used. Receive Channel n Free Buffer Count Registers (RXnFREEBUFFER) Field Values Bit 31−16 15−0 Field Reserved FREEBUF symval† − Value 0 0−FFFFh Description Reserved. This is a write-to-increment field. Receive free buffer count bits contain the count of free buffers available.EMAC Module Registers B. use the notation EMAC_RXnFREEBUFFER_FREEBUF_symval B-86 TMS320C6000 CSL Registers . † For CSL implementation. The RXFILTERLOWTHRESH value is compared with this field to determine if low priority frames should be filtered. -n = value after reset 16 15 FREEBUF R/W-0 0 Table B−86. A value written to this field has no effect. Figure B−80.14 Receive Channel 0−7 Free Buffer Count Registers (RXnFREEBUFFER) The receive channel n free buffer count registers (RXnFREEBUFFER) is shown in Figure B−80 and described in Table B−86.5. This field rolls over to zero on overflow. This is a write-to-increment field.

The queue uses a fixed-priority (channel 7 highest priority) scheme to select the next channel for transmission. Transmit pacing is enabled. R/W = Read/Write. DISABLE ENABLE † 8−7 6 Reserved TXPACE − 0 0 1 Transmit pacing is disabled. Transmit queue priority type bit. The reserved bit location is always read as 0. A value written to this field has no effect. -n = value after reset Table B−87. The reserved bit location is always read as 0. The queue uses a round-robin scheme to select the next channel for transmission. Reserved. A value written to this field has no effect. MAC Control Register (MACCONTROL) 31 Reserved R-0 15 Reserved R-0 7 Reserved R-0 6 TXPACE R/W-0 5 MIIEN R/W-0 4 TXFLOWEN 16 10 9 TXPTYPE R/W-0 8 Reserved R-0 0 FULLDUPLEX 3 RXFLOWEN 2 MTEST R/W-0 1 LOOPBACK R/W-0 R/W-0 R/W-0 R/W-0 Legend: R = Read only. MAC Control Register (MACCONTROL) Field Values Bit 31−10 9 field† Reserved TXPTYPE RROBIN CHANNELPRI 0 1 symval† − Value 0 Description Reserved. Transmit pacing enable bit.EMAC Module Registers B. For CSL implementation. Figure B−81. use the notation EMAC_MACCONTROL_field_symval TMS320C6000 CSL Registers B-87 .15 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure B−81 and described in Table B−87.5.

Half-duplex mode: collisions are initiated when receive flow control is triggered. Loopback mode is enabled. MAC Control Register (MACCONTROL) Field Values (Continued) Bit 5 field† MIIEN DISABLE ENABLE 4 TXFLOWEN 0 1 symval† Value Description MII enable bit. Full-duplex mode: outgoing pause frames are sent when receive flow control is triggered. MII receive and transmit are enabled. RXPAUSE. Loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. For CSL implementation. Full-duplex mode: no outgoing pause frames are sent. Half-duplex mode: no flow control generated collisions are sent. use the notation EMAC_MACCONTROL_field_symval B-88 TMS320C6000 CSL Registers . Full-duplex mode: incoming pause frames are not acted upon. RXPAUSE. Manufacturing test mode bit. Transmit flow control enable bit determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode. DISABLE ENABLE 1 LOOPBACK 0 1 Writes to the BOFFTEST. Receive flow control enable bit. DISABLE ENABLE 3 RXFLOWEN DISABLE 0 0 1 Transmit flow control is disabled.EMAC Module Registers Table B−87. Full-duplex mode: incoming pause frames are acted upon. The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory. and TXPAUSE registers are enabled. Receive flow control is disabled. Receive flow control is enabled. DISABLE ENABLE † ENABLE 1 2 MTEST 0 1 Loopback mode is disabled. Writes to the BOFFTEST. Loopback mode enable bit. The loopback bit should be changed only when MIIEN bit is deasserted. and TXPAUSE registers are disabled. MII receive and transmit are disabled (state machine reset). regardless of this bit setting. Transmit flow control is enabled.

MAC Status Register (MACSTATUS) 31 Reserved R-0 23 TXERRCODE R-0 15 RXERRCODE R-0 7 Reserved R-0 Legend: R = Read only. -n = value after reset 24 20 19 Reserved R-0 18 TXERRCH R-0 10 RXERRCH R-0 3 2 RXQOSACT 16 12 11 Reserved R-0 8 1 RXFLOWACT 0 TXFLOWACT R-0 R-0 R-0 TMS320C6000 CSL Registers B-89 . use the notation EMAC_MACCONTROL_field_symval B.5.EMAC Module Registers Table B−87. Full-duplex mode is enabled. For CSL implementation. 0 1 Half-duplex mode is enabled. Figure B−82. MAC Control Register (MACCONTROL) Field Values (Continued) Bit 0 field† FULLDUPLEX DISABLE ENABLE † symval† Value Description Full-duplex mode enable bit.16 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure B−82 and described in Table B−88.

The host error occurred on transmit channel 1. The reserved bit location is always read as 0. The host error occurred on transmit channel 2. MAC Status Register (MACSTATUS) Field Values Bit 31−24 23−20 field† Reserved TXERRCODE symval† − Value 0 0−Fh Description Reserved. The host should read this field after a host error interrupt (HOSTERRINT) to determine the error. The host error occurred on transmit channel 7. A value written to this field has no effect. The host error occurred on transmit channel 6.EMAC Module Registers Table B−88. The host error occurred on transmit channel 3. No error SOP error Ownership bit is not set in SOP buffer Zero next buffer descriptor pointer is without EOP Zero buffer pointer Zero buffer length Packet length error NOERROR SOPERROR OWNERSHIP NOEOP NULLPTR NULLEN LENRRROR − 19 18−16 Reserved TXERRCH − 0 1h 2h 3h 4h 5h 6h 7h−Fh Reserved 0 0−7h Reserved. The host error occurred on transmit channel 4. Host error interrupts require hardware reset in order to recover. The host error occurred on transmit channel 5. Transmit host error channel bits indicate which transmit channel the host error occurred on. The host error occurred on transmit channel 0. The reserved bit location is always read as 0. DEFAULT 0 1h 2h 3h 4h 5h 6h 7h † For CSL implementation. use the notation EMAC_MACSTATUS_field_symval B-90 TMS320C6000 CSL Registers . Transmit host error code bits indicate EMAC detected transmit DMA related host errors. This field is cleared to 0 on a host read. A value written to this field has no effect.

A value written to this field has no effect. The host error occurred on receive channel 7.EMAC Module Registers Table B−88. The host error occurred on receive channel 1. A value written to this field has no effect. MAC Status Register (MACSTATUS) Field Values (Continued) Bit 15−12 field† RXERRCODE symval† Value 0−Fh Description Receive host error code bits indicate EMAC detected receive DMA related host errors. The host error occurred on receive channel 5. Reserved. The host error occurred on receive channel 2. The host error occurred on receive channel 3. The host error occurred on receive channel 0. Host error interrupts require hardware reset in order to recover. DEFAULT 0 1h 2h 3h 4h 5h 6h 7h 7−3 † Reserved − 0 For CSL implementation. The host error occurred on receive channel 4. use the notation EMAC_MACSTATUS_field_symval TMS320C6000 CSL Registers B-91 . No error SOP error Ownership bit is not set in input buffer Zero next buffer descriptor pointer is without eop Zero buffer pointer Zero buffer length Packet length error NOERROR SOPERROR OWNERSHIP NOEOP NULLPTR NULLEN LENRRROR − 11 10−8 Reserved RXERRCH − 0 1h 2h 3h 4h 5h 6h 7h−Fh Reserved 0 0−7h Reserved. The reserved bit location is always read as 0. The host should read this field after a host error interrupt (HOSTERRINT) to determine the error. This field is cleared to 0 on a host read. The reserved bit location is always read as 0. Receive host error channel bits indicate which receive channel the host error occurred on. The host error occurred on receive channel 6.

DEFAULT 0 1 At least one channel freebuffer count (RXnFREEBUFFER) value is less than or equal to the channel’s corresponding RXnFLOWTHRESH value. Receive quality of service is disabled. Receive quality of service is enabled and that at least one channel freebuffer count (RXnFREEBUFFER) value is less than or equal to the RXFILTERLOWTHRESH value. MAC Status Register (MACSTATUS) Field Values (Continued) Bit 2 field† RXQOSACT DEFAULT 0 1 symval† Value Description Receive quality of service (QOS) active bit. 1 RXFLOWACT 0 TXFLOWACT † For CSL implementation.EMAC Module Registers Table B−88. DEFAULT 0 1 The pause time period is being observed for a received pause frame. Transmit flow control active bit. use the notation EMAC_MACSTATUS_field_symval B-92 TMS320C6000 CSL Registers . Receive flow control active bit. No new transmissions begin while this bit is asserted except for the transmission of pause frames. Any transmission in progress when this bit is asserted will complete.

-n = value after reset Table B−89. A value written to this field has no effect. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Values Bit 31−8 7 6 5 4 3 2 1 0 † field† Reserved TX7PEND TX6PEND TX5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND symval† − Value 0 Description Reserved. Figure B−83.EMAC Module Registers B.5. use the notation EMAC_TXINTSTATRAW_field_symval TMS320C6000 CSL Registers B-93 . TX7PEND raw interrupt read (before mask) TX6PEND raw interrupt read (before mask) TX5PEND raw interrupt read (before mask) TX4PEND raw interrupt read (before mask) TX3PEND raw interrupt read (before mask) TX2PEND raw interrupt read (before mask) TX1PEND raw interrupt read (before mask) TX0PEND raw interrupt read (before mask) For CSL implementation. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) 31 Reserved R-0 7 TX7PEND R-0 6 TX6PEND R-0 5 TX5PEND R-0 4 TX4PEND R-0 3 TX3PEND R-0 2 TX2PEND R-0 1 TX1PEND R-0 0 TX0PEND R-0 8 Legend: R = Read only. The reserved bit location is always read as 0.17 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure B−83 and described in Table B−89.

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Values Bit 31−8 7 6 5 4 3 2 1 0 † field† Reserved TX7PEND TX6PEND TX5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND symval† − Value 0 Description Reserved. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) 31 Reserved R-0 7 TX7PEND R-0 6 TX6PEND R-0 5 TX5PEND R-0 4 TX4PEND R-0 3 TX3PEND R-0 2 TX2PEND R-0 1 TX1PEND R-0 0 TX0PEND R-0 8 Legend: R = Read only. A value written to this field has no effect.5.18 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure B−84 and described in Table B−90. The reserved bit location is always read as 0. -n = value after reset Table B−90. TX7PEND masked interrupt read TX6PEND masked interrupt read TX5PEND masked interrupt read TX4PEND masked interrupt read TX3PEND masked interrupt read TX2PEND masked interrupt read TX1PEND masked interrupt read TX0PEND masked interrupt read For CSL implementation. Figure B−84.EMAC Module Registers B. use the notation EMAC_TXINTSTATMASKED_field_symval B-94 TMS320C6000 CSL Registers .

Transmit channel 6 interrupt is enabled. Write 1 to enable interrupt. write of 0 has no effect.EMAC Module Registers B.19 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure B−85 and described in Table B−91. a write of 0 has no effect. a write of 0 has no effect.5. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 Reserved R-0 7 TX7MASK R/WS-0 6 TX6MASK R/WS-0 5 TX5MASK R/WS-0 4 TX4MASK R/WS-0 3 TX3MASK R/WS-0 2 TX2MASK R/WS-0 1 TX1MASK R/WS-0 0 TX0MASK R/WS-0 8 Legend: R = Read only. A value written to this field has no effect. Transmit channel 7 interrupt mask set bit. Transmit channel 6 interrupt mask set bit. For CSL implementation. No effect. Transmit channel 7 interrupt is enabled. Transmit channel 5 interrupt is enabled. The reserved bit location is always read as 0. -n = value after reset Table B−91. No effect. Write 1 to enable interrupt. Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Values Bit 31−8 7 field† Reserved TX7MASK 0 1 6 TX6MASK 0 1 5 TX5MASK 0 1 † symval† − Value 0 Description Reserved. use the notation EMAC_TXINTMASKSET_field_symval TMS320C6000 CSL Registers B-95 . No effect. a write of 0 has no effect. Figure B−85. WS = Write 1 to set.

a write of 0 has no effect. No effect. a write of 0 has no effect. a write of 0 has no effect. No effect. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Values (Continued) Bit 4 field† TX4MASK 0 1 3 TX3MASK 0 1 2 TX2MASK 0 1 1 TX1MASK 0 1 0 TX0MASK 0 1 † symval† Value Description Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt. Transmit channel 3 interrupt is enabled. Write 1 to enable interrupt.EMAC Module Registers Table B−91. Transmit channel 1 interrupt is enabled. Transmit channel 0 interrupt is enabled. Transmit channel 3 interrupt mask set bit. a write of 0 has no effect. Write 1 to enable interrupt. Write 1 to enable interrupt. No effect. Transmit channel 4 interrupt is enabled. a write of 0 has no effect. Transmit channel 2 interrupt is enabled. For CSL implementation. Transmit channel 2 interrupt mask set bit. use the notation EMAC_TXINTMASKSET_field_symval B-96 TMS320C6000 CSL Registers . Write 1 to enable interrupt. Transmit channel 0 interrupt mask set bit. Transmit channel 1 interrupt mask set bit. No effect. No effect.

5. use the notation EMAC_TXINTMASKCLEAR_field_symval TMS320C6000 CSL Registers B-97 . Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) 31 Reserved R-0 7 TX7MASK R/WC-0 6 TX6MASK R/WC-0 5 TX5MASK R/WC-0 4 TX4MASK R/WC-0 3 TX3MASK R/WC-0 2 TX2MASK R/WC-0 1 TX1MASK R/WC-0 0 TX0MASK R/WC-0 8 Legend: R = Read only. a write of 0 has no effect. Transmit channel 5 interrupt mask clear bit. No effect. a write of 0 has no effect. Transmit channel 7 interrupt mask clear bit.EMAC Module Registers B. -n = value after reset Table B−92. A value written to this field has no effect. Transmit channel 5 interrupt is disabled. Transmit channel 6 interrupt is disabled. No effect. WC = Write 1 to clear. write of 0 has no effect. a write of 0 has no effect. Write 1 to disable interrupt. The reserved bit location is always read as 0. Transmit channel 7 interrupt is disabled. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Values Bit 31−8 7 field† Reserved TX7MASK 0 1 6 TX6MASK 0 1 5 TX5MASK 0 1 † symval† − Value 0 Description Reserved.20 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure B−86 and described in Table B−92. Transmit channel 6 interrupt mask clear bit. Figure B−86. For CSL implementation. Write 1 to disable interrupt. No effect. Write 1 to disable interrupt.

No effect. a write of 0 has no effect. Transmit channel 0 interrupt is disabled. Write 1 to disable interrupt. a write of 0 has no effect. use the notation EMAC_TXINTMASKCLEAR_field_symval B-98 TMS320C6000 CSL Registers . For CSL implementation. No effect. No effect.EMAC Module Registers Table B−92. No effect. Transmit channel 3 interrupt is disabled. Transmit channel 4 interrupt is disabled. Write 1 to disable interrupt. Transmit channel 0 interrupt mask clear bit. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Values (Continued) Bit 4 field† TX4MASK 0 1 3 TX3MASK 0 1 2 TX2MASK 0 1 1 TX1MASK 0 1 0 TX0MASK 0 1 † symval† Value Description Transmit channel 4 interrupt mask clear bit. Transmit channel 2 interrupt is disabled. Write 1 to disable interrupt. No effect. a write of 0 has no effect. a write of 0 has no effect. Write 1 to disable interrupt. Transmit channel 1 interrupt is disabled. a write of 0 has no effect. Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt. Transmit channel 3 interrupt mask clear bit. Transmit channel 2 interrupt mask clear bit.

The reserved bit location is always read as 0. MDIO module link change interrupt (LINKINT) pending status bit. A value written to this field has no effect. you can monitor the status of all device interrupts.5.EMAC Module Registers B. Bit 8 is receive channel 0. MAC Input Vector Register (MACINVECTOR) Field Values Bit 31 30 29−18 17 16 15−8 7−0 † field† USERINT LINKINT Reserved HOSTPEND STATPEND RXPEND TXPEND symval† Value Description MDIO module user interrupt (USERINT) pending status bit. -n = value after reset 30 LINKINT R-0 29 Reserved R-0 8 7 18 17 R-0 16 R-0 0 HOSTPEND STATPEND TXPEND R-0 Table B−93. Bit 0 is transmit channel 0. MACINVECTOR contains the current interrupt status of all individual EMAC and MDIO module interrupts. Figure B−87. EMAC module host error interrupt pending (HOSTPEND) status bit. use the notation EMAC_MACINVECTOR_field_symval TMS320C6000 CSL Registers B-99 . − 0 Reserved. With a single MACINVECTOR read. 0−FFh Transmit channel 0−7 interrupt pending (TXPEND) status bit.21 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure B−87 and described in Table B−93. EMAC module statistics interrupt pending (STATPEND) status bit. 0−FFh Receive channel 0−7 interrupt pending (RXPEND) status bit. MAC Input Vector Register (MACINVECTOR) 31 USERINT R-0 15 RXPEND R-0 Legend: R = Read only. For CSL implementation.

use the notation EMAC_RXINTSTATRAW_field_symval B-100 TMS320C6000 CSL Registers . A value written to this field has no effect. -n = value after reset Table B−94. The reserved bit location is always read as 0. RX7PEND raw interrupt read (before mask) RX6PEND raw interrupt read (before mask) RX5PEND raw interrupt read (before mask) RX4PEND raw interrupt read (before mask) RX3PEND raw interrupt read (before mask) RX2PEND raw interrupt read (before mask) RX1PEND raw interrupt read (before mask) RX0PEND raw interrupt read (before mask) For CSL implementation. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) 31 Reserved R-0 7 RX7PEND R-0 6 RX6PEND R-0 5 RX5PEND R-0 4 RX4PEND R-0 3 RX3PEND R-0 2 RX2PEND R-0 1 RX1PEND R-0 0 RX0PEND R-0 8 Legend: R = Read only. Figure B−88.EMAC Module Registers B. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Values Bit 31−8 7 6 5 4 3 2 1 0 † field† Reserved RX7PEND RX6PEND RX5PEND RX4PEND RX3PEND RX2PEND RX1PEND RX0PEND symval† − Value 0 Description Reserved.22 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure B−88 and described in Table B−94.5.

Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) 31 Reserved R-0 7 RX7PEND R-0 6 RX6PEND R-0 5 RX5PEND R-0 4 RX4PEND R-0 3 RX3PEND R-0 2 RX2PEND R-0 1 RX1PEND R-0 0 RX0PEND R-0 8 Legend: R = Read only.5. RX7PEND masked interrupt read RX6PEND masked interrupt read RX5PEND masked interrupt read RX4PEND masked interrupt read RX3PEND masked interrupt read RX2PEND masked interrupt read RX1PEND masked interrupt read RX0PEND masked interrupt read For CSL implementation. The reserved bit location is always read as 0.EMAC Module Registers B. A value written to this field has no effect. use the notation EMAC_RXINTSTATMASKED_field_symval TMS320C6000 CSL Registers B-101 . -n = value after reset Table B−95. Figure B−89. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Values Bit 31−8 7 6 5 4 3 2 1 0 † field† Reserved RX7PEND RX6PEND RX5PEND RX4PEND RX3PEND RX2PEND RX1PEND RX0PEND symval† − Value 0 Description Reserved.23 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure B−89 and described in Table B−95.

24 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure B−90 and described in Table B−96. write of 0 has no effect. Figure B−90. a write of 0 has no effect. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 Reserved R-0 7 RX7MASK R/WS-0 6 RX6MASK R/WS-0 5 RX5MASK R/WS-0 4 RX4MASK R/WS-0 3 RX3MASK R/WS-0 2 RX2MASK R/WS-0 1 RX1MASK R/WS-0 0 RX0MASK R/WS-0 8 Legend: R = Read only. Receive channel 5 interrupt is enabled. No effect. Receive channel 6 interrupt mask set bit. Write 1 to enable interrupt. Receive channel 7 interrupt mask set bit. Receive channel 7 interrupt is enabled. The reserved bit location is always read as 0. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Values Bit 31−8 7 field† Reserved RX7MASK 0 1 6 RX6MASK 0 1 5 RX5MASK 0 1 † symval† − Value 0 Description Reserved. Receive channel 5 interrupt mask set bit.EMAC Module Registers B. A value written to this field has no effect. a write of 0 has no effect. a write of 0 has no effect. No effect. WS = Write 1 to set. Write 1 to enable interrupt. Receive channel 6 interrupt is enabled. No effect. use the notation EMAC_RXINTMASKSET_field_symval B-102 TMS320C6000 CSL Registers . For CSL implementation. -n = value after reset Table B−96.5. Write 1 to enable interrupt.

No effect. Receive channel 2 interrupt is enabled. Write 1 to enable interrupt. use the notation EMAC_RXINTMASKSET_field_symval TMS320C6000 CSL Registers B-103 . Write 1 to enable interrupt. Receive channel 4 interrupt is enabled.EMAC Module Registers Table B−96. No effect. Receive channel 1 interrupt is enabled. Receive channel 2 interrupt mask set bit. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Values (Continued) Bit 4 field† RX4MASK 0 1 3 RX3MASK 0 1 2 RX2MASK 0 1 1 RX1MASK 0 1 0 RX0MASK 0 1 † symval† Value Description Receive channel 4 interrupt mask set bit. Receive channel 0 interrupt is enabled. For CSL implementation. Write 1 to enable interrupt. Receive channel 1 interrupt mask set bit. Receive channel 3 interrupt is enabled. Receive channel 0 interrupt mask set bit. a write of 0 has no effect. No effect. a write of 0 has no effect. Write 1 to enable interrupt. a write of 0 has no effect. No effect. a write of 0 has no effect. Write 1 to enable interrupt. Receive channel 3 interrupt mask set bit. a write of 0 has no effect. No effect.

For CSL implementation. No effect.25 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure B−91 and described in Table B−97. Receive channel 7 interrupt mask clear bit. WC = Write 1 to clear. No effect. No effect. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Values Bit 31−8 7 field† Reserved RX7MASK 0 1 6 RX6MASK 0 1 5 RX5MASK 0 1 † symval† − Value 0 Description Reserved. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 Reserved R-0 7 RX7MASK R/WC-0 6 RX6MASK R/WC-0 5 RX5MASK R/WC-0 4 RX4MASK R/WC-0 3 RX3MASK R/WC-0 2 RX2MASK R/WC-0 1 RX1MASK R/WC-0 0 RX0MASK R/WC-0 8 Legend: R = Read only. Receive channel 5 interrupt mask clear bit. a write of 0 has no effect. Write 1 to disable interrupt. Write 1 to disable interrupt.5. use the notation EMAC_RXINTMASKCLEAR_field_symval B-104 TMS320C6000 CSL Registers . a write of 0 has no effect. write of 0 has no effect. Receive channel 6 interrupt mask clear bit.EMAC Module Registers B. -n = value after reset Table B−97. Receive channel 7 interrupt is disabled. Receive channel 6 interrupt is disabled. Receive channel 5 interrupt is disabled. Write 1 to disable interrupt. A value written to this field has no effect. a write of 0 has no effect. Figure B−91. The reserved bit location is always read as 0.

Write 1 to disable interrupt. Receive channel 0 interrupt mask clear bit. No effect. Write 1 to disable interrupt. Write 1 to disable interrupt. a write of 0 has no effect. Receive channel 3 interrupt mask clear bit. Receive channel 1 interrupt is disabled. a write of 0 has no effect. Receive channel 1 interrupt mask clear bit. Receive channel 2 interrupt mask clear bit. No effect. a write of 0 has no effect. a write of 0 has no effect. No effect. Receive channel 3 interrupt is disabled. use the notation EMAC_RXINTMASKCLEAR_field_symval TMS320C6000 CSL Registers B-105 . For CSL implementation.EMAC Module Registers Table B−97. Write 1 to disable interrupt. Receive channel 2 interrupt is disabled. a write of 0 has no effect. No effect. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Values (Continued) Bit 4 field† RX4MASK 0 1 3 RX3MASK 0 1 2 RX2MASK 0 1 1 RX1MASK 0 1 0 RX0MASK 0 1 † symval† Value Description Receive channel 4 interrupt mask clear bit. Receive channel 0 interrupt is disabled. No effect. Write 1 to disable interrupt. Receive channel 4 interrupt is disabled.

Figure B−92. Host error interrupt bit. -n = value after reset 16 2 1 HOSTERRINT R-0 0 STATINT R-0 Table B−98. use the notation EMAC_MACINTSTATRAW_field_symval B-106 TMS320C6000 CSL Registers . Statistics interrupt bit. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 Reserved R-0 15 Reserved R-0 Legend: R = Read only.26 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure B−92 and described in Table B−98. A value written to this field has no effect. Raw interrupt read (before mask).EMAC Module Registers B. The reserved bit location is always read as 0. Raw interrupt read (before mask). For CSL implementation. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Values Bit 31−2 1 0 † field† Reserved HOSTERRINT STATINT symval† − Value 0 Description Reserved.5.

Statistics interrupt bit. Figure B−93. Masked interrupt read. A value written to this field has no effect. Masked interrupt read. Host error interrupt bit.5. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) 31 Reserved R-0 15 Reserved R-0 Legend: R = Read only.EMAC Module Registers B. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Values Bit 31−2 1 0 † field† Reserved HOSTERRINT STATINT symval† − Value 0 Description Reserved. The reserved bit location is always read as 0. use the notation EMAC_MACINTSTATMASKED_field_symval TMS320C6000 CSL Registers B-107 .27 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure B−93 and described in Table B−99. -n = value after reset 16 2 1 HOSTERRINT R-0 0 STATINT R-0 Table B−99. For CSL implementation.

WS = Write 1 to set. For CSL implementation.28 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure B−94 and described in Table B−100. use the notation EMAC_MACINTMASKSET_field_symval B-108 TMS320C6000 CSL Registers . a write of 0 has no effect. Write 1 to enable interrupt. The reserved bit location is always read as 0. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Values Bit 31−2 1 field† Reserved HOSTERRINT 0 1 0 STATINT 0 1 † symval† − Value 0 Description Reserved. Host error interrupt is enabled. -n = value after reset 16 2 1 HOSTERRINT R/WS-0 0 STATINT R/WS-0 Table B−100. A value written to this field has no effect.5. Write 1 to enable interrupt. Statistics interrupt mask set bit. Figure B−94.EMAC Module Registers B. No effect. No effect. a write of 0 has no effect. write of 0 has no effect. Statistics interrupt is enabled. Host error interrupt mask set bit. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 Reserved R-0 15 Reserved R-0 Legend: R = Read only.

Host error interrupt mask clear bit. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Values Bit 31−2 1 field† Reserved HOSTERRINT 0 1 0 STATINT 0 1 † symval† − Value 0 Description Reserved. For CSL implementation. A value written to this field has no effect. write of 0 has no effect. a write of 0 has no effect.EMAC Module Registers B. Statistics interrupt is disabled.5. use the notation EMAC_MACINTMASKCLEAR_field_symval TMS320C6000 CSL Registers B-109 . Host error interrupt is disabled. No effect. -n = value after reset 16 2 1 HOSTERRINT R/WC-0 0 STATINT R/WC-0 Table B−101. WC = Write 1 to clear. Write 1 to disable interrupt. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) 31 Reserved R-0 15 Reserved R-0 Legend: R = Read only. Statistics interrupt mask clear bit. Figure B−95.29 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure B−95 and described in Table B−101. Write 1 to disable interrupt. a write of 0 has no effect. The reserved bit location is always read as 0. No effect.

The reserved bit location is always read as 0. use the notation EMAC_MACADDRM_MACADDR8_symval B-110 TMS320C6000 CSL Registers . Figure B−97.30 MAC Address Channel 0−7 Lower Byte Registers (MACADDRLn) The MAC address channel n lower byte register (MACADDRLn) is shown in Figure B−96 and described in Table B−102. or multicast enable is set). For CSL implementation. broadcast. 0−FFh Sixth byte (bits 0−7) of MAC specific address. MAC Address Middle Byte Register (MACADDRM) 31 Reserved R-0 Legend: R = Read only. R/W = Read/Write. -n = value after reset 8 7 MACADDR8 [7−0] R/W-0 0 Table B−102. a channel is disabled when MACADDRLn is written and enabled when MACADDRH is written (provided that the unicast. 0−FFh Fifth byte (bits 8−15) of MAC specific address.5. MAC Address Channel n Lower Byte Register (MACADDRLn) Field Values Bit 31−8 7−0 † Field Reserved MACADDR8 symval† − Value 0 Description Reserved. Figure B−96. R/W = Read/Write. A value written to this field has no effect. In order to facilitate changing the MACADDR values while the device is operating. use the notation EMAC_MACADDRLn_MACADDR8_symval B.5. MAC Address Middle Byte Register (MACADDRM) Field Values Bit 31−8 7−0 † Field Reserved MACADDR8 symval† − Value 0 Description Reserved. MAC Address Channel n Lower Byte Register (MACADDRLn) 31 Reserved R-0 Legend: R = Read only. -n = value after reset 8 7 MACADDR8 [15−8] R/W-0 0 Table B−103. The reserved bit location is always read as 0. MACADDRH should be written last.EMAC Module Registers B. A value written to this field has no effect. For CSL implementation.31 MAC Address Middle Byte Register (MACADDRM) The MAC address middle byte register (MACADDRM) is shown in Figure B−97 and described in Table B−103.

5.32 MAC Address High Bytes Register (MACADDRH) The MAC address high bytes register (MACADDRH) is shown in Figure B−98 and described in Table B−104. writes have no effect. Specific addresses always have this bit cleared to 0.EMAC Module Registers B. [39−32]. [31−24]. MAC Address High Bytes Register (MACADDRH) 31 MACADDR32 ([23−16]. use the notation EMAC_MACADDRH_MACADDR32_symval TMS320C6000 CSL Registers B-111 . Bit 0 corresponds to the group/specific address bit. [47−40]) R/W-0 Legend: R/W = Read/Write. -n = value after reset 0 0 Table B−104. Bit 0 is considered the group/specific bit and is hardwired to 0. MAC Address High Bytes Register (MACADDRH) Field Values Bit 31−0 Field MACADDR32 symval† Value Description 0−FFFF FFFEh First 32 bits (bits 16−47) of MAC specific address. Figure B−98. † For CSL implementation.

DA(10) XOR DA(16) XOR DA(22) XOR DA(28) XOR DA(34) XOR DA(40) XOR DA(46). DA(7) XOR DA(13) XOR DA(19) XOR DA(25) XOR DA(31) XOR DA(37) XOR DA(43). The MAC address hash 1 register (MACHASH1) is shown in Figure B−99 and described in Table B−105. † For CSL implementation. Figure B−99. MAC Address Hash 1 Register (MACHASH1) 31 HASHBITS R/W-0 Legend: R/W = Read/Write. DA(8) XOR DA(14) XOR DA(20) XOR DA(26) XOR DA(32) XOR DA(38) XOR DA(44). If a hash table bit is set.5. use the notation EMAC_MACHASH1_HASHBITS_symval B-112 TMS320C6000 CSL Registers . The hash function creates a 6-bit data value (Hash_fun) from the 48-bit destination address (DA) as follows: Hash_fun(0)=DA(0) Hash_fun(1)=DA(1) Hash_fun(2)=DA(2) Hash_fun(3)=DA(3) Hash_fun(4)=DA(4) Hash_fun(5)=DA(5) XOR XOR XOR XOR XOR XOR DA(6) XOR DA(12) XOR DA(18) XOR DA(24) XOR DA(30) XOR DA(36) XOR DA(42).EMAC Module Registers B. DA(9) XOR DA(15) XOR DA(21) XOR DA(27) XOR DA(33) XOR DA(39) XOR DA(45). -n = value after reset 0 Table B−105. then a group address that hashes to that bit index is accepted. This function is used as an offset into a 64-bit hash table stored in MACHASH1 and MACHASH2 that indicates whether a particular address should be accepted or not.33 MAC Address Hash 1 Register (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address. DA(11) XOR DA(17) XOR DA(23) XOR DA(29) XOR DA(35) XOR DA(41) XOR DA(47). MAC Address Hash 1 Register (MACHASH1) Field Values Bit 31−0 Field HASHBITS symval† Value 0−FFFF FFFFh Description Least-significant 32 bits of the hash table corresponding to hash values 0 to 31.

-n = value after reset 0 Table B−106. † For CSL implementation.EMAC Module Registers B. If a hash table bit is set. Figure B−100. use the notation EMAC_MACHASH2_HASHBITS_symval TMS320C6000 CSL Registers B-113 . MAC Address Hash 2 Register (MACHASH2) 31 HASHBITS R/W-0 Legend: R/W = Read/Write.5. MAC Address Hash 2 Register (MACHASH2) Field Values Bit 31−0 Field HASHBITS symval† Value 0−FFFF FFFFh Description Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. then a group address that hashes to that bit index is accepted.34 MAC Address Hash 2 Register (MACHASH2) The MAC address hash 2 register (MACHASH2) is shown in Figure B−100 and described in Table B−106.

R/W = Read/Write. A value written to this field has no effect. Backoff Test Register (BOFFTEST) 31 BOFFHALT 30 ATTEMPT R/W-0 27 26 BOFFRNG R/W-0 10 9 BOFFCOUNT R/W-0 R-0 16 R/W-0 15 12 11 RETRYCOUNT R/W-0 0 Reserved Legend: R = Read only. The value is reset to 0 and begins counting on the clock after the deassertion of reset.EMAC Module Registers B. Figure B−101. symval† Value Function 30−27 ATTEMPT 26−16 BOFFRNG 15−12 RETRYCOUNT 11−10 Reserved 9−0 BOFFCOUNT − 0−Fh 0 0−3FFh Reserved. Backoff random number generator bits allow the backoff random number generator to be read (or written in test mode only). Backoff current count bits allow the current value of the backoff counter to be observed for test purposes.5.35 Backoff Test Register (BOFFTEST) The backoff test register (BOFFTEST) is shown in Figure B−101 and described in Table B−107. This field can be written only when the MTEST bit in MACCONTROL has previously been set. -n = value after reset Table B−107. The reserved bit location is always read as 0. Backoff Test Register (BOFFTEST) Field Values Field 31 field† BOFFHALT 0−Fh 0−7FFh Initial collision attempt count bits is the number of collisions the current frame has experienced. Reading this field returns the generator’s current value. This field is loaded automatically according to the backoff algorithm and is decremented by 1 for each slot time after the collision. † For CSL implementation. use the notation EMAC_BOFFTEST_field_symval B-114 TMS320C6000 CSL Registers .

EMAC Module Registers B. A transmit frame collision or deferral causes PACEVAL to be loaded with 1Fh (31). the transmitter delays four IPGs between new frame transmissions after each successfully transmitted frame that had no deferrals or collisions. If a transmit frame is deferred or suffers a collision. Transmit Pacing Test Register (TPACETEST) 31 Reserved R-0 Legend: R = Read only. Transmit pacing helps reduce capture effects. A value written to this field has no effect.36 Transmit Pacing Test Register (TPACETEST) The transmit pacing test register (TPACETEST) is shown in Figure B−102 and described in Table B−108.5. the IPG time is not stretched to four times the normal value. use the notation EMAC_TPACETEST_PACEVAL_symval TMS320C6000 CSL Registers B-115 . Pacing register current value. R/W = Read/Write. A nonzero value in this field indicates that transmit pacing is active. Transmit Pacing Test Register (TPACETEST) Field Values Bit 31−5 4−0 Field Reserved PACEVAL symval† − Value 0 0−1Fh Description Reserved. which improves overall network bandwidth. † For CSL implementation. -n = value after reset 5 4 R/W-0 0 PACEVAL Table B−108. good frame transmissions (with no collisions or deferrals) cause PACEVAL to be decremented down to 0. The reserved bit location is always read as 0. When PACEVAL is nonzero. Figure B−102.

This field allows the contents of the receive pause timer to be observed (and written in test mode). The receive pause timer is loaded with FF00h when the EMAC sends an outgoing pause frame (with pause time of FFFFh). Receive Pause Timer Register (RXPAUSE) Field Values Bit 31−16 15−0 Field Reserved PAUSETIMER symval† − Value 0 0−FFFFh Description Reserved. R/W = Read/Write. The reserved bit location is always read as 0.5.EMAC Module Registers B. use the notation EMAC_RXPAUSE_PAUSETIMER_symval B-116 TMS320C6000 CSL Registers . Figure B−103. A value written to this field has no effect. -n = value after reset 16 15 PAUSETIMER R/W-0 0 Table B−109. Receive Pause Timer Register (RXPAUSE) 31 Reserved R-0 Legend: R = Read only. then another outgoing pause frame is sent and the load/decrement process is repeated. † For CSL implementation. Pause timer value bits. The receive pause timer is decremented at slot time intervals. If the receive pause timer decrements to 0.37 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure B−103 and described in Table B−109.

Pause timer value bits – This field allows the contents of the transmit pause timer to be observed (and written in test mode). Transmit Pause Timer Register (TXPAUSE) 31 Reserved R-0 Legend: R = Read only. † For CSL implementation. The reserved bit location is always read as 0. Figure B−104.38 Transmit Pause Timer Register (TXPAUSE) The transmit pause timer register (TXPAUSE) is shown in Figure B−104 and described in Table B−110. R/W = Read/Write. and then decremented at slot time intervals down to 0 at which time EMAC transmit frames are again enabled. Transmit Pause Timer Register (TXPAUSE) Field Values Bit 31−16 15−0 Field Reserved PAUSETIMER symval† − Value 0 0−FFFFh Description Reserved. -n = value after reset 16 15 PAUSETIMER R/W-0 0 Table B−110. The transmit pause timer is loaded by a received (incoming) pause frame.EMAC Module Registers B. A value written to this field has no effect. use the notation EMAC_TXPAUSE_PAUSETIMER_symval TMS320C6000 CSL Registers B-117 .5.

-n = value after reset 0 Table B−112. use the notation EMAC_TXnHDP_DESCPTR_symval B.40 Receive Channel 0−7 DMA Head Descriptor Pointer Registers (RXnHDP) The receive channel n DMA head descriptor pointer register (RXnHDP) is shown in Figure B−106 and described in Table B−112. use the notation EMAC_RXnHDP_DESCPTR_symval B-118 TMS320C6000 CSL Registers . Writing a receive DMA buffer descriptor address to this location allows receive DMA operations in the selected channel when a channel frame is received.5. -n = value after reset 0 Table B−111.5. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Values Bit 31−0 Field DESCPTR symval† Value 0−FFFF FFFFh Description Descriptor pointer bits. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Values Bit 31−0 Field DESCPTR symval† Value 0−FFFF FFFFh Description Descriptor pointer bits. Writing a transmit DMA buffer descriptor address to a head pointer location initiates transmit DMA operations in the queue for the selected channel. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) 31 DESCPTR R/W-0 Legend: R/W = Read/Write.EMAC Module Registers B. Figure B−106. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) 31 DESCPTR R/W-0 Legend: R/W = Read/Write. † For CSL implementation. † For CSL implementation. Host software must initialize these locations to zero on reset. Writing to these locations when they are nonzero is an error (except at reset).39 Transmit Channel 0−7 DMA Head Descriptor Pointer Registers (TXnHDP) The transmit channel n DMA head descriptor pointer register (TXnHDP) is shown in Figure B−105 and described in Table B−111. Figure B−105. Host software must initialize these locations to zero on reset. Writing to these locations when they are nonzero is an error (except at reset).

This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing.5. Transmit Channel n Interrupt Acknowledge Register (TXnINTACK) Field Values Bit 31−0 Field DESCPTR symval† Value 0−FFFF FFFFh Description Transmit host interrupt acknowledge register bits. Figure B−107. † For CSL implementation.EMAC Module Registers B. The EMAC uses the value written to determine if the interrupt should be deasserted. use the notation EMAC_TXnINTACK_DESCPTR_symval TMS320C6000 CSL Registers B-119 .41 Transmit Channel 0−7 Interrupt Acknowledge Registers (TXnINTACK) The transmit channel n interrupt acknowledge register (TXnINTACK) is shown in Figure B−107 and described in Table B−113. Transmit Channel n Interrupt Acknowledge Register (TXnINTACK) 31 DESCPTR R/W-0 Legend: R/W = Read/Write. -n = value after reset 0 Table B−113.

The EMAC uses the value written to determine if the interrupt should be deasserted. Receive Channel n Interrupt Acknowledge Register (RXnINTACK) Field Values Bit 31−0 Field DESCPTR symval† Value 0−FFFF FFFFh Description Receive host interrupt acknowledge register bits. Receive Channel n Interrupt Acknowledge Register (RXnINTACK) 31 DESCPTR R/W-0 Legend: R/W = Read/Write. This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing.5.42 Receive Channel 0−7 Interrupt Acknowledge Registers (RXnINTACK) The receive channel n interrupt acknowledge registers (RXnINTACK) is shown in Figure B−108 and described in Table B−114. use the notation EMAC_RXnINTACK_DESCPTR_symval B-120 TMS320C6000 CSL Registers . The value written is not actually stored in this location. † For CSL implementation. The value read is the interrupt acknowledge value that was written by the EMAC DMA controller. The interrupt is deasserted. -n = value after reset 0 Table B−114. if the two values are equal. Figure B−108.EMAC Module Registers B. The value written to RXnINTACK by the host is compared with the value that the EMAC wrote to determine if the interrupt should remain asserted.

The statistics are mapped into internal memory space and are 32-bits wide. If a value greater than the statistics value is written. The statistics values are cleared to zero. All statistics rollover from FFFF FFFFh to 0000 0000h. -n = value after reset 0 TMS320C6000 CSL Registers B-121 . The value written is subtracted from the register value with the result stored in the register. 38 clocks after the rising edge of reset. When the MIIEN bit in the MACCONTROL register is set. Statistics Register 31 COUNT R/W-0 Legend: R/W = Read/Write.43 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. then zero is written to the register (writing FFFF FFFFh clears a statistics location). so writing 0000 0000h clears a statistics location). all statistics registers are read/write (normal write direct. The statistics registers are 32-bit registers as shown in Figure B−109. if enabled. use: EMAC_register name_COUNT_symval Figure B−109.5.EMAC Module Registers B. The statistics interrupt (STATPEND) is issued. For CSL implementation. all statistics registers are write-to-decrement. The statistics interrupt is removed by writing to decrement any statistics value greater than 8000 0000h. All write accesses must be 32-bit accesses. When the MIIEN bit is cleared. when any statistics value is greater than or equal to 8000 0000h.

6.6.11 B. EMIF Registers Acronym GBLCTL GBLCTL GBLCTL CECTL CECTL CECTL CESEC SDCTL SDCTL SDCTL SDTIM SDEXT PDTCTL Register Name EMIF global control register (C620x/C670x) EMIF global control register (C621x/C671x) EMIF global control register (C64x) EMIF CE space control registers (C620x/C670x) EMIF CE space control registers (C621x/C671x) EMIF CE space control registers (C64x) EMIF CE space secondary control registers (C64x) EMIF SDRAM control register (C620x/C670x) EMIF SDRAM control register (C621x/C671x/C64x) EMIF SDRAM control register (C64x with EMIFA and EMIFB) EMIF SDRAM timing register EMIF SDRAM extension register (C621x/C671x/C64x) EMIF peripheral device transfer control register (C64x) Section B.6.12 B.2 B.3 B.6.6.9 B.6.4 B.6.6 External Memory Interface (EMIF) Registers Table B−115.6.7 B.6.6.1 B.6 B.6.10 B.5 B.13 B-122 TMS320C6000 CSL Registers .External Memory Interface (EMIF) Registers B.6.8 B.6.

Legend: R/W = Read/Write. External device requesting EMIF. 0 1 HOLD input is low. ARDY input bit. -x = value is indeterminate after reset Table B−116.External Memory Interface (EMIF) Registers B. -n = value after reset. EMIF Global Control Register (GBLCTL) Field Values Bit 31−11 10 field† Reserved ARDY LOW HIGH 9 HOLD LOW HIGH 8 HOLDA LOW HIGH † symval† − Value 0 Description Reserved. use the notation EMIF_GBLCTL_field_symval. External device does not own EMIF. External device owns EMIF. No external request pending.6. HOLD input bit. ‡ For C6202/C6203/C6204/C6205 this field is Reserved.1 EMIF Global Control Register (GBLCTL) (C620x/C670x) Figure B−110. HOLD input is high. HOLDA output is high. 0 1 HOLDA output is low. 0 1 ARDY input is low. HOLDA output bit. Writing a value other than the default value to these fields may cause improper operation. A value written to this field has no effect. R = Read only. For CSL implementation. The reserved bit location is always read as 0. The reserved bit fields should always be written with their default values when modifying the GBLCTL. EMIF Global Control Register (GBLCTL) 31 Reserved R/W-0 15 Reserved† R/W-0 7 NOHOLD R/W-0 † 16 12 R/W-0 6 SDCEN R/W-1 R/W-1 5 SSCEN R/W-1 R/W-1 4 CLK1EN R/W-1 11 Reserved R-0 3 CLK2EN‡ R/W-1 10 ARDY R-0 2 SSCRT‡ R/W-0 9 HOLD R-0 1 RBTR8 R/W-0 8 HOLDA R-0 0 MAP R-x The reserved bit fields should always be written with their default values when modifying the GBLCTL. External device is not ready. TMS320C6000 CSL Registers B-123 . Writing a value other than the default value to these fields may cause improper operation. ARDY input is high. External device is ready.

External Memory Interface (EMIF) Registers Table B−116. B-124 TMS320C6000 CSL Registers . SDCLK enable bit. CLKOUT2 is enabled to clock. 0 1 SSCLK runs at 1/2 CPU clock rate. SSCLK is enabled to clock. SSCLK runs at CPU clock rate. 0 1 CLKOUT1 is held high. For CSL implementation. SDCLK is enabled to clock. For C6201/C6701 DSP: SBSRAM clock rate select bit. This bit enables CLKOUT2 if SBSRAM is used in the system (specified by the MTYPE field in in the CE space control register). use the notation EMIF_GBLCTL_field_symval. Hold requests via the HOLD input are acknowledged via the HOLDA output at the earliest possible time. DISABLE ENABLE 5 SSCEN 0 1 SDCLK is held high. DISABLE ENABLE 4 CLK1EN DISABLE ENABLE 3 CLK2EN DISABLE ENABLE 2 SSCRT CPUOVR2 CPU 1 RBTR8 HPRI 8ACC † 0 1 SSCLK is held high. CLKOUT1 is enabled to clock. No hold is disabled. SSCLK enable bit. 0 1 CLKOUT2 is held high. For C6201/C6701 DSP: CLKOUT2 is enabled/disabled using SSCEN/SDCEN bits. The requester controls the EMIF for a minimum of eight accesses. CLKOUT1 enable bit. No hold is enabled. Hold requests via the HOLD input are ignored. EMIF Global Control Register (GBLCTL) Field Values (Continued) Bit 7 field† NOHOLD DISABLE ENABLE 6 SDCEN 0 1 symval† Value Description External NOHOLD enable bit. 0 1 The requester controls the EMIF until a high-priority request occurs. Requester arbitration mode bit. This bit enables CLKOUT2 if SDRAM is used in system (specified by the MTYPE field in in the CE space control register).

use the notation EMIF_GBLCTL_field_symval. External memory located at address 0. 0 1 Map 0 is selected. Internal memory located at address 0. For CSL implementation. TMS320C6000 CSL Registers B-125 . Map 1 is selected. EMIF Global Control Register (GBLCTL) Field Values (Continued) Bit 0 field† MAP MAP0 MAP1 † symval† Value Description Map mode bit contains the value of the memory map mode of the device.External Memory Interface (EMIF) Registers Table B−116.

Legend: R/W = Read/Write. Writing a value other than the default value to these fields may cause improper operation. A value written to this field has no effect.6. -n = value after reset Table B−117. § This bit is reserved on C6713. 0 1 BUSREQ output is low. on other C621x/C671x devices. ARDY input bit.External Memory Interface (EMIF) Registers B. ‡ Available on C6713. use the notation EMIF_GBLCTL_field_symval.2 EMIF Global Control Register (GBLCTL) (C621x/C671x) Figure B−111. C6712C. and C6711C devices only. this field is reserved with R/W-1. EMIF Global Control Register (GBLCTL) Field Values Bit 31−12 11 field† Reserved BUSREQ LOW HIGH 10 ARDY LOW HIGH † ‡ symval† − Value 0 Description Reserved. ARDY input is high. BUSREQ output is high. No access/refresh pending. Access/refresh pending or in progress. C6712C. and C6711C devices with R/W-0. B-126 TMS320C6000 CSL Registers . ECLKOUT does not turn off/on glitch free via EKEN. R = Read only. Bus request (BUSREQ) output bit indicates if the EMIF has an access/refresh pending or in progress. External device is ready. The reserved bit location is always read as 0. Writing a value other than 0 to this bit may cause improper operation. For CSL implementation. EMIF Global Control Register (GBLCTL) 31 Reserved R/W-0 15 Reserved† R/W-0 7 NOHOLD R/W-0 † 16 12 R/W-0 6 Reserved R-1 R/W-1 5 EKEN‡ R/W-1 R/W-1 4 CLK1EN§ R/W-1§ 11 BUSREQ R-0 3 CLK2EN R/W-1 2 10 ARDY R-0 9 HOLD R-0 8 HOLDA R-0 0 Reserved R/W-0 The reserved bit fields should always be written with their default values when modifying the GBLCTL. External device is not ready. 0 1 ARDY input is low.

HOLDA output is low. External device requesting EMIF. Reserved. HOLD input is high. The reserved bit location is always read as 1. External device does not own EMIF. A value written to this field has no effect. Hold requests via the HOLD input are ignored. and C6711C DSP: ECLKOUT enable bit. HOLDA output bit. use the notation EMIF_GBLCTL_field_symval. HOLD input is low. For C6713. On C6713. ECLKOUT does not turn off/on glitch free via EKEN. CLKOUT2 is enabled to clock. External NOHOLD enable bit. A value written to this field has no effect. ECLKOUT is enabled to clock (default). this bit must be programmed to 0 for proper operation. CLKOUT1 is enabled to clock. Reserved − For CSL implementation. and C6711C DSP. External device owns EMIF. TMS320C6000 CSL Registers B-127 . ECLKOUT is held low. Hold requests via the HOLD input are acknowledged via the HOLDA output at the earliest possible time. The reserved bit location is always read as 0. DISABLE ENABLE 3 CLK2EN DISABLE ENABLE 2−0 † ‡ 0 1 CLKOUT1 is held high.External Memory Interface (EMIF) Registers Table B−117. C6712C. No hold is enabled. CLKOUT2 is enabled/disabled using SSCEN/SDCEN bits. HOLDA output is high. No external request pending. EMIF Global Control Register (GBLCTL) Field Values (Continued) Bit 9 field† HOLD LOW HIGH 8 HOLDA LOW HIGH 7 NOHOLD DISABLE ENABLE 6 5 Reserved EKEN‡ DISABLE ENABLE 4 CLK1EN 0 1 − 0 1 1 0 1 0 1 symval† Value Description HOLD input bit. No hold is disabled. and C6711C DSP: CLKOUT1 enable bit. 0 1 0 CLKOUT2 is held high. C6712C. Not on C6713. Reserved. C6712C.

ECLKOUT2 runs at: 1× EMIF input clock (ECLKIN. or CPU/6 clock) rate. or CPU/6 clock) rate. CPU/4 clock.External Memory Interface (EMIF) Registers B. EMIF Global Control Register (GBLCTL) 31 Reserved R/W-0 15 Reserved R/W-0 7 NOHOLD R/W-0 6 EK1HZ R/W-1 14 13 BRMODE R/W-1 5 EK1EN R/W-1 12 Reserved R-0 4 CLK4EN R/W-1 11 BUSREQ R-0 3 CLK6EN R/W-1 20 19 EK2RATE R/W-10 10 ARDY R-0 2 Reserved R/W-1 1 Reserved R/W-0 18 17 EK2HZ R/W-0 9 HOLD R-0 16 EK2EN R/W-1 8 HOLDA R-0 0 Legend: R/W = Read/Write. ECLKOUT2 rate. or CPU/6 clock) rate. The reserved bit location is always read as 0. EMIF Global Control Register (GBLCTL) Field Values Bit 31−20 19−18 field† Reserved EK2RATE§ FULLCLK HALFCLK QUARCLK − 17 EK2HZ‡ CLK HIGHZ † ‡ symval† − Value 0 0−3h 0 1h 2h 3h Description Reserved. -n = value after reset Table B−118. R = Read only. ECLKOUT2 high-impedance control bit. A value written to this field has no effect. ¶ Applies to EMIFA only. § ECLKOUT2 rate should only be changed once during EMIF initialization from the default (1/4x) to either 1/2x or 1x. ECLKOUTn does not turn off/on glitch free via EKnEN or via EKnHZ. use the notation EMIFA_GBLCTL_field_symval or EMIFB_GBLCTL_field_symval. 1/2× EMIF input clock (ECLKIN. 0 1 ECLKOUT2 continues clocking during Hold (if EK2EN = 1).6. CPU/4 clock. B-128 TMS320C6000 CSL Registers . 1/4× EMIF input clock (ECLKIN. ECLKOUT2 is in high-impedance state during Hold. Reserved. For CSL implementation. CPU/4 clock.3 EMIF Global Control Register (GBLCTL) (C64x) Figure B−112.

BUSREQ indicates memory access or refresh pending or in progress. No access/refresh pending. ECLKOUTn does not turn off/on glitch free via EKnEN or via EKnHZ. − 0 1 BUSREQ output is low. 0 1 ARDY input is low. No external request pending. For CSL implementation. − 0 1 0 BUSREQ indicates memory access pending or in progress. Reserved. Reserved.External Memory Interface (EMIF) Registers Table B−118. HOLD input bit. External device requesting EMIF. Bus request mode (BRMODE) bit indicates if BUSREQ shows memory refresh status. ¶ Applies to EMIFA only. § ECLKOUT2 rate should only be changed once during EMIF initialization from the default (1/4x) to either 1/2x or 1x. The reserved bit location is always read as 0. HOLDA output is high. External device is ready. BUSREQ output is high. 0 1 HOLDA output is low. ECLKOUT2 is enabled to clock. 0 1 0 ECLKOUT2 is held low. A value written to this field has no effect. A value written to this field has no effect. Access/refresh pending or in progress. use the notation EMIFA_GBLCTL_field_symval or EMIFB_GBLCTL_field_symval. Valid ARDY bit is shown only when performing asynchronous memory access (when async CEn is active). External device does not own EMIF. TMS320C6000 CSL Registers B-129 . HOLD input is high. Bus request (BUSREQ) output bit indicates if the EMIF has an access/refresh pending or in progress. ARDY input is high. ARDY input bit. External device is not ready. EMIF Global Control Register (GBLCTL) Field Values (Continued) Bit 16 field† EK2EN‡ DISABLE ENABLE 15−14 13 Reserved BRMODE MSTATUS MRSTATUS 12 11 Reserved BUSREQ LOW HIGH 10 ARDY LOW HIGH 9 HOLD LOW HIGH 8 HOLDA LOW HIGH † ‡ symval† Value Description ECLKOUT2 enable bit. 0 1 HOLD input is low. External device owns EMIF. HOLDA output bit. The reserved bit location is always read as 0.

After reset. CLKOUT6 may be configured as GP2 via the GPIO enable register (GPEN). CLKOUT4 is enabled to clock. § ECLKOUT2 rate should only be changed once during EMIF initialization from the default (1/4x) to either 1/2x or 1x. CLKOUT 6 enable bit. CLKOUT6 pin is muxed with GP2 pin. ECLKOUTn does not turn off/on glitch free via EKnEN or via EKnHZ. CLKOUT4 enable bit. No hold is enabled. ¶ Applies to EMIFA only. ECLKOUT1 enable bit. A value written to this field has no effect. Reserved Reserved − − For CSL implementation. CLKOUT4 may be configured as GP1 via the GPIO enable register (GPEN). ECLKOUT1 continues clocking during Hold (if EK1EN = 1). CLKOUT4 pin is muxed with GP1 pin. CLKOUT6 is enabled and clocking. After reset. ECLKOUT1 is held low. DISABLE ENABLE 2 1−0 † ‡ 0 1 1 0 CLKOUT6 is held high. CLKOUT4 is enabled and clocking. No hold is disabled. Reserved. Hold requests via the HOLD input are ignored. Upon exiting reset. A value written to this field has no effect. ECLKOUT1 high-impedance control bit. ECLKOUT1 is in high-impedance state during Hold. CLKOUT6 is enabled to clock. Reserved. DISABLE ENABLE 3 CLK6EN¶ 0 1 CLKOUT4 is held high.External Memory Interface (EMIF) Registers Table B−118. The reserved bit location is always read as 0. EMIF Global Control Register (GBLCTL) Field Values (Continued) Bit 7 field† NOHOLD DISABLE ENABLE 6 EK1HZ‡ CLK HIGHZ 5 EK1EN‡ DISABLE ENABLE 4 CLK4EN¶ 0 1 0 1 0 1 symval† Value Description External NOHOLD enable bit. Hold requests via the HOLD input are acknowledged via the HOLDA output at the earliest possible time. use the notation EMIFA_GBLCTL_field_symval or EMIFB_GBLCTL_field_symval. ECLKOUT1 is enabled to clock. Upon exiting reset. B-130 TMS320C6000 CSL Registers . The reserved bit location is always read as 1.

this is also the setup time of AOE before ARE falls. EMIF CE Space Control Register (CECTL) 31 WRSETUP R/W-1111 15 R/W-0 14 13 RDSTRB R/W-11 1111 28 27 WRSTRB R/W-11 1111 8 7 Rsvd R/W-0 6 MTYPE R/W-010 22 21 20 19 RDSETUP R/W-1111 4 3 Reserved R/W-0 2 1 0 16 WRHLD R/W-11 Reserved RDHLD R/W-11 Legend: R/W-x = Read/Write-Reset value Table B−119.6. use the notation EMIF_CECTL_field_symval. chip enable (CE). Clock cycles are in terms of CLKOUT1 for C620x/C670x DSP. TMS320C6000 CSL Registers B-131 .4 EMIF CE Space Control Register (CECTL) (C620x/C670x) Figure B−113.External Memory Interface (EMIF) Registers B. Reserved. this is also the hold time of AOE after ARE rising. The width of write strobe (AWE) in clock cycles. The reserved bit location is always read as zero. ‡ Reserved. Write strobe width. The width of read strobe (ARE) in clock cycles. For asynchronous read accesses. For asynchronous read accesses. The reserved bit location is always read as zero. Number of clock cycles ‡ of setup time for address (EA). 27−22 21−20 WRSTRB WRHLD OF(value) OF(value) 0−3Fh 0−3h 19−16 RDSETUP OF(value) 0−Fh 15−14 13−8 7 † ‡ Reserved RDSTRB Reserved − OF(value) − 0 0−3Fh 0 For CSL implementation. and byte enables (BE[0-3]) before write strobe falls. A value written to this field has no effect. A value written to this field has no effect. this is also the setup time of AOE before ARE falls. Read setup width. Read strobe width. Number of clock cycles‡ that address (EA) and byte strobes (BE[0-3]) are held after write strobe rises. EMIF CE Space Control Register (CECTL) Field Values Bit 31−28 field† WRSETUP symval† OF(value) Value 0−Fh Description Write setup width. Number of clock cycles ‡ of setup time for address (EA). chip enable (CE). For asynchronous read accesses. and byte enables (BE[0-3]) before read strobe falls. ‡ Write hold width.

A value written to this field has no effect. use the notation EMIF_CECTL_field_symval. The reserved bit location is always read as zero.External Memory Interface (EMIF) Registers Table B−119. CE3 only) 32-bit-wide SBSRAM Reserved Reserved. Number of clock cycles‡ that address (EA) and byte strobes (BE[0-3]) are held after read strobe rises. 8-bit-wide ROM (CE1 only) 16-bit-wide ROM (CE1 only) 32-bit-wide asynchronous interface 32-bit-wide SDRAM (CE0. EMIF CE Space Control Register (CECTL) Field Values (Continued) Bit 6−4 field† MTYPE ASYNC8 ASYNC16 ASYNC32 SDRAM32 SBSRAM32 − 3−2 1−0 Reserved RDHLD − OF(value) 0 1h 2h 3h 4h 5h−7h 0 0−3h symval† Value Description Memory type of the corresponding CE spaces. † ‡ For CSL implementation. Clock cycles are in terms of CLKOUT1 for C620x/C670x DSP. Read hold width. CE2. this is also the hold time of AOE after ARE rising. For asynchronous read accesses. B-132 TMS320C6000 CSL Registers .

For asynchronous read accesses. Number of clock cycles ‡ of setup time for address (EA). or between reads from different CE spaces. Minimum Turn-Around time. and byte enables (BE) before read strobe falls.External Memory Interface (EMIF) Registers B. this is also the setup time of AOE before ARE falls. EMIF CE Space Control Register (CECTL) Field Values Bit 31−28 field† symval† Value 0−Fh Description Write setup width. Write strobe width. TMS320C6000 CSL Registers B-133 . For asynchronous read accesses. Number of clock cycles ‡ of setup time for address (EA). Read strobe width. ‡ Write hold width. § 32-bit interfaces (MTYPE=0010b. Number of clock cycles‡ that address (EA) and byte strobes (BE) are held after write strobe rises. 0100b) do not apply to C6712 DSP. chip enable (CE). The width of write strobe (AWE) in clock cycles. and byte enables (BE) before write strobe falls. Clock cycles are in terms of ECLKOUT for C621x/C671x DSP. chip enable (CE). use the notation EMIF_CECTL_field_symval.5 EMIF CE Space Control Register (CECTL) (C621x/C671x) Figure B−114. Applies only to asynchronous memory types. this is also the hold time of AOE after ARE rising. For asynchronous read accesses. EMIF CE Space Control Register (CECTL) 31 WRSETUP R/W-1111 15 TA R/W-11 14 13 RDSTRB R/W-11 1111 28 27 WRSTRB R/W-11 1111 8 7 MTYPE R/W-0010 22 21 20 19 RDSETUP R/W-1111 4 3 Reserved R-0 2 RDHLD R/W-011 0 16 WRHLD R/W-11 Legend: R/W-x = Read/Write-Reset value Table B−120. 0011b. Turn-around time controls the minimum number of ECLKOUT cycles‡ between a read followed by a write (same or different CE spaces). The width of read strobe (ARE) in clock cycles ‡ WRSETUP OF(value) 27−22 21−20 WRSTRB WRHLD OF(value) OF(value) 0−3Fh 0−3h 19−16 RDSETUP OF(value) 0−Fh 15−14 TA OF(value) 0−3h 13−8 † ‡ RDSTRB OF(value) 0−3Fh For CSL implementation.6. this is also the setup time of AOE before ARE falls. Read setup width.

External Memory Interface (EMIF) Registers Table B−120. 16-bit-wide SDRAM. 16-bit-wide SBSRAM. 8-bit-wide SBSRAM. Read hold width. If C6712 DSP: 8-bit-wide programmable synchronous memory. Reserved. The reserved bit location is always read as 0. 16-bit-wide asynchronous interface. 0011b. B-134 TMS320C6000 CSL Registers . 32-bit-wide SDRAM. Clock cycles are in terms of ECLKOUT for C621x/C671x DSP. 8-bit-wide asynchronous interface. 0 0−7h Reserved. 8-bit-wide SDRAM. this is also the hold time of AOE after ARE rising. use the notation EMIF_CECTL_field_symval. Number of clock cycles‡ that address (EA) and byte strobes (BE) are held after read strobe rises. For asynchronous read accesses. 32-bit-wide asynchronous interface. A value written to this field has no effect. 32-bit-wide SBSRAM. § 32-bit interfaces (MTYPE=0010b. EMIF CE Space Control Register (CECTL) Field Values (Continued) Bit 7−4 field† MTYPE§ ASYNC8 ASYNC16 ASYNC32 SDRAM32 SBSRAM32 − SDRAM8 SDRAM16 SBSRAM8 SYNC8 SBSRAM16 SYNC16 − 3 2−0 Reserved RDHLD − OF(value) symval† Value 0−Fh 0 1h 2h 3h 4h 5h−7h 8h 9h Ah Ah Bh Bh Description Memory type of the corresponding CE spaces. 0100b) do not apply to C6712 DSP. Ch−Fh Reserved. If C6712 DSP: 16-bit-wide programmable synchronous memory. † ‡ For CSL implementation.

For asynchronous read accesses. this is also the hold time of AOE after ARE rising. chip enable (CE). chip enable (CE). 0100b. 1100b. Read setup width. Turn-around time controls the minimum number of ECLKOUT cycles‡ between a read followed by a write (same or different CE spaces). For asynchronous read accesses. this is also the setup time of AOE before ARE falls. Number of clock cycles‡ that address (EA) and byte strobes (BE) are held after write strobe rises. Clock cycles are in terms of ECLKOUT1 for C64x DSP.External Memory Interface (EMIF) Registers B. Write strobe width. Minimum Turn-Around time. and byte enables (BE) before write strobe falls.6. 1110b) do not apply to C64x EMIFB. 0011b. Number of clock cycles ‡ of setup time for address (EA). and byte enables (BE) before read strobe falls. For asynchronous read accesses. EMIF CE Space Control Register (CECTL) 31 WRSETUP R/W-1111 15 TA R/W-11 14 13 RDSTRB R/W-11 1111 28 27 WRSTRB R/W-11 1111 8 7 MTYPE R/W-0 22 21 20 19 RDSETUP R/W-1111 4 3 WRHLDMSB R/W-0 2 RDHLD R/W-011 0 16 WRHLD R/W-11 Legend: R/W-x = Read/Write-Reset value Table B−121. this is also the setup time of AOE before ARE falls. ‡ Write hold width. Number of clock cycles ‡ of setup time for address (EA). Applies only to asynchronous memory types.6 EMIF CE Space Control Register (CECTL) (C64x) Figure B−115. or between reads from different CE spaces. TMS320C6000 CSL Registers B-135 . Read strobe width. 1101b. The width of read strobe (ARE) in clock cycles. ‡ 27−22 21−20 WRSTRB WRHLD OF(value) OF(value) 0−3Fh 0−3h 19−16 RDSETUP OF(value) 0−Fh 15−14 TA OF(value) 0−3h 13−8 † ‡ RDSTRB OF(value) 0−3Fh For CSL implementation. The width of write strobe (AWE) in clock cycles. use the notation EMIFA_CECTL_field_symval or EMIFB_CECTL_field_symval. EMIF CE Space Control Register (CECTL) Field Values Bit 31−28 field† WRSETUP symval† OF(value) Value 0−Fh Description Write setup width. § 32-bit and 64-bit interfaces (MTYPE=0010b.

64-bit-wide programmable synchronous memory. 64-bit-wide asynchronous interface.External Memory Interface (EMIF) Registers Table B−121. 32-bit-wide asynchronous interface. 0011b. 16-bit-wide asynchronous interface. 0100b. 1100b. 32-bit-wide programmable synchronous memory. Clock cycles are in terms of ECLKOUT1 for C64x DSP. EMIF CE Space Control Register (CECTL) Field Values (Continued) Bit 7−4 field† MTYPE§ ASYNC8 ASYNC16 ASYNC32 SDRAM32 SYNC32 − SDRAM8 SDRAM16 SYNC8 SYNC16 ASYNC64 SDRAM64 SYNC64 − 3 2−0 WRHLDMSB RDHLD OF(value) OF(value) symval† Value 0−Fh 0 1h 2h 3h 4h 5h−7h 8h 9h Ah Bh Ch Dh Eh Fh 0−1 0−7h Description Memory type of the corresponding CE spaces. Read hold width. Number of clock cycles‡ that address (EA) and byte strobes (BE) are held after read strobe rises. Write hold width MSB is the most-significant bit of write hold. use the notation EMIFA_CECTL_field_symval or EMIFB_CECTL_field_symval. For asynchronous read accesses. 8-bit-wide asynchronous interface. 16-bit-wide programmable synchronous memory. B-136 TMS320C6000 CSL Registers . 1110b) do not apply to C64x EMIFB. § 32-bit and 64-bit interfaces (MTYPE=0010b. Reserved. 1101b. Reserved. 32-bit-wide SDRAM. 8-bit-wide SDRAM. this is also the hold time of AOE after ARE rising. 8-bit-wide programmable synchronous memory. 64-bit-wide SDRAM. 16-bit-wide SDRAM. † ‡ For CSL implementation.

writes. Synchronization clock selection bit. The SOE timing is controlled by SYNCRL. SADS/SRE signal acts as SADS signal. SADS/SRE signal acts as SRE signal. (used for SBSRAM or ZBT SRAM interface). Read Enable enable bit. The reserved bit location is always read as 0. EMIF CE Space Secondary Control Register (CESEC) Field Values Bit 31−7 6 field† Reserved SNCCLK ECLKOUT1 ECLKOUT2 5 RENEN ADS 0 0 1 symval† − Value 0 Description Reserved. Deselect is issued after a command is completed if no new commands are pending from the EDMA. use the notation EMIFA_CESEC_field_symval or EMIFB_CESEC_field_symval. SADS goes active for reads. (used for FIFO interface). EMIF CE Space Secondary Control Register (CESEC) 31 Reserved R/W-0 15 Reserved R/W-0 Legend: R/W = Read/Write. No deselect cycle is issued. CE extension register ENABLE BIT. TMS320C6000 CSL Registers B-137 . SRE goes low only for reads. On read cycles.6. Read enable mode. ADS mode. INACTIVE ACTIVE 0 1 CE goes inactive after the final command has been issued (not necessarily when all the data has been latched). -n = value after reset 16 7 6 SNCCLK R/W-0 5 RENEN R/W-0 4 R/W-0 3 R/W-0 2 1 0 CEEXT SYNCWL SYNCRL R/W-10 Table B−122. Control/data signals for this CE space are synchronized to ECLKOUT1. the CE signal will go active when SOE goes active and will stay active until SOE goes inactive. A value written to this field has no effect.External Memory Interface (EMIF) Registers B. Control/data for this CE space are synchronized to ECLKOUT2.7 EMIF CE Space Secondary Control Register (CESEC) (C64x) Figure B−116. READ 1 4 CEEXT † For CSL implementation. where CE gates OE). (used for synchronous FIFO reads with glue. and deselect.

For CSL implementation. 1 cycle read latency. B-138 TMS320C6000 CSL Registers . Synchronous interface data read latency. 3 cycle read latency. 2 cycle read latency. use the notation EMIFA_CESEC_field_symval or EMIFB_CESEC_field_symval.External Memory Interface (EMIF) Registers Table B−122. 1 cycle read latency. EMIF CE Space Secondary Control Register (CESEC) Field Values (Continued) Bit 3−2 field† SYNCWL 0CYCLE 1CYCLE 2CYCLE 3CYCLE 1−0 SYNCRL 0CYCLE 1CYCLE 2CYCLE 3CYCLE † symval† Value 0−3h 0 1h 2h 3h 0−3h 0 1h 2h 3h Description Synchronous interface data write latency. 0 cycle read latency. 0 cycle read latency. 2 cycle read latency. 3 cycle read latency.

8 EMIF SDRAM Control Register (SDCTL) (C620x/C670x) Figure B−117. The CPU should initialize all of the CE space control registers before setting INIT = 1. No effect. DISABLE ENABLE 24 INIT NO YES 0 1 0 1 SDRAM refresh is disabled. A value written to this field has no effect. which is equal to CLKOUT2 period for C620x/C670x DSP.External Memory Interface (EMIF) Registers B. EMIF SDRAM Control Register (SDCTL) 31 Reserved R/W-0 15 TRC R/W-1111 Legend: R/W-x = Read/Write-Reset value 27 26 SDWID R/W-0 25 RFEN R/W-1 24 INIT W-1 23 TRCD R/W-1000 20 19 TRP R/W-1000 16 12 11 Reserved R/W-0 0 Table B−123. tcyc refers to the EMIF clock period. This write-only bit forces initialization of all SDRAM present. The reserved bit location is always read as 0. If SDRAM is not used. SDRAM column width select. use the notation EMIF_SDCTL_field_symval. 8 column address pins (256 elements per row). 9 column address pins (512 elements per row). be sure RFEN = 0. Initialize SDRAM in each CE space configured for SDRAM. otherwise. TMS320C6000 CSL Registers B-139 .6. SDRAM refresh is enabled. Reading this bit returns an undefined value. EMIF SDRAM Control Register (SDCTL) Field Values Bit 31−27 26 field† Reserved SDWID 4X8BIT 2X16BIT 25 RFEN 0 1 symval† − Value 0 Description Reserved. BUSREQ may become asserted when SDRAM timer counts down to 0. Refresh enable bit. Specifies the tRCD value of the SDRAM in EMIF clock cycles.‡ TRCD = tRCD / tcyc − 1 23−20 † ‡ TRCD OF(value) 0−Fh For CSL implementation. Initialization bit.

A value written to this field has no effect. B-140 TMS320C6000 CSL Registers . The reserved bit location is always read as 0.‡ TRC = tRC / tcyc − 1 Reserved.‡ TRP = tRP / tcyc − 1 Specifies the tRC value of the SDRAM in EMIF clock cycles. For CSL implementation. which is equal to CLKOUT2 period for C620x/C670x DSP. EMIF SDRAM Control Register (SDCTL) Field Values (Continued) Bit 19−16 15−12 11−0 † ‡ field† TRP TRC Reserved symval† OF(value) OF(value) − Value 0−Fh 0−Fh 0 Description Specifies the tRC value of the SDRAM in EMIF clock cycles.External Memory Interface (EMIF) Registers Table B−123. use the notation EMIF_SDCTL_field_symval. tcyc refers to the EMIF clock period.

Reserved. The reserved bit location is always read as 0. SDRAM row size bits. 13 row address pins (8192 rows per bank). Reserved.9 EMIF SDRAM Control Register (SDCTL) (C621x/C671x/C64x) Figure B−118. SDRAM bank size bit. For CSL implementation. EMIF SDRAM Control Register (SDCTL) 31 Reserved R/W-0 15 TRC R/W-1111 Legend: R/W-x = Read/Write-Reset value 30 SDBSZ R/W-0 29 28 27 26 25 RFEN R/W-1 24 INIT W-0 23 TRCD R/W-0100 20 19 TRP R/W-1000 16 SDRSZ R/W-0 SDCSZ R/W-0 12 11 Reserved R/W-0 0 Table B−124.6. 10 column address pins (1024 elements per row). tcyc refers to the EMIF clock period.External Memory Interface (EMIF) Registers B. 9 column address pins (512 elements per row). 12 row address pins (4096 rows per bank). TMS320C6000 CSL Registers B-141 . use the notation EMIF_SDCTL_field_symval. ECLKOUT1 period for the C64x. Two bank-select pins (four banks). A value written to this field has no effect. SDRAM column size bits. 0 1 0−3h 0 1h 2h 3h 0−3h 0 1h 2h 3h One bank-select pin (two banks). EMIF SDRAM Control Register (SDCTL) Field Values Bit 31 30 field† Reserved SDBSZ 2BANKS 4BANKS 29−28 SDRSZ 11ROW 12ROW 13ROW − 27−26 SDCSZ 9COL 8COL 10COL − † ‡ symval† − Value Description 0 Reserved. 8 column address pins (256 elements per row). 11 row address pins (2048 rows per bank). which is equal to ECLKOUT period for C621x/C671x DSP.

tcyc refers to the EMIF clock period. use the notation EMIF_SDCTL_field_symval. No effect. Specifies the tRCD value of the SDRAM in EMIF clock cycles. DISABLE ENABLE 24 INIT NO YES 0 1 0 1 SDRAM refresh is disabled. EMIF SDRAM Control Register (SDCTL) Field Values (Continued) Bit 25 field† RFEN symval† Value Description Refresh enable bit. be sure RFEN = 0. ECLKOUT1 period for the C64x. otherwise. This write-only bit forces initialization of all SDRAM present. A value written to this field has no effect. If SDRAM is not used.External Memory Interface (EMIF) Registers Table B−124. which is equal to ECLKOUT period for C621x/C671x DSP. SDRAM refresh is enabled. BUSREQ may become asserted when SDRAM timer counts down to 0. The reserved bit location is always read as 0. Initialize SDRAM in each CE space configured for SDRAM. Initialization bit.‡ TRP = tRP / tcyc − 1 Specifies the tRC value of the SDRAM in EMIF clock cycles.‡ TRCD = tRCD / tcyc − 1 Specifies the tRC value of the SDRAM in EMIF clock cycles. 23−20 19−16 15−12 11−0 † ‡ TRCD TRP TRC Reserved OF(value) OF(value) OF(value) − 0−Fh 0−Fh 0−Fh 0 For CSL implementation. B-142 TMS320C6000 CSL Registers . The CPU should initialize all of the CE space control registers and SDRAM extension register before setting INIT = 1.‡ TRC = tRC / tcyc − 1 Reserved. Reading this bit returns an undefined value.

The specified separation is maintained while driving write data one cycle earlier. The reserved bit location is always read as zero. TRCD specifies the number of ECLKOUT1 cycles between an ACTV command and a READ or WRT command (CAS). on EMIFB. EMIF SDRAM Control Register (SDCTL) 31 Reserved R/W-0 15 TRC R/W-1111 30 SDBSZ R/W-0 29 28 27 26 25 RFEN R/W-1 24 INIT W-0 23 TRCD R/W-0100 20 19 TRP R/W-1000 1 Reserved R/W-0 0 SLFRFR† R/W-0 16 SDRSZ R/W-0 SDCSZ R/W-0 12 11 Legend: R/W-x = Read/Write-Reset value † SLFRFR only applies to EMIFA. R/W-0.External Memory Interface (EMIF) Registers B.10 EMIF SDRAM Control Register (SDCTL) (C64x with EMIFA and EMIFB) Figure B−119. §t cyc refers to the EMIF clock period. TMS320C6000 CSL Registers B-143 . use the notation EMIFA_SDCTL_field_symval or EMIFB_SDCTL_field_symval. SDRAM bank size 0 1 One bank-select pin (two banks) Two bank-select pins (four banks) SDRAM row size 0 1h 2h 3h 11 row address pins (2048 rows per bank) 12 row address pins (4096 rows per bank) 13 row address pins (8192 rows per bank) Reserved SDRAM column size 0 1h 2h 3h 9 column address pins (512 elements per row) 8 column address pins (256 elements per row) 10 column address pins (1024 elements per row) Reserved For CSL implementation. Bit 0 is Reserved. A value written to this field has no effect. Table B−125. which is equal to or ECLKOUT1 period for the C64x. EMIF SDRAM Control Register (SDCTL) Field Values Bit 31 30 field Reserved SDBSZ 2BANKS 4BANKS 29−28 SDRSZ 11ROW 12ROW 13ROW − 27−26 SDCSZ 9COL 8COL 10COL − † ‡ symval − Value 0 Description Reserved.6.

This write-only bit forces initialization of all SDRAM present. TRCD specifies the number of ECLKOUT1 cycles between an ACTV command and a READ or WRT command (CAS). BUSREQ may become asserted when SDRAM timer counts down to 0. The reserved bit location is always read as zero. No effect Initialize SDRAM in each CE space configured for SDRAM. if SDRAM is used in the system: 0 1 Self-refresh mode disabled Self-refresh mode enabled If SDRAM is not used: 0 1 † ‡ 23−20 19−16 15−12 11−1 0 TRCD‡ TRP TRC Reserved SLFRFR OF(value) OF(value) OF(value) − 0−Fh 0−Fh 0−Fh 0 General-purpose output SDCKE = 1 General-purpose output SDCKE = 0 For CSL implementation. be sure RFEN = 0. EMIF automatically changes INIT back to 0 after SDRAM initialization is performed. EMIF SDRAM Control Register (SDCTL) Field Values (Continued) Bit 25 field RFEN symval Value Description Refresh enable bit.External Memory Interface (EMIF) Registers Table B−125. The specified separation is maintained while driving write data one cycle earlier. otherwise. Reading this bit returns an undefined value. §t cyc refers to the EMIF clock period. If SDRAM is not used. Specifies the tRCD value of the SDRAM in EMIF clock cycles§ TRCD = tRCD / tcyc − 1 Specifies the tRP value of the SDRAM in EMIF clock cycles§ TRP = tRP / tcyc − 1 Specifies the tRC value of the SDRAM in EMIF clock cycles§ TRC = tRC / tcyc − 1 Reserved. B-144 TMS320C6000 CSL Registers . use the notation EMIFA_SDCTL_field_symval or EMIFB_SDCTL_field_symval. which is equal to or ECLKOUT1 period for the C64x. DISABLE ENABLE 24 INIT NO YES 0 1 0 1 SDRAM refresh is disabled SDRAM refresh is enabled Initialization bit. A value written to this field has no effect. Self-refresh mode.

EMIF clock cycles = CLKOUT2 cycles. For C64x. 1 refresh.External Memory Interface (EMIF) Registers B. use the notation EMIF_SDTIM_field_symval. 2 refreshes. EMIF clock cycles = ECLKOUT1 cycles.‡ EMIFA_SDTIM_field_symval. 3 refreshes. EMIF SDRAM Timing Register (SDTIM) (C620x/C670x) 31 Reserved R/W-0 Legend: R/W-x = Read/Write-Reset value 24 23 CNTR R-040h 12 11 PERIOD R/W-040h 0 Figure B−121. 4 refreshes.6. EMIFB_SDTIM_field_symval. The reserved bit location is always read as 0. Extra refreshes controls the number of refreshes performed to SDRAM when the refresh counter expires. ‡ For C620x/C670x. or CNTR PERIOD OF(value) OF(value) 0−FFFh 0−FFFh For CSL implementation.11 EMIF SDRAM Timing Register (SDTIM) Figure B−120. EMIF SDRAM Timing Register (SDTIM) Field Values Bit 31−24 25−24 field† Reserved XRFR symval† − OF(value) Value 0 0−3h 0 1h 2h 3h 23−12 11−0 † Description Reserved. TMS320C6000 CSL Registers B-145 . For C621x/C671x. A value written to this field has no effect. EMIF SDRAM Timing Register (SDTIM) (C621x/C671x/C64x) 31 Reserved R/W-0 26 25 24 23 CNTR R-5DCh 12 11 PERIOD R/W-5DCh 0 XRFR R/W-0 Legend: R/W-x = Read/Write-Reset value Table B−126. Current value of the refresh counter. EMIF clock cycles = ECLKOUT cycles. Refresh period in EMIF clock cycles.

‡ For C64x. §t cyc refers to the EMIF clock period. The reserved bit location is always read as zero. ECLKOUT1 period for C64x. ECLKOUT referenced in this table is equivalent to ECLKOUT1.External Memory Interface (EMIF) Registers B. EMIF SDRAM Extension Register (SDEXT) Field Values Bit 31−21 20 field† Reserved WR2RD symval† − OF(value) Value 0 Description Reserved. or EMIFB_SDEXT_field_symval. B-146 TMS320C6000 CSL Registers . Specifies minimum number of cycles between WRITE to READ command of the SDRAM in ECLKOUT cycles‡ WR2RD = (# of cycles WRITE to READ) − 1 0−3h Specifies minimum number of cycles between WRITE to DEAC/DCAB command of the SDRAM in ECLKOUT cycles‡ WR2DEAC = (# of cycles WRITE to DEAC/DCAB) − 1 Specifies minimum number of cycles between WRITE to WRITE command of the SDRAM in ECLKOUT cycles‡ WR2WR = (# of cycles WRITE to WRITE) − 1 0−3h Specifies number of of cycles that BEx signals must be high preceding a WRITE interrupting a READ R2WDQM = (# of cycles BEx high) − 1 Specifies number of cycles between READ to WRITE command of the SDRAM in ECLKOUT cycles‡ RD2WR = (# of cycles READ to WRITE) − 1 Specifies number of cycles between READ to DEAC/DCAB of the SDRAM in ECLKOUT cycles‡ RD2DEAC = (# of cycles READ to DEAC/DCAB) − 1 19−18 WR2DEAC OF(value) 17 WR2WR OF(value) 16−15 R2WDQM OF(value) 14−12 RD2WR OF(value) 0−7h 11−10 RD2DEAC OF(value) 0−3h † For CSL implementation. EMIF SDRAM Extension Register (SDEXT) 31 Reserved R/W-0 11 RD2DEAC R/W-11 10 9 RD2RD R/W-1 8 THZP R/W-10 21 20 WR2RD R/W-1 7 6 TWR R/W-01 19 R/W-01 5 18 17 WR2WR R/W-1 4 TRRD R/W-1 3 TRAS R/W-111 16 R/W-11 15 14 RD2WR R/W-101 1 0 TCL R/W-1 12 WR2DEAC R2WDQM Legend: R/W-x = Read/Write-Reset value Table B−127. A value written to this field has no effect. which is equal to ECLKOUT period for the C621x/C671x. use the notation EMIF_SDEXT_field_symval.6.12 EMIF SDRAM Extension Register (SDEXT) (C621x/C671x/C64x) Figure B−122. EMIFA_SDEXT_field_symval.

‡ For C64x. TMS320C6000 CSL Registers B-147 . ECLKOUT1 period for C64x. or EMIFB_SDEXT_field_symval.External Memory Interface (EMIF) Registers Table B−127. §t cyc refers to the EMIF clock period. ECLKOUT referenced in this table is equivalent to ECLKOUT1. which is equal to ECLKOUT period for the C621x/C671x. use the notation EMIF_SDEXT_field_symval. EMIF SDRAM Extension Register (SDEXT) Field Values (Continued) Bit 9 field† RD2RD symval† OF(value) 0 1 8−7 THZP OF(value) 0−3h Value Description Specifies number of cycles between READ to READ command (same CE space) of the SDRAM in ECLKOUT cycles‡ READ to READ = 1 ECLKOUT cycle READ to READ = 2 ECLKOUT cycle Specifies tHZP (also known as tROH) value of the SDRAM in ECLKOUT cycles‡ THZP = tHZP / tcyc − 1§ Specifies tWR value of the SDRAM in ECLKOUT cycles‡ TWR = tWR / tcyc − 1§ Specifies tRRD value of the SDRAM in ECLKOUT cycles‡ 0 1 3−1 0 TRAS TCL OF(value) OF(value) 0 1 † 6−5 4 TWR TRRD OF(value) OF(value) 0−3h TRRD = 2 ECLKOUT cycles TRRD = 3 ECLKOUT cycles Specifies tRAS value of the SDRAM in ECLKOUT cycles‡ TRAS = tRAS / tcyc − 1§ Specified CAS latency of the SDRAM in ECLKOUT cycles‡ CAS latency = 2 ECLKOUT cycles CAS latency = 3 ECLKOUT cycles 0−7h For CSL implementation. EMIFA_SDEXT_field_symval.

EMIF Peripheral Device Transfer Control Register (PDTCTL) Field Values Bit 31−4 3−2 field† Reserved PDTWL 0CYCLE 1CYCLE 2CYCLE 3CYCLE 1−0 PDTRL 0CYCLE 1CYCLE 2CYCLE 3CYCLE † symval† − Value 0 0−3h 0 1h 2h 3h 0−3h 0 1h 2h 3h Description Reserved. PDT signal is asserted 2 cycles prior to the data phase of a write transaction. EMIF Peripheral Device Transfer Control Register (PDTCTL) 31 Reserved R-0 Legend: R/W = Read/Write. B-148 TMS320C6000 CSL Registers . The reserved bit location is always read as 0. use the notation EMIFA_PDTCTL_field_symval. PDT signal is asserted 3 cycles prior to the data phase of a read transaction. PDT signal is asserted 3 cycles prior to the data phase of a write transaction. PDT write latency bits. For CSL implementation.13 EMIF Peripheral Device Transfer Control Register (PDTCTL) (C64x) Figure B−123.6. -n = value after reset 4 3 PDTWL R/W-0 2 1 PDTRL R/W-0 0 Table B−128. R = Read only. PDT signal is asserted 0 cycles prior to the data phase of a write transaction. A value written to this field has no effect. PDT signal is asserted 1 cycle prior to the data phase of a read transaction.External Memory Interface (EMIF) Registers B. PDT signal is asserted 0 cycles prior to the data phase of a read transaction. PDT signal is asserted 2 cycles prior to the data phase of a read transaction. PDT read latency bits. PDT signal is asserted 1 cycle prior to the data phase of a write transaction.

7.7.7.4 B.7.7.6 B.7 General-Purpose Input/Output (GPIO) Registers Table B−129.7.7.7. -n = value after reset 16 0 TMS320C6000 CSL Registers B-149 .7 B.1 GPIO Enable Register (GPEN) Figure B−124.7.General-Purpose Input/Output (GPIO) Registers B.3 B. GPIO Enable Register (GPEN) 31 Reserved R-0 15 GPXEN R/W-0 Legend: R/W = Read/Write.2 B.7. GPIO Registers Acronym GPEN GPDIR GPVAL GPDH GPHM GPDL GPLM GPGC GPPOL Register Name GPIO enabling register GPIO direction register GPIO value register GPIO delta high register GPIO high mask register GPIO delta low register GPIO low mask register GPIO global control register GPIO interrupt polarity register Section B.1 B.8 B.5 B.9 B.

GPx pin is an output.General-Purpose Input/Output (GPIO) Registers Table B−130.7. It defaults to high impedance state. For CSL implementation. The reserved bit location is always read as zero. 0 1 † GPx pin is an input. use the notation GPIO_GPDIR_GPXDIR_symval B-150 TMS320C6000 CSL Registers . Applies when the corresponding GPxEN bit in the GPEN register is set to 1. GPx pin is enabled as general-purpose input/output pin. GPIO Mode enable GPx pin is disabled as general-purpose input/output pin. For CSL implementation. GPx Direction. GPIO Direction Register (GPDIR) Field Values Bit 31−16 15−0 Field Reserved GPXDIR symval† − OF(value) Value 0 Description Reserved. A value written to this field has no effect. The reserved bit location is always read as zero. GPIO Direction Register (GPDIR) 31 Reserved R-0 15 GPXDIR R/W-0 Legend: R/W = Read/Write. -n = value after reset 16 0 Table B−131. GPIO Enable Register (GPEN) Field Values Bit 31−16 15−0 Field Reserved GPXEN symval† − OF(value) 0 1 † Value 0 Description Reserved.2 GPIO Direction Register (GPDIR) Figure B−125. A value written to this field has no effect. It does not function as a GPIO pin and defaults to high impedance state. Controls direction (input or output) of GPIO pin. use the notation GPIO_GPEN_GPXEN_symval B.

GPx signal is driven high. The reserved bit location is always read as zero.General-Purpose Input/Output (GPIO) Registers B. Applies when the corresponding GPXEN bit in the GPEN register is set to 1. 0 1 † GPx signal is driven low. GPIO Value Register (GPVAL) Field Values Bit 31−16 15−0 Field Reserved GPXVAL symval† − OF(value) Value 0 Description Reserved. use the notation GPIO_GPVAL_GPXVAL_symval TMS320C6000 CSL Registers B-151 . For CSL implementation.3 GPIO Value Register (GPVAL) Figure B−126. GPIO Value Register (GPVAL) 31 Reserved R-0 15 GPXVAL R/W-0 Legend: R/W = Read/Write. 0 1 A value of 0 is latched from the GPx input pin. A value written to this field has no effect. -n = value after reset 16 0 Table B−132. Value detected at GPx input/output.7. A value of 1 is latched from the GPx input pin. When GPx pin is an input. When GPx pin is an output.

General-Purpose Input/Output (GPIO) Registers B.4 GPIO Delta High Register (GPDH) Figure B−127. use the notation GPIO_GPDH_GPXDH_symval B-152 TMS320C6000 CSL Registers . GPIO Delta High Register (GPDH) 31 Reserved R-0 15 GPXDH R/W-0 Legend: R/W = Read/Write. Applies when the corresponding GPx pin is enabled as an input (GPXEN = 1 and GPXDIR = 0) 0 1 † A low-to-high transition is not detected on GPx A low-to-high transition is detected on GPx For CSL implementation. A value written to this field has no effect.7. The reserved bit location is always read as zero. GPIO Delta High Register (GPDH) Field Values Bit 31−16 15−0 Field Reserved GPXDH symval† − OF(value) Value 0 Description Reserved. A low-to-high transition is detected on the GPx input. GPx Delta High. -n = value after reset 16 0 Table B−133.

7. Enable interrupt/event generation based on either the corresponding GPxDH or GPxVAL bit in the GPDH and GPVAL registers. respectively. A value written to this field has no effect. use the notation GPIO_GPHM_GPXHM_symval TMS320C6000 CSL Registers B-153 . The reserved bit location is always read as zero. -n = value after reset 16 0 Table B−134. GPx high mask. GPIO High Mask Register (GPHM) 31 Reserved R-0 15 GPXHM R/W-0 Legend: R/W = Read/Write.5 GPIO High Mask Register (GPHM) Figure B−128. For CSL implementation. Interrupt/event generation enabled for GPx. The value or transition on GPx does not cause an interrupt/event generation. GPIO High Mask Register (GPHM) Field Values Bit 31−16 15−0 Field Reserved GPXHM symval† − OF(value) Value 0 Description Reserved. Applies when the corresponding GPxEN bit is enabled as an input (GPXEN = 1 and GPXDIR = 0) 0 1 † Interrupt/event generation disabled for GPx.General-Purpose Input/Output (GPIO) Registers B.

Applies when the corresponding GPx pin is enabled as an input (GPXEN = 1 and GPxDIR = 0). For CSL implementation.7. 0 1 † A high-to-low transition is not detected on GPx. A value written to this field has no effect. GPIO Delta Low Register (GPDL) Field Values Bit 31−16 15−0 Field Reserved GPXDL symval† − OF(value) Value 0 Description Reserved. GPx Delta Low. -n = value after reset 16 0 Table B−135. GPIO Delta Low Register (GPDL) 31 Reserved R-0 15 GPXDL R/W-0 Legend: R/W = Read/Write. A high-to-low transition is detected on GPx. The reserved bit location is always read as zero. use the notation GPIO_GPDL_GPXDL_symval B-154 TMS320C6000 CSL Registers .6 GPIO Delta Low Register (GPDL) Figure B−129.General-Purpose Input/Output (GPIO) Registers B. A high-to-low transition is detected on the GPx input.

respectively. GPIO Low Mask Register (GPLM) 31 Reserved R-0 15 GPXLM R/W-0 Legend: R/W = Read/Write. The reserved bit location is always read as zero. Interrupt/event generation enabled for GPx.General-Purpose Input/Output (GPIO) Registers B. The value or transition on GPx does not cause an interrupt/event generation. -n = value after reset 16 0 Table B−136. Applies when the corresponding GPxEN bit is enabled as an input (GPXEN = 1 and GPXDIR = 0) 0 1 † Interrupt/event generation disabled for GPx.7 GPIO Low Mask Register (GPLM) Figure B−130. GPIO Low Mask Register (GPLM) Field Values Bit 31−16 15−0 Field Reserved GPXLM symval† − OF(value) Value 0 Description Reserved. GPx low mask. A value written to this field has no effect. For CSL implementation. Enable interrupt/event generation based on either the corresponding GPXDL or inverted GPXVAL bit in the GPDL and GPVAL registers.7. use the notation GPIO_GPLM_GPXLM_symval TMS320C6000 CSL Registers B-155 .

0 1 0 Pass Through Mode—GPINT0 interrupt/event generation is based on GP0 input value (GP0VAL in the GPVAL register). The reserved bit location is always read as zero. GPIO Global Control Register (GPGC) Field Values Bit 31−6 5 field† Reserved GP0M GPIOMODE LOGICMODE 4 GPINT0M PASSMODE LOGICMODE 3 2 Reserved GPINTPOL LOGICTRUE LOGICFALSE † symval† − Value 0 Description Reserved.7. Logic Mode—GPINT0 interrupt/event generation is based on GPINT. use the notation GPIO_GPGC_field_symval B-156 TMS320C6000 CSL Registers . For CSL implementation.8 GPIO Global Control Register (GPGC) Figure B−131. The reserved bit location is always read as zero. GPIO Global Control Register (GPGC) 31 Reserved R-0 7 Reserved R-0 6 5 GP0M R/W-0 4 GPINT0M R/W-0 3 Reserved R-0 2 GPINTPOL R/W-0 1 LOGIC R/W-0 0 GPINTDV R/W-0 8 Legend: R/W = Read/Write. -n = value after reset Table B−137. GPINT is active (high) when the logic combination of the GPIO inputs is evaluated false. GP0 Output Mode. GPINT Polarity. Reserved. − 0 1 GPINT is active (high) when the logic combination of the GPIO inputs is evaluated true. A value written to this field has no effect. GPINT0 interrupt/event generation mode. Applies to Logic Mode (GPINT0M = 1) only.General-Purpose Input/Output (GPIO) Registers B. Applies only if GP0 is configured as an output (GP0DIR = 1 in the GPDIR register). 0 1 GPIO Mode—GP0 output is based on GP0 value (GP0VAL in GPVAL register) Logic Mode—GP0 output is based on the value of internal Logic Mode interrupt/event signal GPINT. A value written to this field has no effect.

VALUEMODE 1 † For CSL implementation. Applies to Logic Mode (GPINT0M = 1) only. OR Mode—GPINT is generated based on the logical-OR of all GPx events enabled in the GPHM or GPLM registers. GPIO Global Control Register (GPGC) Field Values (Continued) Bit 1 field† LOGIC ORMODE ANDMODE 0 GPINTDV DELTAMODE 0 0 1 symval† Value Description GPINT Logic. AND Mode—GPINT is generated based on the logical-AND of all GPx events enabled in the GPHM or GPLM registers.General-Purpose Input/Output (GPIO) Registers Table B−137. Applies to Logic Mode (GPINT0M = 1) only. Value Mode—GPINT is generated based on a logic combination of values on the GPx pins. Delta Mode—GPINT is generated based on a logic combination of transitions on the GPx pins. use the notation GPIO_GPGC_field_symval TMS320C6000 CSL Registers B-157 . The corresponding bits in the GPHM and/or GPLM registers must be set. GPINT Delta/Value Mode. The corresponding bits in the GPHM and/or GPLM registers must be set.

GPIO Interrupt Polarity Register (GPPOL) 31 Reserved R-0 15 Reserved R-0 Legend: R/W = Read/Write. GPINTx polarity bit. Applies to pass-through mode only (GPINT0M = 0 in GPGC). The reserved bit location is always read as zero. 0 1 GPINTx is asserted (high) based on a rising edge of GPx (effectively based on the value of the corresponding GPXVAL) GPINTx is asserted (high) based on a falling edge of GPx (effectively based on the inverted value of the corresponding GPXVAL) GPINTXPOL OF(value) † For CSL implementation. GPIO Interrupt Polarity Register (GPPOL) Field Values Bit 31−8 7−0 Field Reserved symval† − Value 0 Description Reserved. A value written to this field has no effect.General-Purpose Input/Output (GPIO) Registers B.9 GPIO Interrupt Polarity Register (GPPOL) Figure B−132.7. use the notation GPIO_GPPOL_GPINTXPOL_symval B-158 TMS320C6000 CSL Registers . -n = value after reset 16 8 7 GPINTXPOL R/W-0 0 Table B−138.

The CPU can access HPIAW and HPIAR. HPID contains the data that is written to the memory. if the current access is a read. HPI Registers for C64x DSP Read/Write Access Acronym HPID HPIAW† HPIAR† HPIC TRCTL † Register Name HPI data register HPI address write register HPI address read register HPI control register HPI transfer request control register Host R/W R/W R/W R/W − CPU − R/W R/W R/W R/W Section B.8.8.1 B.8.4 Host access to the HPIA updates both HPIAW and HPIAR. TMS320C6000 CSL Registers B-159 .8 Host Port Interface (HPI) Register Table B−139.8.1 HPI Data Register (HPID) The HPI data register (HPID) contains the data that was read from the memory accessed by the HPI. independently.8.2 B.2 B.3 Table B−140.1 B.3 B. B.8.8.2 B. HPI Registers for C62x/C67x DSP Read/Write Access Acronym HPID HPIA HPIC Register Name HPI data register HPI address register HPI control register Host R/W R/W R/W CPU − − R/W Section B.8.Host Port Interface (HPI) Register B. if the current access is a write.8.

including the use of general-purpose input/output pins to perform handshaking between the host and the DSP. By separating the HPIA into HPIAW and HPIAR internally. reading HPIA does not indicate the status of a transfer. the value returned corresponds to the address currently being used by the HPI and DMA to transfer data inside the DSP.Host Port Interface (HPI) Register B.2 HPI Address Register (HPIA) The HPI address register (HPIA) contains the address of the memory accessed by the HPI at which the current access occurs. if the most recent HPID access was a read. The two LSBs always function as 0. For the C64x HPI. This can be controlled by any convenient means. B-160 TMS320C6000 CSL Registers . the CPU can update the read and write memory address independently to allow the host to perform read and write to different address ranges. and should not be relied upon to do so. regardless of the value read from their location. The HPIAR/HPIAW registers can be read independently by both the CPU and the external host. The C62x/C67x HPIA is only accessible by the host. The HCNTL[1−0] control bits are set to 01b to indicate an access to HPIA. It is not the address for the current transfer at the external pins. A host read of HPIA returns the value in the most-recently-used HPIAx register. The C64x HPIA is separated into two registers internally: the HPI address write register (HPIAW) and the HPI address read register (HPIAR). a host access to HPIA is identical to the operation of the C62x/C67x HPI. Thus. Systems that update HPIAR/HPIAW internally via the CPU must not allow HPIA updates via the external bus and conversely. if the most recent HPID access was a write. The HPIA is accessible by both the host and the CPU. A host write to HPIA updates both HPIAW and HPIAR internally. then an HPIA read by the external host returns the value in HPIAR. then an HPIA read by the external host returns the value in HPIAW. it is not mapped to the DSP memory.8. When reading HPIA from the CPU. The system must not allow HPID accesses via the external host while the DSP is updating the HPIAR/W registers internally. This address is a 32-bit word address with all 32-bits readable/writable. For example.

HPIC is a 32-bit register with only 16 bits of useful data. In HPI16 mode when setting DSPINT = 1. the host must only write 1 to the lower 16-bit halfword or upper 16-bit halfword. The DSPINT bit must be cleared to 0 in the second halfword write. The HPIC is shown in Figure B−133. Figure B−134(a). From the host’s view (Figure B−133(a). Figure B−134(b). except when writing the DSPINT bits in HPI16 mode.3 HPI Control Register (HPIC) The HPI control register (HPIC) is normally the first register accessed to set configuration bits and initialize the interface.8. From the C6000 CPU view (Figure B−133(b). On C64x DSP in HPI16 mode. care must be taken when writing to HPIC in order not to write an undesired value to HWOB. On C64x DSP. the value of DSPINT in the first halfword write is latched. In HPI32 mode. Therefore. and Figure B−135. Figure B−134.Host Port Interface (HPI) Register B. but not both. both halfwords must be identical. and Figure B−135(a)). HPIC is organized as a 32-bit register with two identical halves. On a host write. meaning the high halfword and low halfword contents are the same. and Figure B−135(b)). Only CPU writes to the lower halfword affect HPIC values and HPI operation. the HWOB bit is writable by the CPU. the upper and lower halfwords must always be identical. and described in Table B−141. TMS320C6000 CSL Registers B-161 .

HPI Control Register (HPIC)—C620x/C670x DSP (a) Host Reference View 31 Reserved HR-0 15 Reserved HR-0 5 21 20 FETCH HR/W-0 4 FETCH HR/W-0 19 HRDY HR-1 3 HRDY HR-1 18 HINT HR/W-0 2 HINT HR/W-0 17 DSPINT HR/W-0 1 DSPINT HR/W-0 16 HWOB HR/W-0 0 HWOB HR/W-0 Legend: H = Host access. -n = value after reset B-162 TMS320C6000 CSL Registers . R = Read only.Host Port Interface (HPI) Register Figure B−133. R/W = Read/Write. -n = value after reset (b) CPU Reference View 31 Reserved R-0 15 Reserved R-0 5 4 FETCH R-0 3 HRDY R-1 2 HINT R/W-0 1 DSPINT R/W-0 0 HWOB R-0 16 Legend: R = Read only. R/W = Read/Write.

R/W = Read/Write. HPI Control Register (HPIC)—C621x/C671x DSP (a) Host Reference View 31 Reserved HR-0 15 Reserved HR-0 4 20 19 Reserved HR-x 3 Reserved HR-x 18 HINT HR/W-0 2 HINT HR/W-0 17 DSPINT HR/W-0 1 DSPINT HR/W-0 16 HWOB HR/W-0 0 HWOB HR/W-0 Legend: H = Host access. -x = value is indeterminate after reset (b) CPU Reference View 31 Reserved R-0 15 Reserved R-0 Legend: R = Read only. R = Read only. -n = value after reset 16 4 3 HRDY R-1 2 HINT R/W-0 1 DSPINT R/W-0 0 HWOB R-0 TMS320C6000 CSL Registers B-163 . R/W = Read/Write.Host Port Interface (HPI) Register Figure B−134. -n = value after reset.

HPI Control Register (HPIC)—C64x DSP (a) Host Reference View 31 Reserved† HR/W-0 15 Reserved† HR/W-0 30 24 23 Reserved† HR-0 8 7 Reserved† HR-0 6 Reserved HR-0 22 Reserved HR-0 4 20 19 Reserved HR-x 3 Reserved HR-x 18 HINT HR/W-0 2 HINT HR/W-0 17 DSPINT HR/W-0 1 DSPINT HR/W-0 16 HWOB HR/W-0 0 HWOB HR/W-0 Reserved HR-0 14 HR-0 Reserved Legend: H = Host access. operation is undefined. -n = value after reset † These bits are writable fields and must be written with 0. otherwise.Host Port Interface (HPI) Register Figure B−135. R/W = Read/Write. -n = value after resett. otherwise. operation is undefined. B-164 TMS320C6000 CSL Registers . (b) CPU Reference View 31 Reserved R-0 15 Reserved† R/W-0 14 R-0 8 7 Reserved† R-0 6 Reserved R-0 4 3 HRDY R-1 2 HINT R/W-0 1 DSPINT R/W-0 0 HWOB R-0 16 Reserved Legend: R = Read only. -x = value is indeterminate after reset † These bits are writable fields and must be written with 0. R/W = Read/Write. R = Read only.

0 HWOB 0 1 Halfword ordering bit affects both data and address transfers. Not masked by HCS (as the HRDY pin is). The first halfword is least significant. Ready signal to host bit.Host Port Interface (HPI) Register Table B−141. 1 DSPINT 0 1 16. 0 1 18. Reserved − For CSL implementation. however. The inverted value of this bit determines the state of the CPU HINT output. The host writes a 1 to this bit to request a fetch into HPID of the word at the address pointed to by HPIA. HWOB must be initialized before the first data or address register access. 0 1 15−5 † 19. The 1 is never actually written to this bit. The value read by the host or CPU is always 0. Reserved. CPU HINT output is logic 0. The reserved bit location is always read as 0. 0 1 CPU HINT output is logic 1. The host processor-to-CPU/DMA interrupt bit. 2 HINT 0 1 17. HPI Control Register (HPIC) Field Values Bit 31−21 20. The reserved bit location is always read as 0. DSP-to-host interrupt bit. For HPI32. Host fetch request bit. Only the host can modify this bit. 0 1 0 The first halfword is most significant. 3 HRDY 0 1 The internal bus is waiting for an HPI data access request to finish. HWOB is not used and the value of HWOB is irrelevant. use the notation HPI_HPIC_field_symval TMS320C6000 CSL Registers B-165 . 4 field† Reserved FETCH 0 1 0 1 symval† − Value 0 Description Reserved.

4 HPI Transfer Request Control Register (TRCTL) (C64x) The HPI transfer request control register (TRCTL) controls how the HPI submits its requests to the EDMA subsystem. the TRSTALL bit needs to be used to ensure a proper transition. SPRU234). This can be done by forcing program execution or data accesses in internal memory. 5) Poll the appropriate PQ bits in the priority queue status register (PQSR) of the EDMA until both queues are empty (see the Enhanced DMA (EDMA) Controller Reference Guide. The TRCTL is shown in Figure B−246 and described in Table B−255. 2) Clear all EDMA event enables (EER) corresponding to both old and new PRI levels to stop EDMA from submitting TR requests on both PRI levels. In this case. B-166 TMS320C6000 CSL Registers . In the same write. Do not manually submit additional events via the EDMA. By halting all requestors at a given level. To safely change the PALLOC or PRI bits in TRCTL. 3) Do not submit new QDMA requests on either old or new PRI level. the desired new PALLOC and PRI fields may be specified.8. 6) Clear the TRSTALL bit to 0 to allow the HPI to continue normal operation. all pending requests corresponding to the old PRI level must be let to complete before HPI is released from stall state. The following procedure must be followed to change the PALLOC or PRI bits: 1) Set the TRSTALL bit to 1 to stop the HPI from submitting TR requests on the current PRI level. Requestors are halted on the old HPI PRI level so that memory ordering can be preserved. Requestors are halted on the new PRI level to ensure that at no time can the sum of all requestor allocations exceed the queue length. 4) Stop L2 cache misses on either old or new PRI level. you can be free to modify the queue allocation counters of each requestor. Another way is to have the CPU executing a tight loop that does not cause additional cache misses.Host Port Interface (HPI) Register B.

Allows HPI requests to be submitted to the EDMA. -n = value after reset.Host Port Interface (HPI) Register Figure B−136. Forces the HPI to stall all HPI requests to the EDMA. Controls the priority queue level that HPI requests are submitted to. Reserved. R/W = Read/Write. HPI Transfer Request Control Register (TRCTL) 31 Reserved R-0 15 Reserved R-0 7 Reserved R-x 6 5 PRI R/W-10 4 3 PALLOC R/W-0100 9 8 TRSTALL R/W-0 0 16 Legend: R = Read only. Urgent priority High priority Medium priority Low priority Controls the total number of outstanding requests that can be submitted by the HPI to the EDMA. Halts the creation of new HPI requests to the EDMA. The reserved bit location is always read as 0. The reserved bit location is always read as 0. -x = value is indeterminate after reset Table B−142. PALLOC 0−Fh For CSL implementation. use the notation HPI_TRCTL_field_symval TMS320C6000 CSL Registers B-167 . This bit allows the safe changing of the PALLOC and PRI fields. HPI Transfer Request Control Register (TRCTL) Field Values Bit 31−9 8 field† Reserved TRSTALL 0 1 7−6 5−4 Reserved PRI − 0 0−3h 0 1h 2h 3h 3−0 † symval† − Value 0 Description Reserved.

9.4 B.1 B.9.9.9.11 B.13 B.9.4 B.9.14 B.9 B.Inter-Integrated Circuit (I2C) Registers B.9. B-168 TMS320C6000 CSL Registers .10 B.7 B.9.6 B.5 B.16 B.8 B.9.15 B.9.9 Inter-Integrated Circuit (I2C) Registers Table B−143.9.9.9.3 B.9.9.2 B.12 B.9.9. I2C Module Registers Address Offset (hex) 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 48 4C 50 54 58 5C — — Acronym I2COAR I2CIER I2CSTR I2CCLKL I2CCLKH I2CCNT I2CDRR I2CSAR I2CDXR I2CMDR I2CISRC I2CEMDR† I2CPSC I2CPID1 I2CPID2 I2CPFUNC† I2CPDIR† I2CPDIN† I2CPDOUT† I2CPDSET† I2CPDCLR† I2CRSR I2CXSR † Register Name I2C own address register I2C interrupt enable register I2C status register I2C clock low-time divider register I2C clock high-time divider register I2C data count register I2C data receive register I2C slave address register I2C data transmit register I2C mode register I2C interrupt source register I2C extended mode register I2C prescaler register I2C peripheral identification register 1 I2C peripheral identification register 2 I2C pin function register I2C pin direction register I2C pin data input register I2C pin data output register I2C pin data set register I2C pin data clear register I2C receive shift register (not accessible to the CPU or EDMA) I2C transmit shift register (not accessible to the CPU or EDMA) Section B.19 — — Available only on C6410/C6413/C6418 DSPs.9.13 B.9.18 B.9.17 B.9.

A value written to this field has no effect.1 I2C Own Address Register (I2COAR) The I2C own address register (I2COAR) is a 32-bit register mapped used to specify its own slave address. only bits 6−0 are used. -n = value after reset 16 10 9 A R/W-0 0 Table B−144. For CSL C macro implementation. Bits 9−7 are ignored. use the notation I2C_I2COAR_A_symval TMS320C6000 CSL Registers B-169 .Inter-Integrated Circuit (I2C) Registers B. In 10-bit addressing mode (XA = 1 in I2CMDR): 0−3FFh † Bits 9−0 provide the 10-bit slave address of the I2C module. In 7-bit addressing mode (XA = 0 in I2CMDR): Bits 6−0 provide the 7-bit slave address of the I2C module. which distinguishes it from other slaves connected to the I2C-bus.9. I2C Own Address Register (I2COAR) Field Values Bit 31−10 9−0 Field Reserved A symval† − OF(value) 0−7Fh Value 0 Description These Reserved bit locations are always read as zeros. The I2COAR is shown in Figure B−137 and described in Table B−144. bits 9−7 are ignored. If the 7-bit addressing mode is selected (XA = 0 in I2CMDR). R/W = Read/write. I2C Own Address Register (I2COAR) 31 Reserved R-0 15 Reserved R-0 Legend: R = Read only. Figure B−137.

Address as slave interrupt enable bit. Figure B−138. For CSL C macro implementation. The I2CIER is shown in Figure B−138 and described Table B−145. Interrupt request is enabled. 0 1 Interrupt request is disabled. Interrupt request is enabled. I2C Interrupt Enable Register (I2CIER) Field Values Bit 31−7 6 field† Reserved AAS MSK UNMSK 5 SCD MSK UNMSK 4 ICXRDY MSK UNMSK 3 ICRRDY MSK UNMSK † symval† − Value 0 Description These Reserved bit locations are always read as zeros. Receive-data-ready interrupt enable bit. Table B−145. -n = value after reset † Available only on C6410/C6413/C6418 DSPs. reserved on all other devices. 0 1 Interrupt request is disabled. Interrupt request is enabled. 0 1 Interrupt request is disabled.Inter-Integrated Circuit (I2C) Registers B.9. Stop condition detected interrupt enable bit.2 I2C Interrupt Enable Register (I2CIER) The I2C interrupt enable register (I2CIER) is used by the CPU to individually enable or disable I2C interrupt requests. Interrupt request is enabled. 0 1 Interrupt request is disabled. R/W = Read/write. A value written to this field has no effect. use the notation I2C_I2CIER_field_symval B-170 TMS320C6000 CSL Registers . Transmit-data-ready interrupt enable bit. I2C Interrupt Enable Register (I2CIER) 31 Reserved R-0 15 Reserved R-0 7 6 AAS† R/W-0 5 SCD† R/W-0 4 ICXRDY R/W-0 3 ICRRDY R/W-0 2 ARDY R/W-0 1 NACK R/W-0 0 AL R/W-0 16 Legend: R = Read only.

use the notation I2C_I2CIER_field_symval B. I2C Status Register (I2CSTR) 31 Reserved R-0 15 Reserved R-0 7 Reserved R-0 14 SDIR† R/W1C-0 6 13 NACKSNT R/W1C-0 5 SCD† R/W-0 12 BB R/W1C-0 4 ICXRDY R/W1C-1 11 RSFULL R-0 3 ICRRDY R/W1C-0 10 XSMT R-1 2 ARDY R/W1C-0 9 AAS R-0 1 NACK R/W1C-0 8 AD0 R-0 0 AL R/W1C-0 16 Legend: R = Read. Figure B−139. The I2CSTR is shown in Figure B−139 and described in Table B−146. 0 1 Interrupt request is disabled. reserved on all other devices. Interrupt request is enabled. Interrupt request is enabled. TMS320C6000 CSL Registers B-171 . -n = value after reset † Available only on C6410/C6413/C6418 DSPs.Inter-Integrated Circuit (I2C) Registers Table B−145. I2C Interrupt Enable Register (I2CIER) Field Values (Continued) Bit 2 field† ARDY MSK UNMSK 1 NACK MSK UNMSK 0 AL MSK UNMSK † symval† Value Description Register-access-ready interrupt enable bit. No-acknowledgement interrupt enable bit. Arbitration-lost interrupt enable bit 0 1 Interrupt request is disabled. 0 1 Interrupt request is disabled. For CSL C macro implementation.3 I2C Status Register (I2CSTR) The I2C status register (I2CSTR) is used by the CPU to determine which interrupt has occurred and to read status information. W1C = Write 1 to clear (writing 0 has no effect).9. Interrupt request is enabled.

NONE 0 NACK is not sent. NACKSNT bit is cleared by any one of the following events: - It is manually cleared. For CSL C macro implementation. Slave direction bit. BB is manually cleared. The I2C module is reset (either when 0 is written to the IRS bit of I2CMDR or when the whole DSP is reset). To clear this bit. I2C module is acting as a master-transmitter/receiver or a slave-receiver. A value written to this field has no effect. SDIR is manually cleared. The I2C module is reset. write a 1 to it.9. SDIR is cleared by any one of the following events: - A STOP or a START condition. Bus busy bit. INT CLR † 1 Bus is busy: The I2C module has received or transmitted a START bit on the bus. NACK sent bit is used when the I2C module is in the receiver mode. To clear this bit. BB indicates whether the I2C-bus is busy or is free for another data transfer. BB is cleared by any one of the following events: - The I2C module receives or transmits a STOP bit (bus free). INT CLR 12 BB NONE 1 NACK is sent: A no-acknowledge bit was sent during the acknowledge cycle on the I2C-bus. write a 1 to it. use the notation I2C_I2CSTR_field_symval B-172 TMS320C6000 CSL Registers .9). the SDIR bit is cleared to 0. One instance in which NACKSNT is affected is when the NACK mode is used (see the description for NACKMOD in section B. INT CLR 13 NACKSNT 1 I2C module is acting as a slave-transmitter. To clear this bit. write a 1 to it. 0 Bus is free. In digital-loopback mode. I2C Status Register (I2CSTR) Field Values Bit 31−15 14 field† Reserved SDIR NONE 0 symval† − Value 0 Description These Reserved bit locations are always read as zeros.Inter-Integrated Circuit (I2C) Registers Table B−146.

8 AD0 † For CSL C macro implementation. Transmit shift register empty bit. XSMT is set by one of the following events: - Data is written to I2CDXR. No underflow is detected. Overrun occurs when the receive shift register (I2CRSR) is full with new data but the previous data has not been read from the data receive register (I2CDRR). INT 10 XSMT 1 Overrun is detected. The next I2CDXR-to-I2CXSR transfer will not occur until new data is in I2CDXR. NONE INT 0 1 AD0 has been cleared by a START or STOP condition. The I2C module is reset. The I2C module is reset. An address of all zeros (general call) is detected. they overwrite the bits in I2CRSR. the previous data may be re-transmitted on the SDA pin. NONE INT 0 1 Underflow is detected. If new data is not transferred in time. XSMT indicates that the transmitter has experienced underflow. I2C Status Register (I2CSTR) Field Values (Continued) Bit 11 field† RSFULL symval† Value Description Receive shift register full bit.Inter-Integrated Circuit (I2C) Registers Table B−146. RSFULL is cleared by any one of the following events: - I2CDRR is read. The new data will not be copied to I2CDRR until the previous data is read. Address 0 bit. NONE 0 No overrun is detected. Underflow occurs when the transmit shift register (I2CXSR) is empty but the data transmit register (I2CDXR) has not been loaded since the last I2CDXR-to-I2CXSR transfer. The AAS bit is also set if the first data word has been received in the free data format (FDF = 1 in I2CMDR). The AAS bit has been cleared by a repeated START condition or by a STOP condition. RSFULL indicates an overrun condition during reception. use the notation I2C_I2CSTR_field_symval TMS320C6000 CSL Registers B-173 . 9 AAS NONE INT 0 1 Addressed-as-slave bit. The I2C module has recognized its own slave address or an address of all zeros (general call). As new bits arrive from the SDA pin.

Inter-Integrated Circuit (I2C) Registers

Table B−146. I2C Status Register (I2CSTR) Field Values (Continued)
Bit 7−6 5 field† Reserved SCD symval† − Value 0 Description These Reserved bit locations are always read as zeros. A value written to this field has no effect. Stop condition detected bit. SCD indicates when a STOP condition has been detected on the I2C bus. The STOP condition could be generated by the I2C module or by another I2C device connected to the bus. NONE 0 No STOP condition has been detected. SCD is cleared by any one of the following events:
-

By reading INCODE bits in I2CICR as 110b. SCD is manually cleared. To clear this bit, write a 1 to it.

INT CLR 4 ICXRDY

1

A STOP condition has been detected.

Transmit-data-ready interrupt flag bit. ICXRDY indicates that the data transmit register (I2CDXR) is ready to accept new data because the previous data has been copied from I2CDXR to the transmit shift register (I2CXSR). The CPU can poll ICXRDY or use the XRDY interrupt request. NONE 0 I2CDXR is not ready. ICXRDY is cleared by one of the following events:
-

Data is written to I2CDXR. ICXRDY is manually cleared. To clear this bit, write a 1 to it.

INT CLR

1

I2CDXR is ready: Data has been copied from I2CDXR to I2CXSR. ICXRDY is forced to 1 when the I2C module is reset.

For CSL C macro implementation, use the notation I2C_I2CSTR_field_symval

B-174

TMS320C6000 CSL Registers

Inter-Integrated Circuit (I2C) Registers

Table B−146. I2C Status Register (I2CSTR) Field Values (Continued)
Bit 3 field† ICRRDY symval† Value Description Receive-data-ready interrupt flag bit. ICRRDY indicates that the data receive register (I2CDRR) is ready to be read because data has been copied from the receive shift register (I2CRSR) to I2CDRR. The CPU can poll ICRRDY or use the RRDY interrupt request. NONE 0 I2CDRR is not ready. ICRRDY is cleared by any one of the following events:
-

I2CDRR is read. ICRRDY is manually cleared. To clear this bit, write a 1 to it. The I2C module is reset.

INT CLR 2 ARDY

1

I2CDRR is ready: Data has been copied from I2CRSR to I2CDRR. Register-access-ready interrupt flag bit (only applicable when the I2C module is in the master mode). ARDY indicates that the I2C module registers are ready to be accessed because the previously programmed address, data, and command values have been used. The CPU can poll ARDY or use the ARDY interrupt request.

NONE

0

The registers are not ready to be accessed. ARDY is cleared by any one of the following events:
-

The I2C module starts using the current register contents. ARDY is manually cleared. To clear this bit, write a 1 to it. The I2C module is reset.

INT CLR

1

The registers are ready to be accessed. In the nonrepeat mode (RM = 0 in I2CMDR): If STP = 0 in I2CMDR, the ARDY bit is set when the internal data counter counts down to 0. If STP = 1, ARDY is not affected (instead, the I2C module generates a STOP condition when the counter reaches 0). In the repeat mode (RM = 1): ARDY is set at the end of each data word transmitted from I2CDXR.

For CSL C macro implementation, use the notation I2C_I2CSTR_field_symval

TMS320C6000 CSL Registers

B-175

Inter-Integrated Circuit (I2C) Registers

Table B−146. I2C Status Register (I2CSTR) Field Values (Continued)
Bit 1 field† NACK symval† Value Description No-acknowledgement interrupt flag bit. NACK applies when the I2C module is a transmitter (master or slave). NACK indicates whether the I2C module has detected an acknowledge bit (ACK) or a no-acknowledge bit (NACK) from the receiver. The CPU can poll NACK or use the NACK interrupt request. NONE 0 ACK received/NACK is not received. This bit is cleared by any one of the following events:
-

An acknowledge bit (ACK) has been sent by the receiver. NACK is manually cleared. To clear this bit, write a 1 to it. The CPU reads the interrupt source register (I2CISR) when the register contains the code for a NACK interrupt. The I2C module is reset.

INT CLR

1

NACK bit is received. The hardware detects that a no-acknowledge (NACK) bit has been received. Note: While the I2C module performs a general call transfer, NACK is 1, even if one or more slaves send acknowledgement.

0

AL

Arbitration-lost interrupt flag bit (only applicable when the I2C module is a master-transmitter). AL primarily indicates when the I2C module has lost an arbitration contest with another master-transmitter. The CPU can poll AL or use the AL interrupt request. NONE 0 Arbitration is not lost. AL is cleared by any one of the following events:
-

AL is manually cleared. To clear this bit, write a 1 to it. The CPU reads the interrupt source register (I2CISR) when the register contains the code for an AL interrupt. The I2C module is reset.

INT CLR

1

Arbitration is lost. AL is set by any one of the following events:
-

The I2C module senses that it has lost an arbitration with two or more competing transmitters that started a transmission almost simultaneously. The I2C module attempts to start a transfer while the BB (bus busy) bit is set to 1.

-

When AL becomes 1, the MST and STP bits of I2CMDR are cleared, and the I2C module becomes a slave-receiver.

For CSL C macro implementation, use the notation I2C_I2CSTR_field_symval

B-176

TMS320C6000 CSL Registers

Inter-Integrated Circuit (I2C) Registers

B.9.4 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
When the I2C module is a master, the module clock is divided down for use as the master clock on the SCL pin. As shown in Figure B−140, the shape of the master clock depends on two divide-down values:
- ICCL in I2CCLKL (shown in Figure B−141 and described in Table B−147).

For each master clock cycle, ICCL determines the amount of time the signal is low.
- ICCH

in I2CCLKH (shown in Figure B−142 and described in Table B−148). For each master clock cycle, ICCH determines the amount of time the signal is high.

The frequency of the master clock can be calculated as: master clock frequency + module clock frequency ( ICCL ) 6 ) ) ( ICCH ) 6 )

Figure B−140. Roles of the Clock Divide-Down Values (ICCL and ICCH)
High-time duration: Tmod × (ICCH + 6)† High-time duration: Tmod × (ICCH + 6)†

SCL

Low-time duration: Tmod × (ICCL + 6)†

Low-time duration: Tmod × (ICCL + 6)†

Tmod = module clock period = 1 / module clock frequency

Figure B−141. I2C Clock Low-Time Divider Register (I2CCLKL)
31 Reserved R-0 15 ICCL R/W-0
Legend: R = Read only; R/W = Read/write; -n = value after reset

16

0

TMS320C6000 CSL Registers

B-177

Inter-Integrated Circuit (I2C) Registers

Table B−147. I2C Clock Low-Time Divider Register (I2CCLKL) Field Values
Bit 31−16 15−0 Field Reserved ICCL symval† − OF(value) Value 0 0−FFFFh Description These Reserved bit locations are always read as zeros. A value written to this field has no effect. Clock low-time divide-down value of 1−65536. The period of the module clock is multiplied by (ICCL + 6) to produce the low-time duration of the master clock on the SCL pin.

For CSL C macro implementation, use the notation I2C_I2CCLKL_ICCL_symval

Figure B−142. I2C Clock High-Time Divider Register (I2CCLKH)
31 Reserved R-0 15 ICCH R/W-0
Legend: R = Read only; R/W = Read/write; -n = value after reset

16

0

Table B−148. I2C Clock High-Time Divider Register (I2CCLKH) Field Values
Bit 31−16 15−0 Field Reserved ICCH symval† − OF(value) Value 0 0−FFFFh Description These Reserved bit locations are always read as zeros. A value written to this field has no effect. Clock high-time divide-down value of 1−65536. The period of the module clock is multiplied by (ICCH + 6) to produce the high-time duration of the master clock on the SCL pin.

For CSL C macro implementation, use the notation I2C_I2CCLKH_ICCH_symval

B-178

TMS320C6000 CSL Registers

Inter-Integrated Circuit (I2C) Registers

B.9.5 I2C Data Count Register (I2CCNT)
The I2C data count register (I2CCNT) is used to indicate how many data words to transfer when the I2C module is configured as a master-transmitter (MST = 1 and TRX = 1 in I2CMDR) and the repeat mode is off (RM = 0 in I2CMDR). In the repeat mode (RM = 1), I2CCNT is not used. The I2CCNT is shown in Figure B−143 and described in Table B−149. The value written to I2CCNT is copied to an internal data counter. The internal data counter is decremented by 1 for each data word transferred (I2CCNT remains unchanged). If a STOP condition is requested (STP = 1 in I2CMDR), the I2C module terminates the transfer with a STOP condition when the countdown is complete (that is, when the last data word has been transferred).

Figure B−143. I2C Data Count Register (I2CCNT)
31 Reserved R-0 15 ICDC R/W-0
Legend: R = Read only; R/W = Read/write; -n = value after reset

16

0

Table B−149. I2C Data Count Register (I2CCNT) Field Values
Bit 31−16 15−0 Field Reserved ICDC symval† − OF(value) Value 0 Description These Reserved bit locations are always read as zeros. A value written to this field has no effect. Data count value. ICDC indicates the number of data words to transfer in the nonrepeat mode (RM = 0 in I2CMDR). The value in I2CCNT is a don’t care when the RM bit in I2CMDR is set to 1. 0 The start value loaded to the internal data counter is 65536.

1h−FFFFh The start value loaded to internal data counter is 1−65535.

For CSL C macro implementation, use the notation I2C_I2CCNT_ICDC_symval

TMS320C6000 CSL Registers

B-179

Inter-Integrated Circuit (I2C) Registers

B.9.6 I2C Data Receive Register (I2CDRR)
The I2C data receive register (I2CDRR) is used by the DSP to read the receive data. The I2CDRR can receive a data value of up to 8 bits; data values with fewer than 8 bits are right-aligned in the D bits and the remaining D bits are undefined. The number of data bits is selected by the bit count bits (BC) of I2CMDR. The I2C receive shift register (I2CRSR) shifts in the received data from the SDA pin. Once data is complete, the I2C module copies the contents of I2CRSR into I2CDRR. The CPU and the EDMA controller cannot access I2CRSR. The I2CDRR is shown in Figure B−144 and described in Table B−150.

Figure B−144. I2C Data Receive Register (I2CDRR)
31 Reserved R-0 15 Reserved R-0
Legend: R = Read only; R/W = Read/write; -n = value after reset

16

8 7 D R/W-0

0

Table B−150. I2C Data Receive Register (I2CDRR) Field Values
Bit 31−8 7−0

Field Reserved D −

symval†

Value 0 0−FFh

Description These Reserved bit locations are always read as zeros. A value written to this field has no effect. Receive data.

OF(value)

For CSL C macro implementation, use the notation I2C_I2CDRR_D_symval

B-180

TMS320C6000 CSL Registers

Inter-Integrated Circuit (I2C) Registers

B.9.7 I2C Slave Address Register (I2CSAR)
The I2C slave address register (I2CSAR) contains a 7-bit or 10-bit slave address. When the I2C module is not using the free data format (FDF = 0 in I2CMDR), it uses this address to initiate data transfers with a slave or slaves. When the address is nonzero, the address is for a particular slave. When the address is 0, the address is a general call to all slaves. If the 7-bit addressing mode is selected (XA = 0 in I2CMDR), only bits 6−0 of I2CSAR are used; bits 9−7 are ignored. The I2CSAR is shown in Figure B−145 and described in Table B−151.

Figure B−145. I2C Slave Address Register (I2CSAR)
31 Reserved R-0 15 Reserved R-0
Legend: R = Read; W = Write; -n = Value after reset

16

10 9 A R/W-3FFh

0

Table B−151. I2C Slave Address Register (I2CSAR) Field Values
Bit 31−10 9−0 Field Reserved A symval† − OF(value) 0−7Fh Value 0 Description These Reserved bit locations are always read as zeros. A value written to this field has no effect. In 7-bit addressing mode (XA = 0 in I2CMDR): Bits 6−0 provide the 7-bit slave address that the I2C module transmits when it is in the master-transmitter mode. Bits 9−7 are ignored. In 10-bit addressing mode (XA = 1 in I2CMDR): 0−3FFh

Bits 9−0 provide the 10-bit slave address that the I2C module transmits when it is in the master-transmitter mode.

For CSL C macro implementation, use the notation I2C_I2CSAR_A_symval

TMS320C6000 CSL Registers

B-181

Inter-Integrated Circuit (I2C) Registers

B.9.8 I2C Data Transmit Register (I2CDXR)
The DSP writes transmit data to the I2C data transmit register (I2CDXR). The I2CDXR can accept a data value of up to 8 bits. When writing a data value with fewer than 8 bits, the DSP must make sure that the value is right-aligned in the D bits. The number of data bits is selected by the bit count bits (BC) of I2CMDR. Once data is written to I2CDXR, the I2C module copies the contents of I2CDXR into the I2C transmit shift register (I2CXSR). The I2CXSR shifts out the transmit data from the SDA pin. The CPU and the EDMA controller cannot access I2CXSR. The I2CDXR is shown in Figure B−146 and described in Table B−152.

Figure B−146. I2C Data Transmit Register (I2CDXR)
31 Reserved R-0 15 Reserved R-0
Legend: R = Read only; R/W = Read/write; -n = value after reset

16

8 7 D R/W-0

0

Table B−152. I2C Data Transmit Register (I2CDXR) Field Values
Bit 31−8 7−0

Field Reserved D −

symval†

Value 0 0−FFh

Description These Reserved bit locations are always read as zeros. A value written to this field has no effect. Transmit data

OF(value)

For CSL C macro implementation, use the notation I2C_I2CDXR_D_symval

B-182

TMS320C6000 CSL Registers

Inter-Integrated Circuit (I2C) Registers

B.9.9 I2C Mode Register (I2CMDR)
The I2C mode register (I2CMDR) contains the control bits of the I2C module.

The I2CMDR is shown in Figure B−147 and described in Table B−153.

Figure B−147. I2C Mode Register (I2CMDR)
31 Reserved R-0 15 NACKMOD R/W-0 7 RM R/W-0 14 FREE R/W-0 6 DLB R/W-0 13 STT R/W-0 5 IRS R/W-0 12 Reserved R-0 4 STB R/W-0 11 STP R/W-0 3 FDF R/W-0 2 BC R/W-0 10 MST R/W-0 9 TRX R/W-0 8 XA R/W-0 0 16

Legend: R/W = Read/write; -n = value after reset

Table B−153. I2C Mode Register (I2CMDR) Field Values
Bit 31−16 15 field† Reserved NACKMOD ACK 0 symval† − Value 0 Description These Reserved bit locations are always read as zeros. A value written to this field has no effect. NACK mode bit is only applicable when the I2C module is acting as a receiver. In slave-receiver mode: The I2C module sends an acknowledge (ACK) bit to the transmitter during the each acknowledge cycle on the bus. The I2C module only sends a no-acknowledge (NACK) bit if you set the NACKMOD bit. In master-receiver mode: The I2C module sends an ACK bit during each acknowledge cycle until the internal data counter counts down to 0. At that point, the I2C module sends a NACK bit to the transmitter. To have a NACK bit sent earlier, you must set the NACKMOD bit. NACK 1 In either slave-receiver or master-receiver mode: The I2C module sends a NACK bit to the transmitter during the next acknowledge cycle on the bus. Once the NACK bit has been sent, NACKMOD is cleared. To send a NACK bit in the next acknowledge cycle, you must set NACKMOD before the rising edge of the last data bit.

For CSL C macro implementation, use the notation I2C_I2CMDR_field_symval

TMS320C6000 CSL Registers

B-183

Inter-Integrated Circuit (I2C) Registers

Table B−153. I2C Mode Register (I2CMDR) Field Values (Continued)
Bit 14 field† FREE symval† Value Description This emulation mode bit is used to determine what the state of the I2C module will be when a breakpoint is encountered in the high-level language debugger. BSTOP 0 When I2C module is master: If SCL is low when the breakpoint occurs, the I2C module stops immediately and keeps driving SCL low, whether the I2C module is the transmitter or the receiver. If SCL is high, the I2C module waits until SCL becomes low and then stops. When I2C module is slave: A breakpoint forces the I2C module to stop when the current transmission/reception is complete. RFREE 13 STT 1 The I2C module runs free; that is, it continues to operate when a breakpoint occurs. START condition bit (only applicable when the I2C module is a master). The RM, STT, and STP bits determine when the I2C module starts and stops data transmissions (see Table B−154). Note that the STT and STP bits can be used to terminate the repeat mode. NONE 0 In the master mode, STT is automatically cleared after the START condition has been generated. In the slave mode, if STT is 0, the I2C module does not monitor the bus for commands from a master. As a result, the I2C module performs no data transfers. START 1 In the master mode, setting STT to 1 causes the I2C module to generate a START condition on the I2C-bus. In the slave mode, if STT is 1, the I2C module monitors the bus and transmits/receives data in response to commands from a master. 12

Reserved

0

This Reserved bit location is always read as zero. A value written to this field has no effect.

For CSL C macro implementation, use the notation I2C_I2CMDR_field_symval

B-184

TMS320C6000 CSL Registers

Inter-Integrated Circuit (I2C) Registers

Table B−153. I2C Mode Register (I2CMDR) Field Values (Continued)
Bit 11 field† STP symval† Value Description STOP condition bit (only applicable when the I2C module is a master). In the master mode, the RM, STT, and STP bits determine when the I2C module starts and stops data transmissions (see Table B−154). Note that the STT and STP bits can be used to terminate the repeat mode. NONE STOP 0 1 STP is automatically cleared after the STOP condition has been generated. STP has been set by the DSP to generate a STOP condition when the internal data counter of the I2C module counts down to 0. Master mode bit. MST determines whether the I2C module is in the slave mode or the master mode. MST is automatically changed from 1 to 0 when the I2C master generates a STOP condition. SLAVE MASTER 9 TRX 0 1 Slave mode. The I2C module is a slave and receives the serial clock from the master. Master mode. The I2C module is a master and generates the serial clock on the SCL pin. Transmitter mode bit. When relevant, TRX selects whether the I2C module is in the transmitter mode or the receiver mode. Table B−155 summarizes when TRX is used and when it is a don’t care. RCV XMT 8 XA 7BIT 0 0 1 Receiver mode. The I2C module is a receiver and receives data on the SDA pin. Transmitter mode. The I2C module is a transmitter and transmits data on the SDA pin. Expanded address enable bit. 7-bit addressing mode (normal address mode). The I2C module transmits 7-bit slave addresses (from bits 6−0 of I2CSAR), and its own slave address has 7 bits (bits 6−0 of I2COAR). 10-bit addressing mode (expanded address mode). The I2C module transmits 10-bit slave addresses (from bits 9−0 of I2CSAR), and its own slave address has 10 bits (bits 9−0 of I2COAR).

10

MST

10BIT

1

For CSL C macro implementation, use the notation I2C_I2CMDR_field_symval

TMS320C6000 CSL Registers

B-185

Inter-Integrated Circuit (I2C) Registers

Table B−153. I2C Mode Register (I2CMDR) Field Values (Continued)
Bit 7 field† RM symval† Value Description Repeat mode bit (only applicable when the I2C module is a master-transmitter). The RM, STT, and STP bits determine when the I2C module starts and stops data transmissions (see Table B−154). NONE 0 Nonrepeat mode. The value in the data count register (I2CCNT) determines how many data words are received/transmitted by the I2C module. Repeat mode. Data words are continuously received/transmitted by the I2C module until the STP bit is manually set to 1, regardless of the value in I2CCNT. Digital loopback mode bit. This bit disables or enables the digital loopback mode of the I2C module. The effects of this bit are shown in Figure B−148. Note that DLB in the free data format mode (DLB = 1 and FDF = 1) is not supported. NONE LOOPBACK 0 1 Digital loopback mode is disabled. Digital loopback mode is enabled. In this mode, the MST bit must be set to 1 and data transmitted out of I2CDXR is received in I2CDRR after n DSP cycles by an internal path, where: n = ((I2C input clock frequency/module clock frequency)  8) The transmit clock is also the receive clock. The address transmitted on the SDA pin is the address in I2COAR. 5 IRS RST NRST

REPEAD

1

6

DLB

I2C