You are on page 1of 40

A Presentation On

Two Stage Operational Amplifier
Summer term Basic Analog Design 20 April 2012

ELEC 2005

Outline

• • • • •

Op amp Topology Single Stage & Two stage Op amp Two stage Op amp Design Methodology Frequency Compensation for Two stage Op amp Low Voltage Techniques for Two stage Op amp

20 April 2012 ELEC 2005

VLSI Design

2

Op amp Topology
Type of op amp topology • Telescopic /Cascode op amp • Folded-Cascode op amp • Two Stage op amp • Gain Boosting op amp
Comparison of performance for various opamp topology

20 April 2012 ELEC 2005

VLSI Design

3

Analog Design Methodology
Define specifications

Extract Netlist, Parasitics from layout

Choose architecture
Layout Versus Schematic (LVS) check

Simulate schematic

Simulate schematic varying T, VDD, process parameters

Extracted schematic simulations

Masks layout

BLOCK DONE! In a complex design, this will be repeated for every block of the design hierarchy.
VLSI Design 4

Design Rules Check (DRC)

20 April 2012 ELEC 2005

Analog Design trade-offs NOISE LINEARITY POWER DISSIPATION GAIN INPUT/OUTPUT IMPEDANCE ANALOG DESIGN OCTAGON SUPPLY VOLTAGE SPEED 20 April 2012 ELEC 2005 VLSI Design VOLTAGE SWINGS 5 .

Outline • • • • • Op amp Topology Single Stage & Two stage Op amp Two stage Op amp Design Methodology Frequency Compensation for Two stage Op amp Low Voltage Techniques for Two stage Op amp 20 April 2012 ELEC 2005 VLSI Design 6 .

Single stage Differential Amplifier Why differential amplifier ? Fig 1 effect of supply noise :Single ended circuit double ended circuit • • Higher Immunity to ―environmental‖ noise Maximum achievable voltage swing. What happens if Vin1 and Vin2 experiences large common mode disturbance or do not have well defined common mode DC level ?. Sensitivity to the input common mode level 20 April 2012 ELEC 2005 VLSI Design 7 . Fig 2 Differential amplifier Fig 3.

• • • • • • A simple modification can resolve this issue. Put a current source at source terminal of both the transistor. Current source make ID1-ID2 independent of Vin. Required Infinite internal resistance of current source.cm. If Vin1=Vin2 .Single stage Differential Amplifier Conti. Fig 5 : Basic differential pair 20 April 2012 ELEC 2005 VLSI Design 8 . bias current of each transistor Iss/2 Assume RD1=RD2=RD Output common mode level is Vdd-RDIss/2 Fig 4 : Basic differential pair • • Current Source Realized by a nMOS transistor operating in saturation mode..

Differential Amplifier with MOS Loads Fig 6 : Differential pair with diode connected load Fig 7 :Differential pair with current source load 20 April 2012 ELEC 2005 VLSI Design 9 .

Second stage provide high output swing. Two stage Isolate Gain and output swing requirement Fig 8 : Two stage opamp with double ended output 20 April 2012 ELEC 2005 VLSI Design 10 .Two Stage Op amp with double ended Output • • • First stage provide high gain.

Two Stage Op amp with double ended Output • • • First stage provide high gain. Two stage Isolate Gain and output swing requirement • Second stage configured by a common pMOS source stage Fig 8 : Two stage opamp with double ended output 20 April 2012 ELEC 2005 VLSI Design 11 . Second stage provide high output swing.

Two Stage Op amp with double ended Output • • • First stage provide high gain. The first stage gain g m 2 (r2 || r4 ) Second Stage Gain g m6 (r6 || r8 ) • The swing at Vout2 VDD VDS 6 VDS 8 Fig 8 : Two stage opamp with double ended output 20 April 2012 ELEC 2005 VLSI Design 12 . Two stage Isolate Gain and output swing requirement • • • • Second stage configured by a common source stage Use Half circuit concept . Second stage provide high output swing.

Two Stage Op amp with Single ended Output How to convert Double ended Output to single ended Output ? • • Convert Differential current of the two output to a single ended voltage. This feature maintain differential nature of the first stage through current mirror M7 and M8 to generate a single ended output. Fig 9 : Two stage opamp with double ended output Fig 10 : Two stage opamp with single ended output 20 April 2012 ELEC 2005 VLSI Design 13 .

Outline • • • • • Op amp Topology Single Stage & Two stage Op amp Two stage Op amp Design Methodology Low Voltage Techniques for Two stage Op amp Frequency Compensation for Two stage Op amp 20 April 2012 ELEC 2005 VLSI Design 14 .

Fig.Two stage Op amp Design Methodology Two Stage Op amp Architecture What difference you have seen from the Previous Structure ? • • Left side common source not present Every Transistor represented by two transistor. 11. Two stage op amp topology 20 April 2012 ELEC 2005 VLSI Design 15 .

14.compound Transistor Pair Fig ..Two stage Op amp Design Methodology conti. Two Stage Op amp Architecture    Fig.13 Equivalent single Transistor[ Tranconductance(gm) Increases Output Impedance(ro) increases Ceq =C1+C2 Fig. Two stage op amp topology 20 April 2012 ELEC 2005 VLSI Design 16 . 12 .

convert complex circuit into its equivalent circuit.Two stage Op amp Design Methodology conti…. 16. Equivalent Configuration of figure 15. 15. 20 April 2012 ELEC 2005 VLSI Design 17 . To Calculate aspect ratio (W/L) simpler way . Bias Fig. Two stage op amp topology Fig. Two Stage Op amp Architecture   Need a biasing circuit.

17. Equivalent Configuration of figure 15 3. For Current Mirror 2I DS 3 2 K n (VG min VSS ) Fig. 4 VG1 m in 20 April 2012 ELEC 2005 V D1 VS1 VSD1 18 VLSI Design . For Input stage g m1 Ceq 2k P W L Ceq I SD1 1 GB W L W L 1.|VTo| W L 5 2 I SD5 K pV 2 SD5 B.Two stage Op amp Design Methodology conti…. A. For current source IM5 = SR Ceq VSD5 = VSG5-|VTo| =VDD-Vpb. 2 2 g m1 2 K p I SD1 C.

17. D. Equivalent Configuration of figure 15 20 April 2012 ELEC 2005 VLSI Design 19 . For Overall gain A g m 2 g m 6 R1 R2 Fig.Two stage Op amp Design Methodology conti…. For Common source Configuration I SD 7 W W L 7 I SD 5 L 5 I DS 6 I DS 7 I DS 6 W L W L 6 I DS 3 3 E.

Noise Issues in Op amp Total input noise currents 2 i0 2 2 gm1veq1 2 2 gm2veq2 2 2 gm3veq3 2 2 gm4veq4 Total input noise Voltage 2 g m3 2 2 2 2 2 veqT veq1 veq2 (veq3 veq4 ) 2 g m1 1. Thermal noise of Individual transistor is given by 8 KT 2 vThermal f 3g m W v 2 Total 4 KT 4 3 2 pCOX W L I D1 1 N 1 P L W L 3 f Fig: 18 Input stage to calculate Input referred noise. Input Referred Noise Flicker noise of Individual transistor is given by v 2 ker flic v 2 total k CoxWLf 2 K Pf K nf N 2 L1 1 W1 L1COX f K Pf P L2 3 2. 1 20 April 2012 ELEC 2005 VLSI Design 20 .

Orientation 2. Fabrication Process 20 April 2012 ELEC 2005 VLSI Design 21 .Noise Optimization in Op amp 1.

Outline • • • • • Op amp Type Single Stage & Two stage Op amp Two stage Op amp Design Methodology Frequency Compensation for Two stage Op amp Low Voltage Techniques for Two stage Op amp 20 April 2012 ELEC 2005 VLSI Design 22 .

• To control overshoot and ringing in the step response. Fig 20: Step response of a two-pole amplifier for various degrees of compensation 20 April 2012 ELEC 2005 VLSI Design 23 .Frequency Compensation What is Frequency Compensation ? • Compensation is a technique to enhance stability of op amp • Compensation is nothing but a negative feedback from output to input. • To stop Oscillation. Fig19: Inverting amplifier Why Frequency Compensation ? • To avoid the unintentional creation of positive feedback.

Understanding Parameters related to Stability 1. Unity gain frequency 4. Phase margin Fig 21 . Gain and Phase Plot 20 April 2012 ELEC 2005 VLSI Design 24 .Gain 2. Bandwidth 3.

Miller Compensation with nulling Resistor.Frequency Compensation Techniques Power and area efficient frequency compensation techniques     Miller Compensation . Miller Compensation with Current Buffer. 20 April 2012 ELEC 2005 VLSI Design 25 . Miller Compensation with Voltage Buffer.

a dominant pole and a RHP zero. Feed forward path is responsible for RHP Zero.Miller Compensation   Miller compensation is done with a capacitor. RHP pole reduces phase which in turn reduces stability. AV ( s Z 1 ) T (s) Transfer Function has form ( s P2 )( s P2 ) Z1  gm2 Cm Fig 22 :Miller Compensation Compensation creates a non dominating pole. In feedback. Fig 23 :Pole zero plot of Miller Compensation   20 April 2012 ELEC 2005 VLSI Design 26 .

Frequency Compensation Techniques Power and area efficient frequency compensation techniques are     Miller Compensation . Miller Compensation with Current Buffer. Miller Compensation with Voltage Buffer. Miller Compensation with nulling Resistor. 20 April 2012 ELEC 2005 VLSI Design 27 .

AV ( s Z 1 ) T (s) Transfer Function has form ( s P2 )( s P2 ) 1 Z1 1 Cm Rm gm2 Compensation creates a non dominating pole. Fig 25 :Pole zero plot of Miller Compensation  20 April 2012 ELEC 2005 VLSI Design 28 . Required more power and large area in IC. Fig 24 :MCNR   A large resistor value is required to eliminate zero. a dominant pole and a RHP zero.Miller Compensation with Nulling Resistor(MCNR)   MCNR is done with a Resistor series with a capacitor in feedback path.

Miller Compensation with nulling Resistor. Miller Compensation with Current Buffer.Frequency Compensation Techniques Power and area efficient frequency compensation techniques are     Miller Compensation . 20 April 2012 ELEC 2005 VLSI Design 29 . Miller Compensation with Voltage Buffer.

 Fig 27 :Pole zero plot of MCVB 20 April 2012 ELEC 2005 VLSI Design 30 .Miller Compensation with Voltage Buffer(MCVB)  MCVB is done with a capacitor in series with a voltage buffer. a dominant pole . Transfer Function has form T (s) AV ( s Z1 )( s Z 2 ) ( s P2 )( s P2 )( s P3 ) Fig 26 :MCVB  Z1 1 Cm Rb Z2 gm2 Cmb  Compensation creates two non dominating pole. a RHP zero and a LHP zero. Output swing decreases.

Miller Compensation with Current Buffer.Frequency Compensation Techniques Power and area efficient frequency compensation techniques are     Miller Compensation . Miller Compensation with Voltage Buffer. Miller Compensation with nulling Resistor. 20 April 2012 ELEC 2005 VLSI Design 31 .

Transfer Function has form T (s) AV ( s Z 1 ) ( s P2 )( s P2 )( s P3 ) Fig 28 :MCCB  P3 g m2 C gs 2 Z1 g mc Cm  Compensation creates two non dominating pole.  Current buffer stages do not require bias voltages. a dominant pole and a LH zero.Miller Compensation with Current Buffer(MCCB)  MCCB is done with a capacitor in series with a Current buffer. Fig 29 :Pole zero plot of MCCB 20 April 2012 ELEC 2005 VLSI Design 32 .

Frequency Compensation Comparisons Capacitor Resistor Area power Stability (degrees) SMC Large No high Moderate 45 MCNR Large Large More than SMC High 63 MCVB Large No High Moderate >60 MCCB Large No High Low >60 20 April 2012 ELEC 2005 VLSI Design 33 .

Outline • • • • • Op amp Type Single Stage & Two stage Op amp Two stage Op amp Design Methodology Frequency Compensation for Two stage Op amp Low Voltage Techniques for Two stage Op amp 20 April 2012 ELEC 2005 VLSI Design 34 .

3. Input Capacitance Depend on the input Bulk Bias 20 April 2012 ELEC 2005 VLSI Design 35 . 2.Low Voltage op amp Design Techniques Cont… 1. Bias voltage to the Bulk changes depletion region between the Bulk and substrate changes. Bulk-Driven Input Stage MOSFETs   Bulk terminal is used as a small signal input Threshold Voltage Modulates Tranconductance g mb diD dv BS gm 2 2 F VBS  Increases the input common mode voltage VBS Fig 30 : Bulk driven Input stage  produces a larger drain current Disadvantage : 1. Power dissipation Increase.

Fig 32 floating gate MOS VLSI Design 20 April 2012 ELEC 2005 36 . A bias dc voltage VG2 is applied at the lower gate and the signal is applied at the upper gate.Low Voltage op amp Design Techniques Cont… 2. Disadvantage : 1. Fabrication of floating Gate Transistor is difficult. Floating Gate MOS   Floating gate MOSFET is generally floating with an electrical charge. Tuning of threshold Voltage Possible  VT VT FG VG 2k1 k2  k1 = CG1/Ctot and k2 = CG2/Ctot Transconductance gain increases gm (eff) = k2gm(FG).

All transistors operating in saturation have the same overdrive voltage. Pseudo Cascode Compensation Technique   Compensation capacitance is divided into two half each of Cc/2 . No external bias circuit required for M 2a and M 3a Fig 34: Pseudo Cascode Compensation 20 April 2012 ELEC 2005 VLSI Design 37 . Lower power 3.Low Voltage op amp Design Techniques 3. Lower Vdd Fig 33: Classical Cascode Compensation 2.(Vov) 1.

Bandwidth. To enhance the stability Frequency compensation is essential. During op amp design care must have to be taken for input transistor pair to be matched in all circumstances. Noise. So through out this presentation . Their key features are analyzed and justified according to the corresponding Gain. area-and-power efficiency. 20 April 2012 ELEC 2005 VLSI Design 38 . Some low voltage analog design techniques are also discussed.Conclusion         So we have discussed a Two stage operation amplifier Design methodology. Among four type Current Buffer frequency compensation is best solution for stability enhancement.design of two stage operational amplifier is analyzed which is gives better output swing than telescopic and Folded op amp. Proper aspect ratio(W/L) have to maintain to get desired performance.

‖ IEEE Trans. vol. Circuits and systems—I: Fundam. T. vol. CMOS Analog Circuit Design.‖Thesis . Jan 2000. Sani and Anas A. Nov 2005. Hurst.M. Comer. 18 Feb 2011 . no. March 2011..― Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs. 46. Razavi.Layton.al. Lewis.‖ IEEE Trans.E. John P. and C. ―The utility of the active cascode in analog CMOS design. Carrillo et. [11] Ka Nang Leung and Philip K.‖ Active Capacitor Multiplier in Miller-Compensated circuits. P. H. Solid state circuits. Keane.‖ Two-Stage Operational Amplifiers: Power-and. [7] Zushu Yan.‖ Analysis of Multistage Amplifier–Frequency Compensation. Hamoui. [2] K. Sep 2001. Mahattanakul.al .Oxford University Press.Vol. Circuits and systems—II: vol 55.‖ Design Procedure for Two-Stage CMOS Operational Amplifiers Employing Current Buffer.C.D.Mak.‖ The International Journal of Electronics.no. 35. 1. 3.‖ Low Voltage Analog CMOS Architecture and Design Methods. [9] J.11. Dyer. vol. Circuits and systems—II:. of solid-state circuits. no.april 2007 [3] J. 2002 Papers: [1] M. 2001. J.Scalable two-Stage Op amp With Enhanced DC Gain an Settling Behavior in 65-nm Digital CMOS.‖ IEEE Trans.Brigham Young University.EooA. Analog Integrated circuit and Systems. pp.no. Rincon-Mora. Circuits and systems—I: Regular papers.‖ IEEE circuits and systems magazine.and Kenneth C.phd thesis . vol.―A Low Voltage Rail-to-rail OPAMP Design for Biomedical Signal FilteringApplications. [2] Willy.Area-Efficient Frequency Compensation for Driving a Wide Range of Capacitive Load. Design of Analog CMOS Integrated Circuits.‖ IEEE journal of Solid-State Circuits.Feb 2007 [5] D. Mok. and R. Martins. Farbod Aram. Comer. .August 2004 [6] Hwang-Cherng Chow and Pu-Nan Weng. vol. No.‖ IEICE Trans.2nd Edition . [12] Gabriel A. 48. [8] Alfio Dario Grasso. Analog Design Essential.no. Petrie. 9. no. 20 April 2012 ELEC 2005 VLSI Design 39 . 2.R. vol. no.‖ IEEE J. 491-502.‖ 1-V Rail-to-Rail CMOS OpAmp With Improved Bulk Driven Input Stage . 42. Yen et. Allen and D. S. Holberg.11. 91. ― 4th IEEE International Symposium on Electronic Design.‖ Low Voltage Analog circuit Design Techniques: A Tutorial. [10] Paul J. M. T.Nov 2008.Bibliography Books: [1] B. McGraw-Hill International Edition.2. March 2007 [4] S. Vol.52. Feb 2004. Theory Appl. ―Miller Compensation Using Current Buffers in Fully Differential CMOS Two-Stage Operational Amplifiers.‖ A 1-V Process-Insensitive Current.Sunsen . D.Test and application.― IEEE Trans. 2006 [3] P. 51.‖ IEEE Trans. Springer . 3.

THANK YOU 20 April 2012 ELEC 2005 VLSI Design 40 .