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write the function for parity calculation and show its invocation. Q3. Define a function to calculate the factorial of a 4-bit number. The output is a 32 bit value .Invoke the function by using stimulus and check result. Q4 Define a task to compute the even parity of a 16-bit number. The result is a 1 bit value .that is assigned to the output after three positive edges of clock. [hint: use a repeat loop in the task]. Q5. Define a task to compute the factorial of a 4-bit number. The output is a 32 bit value .the result is assigned to the output after a delay of 10 time units. Behavioral model Q1.
Q2.design a four bit binary counter uses behavioral modeling. Q3.declare a register called oscillate. Initialize it to 0 and make it toggle every 30 time units. Do not use always statement [Hint : use the forever loop] Q4.design a clock with time period =40 and a duty cycle of 25% by using the always and initial statements. The value of clock at time =0 should be initialized to 0. Q5.Compare the blocking and non blocking statements with examples.
differentaite between initial and always block with examples.Give the significance of zero delay with examples. Q8. Q7. . Data flow model: Q1.differentaite timing control delay and event based delays with examples. Q2. In which you have to use the event OR control and timing delay of (number. Give the significance of case x and case z with suitable examples. Q12. Q11. Q9.Q6. Q10. Verilog code for ripple carry adder using data flow model. Write a Verilog code of level sensitive D latch with asynchronous reset.4-bit full adder with carry looks ahead adder using data flow model. identifier and expression).
define delays: a) Net declaration b) Implicit continuous assignment delay c) Regular assignment delay Gate model Q1. .1:2:3) using gate model . -10/5=? Which operator is used in this statement? Q5.Q3.also apply stimulus for the above circuits. decoder etc using delays (3:2:4. 4: 1 and 8:1 mux using data flow model.T flipflop using dealys (3:2:4. Q4.subtractors.2:4:5.1:2:3) using gate model . Write Verilog code for adder .. mux. Q2.also apply stimulus for the above flipflops. encoder. Q3. demus. Eg: X= 10011010 Fine all reduction operators of the above data.write Verilog code for D.2:4:5. All operators name and function.