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High-Level Design Laboratory
Exercise 1: Hardware Counter
1. As a consequence. is comprised of a number of conveyor belts.g. rotary tables. The exercises should provide the necessary background for the project and consist of implementing very simple applications using the diﬀerent tools. 1. we use high-level tools for developing embedded applications. we will use Xilinx tools to develop the applications in this lab. Figure 1: Model plant used in the HLD lab: baking line This lab is organized in three exercises and a project. In this manner. silos. etc. conﬁguration tables. Xilinx EDK (Embedded Development Kit). etc. The project then covers the most of the lab and is about automating a model plant. 2.1 Introduction In the High-Level Design (HLD) Laboratory.1 Processing platform In this lab we use an FPGA board from Xilinx. automata.. These tools allow abstracting the design process from the code implementation. The baking line. as shown in Fig. which is based on a Xilinx Virtex 5 FPGA.). we use the XC5VLX110T board shown in Fig. the designers can focus on the functional part of an application and do not need to spend much time in programming on their own. speciﬁcally a baking line. a mixer and a oven. Xilinx SDK (Software Development Kit). Among these tools we have Xilinx ISE (Integrated Software Environment). that need to be controlled – more details about the project will be given later. In particular. The necessary code is then generated by the high-level tools from abstract models of the applications (e. The FPGA board is 1 .
For this purpose. provides some hardware required in this lab such as an A/D converter.1 Homework To be able to do this exercise in the lab. 2 . 3. Exercise 1. we will be using the Xilinx Integrated Software Environment (ISE).e. Please consider that you will not have enough time to read the documentation during the class and that you should be well prepared in order to ﬁnish the exercise on time.Figure 2: Xilinx FPGA board: XC5VLX110T connected to the baking line through a number of boards. This switch should be turned oﬀ for all exercises (i. 2 Exercise 1: Hardware Counter The ﬁrst exercise consists of implementing an 8-bit counter in VHDL. Further. IMPORTANT: The HLD board has an emergency-oﬀ switch that separates the baking line from the FPGA board. 2. In principle. 2 and 3) and only be turned on again for the project. LEDs and buttons (separated from those of the FPGA board itself). these boards are responsible for adapting signals from the baking line to the FPGA. you should go through some documentation before coming to the ﬁrst class of the lab. The other Xilinx tools are closely related to ISE and will be introduced in the following exercises as they become necessary.. one of these boards. the HLD board shown in Fig.
e. following features should be implemented: • The output of the counter should be assigned to the LEDs provided on the HLD board.e. • ISE In-Depth Tutorial (version 12. This way. Chapter 4. 2 and 7 of the ISE In-Depth Tutorial is required for implementing the 8-bit hardware counter (i. The purpose here is to roughly understand the development process with ISE – you are not supposed to learn anything by heart. These are suggested sequences of chapters to learn speciﬁc design techniques using ISE.e.Figure 3: The HLD board • Virtex-5 Family Overview: This is less critical for the lab. 5 and 6) are also interesting but their reading is only optional in the context of the lab. In addition. an 8-bit counter should be implemented entirely in VHDL...2 Description As mentioned above. The counter counts pulses (i. However. we recommend you to take a brief look at the description of the Virtex-5 family. you do not need to read all chapters but Chapter 1. However. zero to one transitions) of an input signal.. exercise 1). 2 and 7. 2. to be aware of the characteristics of the FPGA board used here. The remaining chapters of the HDL Design Flow (i.3): The reading of Chapter 1. You will notice that the ISE In-Depth Tutorial is organized into three tutorial ﬂows. for the purpose of doing exercise 1 in this lab. The tutorial ﬂow needed for the ﬁrst exercise (and in general for whole lab) is HDL Design Flow. the counting state can be visualized on the LEDs. 3 .
If this button is pressed once. That is.. to allow visualizing the counting state on the LEDs.e. The counter should start/continue counting when this button is pressed once. • A fourth button should change the frequency of the counter’s input signal. this frequency should be scaled down to 10Hz.. it should be possible to change the frequency of the input signal while counting. 4 . In addition. the counter should continue counting from zero again.e. If this button is pressed once.reset button pressed FPGA . stop. speed and reset Figure 4: Hardware 8-bit counter • The input signal should be derived from the clock signal of the FPGA board. either ERROR LED 1 or ERROR LED 2 – these are the names of the signals provided in toplevel. This button should neither aﬀect the counting state and it should work independently of whether the counter is currently counting or not. At overﬂow.toplevel ERROR_LED_1 clk_100MHz clk_gen counter LEDS BUTTONS 8-bit counting state start. 10Hz). The stop button should not aﬀect the current counting state. one of the LEDs on the FPGA board (i. After a reset the counter is set at zero and it only starts counting again when the start/continue button is pressed. the counter can be restarted by pressing the start/continue button. As a result. • A third button should reset the counter. • A second button on the HLD board should be used to stop the counter.vhd – more information below) should be activated while the reset button is being pressed. the frequency of the input signal should be reduced to 1Hz. Pressing this button a second time. The clock of the FPGA board has a frequency of 100MHz. the input signal goes back to its initial frequency (i. • One of the buttons on the HLD board should be used to start the counter.
You can proceed exactly in the same manner for adding pinout. In particular. The ﬁle toplevel. create a new project by clicking on the menu File and then on New Project or just click on the quick access button New Project.. 7. whereas pinout.ucf (i.vhd from the existing exercise 1 directory in your home. To include these ﬁles. Further. 6. Then select the toplevel.3 Getting started To start Xilinx ISE. The remaining properties are per default set to the values shown in the ﬁgure. 5. user constraints ﬁle) provides the mapping of VHDL signals to FPGA ports. then click on the OK button of this window.. select Family to be Virtex 5 and Device to be XC5VLX110T according to the used FPGA board.4 generates the input signal for the second block counter.4. This opens up the following window shown in Fig.Figure 5: New project A schematic representation of the hardware counter is shown in Fig.vhd is the ﬁrst hierarchy level of the project.e. 2. click on the menu Project and then on Add Source. Clicking on Next once again will bring you to the Project Summary window. There if you click on the Finish button. The block clk gen in Fig. click on the Next button of the window of Fig. The property Package here should be set to FF1136 as shown in Fig. The project name should be exercise 1 and the top-level source type should be HDL as shown in Fig.ucf to your project. VHDL modules) are recommended. your project will be created. 5 and conﬁgure the project properties as shown in Fig. 5 .e. double click on the ISE icon that you will ﬁnd on the desktop after log-in. Now. 6. Here two separated blocks (i. Two source ﬁles are given for this ﬁrst exercise and should be included in your VHDL project. whereas the block counter implements the 8-bit hardware counter itself required in this exercise.
it contains an entity called hld test that is necessary for performing this ﬁrst exercise. you will not be able to modify it). Now. 8 opens up. For this purpose. you can add new source ﬁles to your project. The window of Fig. you will need to create your own VHDL ﬁle which you then can modify and where you can instantiate hld test accordingly. However..e. you will need to add two new source ﬁles.e. So. Figure 7: Add source ﬁle 6 . Click on the menu Project and then on New Source. two separated VHDL modules) clk gen and counter. which consists of two separated blocks (i. We recommend using the structure shown in Fig. 4.vhd is read-only (i.Figure 6: Project settings HINT: The ﬁle toplevel.. to make use of hld test.
you can proceed to add a new source ﬁle called counter according to the block diagram suggested in Fig. 9 not all I/O ports are shown that might be required for implementing the whole functionality of the counter. Once you have added all source ﬁles to your project. 4. You can verify that your project can be synthesized using XST (Xilinx Synthesis Technology). After clicking on the button Next. you need to generate the programming ﬁle out of your ISE project. There you can deﬁne input and output (I/O) ports for the module clk gen. Further. Notice that in Fig. the window of Fig. to program the FPGA. you can edit them by double clicking on the desired ﬁle name in the Hierarchy Pane – normally in the left upper corner of the ISE software framework.Figure 8: Add new source ﬁle where you can select the name and type of the new source. In a similar manner. The programming ﬁle can then Figure 9: Deﬁne I/O ports clk gen 7 . 9 appears.
select the bitstream ﬁle toplevel. The generation of the programming ﬁle may take a few minutes. Notice that the FPGA board should be turned on and connected to the PC using the JTAG cable. Once the programming ﬁle has been ﬁnished without errors. Finally. where you can select the device which to assign a conﬁguration ﬁle to. In the iMPACT Flows Pane. you can start iMPACT by double clicking on Conﬁgure Target Device.. right click on the icon of the xc5vlx110t device and select program.bit that was generated from your project – this is normally in the project directory. The main windows of iMPACT should by now be updated as shown in Fig.e.Figure 10: Programming the FPGA board be downloaded to the FPGA using iMPACT. but we will not use any in this lab.vhd in the Hierarchy Pane and then double click on Generate Programming File in the Processes Pane. A new popup window appears. Click on the Bypass button until the device xc5vlx110t is highlighted in green. In order to generate the programming ﬁle. click on the Boundary Scan and then start the Initialize Chain process. 10. The programming takes a few seconds. i. The device we are using supports attached PROMs. in the exercise 1 directory existing in your home. 8 . Now. select toplevel. Continue assigning conﬁguration ﬁles by clicking on Yes button in the pop-up window.
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