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 2003 Microchip Technology Inc.

DS39582B
PIC16F87XA
Data Sheet
28/40/44-Pin Enhanced Flash
Microcontrollers
DS39582B-page ii  2003 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
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components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
®
8-bit MCUs, KEELOQ
®
code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2003 Microchip Technology Inc. DS39582B-page 1
PIC16F87XA
Devices Included in this Data Sheet:
High-Performance RISC CPU:
• Only 35 single-word instructions to learn
• All single-cycle instructions except for program
branches, which are two-cycle
• Operating speed: DC – 20 MHz clock input
DC – 200 ns instruction cycle
• Up to 8K x 14 words of Flash Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM),
Up to 256 x 8 bytes of EEPROM Data Memory
• Pinout compatible to other 28-pin or 40/44-pin
PIC16CXXX and PIC16FXXX microcontrollers
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during Sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Synchronous Serial Port (SSP) with SPI™
(Master mode) and I
2
C™

(Master/Slave)
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Parallel Slave Port (PSP) – 8 bits wide with
external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
Analog Features:
• 10-bit, up to 8-channel Analog-to-Digital
Converter (A/D)
• Brown-out Reset (BOR)
• Analog Comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs are externally accessible
Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Data EEPROM Retention > 40 years
• Self-reprogrammable under software control
• In-Circuit Serial Programming™ (ICSP™)
via two pins
• Single-supply 5V In-Circuit Serial Programming
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator options
• In-Circuit Debug (ICD) via two pins
CMOS Technology:
• Low-power, high-speed Flash/EEPROM
technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption
• PIC16F873A
• PIC16F874A
• PIC16F876A
• PIC16F877A
Device
Program Memory
Data
SRAM
(Bytes)
EEPROM
(Bytes)
I/O
10-bit
A/D (ch)
CCP
(PWM)
MSSP
USART
Timers
8/16-bit
Comparators
Bytes
# Single Word
Instructions
SPI
Master
I
2
C
PIC16F873A 7.2K 4096 192 128 22 5 2 Yes Yes Yes 2/1 2
PIC16F874A 7.2K 4096 192 128 33 8 2 Yes Yes Yes 2/1 2
PIC16F876A 14.3K 8192 368 256 22 5 2 Yes Yes Yes 2/1 2
PIC16F877A 14.3K 8192 368 256 33 8 2 Yes Yes Yes 2/1 2
28/40/44-Pin Enhanced Flash Microcontrollers
PIC16F87XA
DS39582B-page 2  2003 Microchip Technology Inc.
Pin Diagrams
P
I
C
1
6
F
8
7
3
A
/
8
7
6
A
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
28-Pin PDIP, SOIC, SSOP
2
3
4
5
6
1
7
M
C
L
R
/
V
P
P
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
OSC1/CLKI
15
16
17
18
19
20
21 RB3/PGM
VDD
VSS
RB0/INT
RC7/RX/DT
R
C
1
/
T
1
O
S
I
/
C
C
P
2
R
C
2
/
C
C
P
1
R
C
3
/
S
C
K
/
S
C
L
R
C
4
/
S
D
I
/
S
D
A
R
C
5
/
S
D
O
R
C
6
/
T
X
/
C
K
2
3
2
4
2
5
2
6
2
7
2
8
2
2
R
A
1
/
A
N
1
R
A
0
/
A
N
0
R
B
7
/
P
G
D
R
B
6
/
P
G
C
R
B
5
R
B
4
1
0
1
1
8 9 1
2
1
3
1
4
28-Pin QFN
PIC16F873A
PIC16F876A
RB2
RB1
R
C
0
/
T
1
O
S
O
/
T
1
C
K
I
OSC2/CLKO
10
11
2
3
4
5
6
1
1
8
1
9
2
0
2
1
2
2
1
2
1
3
1
4
1
5
3
8
8
7
4
4
4
3
4
2
4
1
4
0
3
9
1
6
1
7
29
30
31
32
33
23
24
25
26
27
28
3
6
3
4
3
5
9
PIC16F874A
3
7
R
A
3
/
A
N
3
/
V
R
E
F
+
R
A
2
/
A
N
2
/
V
R
E
F
-
/
C
V
R
E
F
R
A
1
/
A
N
1
R
A
0
/
A
N
0
M
C
L
R
/
V
P
P
R
B
3
/
P
G
M
R
B
7
/
P
G
D
R
B
6
/
P
G
C
R
B
5
R
B
4
N
C
R
C
6
/
T
X
/
C
K
R
C
5
/
S
D
O
R
C
4
/
S
D
I
/
S
D
A
R
D
3
/
P
S
P
3
R
D
2
/
P
S
P
2
R
D
1
/
P
S
P
1
R
D
0
/
P
S
P
0
R
C
3
/
S
C
K
/
S
C
L
R
C
2
/
C
C
P
1
R
C
1
/
T
1
O
S
I
/
C
C
P
2
R
C
0
/
T
1
O
S
O
/
T
1
C
K
I
OSC2/CLKO
OSC1/CLKI
VSS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
VDD
RB0/INT
RB1
RB2
44-Pin QFN
PIC16F877A
 2003 Microchip Technology Inc. DS39582B-page 3
PIC16F87XA
Pin Diagrams (Continued)
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P
I
C
1
6
F
8
7
4
A
/
8
7
7
A
40-Pin PDIP
10
11
12
13
14
15
16
17
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
4
4
8
7
6 5 4 3 2 1
2
7
2
8
29
30
31
32
33
34
35
36
37
38
39
4
0
4
1
4
2
4
3
9
PIC16F874A
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CK1
NC
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
R
A
3
/
A
N
3
/
V
R
E
F
+
R
A
2
/
A
N
2
/
V
R
E
F
-
/
C
V
R
E
F
R
A
1
/
A
N
1
R
A
0
/
A
N
0
M
C
L
R
/
V
P
P
N
C
R
B
7
/
P
G
D
R
B
6
/
P
G
C
R
B
5
R
B
4
N
C
N
C
R
C
6
/
T
X
/
C
K
R
C
5
/
S
D
O
R
C
4
/
S
D
I
/
S
D
A
R
D
3
/
P
S
P
3
R
D
2
/
P
S
P
2
R
D
1
/
P
S
P
1
R
D
0
/
P
S
P
0
R
C
3
/
S
C
K
/
S
C
L
R
C
2
/
C
C
P
1
R
C
1
/
T
1
O
S
I
/
C
C
P
2
10
11
2
3
4
5
6
1
1
8
1
9
2
0
2
1
2
2
1
2
1
3
1
4
1
5
3
8
8
7
4
4
4
3
4
2
4
1
4
0
3
9
1
6
1
7
29
30
31
32
33
23
24
25
26
27
28
3
6
3
4
3
5
9
PIC16F874A
3
7
R
A
3
/
A
N
3
/
V
R
E
F
+
R
A
2
/
A
N
2
/
V
R
E
F
-
/
C
V
R
E
F
R
A
1
/
A
N
1
R
A
0
/
A
N
0
M
C
L
R
/
V
P
P
N
C
R
B
7
/
P
G
D
R
B
6
/
P
G
C
R
B
5
R
B
4
N
C
R
C
6
/
T
X
/
C
K
R
C
5
/
S
D
O
R
C
4
/
S
D
I
/
S
D
A
R
D
3
/
P
S
P
3
R
D
2
/
P
S
P
2
R
D
1
/
P
S
P
1
R
D
0
/
P
S
P
0
R
C
3
/
S
C
K
/
S
C
L
R
C
2
/
C
C
P
1
R
C
1
/
T
1
O
S
I
/
C
C
P
2
N
C
NC
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
44-Pin PLCC
44-Pin TQFP
PIC16F877A
PIC16F877A
RC7/RX/DT
PIC16F87XA
DS39582B-page 4  2003 Microchip Technology Inc.
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................ 15
3.0 Data EEPROM and Flash Program Memory ............................................................................................................................ 33
4.0 I/O Ports.................................................................................................................................................................................... 41
5.0 Timer0 Module.......................................................................................................................................................................... 53
6.0 Timer1 Module.......................................................................................................................................................................... 57
7.0 Timer2 Module.......................................................................................................................................................................... 61
8.0 Capture/Compare/PWM Modules............................................................................................................................................. 63
9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 71
10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................ 111
11.0 Analog-to-Digital Converter (A/D) Module .............................................................................................................................. 127
12.0 Comparator Module ................................................................................................................................................................ 135
13.0 Comparator Voltage Reference Module ................................................................................................................................. 141
14.0 Special Features of the CPU .................................................................................................................................................. 143
15.0 Instruction Set Summary......................................................................................................................................................... 159
16.0 Development Support ............................................................................................................................................................. 167
17.0 Electrical Characteristics......................................................................................................................................................... 173
18.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 197
19.0 Packaging Information ............................................................................................................................................................ 209
Appendix A: Revision History ............................................................................................................................................................ 219
Appendix B: Device Differences........................................................................................................................................................ 219
Appendix C: Conversion Considerations........................................................................................................................................... 220
Index ................................................................................................................................................................................................. 221
On-Line Support ................................................................................................................................................................................ 229
Systems Information and Upgrade Hot Line ..................................................................................................................................... 229
Reader Response ............................................................................................................................................................................. 230
PIC16F87XA Product Identification System...................................................................................................................................... 231
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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 2003 Microchip Technology Inc. DS39582B-page 5
PIC16F87XA
1.0 DEVICE OVERVIEW
This document contains device specific information
about the following devices:
• PIC16F873A
• PIC16F874A
• PIC16F876A
• PIC16F877A
PIC16F873A/876A devices are available only in 28-pin
packages, while PIC16F874A/877A devices are avail-
able in 40-pin and 44-pin packages. All devices in the
PIC16F87XA family share common architecture with
the following differences:
• The PIC16F873A and PIC16F874A have one-half
of the total on-chip memory of the PIC16F876A
and PIC16F877A
• The 28-pin devices have three I/O ports, while the
40/44-pin devices have five
• The 28-pin devices have fourteen interrupts, while
the 40/44-pin devices have fifteen
• The 28-pin devices have five A/D input channels,
while the 40/44-pin devices have eight
• The Parallel Slave Port is implemented only on
the 40/44-pin devices
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F873A/876A and
PIC16F874A/877A devices are provided in Figure 1-1
and Figure 1-2, respectively. The pinouts for these
device families are listed in Table 1-2 and Table 1-3.
Additional information may be found in the PICmicro
®
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip web site. The
Reference Manual should be considered a complemen-
tary document to this data sheet and is highly recom-
mended reading for a better understanding of the device
architecture and operation of the peripheral modules.
TABLE 1-1: PIC16F87XA DEVICE FEATURES
Key Features PIC16F873A PIC16F874A PIC16F876A PIC16F877A
Operating Frequency DC – 20 MHz DC – 20 MHz DC – 20 MHz DC – 20 MHz
Resets (and Delays) POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
Flash Program Memory
(14-bit words)
4K 4K 8K 8K
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Timers 3 3 3 3
Capture/Compare/PWM modules 2 2 2 2
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Analog Comparators 2 2 2 2
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packages 28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
PIC16F87XA
DS39582B-page 6  2003 Microchip Technology Inc.
FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM
Flash
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
Status reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RB0/INT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
8
Brown-out
Reset
Note 1: Higher order bits are from the Status register.
USART CCP1,2
Synchronous
10-bit A/D Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
8
3
Data EEPROM
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
In-Circuit
Debugger
Low-Voltage
Programming
Comparator
Voltage
Reference
Device Program Flash Data Memory Data EEPROM
PIC16F873A 4K words 192 Bytes 128 Bytes
PIC16F876A 8K words 368 Bytes 256 Bytes
Program
Memory
 2003 Microchip Technology Inc. DS39582B-page 7
PIC16F87XA
FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
Status reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
8
Brown-out
Reset
Note 1: Higher order bits are from the Status register.
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
Parallel
8
3
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
In-Circuit
Debugger
Low-Voltage
Programming
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
USART CCP1,2
Synchronous
10-bit A/D Timer0 Timer1 Timer2
Serial Port
Data EEPROM Comparator
Voltage
Reference
Device Program Flash Data Memory Data EEPROM
PIC16F874A 4K words 192 Bytes 128 Bytes
PIC16F877A 8K words 368 Bytes 256 Bytes
Flash
Program
Memory
Slave Port
PIC16F87XA
DS39582B-page 8  2003 Microchip Technology Inc.
TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION
Pin Name
PDIP, SOIC,
SSOP Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
OSC1/CLKI
OSC1
CLKI
9
6
I
I
ST/CMOS
(3)
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode; otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
OSC2/CLKO
OSC2
CLKO
10 7
O
O
— Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
MCLR/VPP
MCLR
VPP
1 26
I
P
ST Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active low Reset
to the device.
Programming voltage input.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2 27
I/O
I
TTL
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3 28
I/O
I
TTL
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREF-
CVREF
4 1
I/O
I
I
O
TTL
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator VREF output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5 2
I/O
I
I
TTL
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6 3
I/O
I
O
ST
Digital I/O – Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
RA5/AN4/SS/C2OUT
RA5
AN4
SS
C2OUT
7 4
I/O
I
I
O
TTL
Digital I/O.
Analog input 4.
SPI slave select input.
Comparator 2 output.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
 2003 Microchip Technology Inc. DS39582B-page 9
PIC16F87XA
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT
RB0
INT
21 18
I/O
I
TTL/ST
(1)
Digital I/O.
External interrupt.
RB1 22 19 I/O TTL Digital I/O.
RB2 23 20 I/O TTL Digital I/O.
RB3/PGM
RB3
PGM
24 21
I/O
I
TTL
Digital I/O.
Low-voltage (single-supply) ICSP programming enable pin.
RB4 25 22 I/O TTL Digital I/O.
RB5 26 23 I/O TTL Digital I/O.
RB6/PGC
RB6
PGC
27 24
I/O
I
TTL/ST
(2)
Digital I/O.
In-circuit debugger and ICSP programming clock.
RB7/PGD
RB7
PGD
28 25
I/O
I/O
TTL/ST
(2)
Digital I/O.
In-circuit debugger and ICSP programming data.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 8
I/O
O
I
ST
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
12 9
I/O
I
I/O
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
13 10
I/O
I/O
ST
Digital I/O.
Capture1 input, Compare1 output, PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 11
I/O
I/O
I/O
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C mode.
RC4/SDI/SDA
RC4
SDI
SDA
15 12
I/O
I
I/O
ST
Digital I/O.
SPI data in.
I
2
C data I/O.
RC5/SDO
RC5
SDO
16 13
I/O
O
ST
Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
17 14
I/O
O
I/O
ST
Digital I/O.
USART asynchronous transmit.
USART1 synchronous clock.
RC7/RX/DT
RC7
RX
DT
18 15
I/O
I
I/O
ST
Digital I/O.
USART asynchronous receive.
USART synchronous data.
VSS 8, 19 5, 6 P — Ground reference for logic and I/O pins.
VDD 20 17 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED)
Pin Name
PDIP, SOIC,
SSOP Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PIC16F87XA
DS39582B-page 10  2003 Microchip Technology Inc.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION
Pin Name
PDIP
Pin#
PLCC
Pin#
TQFP
Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
OSC1/CLKI
OSC1
CLKI
13 14 30 32
I
I
ST/CMOS
(4)
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
otherwise CMOS.
External clock source input. Always associated
with pin function OSC1 (see OSC1/CLKI,
OSC2/CLKO pins).
OSC2/CLKO
OSC2
CLKO
14 15 31 33
O
O
— Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal
Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
MCLR/VPP
MCLR
VPP
1 2 18 18
I
P
ST Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active
low Reset to the device.
Programming voltage input.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2 3 19 19
I/O
I
TTL
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3 4 20 20
I/O
I
TTL
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
4 5 21 21
I/O
I
I
O
TTL
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator VREF output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5 6 22 22
I/O
I
I
TTL
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6 7 23 23
I/O
I
O
ST
Digital I/O – Open-drain when configured as
output.
Timer0 external clock input.
Comparator 1 output.
RA5/AN4/SS/C2OUT
RA5
AN4
SS
C2OUT
7 8 24 24
I/O
I
I
O
TTL
Digital I/O.
Analog input 4.
SPI slave select input.
Comparator 2 output.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
 2003 Microchip Technology Inc. DS39582B-page 11
PIC16F87XA
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT
RB0
INT
33 36 8 9
I/O
I
TTL/ST
(1)
Digital I/O.
External interrupt.
RB1 34 37 9 10 I/O TTL Digital I/O.
RB2 35 38 10 11 I/O TTL Digital I/O.
RB3/PGM
RB3
PGM
36 39 11 12
I/O
I
TTL
Digital I/O.
Low-voltage ICSP programming enable pin.
RB4 37 41 14 14 I/O TTL Digital I/O.
RB5 38 42 15 15 I/O TTL Digital I/O.
RB6/PGC
RB6
PGC
39 43 16 16
I/O
I
TTL/ST
(2)
Digital I/O.
In-circuit debugger and ICSP programming clock.
RB7/PGD
RB7
PGD
40 44 17 17
I/O
I/O
TTL/ST
(2)
Digital I/O.
In-circuit debugger and ICSP programming data.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
Pin Name
PDIP
Pin#
PLCC
Pin#
TQFP
Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PIC16F87XA
DS39582B-page 36  2003 Microchip Technology Inc.
3.5 Reading Flash Program Memory
To read a program memory location, the user must write
two bytes of the address to the EEADR and EEADRH
registers, set the EEPGD control bit (EECON1<7>) and
then set control bit RD (EECON1<0>). Once the read
control bit is set, the program memory Flash controller
will use the next two instruction cycles to read the data.
This causes these two instructions immediately follow-
ing the “BSF EECON1, RD” instruction to be ignored.
The data is available in the very next cycle in the
EEDATA and EEDATH registers; therefore, it can be
read as two bytes in the following instructions. EEDATA
and EEDATH registers will hold this value until another
read or until it is written to by the user (during a write
operation).
EXAMPLE 3-3: FLASH PROGRAM READ
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Ba nk 2
MOVLW MS_PROG_EE_ADDR ;
MOVWF EEADRH ; MS Byt e of Pr ogr a m Addr e s s t o r e a d
MOVLW LS_PROG_EE_ADDR ;
MOVWF EEADR ; LS Byt e of Pr ogr a m Addr e s s t o r e a d
BSF STATUS, RP0 ; Ba nk 3
BSF EECON1, EEPGD ; Poi nt t o PROGRAM me mor y
BSF EECON1, RD ; EE Re a d
;
NOP
NOP ; Any i ns t r uc t i ons he r e a r e i gnor e d a s pr ogr a m
; me mor y i s r e a d i n s e c ond c yc l e a f t e r BSF EECON1, RD
;
BCF STATUS, RP0 ; Ba nk 2
MOVF EEDATA, W ; W= LS Byt e of Pr ogr a m EEDATA
MOVWF DATAL ;
MOVF EEDATH, W ; W= MS Byt e of Pr ogr a m EEDATA
MOVWF DATAH ;
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 2003 Microchip Technology Inc. DS39582B-page 37
PIC16F87XA
3.6 Writing to Flash Program Memory
Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT1:WRT0 of
the device configuration word (Register 14-1). Flash
program memory must be written in four-word blocks. A
block consists of four words with sequential addresses,
with a lower boundary defined by an address, where
EEADR<1:0> = 00. At the same time, all block writes to
program memory are done as erase and write opera-
tions. The write operation is edge-aligned and cannot
occur across boundaries.
To write program data, it must first be loaded into the
buffer registers (see Figure 3-1). This is accomplished
by first writing the destination address to EEADR and
EEADRH and then writing the data to EEDATA and
EEDATH. After the address and data have been set up,
then the following sequence of events must be
executed:
1. Set the EEPGD control bit (EECON1<7>).
2. Write 55h, then AAh, to EECON2 (Flash
programming sequence).
3. Set the WR control bit (EECON1<1>).
All four buffer register locations MUST be written to with
correct data. If only one, two or three words are being
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the pro-
gram location(s) not being written and loads it into the
EEDATA and EEDATH registers. Then the sequence of
events to transfer data to the buffer registers must be
executed.
To transfer data from the buffer registers to the program
memory, the EEADR and EEADRH must point to the last
location in the four-word block (EEADR<1:0> = 11).
Then the following sequence of events must be
executed:
1. Set the EEPGD control bit (EECON1<7>).
2. Write 55h, then AAh, to EECON2 (Flash
programming sequence).
3. Set control bit WR (EECON1<1>) to begin the
write operation.
The user must follow the same specific sequence to ini-
tiate the write for each word in the program block, writ-
ing each program word in sequence (00, 01, 10, 11).
When the write is performed on the last word
(EEADR<1:0> = 11), the block of four words are
automatically erased and the contents of the buffer
registers are written into the program memory.
After the “BSF EECON1, WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in
which the erase takes place (i.e., the last word of the
four-word block). This is not Sleep mode as the clocks
and peripherals will continue to run. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 write instruction. If the
sequence is performed to any other location, the action
is ignored.
FIGURE 3-1: BLOCK WRITES TO FLASH PROGRAM MEMORY
14 14 14 14
Program Memory
Buffer Register
EEADR<1:0> = 00
Buffer Register
EEADR<1:0> = 01
Buffer Register
EEADR<1:0> = 10
Buffer Register
EEADR<1:0> = 11
EEDATA EEDATH
7 5 0 7 0
6 8
First word of block
to be written
Four words of
to Flash
automatically
after this word
is written
are transferred
Flash are erased,
then all buffers
PIC16F87XA
DS39582B-page 38  2003 Microchip Technology Inc.
An example of the complete four-word write sequence
is shown in Example 3-4. The initial address is loaded
into the EEADRH:EEADR register pair; the four words
of data are loaded using indirect addressing.
EXAMPLE 3-4: WRITING TO FLASH PROGRAM MEMORY
; Thi s wr i t e r out i ne a s s ume s t he f ol l owi ng:
;
; 1. A va l i d s t a r t i ng a ddr e s s ( t he l e a s t s i gni f i c a nt bi t s = ‘ 00’ ) i s l oa de d i n ADDRH: ADDRL
; 2. The 8 byt e s of da t a a r e l oa de d, s t a r t i ng a t t he a ddr e s s i n DATADDR
; 3. ADDRH, ADDRL a nd DATADDR a r e a l l l oc a t e d i n s ha r e d da t a me mor y 0x70 - 0x7f
;
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Ba nk 2
MOVF ADDRH, W ; Loa d i ni t i a l a ddr e s s
MOVWF EEADRH ;
MOVF ADDRL, W ;
MOVWF EEADR ;
MOVF DATAADDR, W ; Loa d i ni t i a l da t a a ddr e s s
MOVWF FSR ;
LOOP MOVF I NDF, W ; Loa d f i r s t da t a byt e i nt o l owe r
MOVWF EEDATA ;
I NCF FSR, F ; Ne xt byt e
MOVF I NDF, W ; Loa d s e c ond da t a byt e i nt o uppe r
MOVWF EEDATH ;
I NCF FSR, F ;
BSF STATUS, RP0 ; Ba nk 3
BSF EECON1, EEPGD ; Poi nt t o pr ogr a m me mor y
BSF EECON1, WREN ; Ena bl e wr i t e s
BCF I NTCON, GI E ; Di s a bl e i nt e r r upt s ( i f us i ng)
MOVLW 55h ; St a r t of r e qui r e d wr i t e s e que nc e :
MOVWF EECON2 ; Wr i t e 55h
MOVLW AAh ;
MOVWF EECON2 ; Wr i t e AAh
BSF EECON1, WR ; Se t WR bi t t o be gi n wr i t e
NOP ; Any i ns t r uc t i ons he r e a r e i gnor e d a s pr oc e s s or
; ha l t s t o be gi n wr i t e s e que nc e
NOP ; pr oc e s s or wi l l s t op he r e a nd wa i t f or wr i t e c ompl e t e
; a f t e r wr i t e pr oc e s s or c ont i nue s wi t h 3r d i ns t r uc t i on
BCF EECON1, WREN ; Di s a bl e wr i t e s
BSF I NTCON, GI E ; Ena bl e i nt e r r upt s ( i f us i ng)
BCF STATUS, RP0 ; Ba nk 2
I NCF EEADR, F ; I nc r e me nt a ddr e s s
MOVF EEADR, W ; Che c k i f l owe r t wo bi t s of a ddr e s s a r e ‘ 00’
ANDLW 0x03 ; I ndi c a t e s whe n f our wor ds ha ve be e n pr ogr a mme d
XORLW 0x03 ;
BTFSC STATUS, Z ; Exi t i f mor e t ha n f our wor ds ,
GOTO LOOP ; Cont i nue i f l e s s t ha n f our wor ds
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 2003 Microchip Technology Inc. DS39582B-page 39
PIC16F87XA
3.7 Protection Against Spurious Write
There are conditions when the device should not write
to the data EEPROM or Flash program memory. To
protect against spurious writes, various mechanisms
have been built-in. On power-up, WREN is cleared.
Also, the Power-up Timer (72 ms duration) prevents an
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
3.8 Operation During Code-Protect
When the data EEPROM is code-protected, the micro-
controller can read and write to the EEPROM normally.
However, all external access to the EEPROM is
disabled. External write access to the program memory
is also disabled.
When program memory is code-protected, the microcon-
troller can read and write to program memory normally,
as well as execute instructions. Writes by the device may
be selectively inhibited to regions of the memory depend-
ing on the setting of bits WR1:WR0 of the configuration
word (see Section 14.1 “Configuration Bits” for addi-
tional information). External access to the memory is also
disabled.
TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND
FLASH PROGRAM MEMORIES
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-on
Reset
Value on
all other
Resets
10Ch EEDATA EEPROM/Flash Data Register Low Byte xxxx xxxx uuuu uuuu
10Dh EEADR EEPROM/Flash Address Register Low Byte xxxx xxxx uuuu uuuu
10Eh EEDATH — — EEPROM/Flash Data Register High Byte xxxx xxxx - - - 0 q000
10Fh EEADRH — — — EEPROM/Flash Address Register High Byte xxxx xxxx - - - - - - - -
18Ch EECON1 EEPGD — — — WRERR WREN WR RD x- - - x000 - - - 0 q000
18Dh EECON2 EEPROM Control Register 2 (not a physical register) - - - - - - - - - - - - - - - -
0Dh PIR2 — CMIF — EEIF BCLIF — — CCP2IF - 0- 0 0- - 0 - 0- 0 0- - 0
8Dh PIE2 — CMIE — EEIE BCLIE — — CCP2IE - 0- 0 0- - 0 - 0- 0 0- - 0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM or Flash program memory.
PIC16F87XA
DS39582B-page 40  2003 Microchip Technology Inc.
NOTES:
 2003 Microchip Technology Inc. DS39582B-page 41
PIC16F87XA
4.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro™ Mid-Range Reference Manual (DS33023).
4.1 PORTA and the TRISA Register
PORTA is a 6-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open-drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and the analog VREF input for both the A/D converters
and the comparators. The operation of each pin is
selected by clearing/setting the appropriate control bits
in the ADCON1 and/or CMCON registers.
The TRISA register controls the direction of the port
pins even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 4-1: INITIALIZING PORTA
FIGURE 4-1: BLOCK DIAGRAM OF
RA3:RA0 PINS
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as ‘0’.
The comparators are in the off (digital)
state.
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Ba nk0
CLRF PORTA ; I ni t i a l i z e PORTA by
; c l e a r i ng out put
; da t a l a t c he s
BSF STATUS, RP0 ; Se l e c t Ba nk 1
MOVLW 0x06 ; Conf i gur e a l l pi ns
MOVWF ADCON1 ; a s di gi t a l i nput s
MOVLW 0xCF ; Va l ue us e d t o
; i ni t i a l i z e da t a
; di r e c t i on
MOVWF TRI SA ; Se t RA<3: 0> a s i nput s
; RA<5: 4> a s out put s
; TRI SA<7: 6>a r e a l wa ys
; r e a d a s ' 0' .
Data
Bus
Q D
Q CK
Q D
Q CK
Q D
EN
P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
VSS
VDD
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter or Comparator
TRISA
PIC16F87XA
DS39582B-page 42  2003 Microchip Technology Inc.
FIGURE 4-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
FIGURE 4-3: BLOCK DIAGRAM OF RA5 PIN
Data Bus
WR PORTA
WR TRISA
RD PORTA
Data Latch
TRIS Latch
RD TRISA
Schmitt
Trigger
Input
Buffer
N
VSS
I/O pin
(1)
TMR0 Clock Input
Q D
Q CK
Q D
Q CK
EN
Q D
EN
C1OUT
Note 1: I/O pin has protection diodes to VSS only.
CMCON<2:0> = x01 or 011
1
0
Data Bus
WR PORTA
WR TRISA
RD PORTA
Data Latch
TRIS Latch
RD TRISA
TTL
Input
Buffer
I/O pin
(1)
A/D Converter or SS Input
Q D
Q CK
Q D
Q CK
EN
Q D
EN
C2OUT
CMCON<2:0> = 011 or 101
1
0
P
N
VSS
VDD
Note 1: I/O pin has protection diodes to VDD and VSS.
Analog
IIP Mode
 2003 Microchip Technology Inc. DS39582B-page 43
PIC16F87XA
TABLE 4-1: PORTA FUNCTIONS
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit 0 TTL Input/output or analog input.
RA1/AN1 bit 1 TTL Input/output or analog input.
RA2/AN2/VREF-/CVREF bit 2 TTL Input/output or analog input or VREF- or CVREF.
RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+.
RA4/T0CKI/C1OUT bit 4 ST Input/output or external clock input for Timer0 or comparator output.
Output is open-drain type.
RA5/AN4/SS/C2OUT bit 5 TTL Input/output or analog input or slave select input for synchronous serial
port or comparator output.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 - - 0x 0000 - - 0u 0000
85h TRISA — — PORTA Data Direction Register - - 11 1111 - - 11 1111
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00- - 0000 00- - 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111.
PIC16F87XA
DS39582B-page 44  2003 Microchip Technology Inc.
4.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
Three pins of PORTB are multiplexed with the In-Circuit
Debugger and Low-Voltage Programming function:
RB3/PGM, RB6/PGC and RB7/PGD. The alternate
functions of these pins are described in Section 14.0
“Special Features of the CPU”.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 4-4: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB port change
interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the application
note, AN552, “Implementing Wake-up on Key Stroke”
(DS00552).
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 14.11.1 “INT
Interrupt”.
FIGURE 4-5: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU
(2)
P
VDD
Q D
CK
Q D
CK
Q D
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
RB0/INT
I/O pin
(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
RB3/PGM
Data Latch
From other
RBPU
(2)
P
VDD
I/O pin
(1)
Q D
CK
Q D
CK
Q D
EN
Q D
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
Weak
Pull-up
RD Port
Latch
TTL
Input
Buffer ST
Buffer
RB7:RB6
Q3
Q1
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
In Serial Programming Mode
 2003 Microchip Technology Inc. DS39582B-page 45
PIC16F87XA
TABLE 4-3: PORTB FUNCTIONS
TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit 0 TTL/ST
(1)
Input/output pin or external interrupt input. Internal software programmable
weak pull-up.
RB1 bit 1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit 2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3/PGM
(3)
bit 3 TTL Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5 bit 5 TTL Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6/PGC bit 6 TTL/ST
(2)
Input/output pin (with interrupt-on-change) or in-circuit debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD bit 7 TTL/ST
(2)
Input/output pin (with interrupt-on-change) or in-circuit debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode or in-circuit debugger.
3: Low-Voltage ICSP Programming (LVP) is enabled by default which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16F87XA
DS39582B-page 46  2003 Microchip Technology Inc.
4.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
When the I
2
C module is enabled, the PORTC<4:3>
pins can be configured with normal I
2
C levels, or with
SMBus levels, by using the CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as the
destination, should be avoided. The user should refer
to the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 4-6: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5>
FIGURE 4-7: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3>
Port/Peripheral Select
(2)
Data Bus
WR Port
WR TRIS
Data Latch
TRIS Latch
Schmitt
Trigger
Q D
Q CK
Q D
EN
Peripheral Data Out
0
1
Q D
Q CK
P
N
VDD
VSS
RD Port
Peripheral
OE
(3)
Peripheral Input
I/O
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port
data and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
RD TRIS
Port/Peripheral Select
(2)
Data Bus
WR Port
WR TRIS
Data Latch
TRIS Latch
Schmitt
Trigger
Q D
Q CK
Q D
EN
Peripheral Data Out
0
1
Q D
Q CK
P
N
VDD
VSS
RD Port
Peripheral
OE
(3)
SSP Input
I/O
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port data
and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
0
1
CKE
SSPSTAT<6>
Schmitt
Trigger
with
SMBus
Levels
RD TRIS
 2003 Microchip Technology Inc. DS39582B-page 47
PIC16F87XA
TABLE 4-5: PORTC FUNCTIONS
TABLE 4-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit 1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and
I
2
C modes.
RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I
2
C mode).
RC5/SDO bit 5 ST Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK bit 6 ST Input/output port pin or USART asynchronous transmit or
synchronous clock.
RC7/RX/DT bit 7 ST Input/output port pin or USART asynchronous receive or
synchronous data.
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
PIC16F87XA
DS39582B-page 48  2003 Microchip Technology Inc.
4.4 PORTD and TRISD Registers
PORTD is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individually configurable as an input
or output.
PORTD can be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting
control bit, PSPMODE (TRISE<4>). In this mode, the
input buffers are TTL.
FIGURE 4-8: PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-7: PORTD FUNCTIONS
TABLE 4-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Note: PORTD and TRISD are not implemented
on the 28-pin devices. Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Q D
CK
Q D
CK
EN
Q D
EN
TRIS
Name Bit# Buffer Type Function
RD0/PSP0 bit 0 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 0.
RD1/PSP1 bit 1 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 1.
RD2/PSP2 bit2 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 2.
RD3/PSP3 bit 3 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 3.
RD4/PSP4 bit 4 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 4.
RD5/PSP5 bit 5 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 5.
RD6/PSP6 bit 6 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 6.
RD7/PSP7 bit 7 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 - 111 0000 - 111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
 2003 Microchip Technology Inc. DS39582B-page 49
PIC16F87XA
4.5 PORTE and TRISE Register
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7) which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
The PORTE pins become the I/O control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>) is
set. In this mode, the user must make certain that the
TRISE<2:0> bits are set and that the pins are configured
as digital inputs. Also, ensure that ADCON1 is config-
ured for digital I/O. In this mode, the input buffers are
TTL.
Register 4-1 shows the TRISE register which also
controls the Parallel Slave Port operation.
PORTE pins are multiplexed with analog inputs. When
selected for analog input, these pins will read as ‘0’s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 4-9: PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-9: PORTE FUNCTIONS
Note: PORTE and TRISE are not implemented
on the 28-pin devices.
Note: On a Power-on Reset, these pins are
configured as analog inputs and read as ‘0’.
Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
Q D
CK
Q D
CK
EN
Q D
EN
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
TRIS
Name Bit# Buffer Type Function
RE0/RD/AN5 bit 0 ST/TTL
(1)
I/O port pin or read control input in Parallel Slave Port mode or analog input:
RD
1 = Idle
0 = Read operation. Contents of PORTD register are output to PORTD
I/O pins (if chip selected).
RE1/WR/AN6 bit 1 ST/TTL
(1)
I/O port pin or write control input in Parallel Slave Port mode or analog input:
WR
1 = Idle
0 = Write operation. Value of PORTD I/O pins is latched into PORTD
register (if chip selected).
RE2/CS/AN7 bit 2 ST/TTL
(1)
I/O port pin or chip select control input in Parallel Slave Port mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
PIC16F87XA
DS39582B-page 50  2003 Microchip Technology Inc.
TABLE 4-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
REGISTER 4-1: TRISE REGISTER (ADDRESS 89h)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
09h PORTE — — — — — RE2 RE1 RE0 - - - - - xxx - - - - - uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 - 111 0000 - 111
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00- - 0000 00- - 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — Bit 2 Bit 1 Bit 0
bit 7 bit 0
Parallel Slave Port Status/Control Bits:
bit 7 IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in
software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = PORTD functions in Parallel Slave Port mode
0 = PORTD functions in general purpose I/O mode
bit 3 Unimplemented: Read as ‘0’
PORTE Data Direction Bits:
bit 2 Bit 2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1 Bit 1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0 Bit 0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc. DS39582B-page 51
PIC16F87XA
4.6 Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F873A or PIC16F876A.
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port, when control bit PSPMODE
(TRISE<4>) is set. In Slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD/AN5, and WR control input
pin, RE1/WR/AN6.
The PSP can directly interface to an 8-bit
microprocessor data bus. The external microprocessor
can read or write the PORTD latch as an 8-bit latch.
Setting bit PSPMODE enables port pin RE0/RD/AN5 to
be the RD input, RE1/WR/AN6 to be the WR input and
RE2/CS/AN7 to be the CS (Chip Select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set). The A/D port configuration bits,
PCFG3:PCFG0 (ADCON1<3:0>), must be set to
configure pins RE2:RE0 as digital I/O.
There are actually two 8-bit latches: one for data output
and one for data input. The user writes 8-bit data to the
PORTD data latch and reads data from the port pin
latch (note that they have the same address). In this
mode, the TRISD register is ignored since the external
device is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 4-11). The interrupt flag bit, PSPIF
(PIR1<7>), is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared
immediately (Figure 4-12), indicating that the PORTD
latch is waiting to be read by the external bus. When
either the CS or RD pin becomes high (level triggered),
the interrupt flag bit PSPIF is set on the Q4 clock cycle,
following the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
FIGURE 4-10: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
WR
Port
RD Port
RDx pin
Q D
CK
EN
Q D
EN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
TTL
TTL
TTL
TTL
Note 1: I/O pins have protection diodes to VDD and VSS.
PIC16F87XA
DS39582B-page 52  2003 Microchip Technology Inc.
FIGURE 4-11: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 4-12: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 4-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
08h PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — — RE2 RE1 RE0 - - - - - xxx - - - - - uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 - 111 0000 - 111
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00- - 0000 00- - 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873A/876A; always maintain these bits clear.
 2003 Microchip Technology Inc. DS39582B-page 53
PIC16F87XA
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is
available in the PICmicro
®
Mid-Range MCU Family
Reference Manual (DS33023).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If the TMR0 register is written, the incre-
ment is inhibited for the following two instruction cycles.
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2 “Using Timer0 with
an External Clock”.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 5.3
“Prescaler” details the operation of the prescaler.
5.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit TMR0IF (INTCON<2>). The interrupt can be
masked by clearing bit TMR0IE (INTCON<5>). Bit
TMR0IF must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The TMR0 interrupt cannot awaken the
processor from Sleep since the timer is shut-off during
Sleep.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
pin
M
U
X
CLKO (= FOSC/4)
Sync
2
Cycles
TMR0 Reg
8-bit Prescaler
8-to-1 MUX
M
U
X
MUX
Watchdog
Timer
PSA
0
1
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
1 0
1
Data Bus
Set Flag bit TMR0IF
on Overflow
8
PSA
T0CS
PRESCALER
PIC16F87XA
DS39582B-page 54  2003 Microchip Technology Inc.
5.2 Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.3 Prescaler
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer and vice versa. This prescaler is not
readable or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
REGISTER 5-1: OPTION_REG REGISTER
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU
bit 6 INTEDG
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: To avoid an unintended device Reset, the instruction sequence shown in the
PICmicro
®
Mid-Range MCU Family Reference Manual (DS33023) must be exe-
cuted when changing the prescaler assignment from Timer0 to the WDT. This
sequence must be followed even if the WDT is disabled.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
 2003 Microchip Technology Inc. DS39582B-page 55
PIC16F87XA
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
01h,101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
PIC16F87XA
DS39582B-page 56  2003 Microchip Technology Inc.
NOTES:
 2003 Microchip Technology Inc. DS39582B-page 57
PIC16F87XA
6.0 TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled,
is generated on overflow which is latched in interrupt
flag bit, TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
• As a Timer
• As a Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON<0>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by either of the two CCP modules
(Section 8.0 “Capture/Compare/PWM Modules”).
Register 6-1 shows the Timer1 Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the PICmicro
®
Mid-Range MCU Family Reference
Manual (DS33023).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 prescale value
10 = 1:4 prescale value
01 = 1:2 prescale value
00 = 1:1 prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582B-page 58  2003 Microchip Technology Inc.
6.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit, T1SYNC
(T1CON<2>), has no effect since the internal clock is
always in sync.
6.2 Timer1 Counter Operation
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
6.3 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during Sleep mode, Timer1 will not
increment even if the external clock is present since the
synchronization circuit is shut-off. The prescaler,
however, will continue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
TMR1H TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Q Clock
T1OSCEN
Enable
Oscillator
(1)
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(2)
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
Set Flag bit
TMR1IF on
Overflow
TMR1
 2003 Microchip Technology Inc. DS39582B-page 59
PIC16F87XA
6.4 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt-on-overflow which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer.
In Asynchronous Counter mode, Timer1 cannot be
used as a time base for capture or compare operations.
6.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers while the
register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PICmicro
®
Mid-Range
MCU Family Reference Manual (DS33023) show how
to read and write Timer1 when it is running in
Asynchronous mode.
6.5 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low-power oscillator, rated up to 200 kHz. It
will continue to run during Sleep. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 6-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.6 Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 or CCP2 module is configured in Compare
mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
Osc Type Freq. C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit, TMR1IF (PIR1<0>).
PIC16F87XA
DS39582B-page 60  2003 Microchip Technology Inc.
6.7 Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other Reset, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset,
or a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
6.8 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON - - 00 0000 - - uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
 2003 Microchip Technology Inc. DS39582B-page 61
PIC16F87XA
7.0 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable and is cleared on any device
Reset.
The input clock (FOSC/4) has a prescale option of
1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit,
TMR2IF (PIR1<1>)).
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Register 7-1 shows the Timer2 Control register.
Additional information on timer modules is available in
the PICmicro
®
Mid-Range MCU Family Reference
Manual (DS33023).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
TMR2
Sets Flag
TMR2 Reg
Output
(1)
Reset
Postscaler
Prescaler
PR2 Reg
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
T2OUTPS3:
T2OUTPS0
T2CKPS1:
T2CKPS0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 postscale
0001 = 1:2 postscale
0010 = 1:3 postscale



1111 = 1:16 postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582B-page 62  2003 Microchip Technology Inc.
7.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
7.2 Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate the
shift clock.
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 - 000 0000 - 000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
 2003 Microchip Technology Inc. DS39582B-page 63
PIC16F87XA
8.0 CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1 except where noted.
CCP1 Module:
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
CCP2 Module:
Capture/Compare/PWM Register 2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Additional information on CCP modules is available in
the PICmicro
®
Mid-Range MCU Family Reference
Manual (DS33023) and in application note AN594,
“Using the CCP Module(s)” (DS00594).
TABLE 8-1: CCP MODE – TIMER
RESOURCES REQUIRED
TABLE 8-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time base
Capture Compare The compare should be configured for the special event trigger which clears TMR1
Compare Compare The compare(s) should be configured for the special event trigger which clears TMR1
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt)
PWM Capture None
PWM Compare None
PIC16F87XA
DS39582B-page 64  2003 Microchip Technology Inc.
REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1
resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is
enabled)
11xx = PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc. DS39582B-page 65
PIC16F87XA
8.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the
following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits,
CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap-
ture is made, the interrupt request flag bit, CCP1IF
(PIR1<2>), is set. The interrupt flag must be cleared in
software. If another capture occurs before the value in
register CCPR1 is read, the old captured value is
overwritten by the new value.
8.1.1 CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
FIGURE 8-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
8.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
8.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any Reset will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 8-1: CHANGING BETWEEN
CAPTURE PRESCALERS
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
Capture condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Qs
CCP1CON<3:0>
RC2/CCP1
Prescaler
1, 4, 16
and
Edge Detect
pin
CLRF CCP1CON ; Tur n CCP modul e of f
MOVLW NEW_CAPT_PS ; Loa d t he Wr e g wi t h
; t he ne w pr e s c a l e r
; move va l ue a nd CCP ON
MOVWF CCP1CON ; Loa d CCP1CON wi t h t hi s
; va l ue
PIC16F87XA
DS39582B-page 66  2003 Microchip Technology Inc.
8.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
8.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
8.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
8.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
Q S
R
Output
Logic
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Match
RC2/CCP1
TRISC<2>
CCP1CON<3:0>
Mode Select
Output Enable
pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>)
and set bit GO/DONE (ADCON0<2>).
Note: The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
 2003 Microchip Technology Inc. DS39582B-page 67
PIC16F87XA
8.3 PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3 “Setup
for PWM Operation”.
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 8-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4: PWM OUTPUT
8.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM Duty Cycle =(CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitch-free PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the following formula.
EQUATION 8-1:
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R Q
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit time
base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Timer2 postscaler (see Section 7.1
“Timer2 Prescaler and Postscaler”) is
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
log(
FPWM
log(2)
FOSC
)
bits Resolution =
PIC16F87XA
DS39582B-page 68  2003 Microchip Technology Inc.
8.3.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h
Maximum Resolution (bits) 10 10 10 8 7 5.5
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF - - - - - - - 0 - - - - - - - 0
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE - - - - - - - 0 - - - - - - - 0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON - - 00 0000 - - uu uuuu
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 - - 00 0000 - - 00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 - - 00 0000 - - 00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on 28-pin devices; always maintain these bits clear.
 2003 Microchip Technology Inc. DS39582B-page 69
PIC16F87XA
TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF - - - - - - - 0 - - - - - - - 0
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE - - - - - - - 0 - - - - - - - 0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 - 000 0000 - 000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 - - 00 0000 - - 00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 - - 00 0000 - - 00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
PIC16F87XA
DS39582B-page 70  2003 Microchip Technology Inc.
NOTES:
 2003 Microchip Technology Inc. DS39582B-page 71
PIC16F87XA
9.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
9.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
2
C)
- Full Master mode
- Slave mode (with general address call)
The I
2
C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
9.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I
2
C mode.
Additional details are provided under the individual
sections.
9.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/C2OUT
Figure 9-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 9-1: MSSP BLOCK DIAGRAM
(SPI MODE)
Note: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the state of the SS pin can affect the state
read back from the TRISC<5> bit. The
Peripheral OE signal from the SSP mod-
ule in PORTC controls the state that is
read back from the TRISC<5> bit (see
Section 4.3 “PORTC and the TRISC
Register” for information on PORTC). If
Read-Modify-Write instructions, such as
BSF, are performed on the TRISC register
while the SS pin is high, this will cause the
TRISC<5> bit to be set, thus disabling the
SDO output.
Read Write
Internal
Data Bus
SSPSR reg
SSPM3:SSPM0
bit0
Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TOSC Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
RC5/SDO

SSPBUF reg
RC4/SDI/SDA
RA5/AN4/
RC3/SCK/SCL
Peripheral OE
SS/C2OUT
PIC16F87XA
DS39582B-page 72  2003 Microchip Technology Inc.
9.3.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register (SSPCON)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON regis-
ter is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
REGISTER 9-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
bit 5 D/A: Data/Address bit
Used in I
2
C mode only.
bit 4 P: Stop bit
Used in I
2
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I
2
C mode only.
bit 2 R/W: Read/Write bit information
Used in I
2
C mode only.
bit 1 UA: Update Address bit
Used in I
2
C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc. DS39582B-page 73
PIC16F87XA
REGISTER 9-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be
cleared in software.)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. (Must be
cleared in software.)
0 = No overflow
Note: In Master mode, the overflow bit is not set, since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note: Bit combinations not specifically listed here are either reserved or implemented in
I
2
C mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582B-page 74  2003 Microchip Technology Inc.
9.3.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the eight bits of
data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit, WCOL
(SSPCON<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
Full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 9-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 9-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ; Ha s da t a be e n r e c e i ve d( t r a ns mi t c ompl e t e ) ?
BRA LOOP ; No
MOVF SSPBUF, W ; WREG r e g = c ont e nt s of SSPBUF
MOVWF RXDATA ; Sa ve i n us e r RAM, i f da t a i s me a ni ngf ul
MOVF TXDATA, W ; Wr e g = c ont e nt s of TXDATA
MOVWF SSPBUF ; Ne w da t a t o xmi t
 2003 Microchip Technology Inc. DS39582B-page 75
PIC16F87XA
9.3.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISC<4> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
9.3.4 TYPICAL CONNECTION
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
FIGURE 9-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock
PIC16F87XA
DS39582B-page 76  2003 Microchip Technology Inc.
9.3.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
Figure 9-3, Figure 9-5 and Figure 9-6, where the MSB
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the
following:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 9-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 9-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7 bit 0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycle
after Q2
 2003 Microchip Technology Inc. DS39582B-page 77
PIC16F87XA
9.3.6 SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
9.3.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON<3:0> = 04h). The pin must not be driven low
for the SS pin to function as an input. The data latch
must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven
even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
may be desirable, depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is used in Slave Mode with CKE
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7
bit 0
Next Q4 Cycle
after Q2
PIC16F87XA
DS39582B-page 78  2003 Microchip Technology Inc.
FIGURE 9-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 9-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
Next Q4 Cycle
after Q2
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2
 2003 Microchip Technology Inc. DS39582B-page 79
PIC16F87XA
9.3.8 SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
9.3.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
9.3.10 BUS MODE COMPATIBILITY
Table 9-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 9-1: SPI BUS MODES
There is also a SMP bit which controls when the data is
sampled.
TABLE 9-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA — PORTA Data Direction Register - - 11 1111 - - 11 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices; always maintain these bits clear.
PIC16F87XA
DS39582B-page 80  2003 Microchip Technology Inc.
9.4 I
2
C Mode
The MSSP module in I
2
C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on Start and Stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 9-7: MSSP BLOCK DIAGRAM
(I
2
C MODE)
9.4.1 REGISTERS
The MSSP module has six registers for I
2
C operation.
These are:
• MSSP Control Register (SSPCON)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I
2
C mode operation. The
SSPCON and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address
when the SSP is configured in I
2
C Slave mode. When
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
Read Write
SSPSR reg
Match Detect
SSPADD reg
Start and
Stop bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/SDI/
Shift
Clock
MSb LSb
SDA
 2003 Microchip Technology Inc. DS39582B-page 81
PIC16F87XA
REGISTER 9-3: SSPSTAT: MSSP STATUS REGISTER (I
2
C MODE) (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 3 S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 2 R/W: Read/Write bit information (I
2
C mode only)
In Slave mode:
1 = Read
0 = Write
Note: This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Idle mode.
bit 1 UA: Update Address (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data Transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582B-page 82  2003 Microchip Technology Inc.
REGISTER 9-4: SSPCON1: MSSP CONTROL REGISTER 1 (I
2
C MODE) (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I
2
C conditions were not valid for
a transmission to be started. (Must be cleared in software.)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be
cleared in software.)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. (Must be
cleared in software.)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables the serial port and configures these pins as I/O port pins
Note: When enabled, the SDA and SCL pins must be properly configured as input or output.
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I
2
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I
2
C Firmware Controlled Master mode (Slave Idle)
1000 = I
2
C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I
2
C Slave mode, 10-bit address
0110 = I
2
C Slave mode, 7-bit address
Note: Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc. DS39582B-page 83
PIC16F87XA
REGISTER 9-5: SSPCON2: MSSP CONTROL REGISTER 2 (I
2
C MODE) (ADDRESS 91h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note: Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master mode only)
1 = Enables Receive mode for I
2
C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enabled bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is enabled for slave transmit only (PIC16F87X compatibility)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
2
C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
PIC16F87XA
DS39582B-page 84  2003 Microchip Technology Inc.
9.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON register allows control of the I
2
C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
C modes to be selected:
• I
2
C Master mode, clock = OSC/4 (SSPADD + 1)
• I
2
C Slave mode (7-bit address)
• I
2
C Slave mode (10-bit address)
• I
2
C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I
2
C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I
2
C Firmware Controlled Master mode, slave is
Idle
Selection of any I
2
C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
9.4.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I
2
C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The buffer full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
2
C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
9.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is com-
pared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for
10-bit address is as follows, with steps 7 through 9 for
the slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
 2003 Microchip Technology Inc. DS39582B-page 85
PIC16F87XA
9.4.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the No Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
If SEN is enabled (SSPCON<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data trans-
fer. The clock must be released by setting bit CKP
(SSPCON<4>). See Section 9.4.4 “Clock Stretching”
for more detail.
9.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is loaded
into the SSPBUF register. The ACK pulse will be sent on
the ninth bit and pin RC3/SCK/SCL is held low regard-
less of SEN (see Section 9.4.4 “Clock Stretching” for
more detail). By stretching the clock, the master will be
unable to assert another clock pulse until the slave is
done preparing the transmit data. The transmit data
must be loaded into the SSPBUF register, which also
loads the SSPSR register. Then pin RC3/SCK/SCL
should be enabled by setting bit CKP (SSPCON<4>).
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 9-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
PIC16F87XA
DS39582B-page 86  2003 Microchip Technology Inc.
FIGURE 9-8: I
2
C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
S
D
A
S
C
L
S
S
P
I
F

B
F

(
S
S
P
S
T
A
T
<
0
>
)
S
S
P
O
V

(
S
S
P
C
O
N
<
6
>
)
S
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 2003 Microchip Technology Inc. DS39582B-page 87
PIC16F87XA
FIGURE 9-9: I
2
C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
S
D
A
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C
L
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P
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(
P
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1
<
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0
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PIC16F87XA
DS39582B-page 88  2003 Microchip Technology Inc.
FIGURE 9-10: I
2
C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
S
D
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P
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 2003 Microchip Technology Inc. DS39582B-page 89
PIC16F87XA
FIGURE 9-11: I
2
C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
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PIC16F87XA
DS39582B-page 90  2003 Microchip Technology Inc.
9.4.4 CLOCK STRETCHING
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
9.4.4.1 Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON register is
automatically cleared, forcing the SCL output to be
held low. The CKP bit being cleared to ‘0’ will assert
the SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 9-13).
9.4.4.2 Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address, with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
9.4.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the ninth
clock, if the BF bit is clear. This occurs regardless of the
state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 9-9).
9.4.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 9-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching, on the basis of the
state of the BF bit, only occurs during a
data sequence, not an address sequence.
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
 2003 Microchip Technology Inc. DS39582B-page 91
PIC16F87XA
9.4.4.5 Clock Synchronization and the
CKP Bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the SCL line
until an external I
2
C master device has already
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I
2
C
bus have deasserted SCL. This ensures that a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 9-12).
FIGURE 9-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1 DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
PIC16F87XA
DS39582B-page 92  2003 Microchip Technology Inc.
FIGURE 9-13: I
2
C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
S
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 2003 Microchip Technology Inc. DS39582B-page 93
PIC16F87XA
FIGURE 9-14: I
2
C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
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PIC16F87XA
DS39582B-page 94  2003 Microchip Technology Inc.
9.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I
2
C bus is such that
the first byte after the Start condition usually determines
which device will be the slave addressed by the master.
The exception is the general call address which can
address all devices. When this address is used, all
devices should, in theory, respond with an Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I
2
C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 9-15).
FIGURE 9-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL
S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Cleared in software
SSPBUF is read
R/W = 0
ACK
General Call Address
Address is compared to general call address.
GCEN (SSPCON2<7>)
Receiving Data ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
After ACK, set interrupt.
‘0’
‘1’
 2003 Microchip Technology Inc. DS39582B-page 95
PIC16F87XA
9.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I
2
C bus may be taken when the P bit is set or the
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
2
C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register, initiating
transmission of data/address.
4. Configure the I
2
C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 9-16: MSSP BLOCK DIAGRAM (I
2
C MASTER MODE)
Note: The MSSP module, when configured in
I
2
C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condi-
tion is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
Start bit Detect
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
R
e
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SSPADD<6:0>
Baud
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Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
PIC16F87XA
DS39582B-page 96  2003 Microchip Technology Inc.
9.4.6.1 I
2
C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I
2
C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
The baud rate generator used for the SPI mode opera-
tion is used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I
2
C operation. See
Section 9.4.7 “Baud Rate Generator” for more detail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required Start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
 2003 Microchip Technology Inc. DS39582B-page 97
PIC16F87XA
9.4.7 BAUD RATE GENERATOR
In I
2
C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 9-17). When a write occurs to
SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I
2
C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 9-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 9-17: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 9-3: I
2
C CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter CLKO FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
FCY FCY*2 BRG Value
FSCL
(2 Rollovers of BRG)
10 MHz 20 MHz 19h 400 kHz
(1)
10 MHz 20 MHz 20h 312.5 kHz
10 MHz 20 MHz 3Fh 100 kHz
4 MHz 8 MHz 0Ah 400 kHz
(1)
4 MHz 8 MHz 0Dh 308 kHz
4 MHz 8 MHz 28h 100 kHz
1 MHz 2 MHz 03h 333 kHz
(1)
1 MHz 2 MHz 0Ah 100 kHz
1 MHz 2 MHz 00h 1 MHz
(1)
Note 1: The I
2
C interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
PIC16F87XA
DS39582B-page 98  2003 Microchip Technology Inc.
9.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 9-17).
FIGURE 9-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX-1 DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
 2003 Microchip Technology Inc. DS39582B-page 99
PIC16F87XA
9.4.8 I
2
C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start con-
dition enable bit, SEN (SSPCON2<0>). If the SDA and
SCL pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the Baud Rate Generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the Start condition and
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Generator is reloaded with the con-
tents of SSPADD<6:0> and resumes its count. When
the Baud Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by hard-
ware, the Baud Rate Generator is suspended, leaving
the SDA line held low and the Start condition is
complete.
9.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-19: FIRST START BIT TIMING
Note: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the Start condition is aborted and the
I
2
C module is reset into its Idle state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
SDA
SCL
S
TBRG
1st Bit 2nd Bit
TBRG
SDA = 1,
At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit
PIC16F87XA
DS39582B-page 100  2003 Microchip Technology Inc.
9.4.9 I
2
C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I
2
C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Genera-
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
9.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-20: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Write to SSPBUF occurs here
Falling edge of ninth clock,
end of Xmit
At completion of Start bit,
hardware clears RSEN bit
1st Bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change)
SCL = 1
occurs here,
TBRG TBRG TBRG
and sets SSPIF
 2003 Microchip Technology Inc. DS39582B-page 101
PIC16F87XA
9.4.10 I
2
C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification, parameter
#106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification,
parameter #107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time, if an
address match occurred or if data was received prop-
erly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 9-21).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
9.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all eight bits are shifted out.
9.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
9.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does Not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
9.4.11 I
2
C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After the
falling edge of the eighth clock, the receive enable flag
is automatically cleared, the contents of the SSPSR are
loaded into the SSPBUF, the BF flag bit is set, the
SSPIF flag bit is set and the Baud Rate Generator is
suspended from counting, holding SCL low. The MSSP
is now in Idle state, awaiting the next command. When
the buffer is read by the CPU, the BF flag bit is automat-
ically cleared. The user can then send an Acknowledge
bit at the end of reception by setting the Acknowledge
Sequence Enable bit, ACKEN (SSPCON2<4>).
9.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
9.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
9.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
PIC16F87XA
DS39582B-page 102  2003 Microchip Technology Inc.
FIGURE 9-21: I
2
C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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 2003 Microchip Technology Inc. DS39582B-page 103
PIC16F87XA
FIGURE 9-22: I
2
C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
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PIC16F87XA
DS39582B-page 104  2003 Microchip Technology Inc.
9.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the baud rate generator is turned off and the
MSSP module then goes into Idle mode (Figure 9-23).
9.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
9.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A TBRG later, the PEN bit is cleared and the SSPIF
bit is set (Figure 9-24).
9.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-23: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 9-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
Set SSPIF at the end
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
Cleared in
TBRG TBRG
of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software Set SSPIF at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
 2003 Microchip Technology Inc. DS39582B-page 105
PIC16F87XA
9.4.14 SLEEP OPERATION
While in Sleep mode, the I
2
C module can receive
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
Sleep (if the MSSP interrupt is enabled).
9.4.15 EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
9.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I
2
C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is at
the expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
9.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I
2
C port to its Idle state (Figure 9-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I
2
C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the con-
dition is aborted, the SDA and SCL lines are deasserted
and the respective control bits in the SSPCON2 register
are cleared. When the user services the bus collision
Interrupt Service Routine and if the I
2
C bus is free, the
user can resume communication by asserting a Start
condition.
The Master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I
2
C bus can
be taken when the P bit is set in the SSPSTAT register or
the bus is Idle and the S and P bits are cleared.
FIGURE 9-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data doesn’t match what is driven
Set bus collision
interrupt (BCLIF)
by the master. Bus collision has occurred.
by master
Data changes
while SCL = 0
PIC16F87XA
DS39582B-page 106  2003 Microchip Technology Inc.
9.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 9-26).
b) SCL is sampled low before SDA is asserted low
(Figure 9-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 9-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0 and during this time, if the SCL pin is
sampled as ‘0’, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
FIGURE 9-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
Set BCLIF,
Start condition. Set BCLIF.
S
 2003 Microchip Technology Inc. DS39582B-page 107
PIC16F87XA
FIGURE 9-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 9-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN
bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
‘0’ ‘0’
‘0’ ‘0’
SDA
SCL
SEN
Set S
Less than TBRG
TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in software
set SSPIF
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SSPIF
‘0’
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
PIC16F87XA
DS39582B-page 108  2003 Microchip Technology Inc.
9.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 9-29). If SDA is sampled high, the BRG is
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(Figure 9-30).
If at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 9-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 9-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
 2003 Microchip Technology Inc. DS39582B-page 109
PIC16F87XA
9.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 9-31). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 9-32).
FIGURE 9-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 9-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA
SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
PIC16F87XA
DS39582B-page 110  2003 Microchip Technology Inc.
NOTES:
 2003 Microchip Technology Inc. DS39582B-page 111
PIC16F87XA
10.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be
set in order to configure pins RC6/TX/CK and RC7/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
The USART module also has a multi-processor
communication capability using 9-bit address detection.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in Sync mode.
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as ‘0’
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data, can be Parity bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582B-page 112  2003 Microchip Technology Inc.
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8>
is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc. DS39582B-page 113
PIC16F87XA
10.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16 (X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
10.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 10-1: BAUD RATE FORMULA
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64 (X + 1))
(Synchronous) Baud Rate = FOSC/(4 (X + 1))
Baud Rate = FOSC/(16 (X + 1))
N/A
Legend: X = value in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 - 010 0000 - 010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
PIC16F87XA
DS39582B-page 114  2003 Microchip Technology Inc.
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 - - - - - - - - -
1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129
2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64
9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15
19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7
28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4
33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4
57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2
HIGH 1.221 - 255 0.977 - 255 0.610 - 255
LOW 312.500 - 0 250.000 - 0 156.250 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 0.300 0 207 0.3 0 191
1.2 1.202 0.17 51 1.2 0 47
2.4 2.404 0.17 25 2.4 0 23
9.6 8.929 6.99 6 9.6 0 5
19.2 20.833 8.51 2 19.2 0 2
28.8 31.250 8.51 1 28.8 0 1
33.6 - - - - - -
57.6 62.500 8.51 0 57.6 0 0
HIGH 0.244 - 255 0.225 - 255
LOW 62.500 - 0 57.6 - 0
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 - - - - - - - - -
1.2 - - - - - - - - -
2.4 - - - - - - 2.441 1.71 255
9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64
19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31
28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21
33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18
57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10
HIGH 4.883 - 255 3.906 - 255 2.441 - 255
LOW 1250.000 - 0 1000.000 0 625.000 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 - - - - - -
1.2 1.202 0.17 207 1.2 0 191
2.4 2.404 0.17 103 2.4 0 95
9.6 9.615 0.16 25 9.6 0 23
19.2 19.231 0.16 12 19.2 0 11
28.8 27.798 3.55 8 28.8 0 7
33.6 35.714 6.29 6 32.9 2.04 6
57.6 62.500 8.51 3 57.6 0 3
HIGH 0.977 - 255 0.9 - 255
LOW 250.000 - 0 230.4 - 0
 2003 Microchip Technology Inc. DS39582B-page 115
PIC16F87XA
10.2 USART Asynchronous Mode
In this mode, the USART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip, dedicated, 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The USART transmits
and receives the LSb first. The transmitter and receiver
are functionally independent but use the same data
format and baud rate. The baud rate generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware but can be implemented in
software (and stored as the ninth data bit).
Asynchronous mode is stopped during Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
10.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit, TXIF (PIR1<4>), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA<1>),
shows the status of the TSR register. Status bit TRMT
is a read-only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit so the user
has to poll this bit in order to determine if the TSR
register is empty.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to high-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator
TX9D
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8

PIC16F87XA
DS39582B-page 116  2003 Microchip Technology Inc.
When setting up an Asynchronous Transmission,
follow these steps:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 10.1 “USART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 - 00x 0000 - 00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 - 010 0000 - 010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
Word 1
Stop Bit
Word 1
Transmit Shift Reg
Start Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1
Word 2
Start Bit
Stop Bit
Start Bit
Transmit Shift Reg.
Word 1 Word 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
 2003 Microchip Technology Inc. DS39582B-page 117
PIC16F87XA
10.2.2 USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter, operating at x16 times the
baud rate; whereas the main receive serial shifter
operates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the Receive (Serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit, RCIF (PIR1<5>), is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit, RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the Stop bit of the third byte, if the RCREG register is
still full, the Overrun Error bit, OERR (RCSTA<1>), will
be set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in soft-
ware. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited and no further data will be received. It is, therefore,
essential to clear error bit OERR if it is set. Framing
error bit, FERR (RCSTA<2>), is set if a Stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading the RCREG register in
order not to lose the old FERR and RX9D information.
FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register MSb LSb
RX9D RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
64
16
or
Stop Start
(8) 7 1 0
RX9

FOSC
PIC16F87XA
DS39582B-page 118  2003 Microchip Technology Inc.
FIGURE 10-5: ASYNCHRONOUS RECEPTION
When setting up an Asynchronous Reception, follow
these steps:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 10.1 “USART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8 bit 1 bit 0 bit 7/8 bit 0 Stop
bit
Start
bit
Start
bit bit 7/8 Stop
bit
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 - 00x 0000 - 00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 - 010 0000 - 010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
 2003 Microchip Technology Inc. DS39582B-page 119
PIC16F87XA
10.2.3 SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
When setting up an Asynchronous Reception with
address detect enabled:
• Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer and interrupt the
CPU.
FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register MSb LSb
RX9D RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
64
16
or
Stop Start (8) 7 1 0
RX9

RX9
ADDEN
RX9
ADDEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
FOSC
PIC16F87XA
DS39582B-page 120  2003 Microchip Technology Inc.
FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 10-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit bit 1 bit 0 bit 8 bit 0 Stop
bit
Start
bit bit 8 Stop
bit
RC7/RX/DT
Load RSR
Read
RCIF
Word 1
RCREG
Bit 8 = 0, Data Byte Bit 8 = 1, Address Byte
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
(pin)
Start
bit bit 1 bit 0 bit 8 bit 0 Stop
bit
Start
bit bit 8 Stop
bit
RC7/RX/DT
Load RSR
Read
RCIF
Word 1
RCREG
Bit 8 = 1, Address Byte Bit 8 = 0, Data Byte
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
(pin)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 - 010 0000 - 010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
 2003 Microchip Technology Inc. DS39582B-page 121
PIC16F87XA
10.3 USART Synchronous
Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit, SYNC (TXSTA<4>). In
addition, enable bit, SPEN (RCSTA<7>), is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit, CSRC (TXSTA<7>).
10.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 10-6. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and inter-
rupt bit, TXIF (PIR1<4>), is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA<1>),
shows the status of the TSR register. TRMT is a read-
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty. The
TSR is not mapped in data memory so it is not available
to the user.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is
stable around the falling edge of the synchronous clock
(Figure 10-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-10). This is advantageous when slow
baud rates are selected since the BRG is kept in Reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty so a transfer to the
TXREG register will result in an immediate transfer to
TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to high-
impedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a high-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from High-
Impedance Receive mode to transmit and start driving.
To avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
PIC16F87XA
DS39582B-page 122  2003 Microchip Technology Inc.
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-9: SYNCHRONOUS TRANSMISSION
FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 - 00x 0000 - 00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 - 010 0000 - 010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
bit 0 bit 1 bit 7
Word 1
Q1Q2 Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX/DT
RC6/TX/CK
Write to
TXREG reg
TXIF bit
(Interrupt Flag)
TXEN bit
‘1’ ‘1’
Word 2
TRMT bit
Write Word 1
Write Word 2
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
pin
pin
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
 2003 Microchip Technology Inc. DS39582B-page 123
PIC16F87XA
10.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit, SREN
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit, RCIF
(PIR1<5>), is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit, RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double-buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then Overrun Error bit, OERR
(RCSTA<1>), is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
When setting up a Synchronous Master Reception:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 - 00x 0000 - 00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 - 010 0000 - 010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
PIC16F87XA
DS39582B-page 124  2003 Microchip Technology Inc.
FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
10.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit, CSRC (TXSTA<7>).
10.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
When setting up a Synchronous Slave Transmission,
follow these steps:
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
CREN bit
RC7/RX/DT
RC6/TX/CK
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
Q3 Q4Q1Q2Q3 Q4Q1Q2Q3 Q4 Q2 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1 Q2Q3 Q4Q1Q2 Q3Q4 Q1 Q2Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Q1 Q2Q3Q4
pin
pin
 2003 Microchip Technology Inc. DS39582B-page 125
PIC16F87XA
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
10.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR reg-
ister will transfer the data to the RCREG register and if
enable bit RCIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
When setting up a Synchronous Slave Reception,
follow these steps:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 - 010 0000 - 010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 - 010 0000 - 010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
PIC16F87XA
DS39582B-page 126  2003 Microchip Technology Inc.
NOTES:
 2003 Microchip Technology Inc. DS39582B-page 127
PIC16F87XA
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has five
inputs for the 28-pin devices and eight for the 40/44-pin
devices.
The conversion of an analog input signal results in a
corresponding 10-bit digital number. The A/D module
has high and low-voltage reference input that is soft-
ware selectable to some combination of VDD, VSS, RA2
or RA3.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D clock must be derived from
the A/D’s internal RC oscillator.
The A/D module has four registers. These registers are:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage
reference) or as digital I/O.
Additional information on using the A/D module can be
found in the PICmicro
®
Mid-Range MCU Family
Reference Manual (DS33023).
REGISTER 11-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON
bit 7 bit 0
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
bit 5-3 CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (AN0)
001 = Channel 1 (AN1)
010 = Channel 2 (AN2)
011 = Channel 3 (AN3)
100 = Channel 4 (AN4)
101 = Channel 5 (AN5)
110 = Channel 6 (AN6)
111 = Channel 7 (AN7)
Note: The PIC16F873A/876A devices only implement A/D channels 0 through 4; the
unimplemented selections are reserved. Do not select any unimplemented
channels with these devices.
bit 2 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 1 Unimplemented: Read as ‘0’
bit 0 ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
ADCON1
<ADCS2>
ADCON0
<ADCS1:ADCS0>
Clock Conversion
0 00 FOSC/2
0 01 FOSC/8
0 10 FOSC/32
0 11 FRC (clock derived from the internal A/D RC oscillator)
1 00 FOSC/4
1 01 FOSC/16
1 10 FOSC/64
1 11 FRC (clock derived from the internal A/D RC oscillator)
PIC16F87XA
DS39582B-page 128  2003 Microchip Technology Inc.
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in shaded area and in bold)
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be an analog input.
ADCON1
<ADCS2>
ADCON0
<ADCS1:ADCS0>
Clock Conversion
0 00 FOSC/2
0 01 FOSC/8
0 10 FOSC/32
0 11 FRC (clock derived from the internal A/D RC oscillator)
1 00 FOSC/4
1 01 FOSC/16
1 10 FOSC/64
1 11 FRC (clock derived from the internal A/D RC oscillator)

A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
PCFG
<3:0>
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C/R
0000 A A A A A A A A VDD VSS 8/0
0001 A A A A VREF+ A A A AN3 VSS 7/1
0010 D D D A A A A A VDD VSS 5/0
0011 D D D A VREF+ A A A AN3 VSS 4/1
0100 D D D D A D A A VDD VSS 3/0
0101 D D D D VREF+ D A A AN3 VSS 2/1
011x D D D D D D D D — — 0/0
1000 A A A A VREF+ VREF- A A AN3 AN2 6/2
1001 D D A A A A A A VDD VSS 6/0
1010 D D A A VREF+ A A A AN3 VSS 5/1
1011 D D A A VREF+ VREF- A A AN3 AN2 4/2
1100 D D D A VREF+ VREF- A A AN3 AN2 3/2
1101 D D D D VREF+ VREF- A A AN3 AN2 2/2
1110 D D D D D D D A VDD VSS 1/0
1111 D D D D VREF+ VREF- D A AN3 AN2 1/2
 2003 Microchip Technology Inc. DS39582B-page 129
PIC16F87XA
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D Result
register pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block
diagram of the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 11.1 “A/D
Acquisition Requirements”. After this acquisition
time has elapsed, the A/D conversion can be started.
To do an A/D Conversion, follow these steps:
1. Configure the A/D module:
• Configure analog pins/voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete by either:
• Polling for the GO/DONE bit to be cleared
(interrupts disabled); OR
• Waiting for the A/D interrupt
6. Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
7. For the next conversion, go to step 1 or step 2
as required. The A/D conversion time per bit is
defined as TAD.
FIGURE 11-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
(Reference
Voltage)
VDD
PCFG3:PCFG0
CHS2:CHS0
RE2/AN7
(1)
RE1/AN6
(1)
RE0/AN5
(1)
RA5/AN4
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
111
110
101
100
011
010
001
000
A/D
Converter
Note 1: Not available on 28-pin devices.
VREF-
(Reference
Voltage)
VSS
PCFG3:PCFG0
PIC16F87XA
DS39582B-page 130  2003 Microchip Technology Inc.
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch
impedance (RSS) directly affect the time required to
charge the capacitor CHOLD. The sampling switch
(RSS) impedance varies over the device voltage (VDD);
see Figure 11-2. The maximum recommended
impedance for analog sources is 2.5 k . As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro
®
Mid-Range MCU Family Reference
Manual (DS33023).
EQUATION 11-1: ACQUISITION TIME

FIGURE 11-2: ANALOG INPUT MODEL
TACQ
TC
TACQ
=
=
=
=
=
=
=
=
Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
2 s + TC + [(Temperature – 25°C)(0.05 s/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120 pF (1 k + 7 k + 10 k ) In(0.0004885)
16.47 s
2 s + 16.47 s + [(50°C – 25 C)(0.05 s/ C)
19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 2.5 k . This is required to meet the pin
leakage specification.
CPIN
VA
RS
ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V
ILEAKAGE
RIC 1K
Sampling
Switch
SS
RSS
CHOLD
= DAC Capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
5 6 7 8 9 10 11
(k )
VDD
= 120 pF
± 500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
 2003 Microchip Technology Inc. DS39582B-page 131
PIC16F87XA
11.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12 TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The seven possible options for TAD
are:
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal A/D module RC oscillator (2-6 s)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
Table 11-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
11.3 Configuring Analog Port Pins
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (F))
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an analog
input. Analog levels on a digitally config-
ured input will not affect the conversion
accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins) may cause the input buffer to con-
sume current that is out of the device
specifications.
AD Clock Source (TAD)
Maximum Device Frequency
Operation ADCS2:ADCS1:ADCS0
2 TOSC 000 1.25 MHz
4 TOSC 100 2.5 MHz
8 TOSC 001 5 MHz
16 TOSC 101 10 MHz
32 TOSC 010 20 MHz
64 TOSC 110 20 MHz
RC
(1, 2, 3)
x11 (Note 1)
Note 1: The RC source has a typical TAD time of 4 s but can vary between 2-6 s.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for Sleep operation.
3: For extended voltage devices (LF), please refer to Section 17.0 “Electrical Characteristics”.
PIC16F87XA
DS39582B-page 132  2003 Microchip Technology Inc.
11.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, the next acquisition on the selected channel
is automatically started. The GO/DONE bit can then be
set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time
segment has a minimum of TCY and a maximum of TAD.

FIGURE 11-3: A/D CONVERSION TAD CYCLES
11.4.1 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general
purpose 8-bit registers.
FIGURE 11-4: A/D RESULT JUSTIFICATION
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2
TAD10 TAD11
b1 b0
TCY to TAD
Conversion starts
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
10-bit Result
ADRESH ADRESL
0000 00
ADFM = 0
0 2 1 0 7 7
10-bit Result
ADRESH ADRESL
10-bit Result
0000 00
7 0 7 6 5 0
ADFM = 1
Right Justified Left Justified
 2003 Microchip Technology Inc. DS39582B-page 133
PIC16F87XA
11.5 A/D Operation During Sleep
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.

11.6 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D
Note: For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during Sleep, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
MCLR, WDT
0Bh,8Bh,
10Bh,18Bh
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00- 0 0000 00- 0
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00- - 0000 00- - 0000
85h TRISA — — PORTA Data Direction Register - - 11 1111 - - 11 1111
05h PORTA — — PORTA Data Latch when written: PORTA pins when read - - 0x 0000 - - 0u 0000
89h
(1)
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 - 111 0000 - 111
09h
(1)
PORTE — — — — — RE2 RE1 RE0 - - - - - xxx - - - - - uuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers are not available on 28-pin devices.
PIC16F87XA
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NOTES:
 2003 Microchip Technology Inc. DS39582B-page 135
PIC16F87XA
12.0 COMPARATOR MODULE
The comparator module contains two analog compara-
tors. The inputs to the comparators are multiplexed
with I/O port pins RA0 through RA3, while the outputs
are multiplexed to pins RA4 and RA5. The on-chip volt-
age reference (Section 13.0 “Comparator Voltage
Reference Module”) can also be an input to the
comparators.
The CMCON register (Register 12-1) controls the com-
parator input and output multiplexers. A block diagram
of the various comparator configurations is shown in
Figure 12-1.
REGISTER 12-1: CMCON REGISTER
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3 CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN- connects to RA3/AN3
C2 VIN- connects to RA2/AN2
0 = C1 VIN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2 CM2:CM0: Comparator Mode bits
Figure 12-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582B-page 136  2003 Microchip Technology Inc.
12.1 Comparator Configuration
There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 12-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 17.0 “Electrical Characteristics”.
FIGURE 12-1: COMPARATOR I/O OPERATING MODES
Note: Comparator interrupts should be disabled
during a Comparator mode change.
Otherwise, a false interrupt may occur.
C1
RA0/AN0
VIN-
VIN+
RA3/AN3
Off (Read as ‘0’)
Comparators Reset
A
A
CM2:CM0 = 000
C2
RA1/AN1
VIN-
VIN+
RA2/AN2
Off (Read as ‘0’)
A
A
C1
RA0/AN0
VIN-
VIN+
RA3/AN3
C1OUT
Two Independent Comparators
A
A
CM2:CM0 = 010
C2
RA1/AN1
VIN-
VIN+
RA2/AN2
C2OUT
A
A
C1
RA0/AN0
VIN-
VIN+
RA3/AN3
C1OUT
Two Common Reference Comparators
A
A
CM2:CM0 = 100
C2
RA1/AN1
VIN-
VIN+
RA2/AN2
C2OUT
A
D
C2
RA1/AN1
VIN-
VIN+
RA2/AN2
Off (Read as ‘0’)
One Independent Comparator with Output
D
D
CM2:CM0 = 001
C1
RA0/AN0
VIN-
VIN+
RA3/AN3
C1OUT
A
A
C1
RA0/AN0
VIN-
VIN+
RA3/AN3
Off (Read as ‘0’)
Comparators Off (POR Default Value)
D
D
CM2:CM0 = 111
C2
RA1/AN1
VIN-
VIN+
RA2/AN2
Off (Read as ‘0’)
D
D
C1
RA0/AN0
VIN-
VIN+
RA3/AN3
C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM2:CM0 = 110
C2
RA1/AN1
VIN-
VIN+
RA2/AN2
C2OUT
A
A
From Comparator
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
RA0/AN0
VIN-
VIN+
RA3/AN3
C1OUT
Two Common Reference Comparators with Outputs
A
A
CM2:CM0 = 101
C2
RA1/AN1
VIN-
VIN+
RA2/AN2
C2OUT
A
D
A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.
CVREF
C1
RA0/AN0
VIN-
VIN+
RA3/AN3
C1OUT
Two Independent Comparators with Outputs
A
A
CM2:CM0 = 011
C2
RA1/AN1
VIN-
VIN+
RA2/AN2
C2OUT
A
A
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
VREF Module
 2003 Microchip Technology Inc. DS39582B-page 137
PIC16F87XA
12.2 Comparator Operation
A single comparator is shown in Figure 12-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 12-2 represent
the uncertainty due to input offsets and response time.
12.3 Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingly (Figure 12-2).
FIGURE 12-2: SINGLE COMPARATOR
12.3.1 EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
12.3.2 INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the compara-
tors. Section 13.0 “Comparator Voltage Reference
Module” contains a detailed description of the Compar-
ator Voltage Reference module that provides this signal.
The internal reference signal is used when comparators
are in mode, CM<2:0> = 110 (Figure 12-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
12.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the com-
parator output has a valid level. If the internal reference
is changed, the maximum delay of the internal voltage
reference must be considered when using the compar-
ator outputs. Otherwise, the maximum delay of the
comparators should be used (Section 17.0 “Electrical
Characteristics”).
12.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA4 and RA5
I/O pins. When enabled, multiplexors in the output path
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 12-3 shows the
comparator output block diagram.
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5>).

+
VIN+
VIN-
Output
VIN–
VIN+
Output
Output
VIN+
VIN-
Note 1: When reading the Port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume more current than is specified.
3: RA4 is an open collector I/O pin. When
used as an output, a pull-up resistor is
required.
PIC16F87XA
DS39582B-page 138  2003 Microchip Technology Inc.
FIGURE 12-3: COMPARATOR OUTPUT BLOCK DIAGRAM
12.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it (‘0’). Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
D Q
EN
To RA4 or
RA5 Pin
Bus
Data
Read CMCON
Set
MULTIPLEX
CMIF
bit
- +
D Q
EN
CL
Port Pins
Read CMCON
Reset
From
Other
Comparator
CxINV
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
 2003 Microchip Technology Inc. DS39582B-page 139
PIC16F87XA
12.7 Comparator Operation During
Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current as shown in the com-
parator specifications. To minimize power consumption
while in Sleep mode, turn off the comparators,
CM<2:0> = 111, before entering Sleep. If the device
wakes up from Sleep, the contents of the CMCON
register are not affected.
12.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the
Comparator Off mode, CM<2:0> = 111. This ensures
compatibility to the PIC16F87X devices.
12.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 12-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is rec-
ommended for the analog sources. Any external com-
ponent connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little
leakage current.
FIGURE 12-4: ANALOG INPUT MODEL
VA
RS < 10K
AIN
CPIN
5 pF
VDD
VT = 0.6 V
VT = 0.6 V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
PIC16F87XA
DS39582B-page 140  2003 Microchip Technology Inc.
TABLE 12-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE/
GIEH
PEIE/
GIEL
TMR0IE INTIE RBIE TMR0IF INTIF RBIF 0000 000x 0000 000u
0Dh PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF - 0- - 0000 - 0- - 0000
8Dh PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE - 0- - 0000 - 0- - 0000
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 - - 0x 0000 - - 0u 0000
85h TRISA — — PORTA Data Direction Register - - 11 1111 - - 11 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
 2003 Microchip Technology Inc. DS39582B-page 141
PIC16F87XA
13.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The Comparator Voltage Reference Generator is a
16-tap resistor ladder network that provides a fixed
voltage reference when the comparators are in mode
‘110’. A programmable register controls the function of
the reference generator. Register 13-1 lists the bit
functions of the CVRCON register.
As shown in Figure 13-1, the resistor ladder is seg-
mented to provide two ranges of CVREF values and has
a power-down function to conserve power when the
reference is not being used. The comparator reference
supply voltage (also referred to as CVRSRC) comes
directly from VDD. It should be noted, however, that the
voltage at the top of the ladder is CVRSRC – VSAT,
where VSAT is the saturation voltage of the power
switch transistor. This reference will only be as
accurate as the values of CVRSRC and VSAT.
The output of the reference generator may be con-
nected to the RA2/AN2/VREF-/CVREF pin. This can be
used as a simple D/A function by the user if a very high-
impedance load is used. The primary purpose of this
function is to provide a test path for testing the
reference generator function.
REGISTER 13-1: CVRCON CONTROL REGISTER (ADDRESS 9Dh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin
0 = CVREF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.75 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits 0 VR3:VR0 15
When CVRR = 1:
CVREF = (VR<3:0>/ 24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (VR3:VR0/ 32) (CVRSRC)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582B-page 142  2003 Microchip Technology Inc.
FIGURE 13-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
TABLE 13-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CVRR
8R
CVR3
CVR0
16:1 Analog MUX
8R R R R R
CVREN
CVREF
16 Stages
Input to
Comparator
CVROE
RA2/AN2/VREF-/CVREF
VDD
CVR2
CVR1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
 2003 Microchip Technology Inc. DS39582B-page 143
PIC16F87XA
14.0 SPECIAL FEATURES OF THE
CPU
All PIC16F87XA devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code
protection. These are:
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
• Low-Voltage In-Circuit Serial Programming
• In-Circuit Debugger
PIC16F87XA devices have a Watchdog Timer which
can be shut-off only through configuration bits. It runs
off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in Reset until the crystal oscil-
lator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on power-up only. It is designed to keep the part in
Reset while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry.
Sleep mode is designed to offer a very low current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits is used to
select various options.
Additional information on special features is available
in the PICmicro
®
Mid-Range MCU Family Reference
Manual (DS33023).
14.1 Configuration Bits
The configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’) to select various
device configurations. The erased or unprogrammed
value of the Configuration Word register is 3FFFh.
These bits are mapped in program memory location
2007h.
It is important to note that address 2007h is beyond the
user program memory space which can be accessed
only during programming.
PIC16F87XA
DS39582B-page 144  2003 Microchip Technology Inc.
REGISTER 14-1: CONFIGURATION WORD (ADDRESS 2007h)
(1)

R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
CP — DEBUG WRT1 WRT0 CPD LVP BOREN — — PWRTEN WDTEN FOSC1 FOSC0
bit 13 bit0
bit 13 CP: Flash Program Memory Code Protection bit
1 = Code protection off
0 = All program memory code-protected
bit 12 Unimplemented: Read as ‘1’
bit 11 DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
bit 10-9 WRT1:WRT0 Flash Program Memory Write Enable bits
For PIC16F876A/877A:
11 = Write protection off; all program memory may be written to by EECON control
10 = 0000h to 00FFh write-protected; 0100h to 1FFFh may be written to by EECON control
01 = 0000h to 07FFh write-protected; 0800h to 1FFFh may be written to by EECON control
00 = 0000h to 0FFFh write-protected; 1000h to 1FFFh may be written to by EECON control
For PIC16F873A/874A:
11 = Write protection off; all program memory may be written to by EECON control
10 = 0000h to 00FFh write-protected; 0100h to 0FFFh may be written to by EECON control
01 = 0000h to 03FFh write-protected; 0400h to 0FFFh may be written to by EECON control
00 = 0000h to 07FFh write-protected; 0800h to 0FFFh may be written to by EECON control
bit 8 CPD: Data EEPROM Memory Code Protection bit
1 = Data EEPROM code protection off
0 = Data EEPROM code-protected
bit 7 LVP: Low-Voltage (Single-Supply) In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function; low-voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6 BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5-4 Unimplemented: Read as ‘1’
bit 3 PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Note 1: The erased (unprogrammed) value of the Configuration Word is 3FFFh.
 2003 Microchip Technology Inc. DS39582B-page 145
PIC16F87XA
14.2 Oscillator Configurations
14.2.1 OSCILLATOR TYPES
The PIC16F87XA can be operated in four different
oscillator modes. The user can program two configura-
tion bits (FOSC1 and FOSC0) to select one of these four
modes:
• LP Low-Power Crystal
• XT Crystal/Resonator
• HS High-Speed Crystal/Resonator
• RC Resistor/Capacitor
14.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKI and OSC2/CLKO pins
to establish oscillation (Figure 14-1). The PIC16F87XA
oscillator design requires the use of a parallel cut crys-
tal. Use of a series cut crystal may give a frequency out
of the crystal manufacturer’s specifications. When in
XT, LP or HS modes, the device can have an external
clock source to drive the OSC1/CLKI pin (Figure 14-2).
FIGURE 14-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 14-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC CONFIGURATION)
TABLE 14-1: CERAMIC RESONATORS
Note 1: See Table 14-1 and Table 14-2 for recommended
values of C1 and C2.
2: A series resistor (R
s
) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
C1
(1)
C2
(1)
XTAL
OSC2
OSC1
RF
(3)
Sleep
To
Logic
PIC16F87XA
R
s
(2)
Internal
Ranges Tested:
Mode Freq. OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS 8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
These values are for design guidance only.
See notes following Table 14-2.
Resonators Used:
2.0 MHz Murata Erie CSA2.00MG – 0.5%
4.0 MHz Murata Erie CSA4.00MG – 0.5%
8.0 MHz Murata Erie CSA8.00MT – 0.5%
16.0 MHz Murata Erie CSA16.00MX – 0.5%
All resonators used did not have built-in capacitors.
OSC1
OSC2 Open
Clock from
Ext. System
PIC16F87XA
PIC16F87XA
DS39582B-page 146  2003 Microchip Technology Inc.
TABLE 14-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
14.2.3 RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used. Figure 14-3 shows how the R/C
combination is connected to the PIC16F87XA.
FIGURE 14-3: RC OSCILLATOR MODE
Osc Type
Crystal
Freq.
Cap. Range
C1
Cap. Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
These values are for design guidance only.
See notes following this table.
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
3: R
s
may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PICmicro
®
devices, oscillator performance should be
verified.
OSC2/CLKO
CEXT
REXT
PIC16F87XA
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 k REXT 100 k
CEXT > 20 pF
 2003 Microchip Technology Inc. DS39582B-page 147
PIC16F87XA
14.3 Reset
The PIC16F87XA differentiates between various kinds
of Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT Reset (during normal operation)
• WDT Wake-up (during Sleep)
• Brown-out Reset (BOR)
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCL3(3(3(3(30.0035 Tck)10.6(noco)12.3(3(c0.51.1( op6n)12.5an)13.3(d)]T 1.6(t .3( )3e)-1.31)M)333351.7( th159 713.9603b5a0.004 0.1i)d0.144.96071n12Lrr4 0R5t 2S2Lrr4 e2.6(t)162CL)12.3m8)r.9603 a1o3.960ao 1 2.3.2(us 636 refBT9 042c.147a- 2.33MB1286.51.1(o 1 2 a)132k0035 r4 e2.6(t8)9603)12O6.5KbC0 g80.99.9(ra4(e w8)9603)12O6.6(t9G2(T)-.122O6.03)12O6 2.37T 1.6q31286.51.1(t)-13.3r•o u3.2(p7eTc)2.1(t4.3(3( 1(t)-13.4.3(3( 19-1.31)M: 1(t)2 -0.01434bi56r43 4688n.2 ope)11.(d)]T 1.6014.9( dur)16.6(ing)121(t)-16614o.a)13uec)10.8(t)6667 )13.3(614o.u3.2(p7k)12O6 2.37T 1.6q78 2.39phr)]T 1.6cn25.44e2O6 2. 31(t)-135.44e2O14 ( ac)10.8(33e w(o)127 .601730.07c)10.8(a/R1.3(3( 19-19n738-19n7T*0.0-0.01438-19n738-1tai12.6(r )-19n7T*614o.u3.ot.44e2O6 2. 31(t)-135.r )4o.u3.o2s3T(t4.3(3(t)-135.r S2Lre-132O6 2. 3T2s3Tou3.2(p02 743)1.3r2s3Tou3.5M 722.e22a2 Tw[6(t)162CL406 r3)r2(u41( POR)n4[dK7 19-1-)n4[dK7 10024 Tct8).5Kf3 R)5.6(10.7(h13)r2(u4u3.o2s8g22a2 T(t9G2rBKf3656.000m3(•)-647.4(W)071n1(ebi56r--20m3(•)-647.4(Wt)2.4(e .4(r)12O6 r3667 )13.3(614o.u3.2(p7k00433 TDec)10.8(r--20m3(•bi5Lp7 1.6q355d 1.60s)9.4( K7 19-1-1-1-5m3(•bi5a43s)9.4( K7 19-1N)74u)-13(i6 2. r)12Or2(u).1()m1 196q35.94TJ-21.99.4(t)03(614odoee( 656. /0aI m)n4)u95d5.94TJ-21. I 1b.4( K7 ).1(gO6.5KbaD3Tou3.21a4w13.5( 0 9 5nh22.e53s)9.4( )gO6.5(•bii5nh2. /0aI5nhc.u3.713.3(3999 wt.44e2O6 2. 31(t)-135.r )4o5I 1boyJ-5 3uha)13.2(nge)13nar99 wt.P4 2 )13.3(D)-8.-5 3u(3999HBes)9.4(24 Tc0.14( )gO643ot.P4 2 )13.3(D)-8.-5 4 2 )13.3(D)-8.-5 3u(3999HBes)9.4(24 Tc0.14( )gO643R)]TJET 14( )e2gO649rM)8.7DbaD3Tou32n- 27 6.5J(ebi56rDbaD3Tp.-D)-8..R)]TJEs ope)1e 1.9bi56rr5rc.14( )e2gJE2 (i5nrr5rc.hc.u22 3hc.u22 r7 )e2gJn)11.7( the7(nFP32n- 2CO6.6(t1-)ow13.5( 0 9 5nh22.e53s)9.4( )eMDs2s)9.48tFdo ope)3-u(i3 Tw[(WDT)14FTJEs oa43s)9.(W)48r60s3ToDope)3-Oan)13.3506)3u(3999HB514 oa5ac9.4(24 Tc)13.3(614o.u3)11.7(2u5ac9.4(24 t..0a )130s3To212O6.6(t9G5[(WD 5-7th159 5uT)14D 5-7th19( dv.9603r53.3(e 5uTa 0 929( d/TMB12. oa5ac9-)]T 1.6et) 2 )13.r35uTa9-)]T)13nar8(9603r53.3(P4o5I 1boyI 1 1boyoI 133o614o.a)1t., on)5boyI a1730.07c)1e-dv.962. 0Bpe M
 2003 Microchip Technology Inc. DS39582B-page 159
PIC16F87XA
15.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode which specifies the instruction type and one or
more operands which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 15-1, while the various opcode
fields are summarized in Table 15-1.
Table 15-2 lists the instructions recognized by the
MPASM™ Assembler. A complete description of each
instruction is also available in the PICmicro
®
Mid-Range
MCU Family Reference Manual (DS33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the bit affected by the opera-
tion, while ‘f’ represents the address of the file in which
the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven-bit constant or literal value
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles with the
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
15.1 READ-MODIFY-WRITE
OPERATIONS
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unin-
tended result that the condition that sets the RBIF flag
would be cleared.
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Note: To maintain upward compatibility with
future PIC16F87XA products, do not use
the OPTI ON and TRI S instructions.
Field Description
f Register file address (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don't care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
PD Power-down bit
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16F87XA
DS39582B-page 160  2003 Microchip Technology Inc.
TABLE 15-2: PIC16F87XA INSTRUCTION SET
Mnemonic,
Operands
Description Cycles
14-Bit Opcode
Status
Affected
Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
df f f
df f f
l f f f
0xxx
df f f
df f f
df f f
df f f
df f f
df f f
df f f
l f f f
0xx0
df f f
df f f
df f f
df f f
df f f
f f f f
f f f f
f f f f
xxxx
f f f f
f f f f
f f f f
f f f f
f f f f
f f f f
f f f f
f f f f
0000
f f f f
f f f f
f f f f
f f f f
f f f f
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bf f f
bf f f
bf f f
bf f f
f f f f
f f f f
f f f f
f f f f
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add Literal and W
AND Literal with W
Call Subroutine
Clear Watchdog Timer
Go to Address
Inclusive OR Literal with W
Move Literal to W
Return from Interrupt
Return with Literal in W
Return from Subroutine
Go into Standby mode
Subtract W from Literal
Exclusive OR Literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro
®
Mid-Range MCU
Family Reference Manual (DS33023).
 2003 Microchip Technology Inc. DS39582B-page 161
PIC16F87XA
15.2 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 127
d |
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Description: Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND Literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 127
d |
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next instruc-
tion is discarded and a NOP is
executed instead, making this a
2 TCY instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded and a NOP
is executed instead, making this a
2 TCY instruction.
PIC16F87XA
DS39582B-page 162  2003 Microchip Technology Inc.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits,
TO and PD, are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
 2003 Microchip Technology Inc. DS39582B-page 163
PIC16F87XA
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next instruc-
tion is executed. If the result is ‘0’,
then a NOP is executed instead,
making it a 2 TCY instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next instruc-
tion is executed. If the result is ‘0’,
a NOP is executed instead, making
it a 2 TCY instruction.
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destination)
Status Affected: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
PIC16F87XA
DS39582B-page 164  2003 Microchip Technology Inc.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through the
Carry flag. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
Register f C
Register f C
SLEEP
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected: TO, PD
Description: The power-down status bit, PD,
is cleared. Time-out status bit,
TO, is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status
Affected:
C, DC, Z
Description: Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
 2003 Microchip Technology Inc. DS39582B-page 165
PIC16F87XA
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW Exclusive OR Literal with W
Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Affected: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
PIC16F87XA
DS39582B-page 166  2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS39582B-page167
PIC16F87XA
16.0 DEVELOPMENT SUPPORT
The PICmicro
®
microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB
®
IDE Software
• Assemblers/Compilers/Linkers
- MPASM
TM
Assembler
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINK
TM
Object Linker/
MPLIB
TM
Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PRO MATE
®
II Universal Device Programmer
- PICSTART
®
Plus Development Programmer
• Low Cost Demonstration Boards
- PICDEM
TM
1 Demonstration Board
- PICDEM.net
TM
Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
- KEELOQ
®
- PICDEM MSC
- microID
®
- CAN
- PowerSmart
®
- Analog
16.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows
®
based application that contains:
• An interface to debugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High level source code debugging
• Mouse over variable inspection
• Extensive on-line help
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Debug using:
- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
16.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel
®
standard HEX
files, MAP files to detail memory usage and symbol ref-
erence, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
PIC16F87XA
DS39582B-page 168 2003 Microchip Technology Inc.
16.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
16.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of pre-compiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
16.5 MPLAB C30 C Compiler
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command-
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabili-
ties, and afford fine control of the compiler code
generator.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping, and math functions (trigonometric, exponen-
tial and hyperbolic). The compiler provides symbolic
information for high level source debugging with the
MPLAB IDE.
16.6 MPLAB ASM30 Assembler, Linker,
and Librarian
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
16.7 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execu-
tion can be performed in Single-Step, Execute Until
Break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
16.8 MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
2003 Microchip Technology Inc. DS39582B-page169
PIC16F87XA
16.9 MPLAB ICE 2000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft
®
Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
16.10 MPLAB ICE 4000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory, and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were cho-
sen to best make these features available in a simple,
unified application.
16.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial Programming
TM
(ICSP
TM
)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB Inte-
grated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
16.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify, and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
16.13 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
PIC16F87XA
DS39582B-page 170 2003 Microchip Technology Inc.
16.14 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device program-
mer, or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A pro-
totype area extends the circuitry for additional applica-
tion components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
16.15 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface, and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham.
16.16 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18-, 28-, and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary hardware and software is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
16.17 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
16.18 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14, and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320 fam-
ily of microcontrollers. PICDEM 4 is intended to show-
case the many features of these low pin count parts,
including LIN and Motor Control using ECCP. Special
provisions are made for low power operation with the
supercapacitor circuit, and jumpers allow on-board
hardware to be disabled to eliminate current draw in
this mode. Included on the demo board are provisions
for Crystal, RC or Canned Oscillator modes, a five volt
regulator for use with a nine volt wall adapter or battery,
DB-9 RS-232 interface, ICD connector for program-
ming via ICSP and development with MPLAB ICD 2,
2x16 liquid crystal display, PCB footprints for H-Bridge
motor driver, LIN transceiver and EEPROM. Also
included are: header for expansion, eight LEDs, four
potentiometers, three push buttons and a prototyping
area. Included with the kit is a PIC16F627A and a
PIC18F1320. Tutorial firmware is included along with
the User’s Guide.
16.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development pro-
grammer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
2003 Microchip Technology Inc. DS39582B-page171
PIC16F87XA
16.20 PICDEM 18R PIC18C601/801
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
16.21 PICDEM LIN PIC16C43X
Demonstration Board
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash micro-
controller serves as the master. All three microcontrol-
lers are programmed with firmware to provide LIN bus
communication.
16.22 PICkit
TM
1 Flash Starter Kit
A complete “development system in a box”, the PICkit
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC
®
microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the user's guide (on
CD ROM), PICkit

1 tutorial software and code for vari-
ous applications. Also included are MPLAB
®
IDE (Inte-
grated Development Environment) software, software
and hardware “Tips 'n Tricks for 8-pin Flash PIC
®
Microcontrollers” Handbook and a USB Interface
Cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
16.23 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
16.24 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA
®
development kit
• microID development and rfLab
TM
development
software
• SEEVAL
®
designer kit for memory evaluation and
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high power IR driver, delta sigma
ADC, and flow rate sensor
Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.
PIC16F87XA
DS39582B-page 172 2003 Microchip Technology Inc.
NOTES:
 2003 Microchip Technology Inc. DS39582B-page 173
PIC16F87XA
17.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias................................................................................................................ .-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V
Total power dissipation (Note 1) ............................................................................................................................... 1.0W
Maximum current out of VSS pin ........................................................................................................................... 300 mA
Maximum current into VDD pin .............................................................................................................................. 250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) – 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) – 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin .................................................................................................... 25 mA
Maximum current sunk by PORTA, PORTB and PORTE (combined) (Note 3) .................................................... 200 mA
Maximum current sourced by PORTA, PORTB and PORTE (combined) (Note 3)............................................... 200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................ 200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than
pulling this pin directly to VSS.
3: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16F87XA
DS39582B-page 174  2003 Microchip Technology Inc.
FIGURE 17-1: PIC16F87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED)
FIGURE 17-2: PIC16LF87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
V
o
l
t
a
g
e
6.0V
5.5V
4.5V
4.0V
2.0V
20 MHz
5.0V
3.5V
3.0V
2.5V
PIC16F87XA
Frequency
V
o
l
t
a
g
e
6.0V
5.5V
4.5V
4.0V
2.0V
5.0V
3.5V
3.0V
2.5V
FMAX = (6.0 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro
®
device in the application.
4 MHz 10 MHz
Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16LF87XA
 2003 Microchip Technology Inc. DS39582B-page 175
PIC16F87XA
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial)
PIC16LF873A/874A/ 876A/877A
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Symbol
Characteristic/
Device
Min Typ† Max Units Conditions
VDD Supply Voltage
D001 16LF87XA 2.0 — 5.5 V All configurations
(DC to 10 MHz)
D001 16F87XA 4.0 — 5.5 V All configurations
D001A VBOR 5.5 V BOR enabled, FMAX = 14 MHz
(7)
D002 VDR RAM Data Retention
Voltage
(1)
— 1.5 — V
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
— VSS — V See Section 14.5 “Power-on
Reset (POR)” for details
D004 SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05 — — V/ms See Section 14.5 “Power-on
Reset (POR)” for details
D005 VBOR Brown-out Reset
Voltage
3.65 4.0 4.35 V BODEN bit in configuration word
enabled
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k .
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F87XA
DS39582B-page 176  2003 Microchip Technology Inc.
IDD Supply Current
(2,5)
D010 16LF87XA — 0.6 2.0 mA XT, RC osc configurations,
FOSC = 4 MHz, VDD = 3.0V
D010 16F87XA — 1.6 4 mA XT, RC osc configurations,
FOSC = 4 MHz, VDD = 5.5V
D010A 16LF87XA — 20 35 A LP osc configuration,
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
D013 16F87XA — 7 15 mA HS osc configuration,
FOSC = 20 MHz, VDD = 5.5V
D015 IBOR Brown-out
Reset Current
(6)
— 85 200 A BOR enabled, VDD = 5.0V
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
PIC16LF873A/874A/ 876A/877A
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Symbol
Characteristic/
Device
Min Typ† Max Units Conditions
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k .
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
 2003 Microchip Technology Inc. DS39582B-page 177
PIC16F87XA
IPD Power-down Current
(3,5)
D020 16LF87XA — 7.5 30 A VDD = 3.0V, WDT enabled,
-40 C to +85 C
D020 16F87XA — 10.5 42
60
A
A
VDD = 4.0V, WDT enabled,
-40 C to +85 C
VDD = 4.0V, WDT enabled,
-40 C to +125 C (extended)
D021 16LF87XA — 0.9 5 A VDD = 3.0V, WDT disabled,
0 C to +70 C
D021 16F87XA — 1.5 16
20
A
A
VDD = 4.0V, WDT disabled,
-40 C to +85 C
VDD = 4.0V, WDT disabled,
-40 C to +125 C (extended)
D021A 16LF87XA 0.9 5 A VDD = 3.0V, WDT disabled,
-40 C to +85 C
D021A 16F87XA 1.5 19 A VDD = 4.0V, WDT disabled,
-40 C to +85 C
D023 IBOR Brown-out
Reset Current
(6)

— 85 200 A BOR enabled, VDD = 5.0V
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
PIC16LF873A/874A/ 876A/877A
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Symbol
Characteristic/
Device
Min Typ† Max Units Conditions
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k .
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F87XA
DS39582B-page 178  2003 Microchip Technology Inc.
17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC specification
(Section 17.1)
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buffer VSS — 0.15 VDD V For entire VDD range
D030A VSS — 0.8V V 4.5V VDD 5.5V
D031 with Schmitt Trigger buffer VSS — 0.2 VDD V
D032 MCLR, OSC1 (in RC mode) VSS — 0.2 VDD V
D033 OSC1 (in XT and LP modes) VSS — 0.3V V (Note 1)
OSC1 (in HS mode) VSS — 0.3 VDD V
Ports RC3 and RC4: —
D034 with Schmitt Trigger buffer VSS — 0.3 VDD V For entire VDD range
D034A with SMBus -0.5 — 0.6 V For VDD = 4.5 to 5.5V
VIH Input High Voltage
I/O ports: —
D040 with TTL buffer 2.0 — VDD V 4.5V VDD 5.5V
D040A 0.25 VDD
+ 0.8V
— VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8 VDD — VDD V For entire VDD range
D042 MCLR 0.8 VDD — VDD V
D042A OSC1 (in XT and LP modes) 1.6V — VDD V (Note 1)
OSC1 (in HS mode) 0.7 VDD — VDD V
D043 OSC1 (in RC mode) 0.9 VDD — VDD V
Ports RC3 and RC4:
D044 with Schmitt Trigger buffer 0.7 VDD — VDD V For entire VDD range
D044A with SMBus 1.4 — 5.5 V For VDD = 4.5 to 5.5V
D070 IPURB PORTB Weak Pull-up Current 50 250 400 A VDD = 5V, VPIN = VSS,
-40°C TO +85°C
IIL
Input Leakage Current
(2, 3)
D060 I/O ports — — – 1 A VSS VPIN VDD,
pin at high-impedance
D061 MCLR, RA4/T0CKI — — – 5 A VSS VPIN VDD
D063 OSC1 — — – 5 A VSS VPIN VDD, XT, HS
and LP osc configuration
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87XA be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 2003 Microchip Technology Inc. DS39582B-page 179
PIC16F87XA
VOL Output Low Voltage
D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40 C to +85 C
D083 OSC2/CLKO (RC osc config) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40 C to +85 C
VOH Output High Voltage
D090 I/O ports
(3)
VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V,
-40 C to +85 C
D092 OSC2/CLKO (RC osc config) VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V,
-40 C to +85 C
D150* VOD Open-Drain High Voltage — — 8.5 V RA4 pin
Capacitive Loading Specs on
Output Pins
D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101
D102
CIO
CB
All I/O pins and OSC2 (RC mode)
SCL, SDA (I
2
C mode)




50
400
pF
pF
Data EEPROM Memory
D120 ED Endurance 100K 1M — E/W -40 C to +85 C
D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write,
VMIN = min. operating voltage
D122 TDEW Erase/write cycle time — 4 8 ms
Program Flash Memory
D130 EP Endurance 10K 100K — E/W -40 C to +85 C
D131 VPR VDD for read VMIN — 5.5 V VMIN = min. operating voltage
D132A VDD for erase/write VMIN — 5.5 V Using EECON to read/write,
VMIN = min. operating voltage
D133 TPEW Erase/Write cycle time — 4 8 ms
17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC specification
(Section 17.1)
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87XA be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC16F87XA
DS39582B-page 180  2003 Microchip Technology Inc.
TABLE 17-1: COMPARATOR SPECIFICATIONS
TABLE 17-2: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Sym Characteristics Min Typ Max Units Comments
D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV
D301 VICM Input Common Mode Voltage* 0 - VDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio* 55 - — dB
300
300A
TRESP Response Time*
(1)
— 150 400
600
ns
ns
PIC16F87XA
PIC16LF87XA
301 TMC2OV Comparator Mode Change to
Output Valid*
— — 10 s
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from
VSS to VDD.
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)
Spec
No.
Sym Characteristics Min Typ Max Units Comments
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy —



1/2
1/2
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
D312 VRUR Unit Resistor Value (R)* — 2k —
310 TSET Settling Time*
(1)
— — 10 s
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
 2003 Microchip Technology Inc. DS39582B-page 181
PIC16F87XA
17.3 Timing Parameter Symbology
The timing parameter symbols have been created
following one of the following formats:
FIGURE 17-3: LOAD CONDITIONS
1. TppS2ppS
3. TCC:ST (I
2
C specifications only)
2. TppS
4. Ts (I
2
C specifications only)
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
I
2
C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I
2
C specifications only)
CC
HD Hold SU Setup
ST
DAT Data input hold STO Stop condition
STA Start condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL = 464
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports,
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
Load Condition 1 Load Condition 2
PIC16F87XA
DS39582B-page 182  2003 Microchip Technology Inc.
FIGURE 17-4: EXTERNAL CLOCK TIMING
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3 3 4 4
TABLE 17-3: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
FOSC External CLKI Frequency
(Note 1)
DC — 1 MHz XT and RC Osc mode
DC — 20 MHz HS Osc mode
DC — 32 kHz LP Osc mode
Oscillator Frequency
(Note 1)
DC — 4 MHz RC Osc mode
0.1 — 4 MHz XT Osc mode
4
5


20
200
MHz
kHz
HS Osc mode
LP Osc mode
1 TOSC External CLKI Period
(Note 1)
1000 — — ns XT and RC Osc mode
50 — — ns HS Osc mode
5 — — s LP Osc mode
Oscillator Period
(Note 1)
250 — — ns RC Osc mode
250 — 1 s XT Osc mode
100 — 250 ns HS Osc mode
50 — 250 ns HS Osc mode
31.25 — — s LP Osc mode
2 TCY Instruction Cycle Time
(Note 1)
200 TCY DC ns TCY = 4/FOSC
3 TOSL,
TOSH
External Clock in (OSC1) High or
Low Time
100 — — ns XT oscillator
2.5 — — s LP oscillator
15 — — ns HS oscillator
4 TOSR,
TOSF
External Clock in (OSC1) Rise or
Fall Time
— — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time
limit is “DC” (no clock) for all devices.
 2003 Microchip Technology Inc. DS39582B-page 183
PIC16F87XA
FIGURE 17-5: CLKO AND I/O TIMING
TABLE 17-4: CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value New Value
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
10* TOSH2CKL OSC1 to CLKO — 75 200 ns (Note 1)
11* TOSH2CKH OSC1 to CLKO — 75 200 ns (Note 1)
12* TCKR CLKO Rise Time — 35 100 ns (Note 1)
13* TCKF CLKO Fall Time — 35 100 ns (Note 1)
14* TCKL2IOV CLKO to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)
15* TIOV2CKH Port In Valid before CLKO TOSC + 200 — — ns (Note 1)
16* TCKH2IOI Port In Hold after CLKO 0 — — ns (Note 1)
17* TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid — 100 255 ns
18* TOSH2IOI OSC1 (Q2 cycle) to Port Input
Invalid (I/O in hold time)
Standard (F) 100 — — ns
Extended (LF) 200 — — ns
19* TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns
20* TIOR Port Output Rise Time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
21* TIOF Port Output Fall Time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
22††* TINP INT pin High or Low Time TCY — — ns
23††* TRBP RB7:RB4 Change INT High or Low Time TCY — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC.
PIC16F87XA
DS39582B-page 184  2003 Microchip Technology Inc.
FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 17-7: BROWN-OUT RESET TIMING
TABLE 17-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 17-3 for load conditions.
VDD
VBOR
35
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C
31* TWDT Watchdog Timer Time-out Period
(no prescaler)
7 18 33 ms VDD = 5V, -40°C to +85°C
32 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
33* TPWRT Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
— — 2.1 s
35 TBOR Brown-out Reset Pulse Width 100 — — s VDD VBOR (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
 2003 Microchip Technology Inc. DS39582B-page 185
PIC16F87XA
FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* TT0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4,..., 256)
45* TT1H T1CKI High
Time
Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler = 2, 4, 8
Standard(F) 15 — — ns
Extended(LF) 25 — — ns
Asynchronous Standard(F) 30 — — ns
Extended(LF) 50 — — ns
46* TT1L T1CKI Low Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler = 2, 4, 8
Standard(F) 15 — — ns
Extended(LF) 25 — — ns
Asynchronous Standard(F) 30 — — ns
Extended(LF) 50 — — ns
47* TT1P T1CKI Input
Period
Synchronous Standard(F) Greater of:
30 or TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Extended(LF) Greater of:
50 or TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous Standard(F) 60 — — ns
Extended(LF) 100 — — ns
FT1 Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
DC — 200 kHz
48 TCKEZTMR1 Delay from External Clock Edge to Timer Increment 2 TOSC — 7 TOSC —
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 17-3 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 or TMR1
PIC16F87XA
DS39582B-page 186  2003 Microchip Technology Inc.
FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 17-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Note: Refer to Figure 17-3 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
50* TCCL CCP1 and CCP2
Input Low Time
No Prescaler 0.5 TCY + 20 — — ns
With Prescaler
Standard(F) 10 — — ns
Extended(LF) 20 — — ns
51* TCCH CCP1 and CCP2
Input High Time
No Prescaler 0.5 TCY + 20 — — ns
With Prescaler
Standard(F) 10 — — ns
Extended(LF) 20 — — ns
52* TCCP CCP1 and CCP2 Input Period 3 TCY + 40
N
— — ns N = prescale value
(1, 4 or 16)
53* TCCR CCP1 and CCP2 Output Rise Time Standard(F) — 10 25 ns
Extended(LF) — 25 50 ns
54* TCCF CCP1 and CCP2 Output Fall Time Standard(F) — 10 25 ns
Extended(LF) — 25 45 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
 2003 Microchip Technology Inc. DS39582B-page 187
PIC16F87XA
FIGURE 17-10: PARALLEL SLAVE PORT TIMING (PIC16F874A/ 877A ONLY)
TABLE 17-8: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/ 877A ONLY)
Note: Refer to Figure 17-3 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
62 TDTV2WRH Data In Valid before WR or CS (setup time) 20 — — ns
63* TWRH2DTI WR or CS to Data–in Invalid
(hold time)
Standard(F) 20 — — ns
Extended(LF) 35 — — ns
64 TRDL2DTV RD and CS to Data–out Valid — — 80 ns
65 TRDH2DTI RD or CS to Data–out Invalid 10 — 30 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
PIC16F87XA
DS39582B-page 188  2003 Microchip Technology Inc.
FIGURE 17-11: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 17-12: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
78 79
80
79 78
MSb LSb Bit 6 - - - - - -1
MSb In
LSb In Bit 6 - - - -1
Note: Refer to Figure 17-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
Bit 6 - - - - - -1
LSb In Bit 6 - - - -1
LSb
Note: Refer to Figure 17-3 for load conditions.
 2003 Microchip Technology Inc. DS39582B-page 189
PIC16F87XA
FIGURE 17-13: SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 17-14: SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
77
78 79
80
79 78
SDI
MSb LSb Bit 6 - - - - - -1
MSb In Bit 6 - - - -1 LSb In
83
Note: Refer to Figure 17-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb Bit 6 - - - - - -1 LSb
77
MSb In Bit 6 - - - -1 LSb In
80
83
Note: Refer to Figure 17-3 for load conditions.
PIC16F87XA
DS39582B-page 190  2003 Microchip Technology Inc.
TABLE 17-9: SPI MODE REQUIREMENTS
FIGURE 17-15: I
2
C BUS START/STOP BITS TIMING
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
70* TSSL2SCH,
TSSL2SCL
SS to SCK or SCK Input TCY — — ns
71* TSCH SCK Input High Time (Slave mode) TCY + 20 — — ns
72* TSCL SCK Input Low Time (Slave mode) TCY + 20 — — ns
73* TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — — ns
74* TSCH2DIL,
TSCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — — ns
75* TDOR SDO Data Output Rise Time Standard(F)
Extended(LF)


10
25
25
50
ns
ns
76* TDOF SDO Data Output Fall Time — 10 25 ns
77* TSSH2DOZ SS to SDO Output High-Impedance 10 — 50 ns
78* TSCR SCK Output Rise Time
(Master mode)
Standard(F)
Extended(LF)


10
25
25
50
ns
ns
79* TSCF SCK Output Fall Time (Master mode) — 10 25 ns
80* TSCH2DOV,
TSCL2DOV
SDO Data Output Valid after
SCK Edge
Standard(F)
Extended(LF)




50
145
ns
81* TDOV2SCH,
TDOV2SCL
SDO Data Output Setup to SCK Edge TCY — — ns
82* TSSL2DOV SDO Data Output Valid after SS Edge — — 50 ns
83* TSCH2SSH,
TSCL2SSH
SS after SCK Edge 1.5 TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 17-3 for load conditions.
91
93
SCL
SDA
Start
Condition
Stop
Condition
90 92
 2003 Microchip Technology Inc. DS39582B-page 191
PIC16F87XA
TABLE 17-10: I
2
C BUS START/STOP BITS REQUIREMENTS
FIGURE 17-16: I
2
C BUS DATA TIMING
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
90 TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Start
condition
Setup time 400 kHz mode 600 — —
91 THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first clock pulse
is generated
Hold time 400 kHz mode 600 — —
92 TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note: Refer to Figure 17-3 for load conditions.
90
91 92
100
101
103
106
107
109 109
110
102
SCL
SDA
In
SDA
Out
PIC16F87XA
DS39582B-page 192  2003 Microchip Technology Inc.
TABLE 17-11: I
2
C BUS DATA REQUIREMENTS
Param
No.
Sym Characteristic Min Max Units Conditions
100 THIGH Clock High Time 100 kHz mode 4.0 — s
400 kHz mode 0.6 — s
SSP Module 0.5 TCY —
101 TLOW Clock Low Time 100 kHz mode 4.7 — s
400 kHz mode 1.3 — s
SSP Module 0.5 TCY —
102 TR SDA and SCL Rise
Time
100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB 300 ns Cb is specified to be from 10 to
400 pF
103 TF SDA and SCL Fall
Time
100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to
400 pF
90 TSU:STA Start Condition Setup
Time
100 kHz mode 4.7 — s Only relevant for Repeated Start
condition
400 kHz mode 0.6 — s
91 THD:STA Start Condition Hold
Time
100 kHz mode 4.0 — s After this period, the first clock
pulse is generated
400 kHz mode 0.6 — s
106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO Stop Condition Setup
Time
100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109 TAA Output Valid from
Clock
100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before
a new transmission can start
400 kHz mode 1.3 — s
CB Bus Capacitive Loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A fast mode (400 kHz) I
2
C bus device can be used in a standard mode (100 kHz) I
2
C bus system, but the requirement
that, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, TR MAX. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I
2
C bus specification),
before the SCL line is released.
 2003 Microchip Technology Inc. DS39582B-page 193
PIC16F87XA
FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 17-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
121
121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
120 TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid Standard(F) — — 80 ns
Extended(LF) — — 100 ns
121 TCKRF Clock Out Rise Time and Fall Time
(Master mode)
Standard(F) — — 45 ns
Extended(LF) — — 50 ns
122 TDTRF Data Out Rise Time and Fall Time Standard(F) — — 45 ns
Extended(LF) — — 50 ns
† Data in “Typ” column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note: Refer to Figure 17-3 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
125 TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Setup before CK (DT setup time) 15 — — ns
126 TCKL2DTL Data Hold after CK (DT hold time) 15 — — ns
† Data in “Typ” column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance
only and are not tested.
PIC16F87XA
DS39582B-page 194  2003 Microchip Technology Inc.
TABLE 17-14: A/D CONVERTER CHARACTERISTICS:PIC16F873A/874A/876A/877A (INDUSTRIAL)
PIC16LF873A/874A/876A/877A (INDUSTRIAL)
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V,
VSS VAIN VREF
A03 EIL Integral Linearity Error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A04 EDL Differential Linearity Error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A06 EOFF Offset Error — — < ± 2 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A07 EGN Gain Error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A10 — Monotonicity — guaranteed
(3)
— — VSS VAIN VREF
A20 VREF Reference Voltage (VREF+ – VREF-) 2.0 — VDD + 0.3 V
A21 VREF+ Reference Voltage High AVDD – 2.5V AVDD + 0.3V V
A22 VREF- Reference Voltage Low AVSS – 0.3V VREF+ – 2.0V V
A25 VAIN Analog Input Voltage VSS – 0.3V — VREF + 0.3V V
A30 ZAIN Recommended Impedance of
Analog Voltage Source
— — 2.5 k (Note 4)
A40 IAD A/D Conversion
Current (VDD)
PIC16F87XA — 220 — A Average current
consumption when A/D is
on (Note 1)
PIC16LF87XA — 90 — A
A50 IREF VREF Input Current (Note 2) —



5
150
A
A
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 11.1
“A/D Acquisition
Requirements”.
During A/D conversion
cycle
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec
includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
4: Maximum allowed impedance for analog voltage source is 10 k This requires higher acquisition time.
 2003 Microchip Technology Inc. DS39582B-page 195
PIC16F87XA
FIGURE 17-19: A/D CONVERSION TIMING
TABLE 17-15: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
(TOSC/2)
(1)
9 8 7 2 1 0
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
1 TCY

Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
130 TAD A/D Clock Period PIC16F87XA 1.6 — — s TOSC based, VREF 3.0V
PIC16LF87XA 3.0 — — s TOSC based, VREF 2.0V
PIC16F87XA 2.0 4.0 6.0 s A/D RC mode
PIC16LF87XA 3.0 6.0 9.0 s A/D RC mode
131 TCNV Conversion Time (not including S/H time)
(Note 1)
— 12 TAD
132 TACQ Acquisition Time (Note 2)
10*
40



s
s The minimum time is the
amplifier settling time. This may
be used if the “new” input volt-
age has not changed by more
than 1 LSb (i.e., 20.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134 TGO Q4 to A/D Clock Start — TOSC/2 § — — If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 “A/D Acquisition Requirements” for minimum conditions.
PIC16F87XA
DS39582B-page 196  2003 Microchip Technology Inc.
NOTES:
 2003 Microchip Technology Inc. DS39582B-page 197
PIC16F87XA
18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
“Typical” represents the mean of the distribution at 25 C. “Maximum” or “minimum” represents (mean + 3 ) or (mean – 3 )
respectively, where is a standard deviation, over the whole temperature range.
FIGURE 18-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
FIGURE 18-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
0
1
2
3
4
5
6
7
4 6 8 10 12 14 16 18 20
FOSC (MHz)
I
D
D

(
m
A
)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
1
2
3
4
5
6
7
8
4 6 8 10 12 14 16 18 20
FOSC (MHz)
I
D
D

(
m
A
)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582B-page 198  2003 Microchip Technology Inc.
FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 500 1000 1500 2000 2500 3000 3500 4000
FOSC (MHz)
I
D
D

(
m
A
)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
0 500 1000 1500 2000 2500 3000 3500 4000
FOSC (MHz)
I
D
D

(
m
A
)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
 2003 Microchip Technology Inc. DS39582B-page 199
PIC16F87XA
FIGURE 18-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
FIGURE 18-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
0
10
20
30
40
50
60
70
20 30 40 50 60 70 80 90 100
FOSC (kHz)
I
D
D

(
u
A
)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
20
40
60
80
100
120
20 30 40 50 60 70 80 90 100
FOSC (kHz)
I
D
D

(
u
A
)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582B-page 200  2003 Microchip Technology Inc.
FIGURE 18-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25 C)
FIGURE 18-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, +25 C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
F
r
e
q

(
M
H
z
)
100 kOhm
10 kOhm
5.1 kOhm
Operation above 4 MHz is not recommended
0.0
0.5
1.0
1.5
2.0
2.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
F
r
e
q

(
M
H
z
)
100 kOhm
10 kOhm
5.1 kOhm
3.3 kOhm
 2003 Microchip Technology Inc. DS39582B-page 201
PIC16F87XA
FIGURE 18-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, +25 C)
FIGURE 18-10: IPD vs. VDD, -40 C TO +125 C (SLEEP MODE, ALL PERIPHERALS DISABLED)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
F
r
e
q

(
M
H
z
)
100 kOhm
10 kOhm
5.1 kOhm
3.3 kOhm
0.001
0.01
0.1
1
10
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
u
A
)
Typ (25°C)
Max (85°C)
Max (125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582B-page 202  2003 Microchip Technology Inc.
FIGURE 18-11: TYPICAL AND MAXIMUM ITMR1 vs. VDD OVER TEMPERATURE (-10 C TO +70 C,
TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF)
FIGURE 18-12: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)
0
2
4
6
8
10
12
14
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
u
A
)
Typ (25C)
Max (70C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-10°C to +70°C)
Minimum: mean – 3 (-10°C to +70°C)
I
P
D

(

A
)
Max (+70°C)
Typ (+25°C)
0.1
1
10
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
u
A
)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
Max (+125°C)
Max (+85°C)
Typ (+25°C)
 2003 Microchip Technology Inc. DS39582B-page 203
PIC16F87XA
FIGURE 18-13: IBOR vs. VDD OVER TEMPERATURE
FIGURE 18-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40 C TO +125 C)
10
100
1,000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
D
D

(

A
)
Device in
Reset
Device in
Sleep
Indeterminant
State
Max (125°C)
Typ (25°C)
Max (125°C)
Typ (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
Note: Device current in Reset
depends on oscillator mode,
frequency and circuit.
0
5
10
15
20
25
30
35
40
45
50
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
W
D
T

P
e
r
i
o
d

(
m
s
)
Max
(125°C)
Typ
(25°C)
Min
(-40°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582B-page 204  2003 Microchip Technology Inc.
FIGURE 18-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40 C TO +125 C)
FIGURE 18-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40 C TO +125 C)
0
5
10
15
20
25
30
35
40
45
50
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
W
D
T

P
e
r
i
o
d

(
m
s
)
125°C
85°C
25°C
-40°C
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0 5 10 15 20 25
IOH (-mA)
V
O
H

(
V
)
Max
Typ (25°C)
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
 2003 Microchip Technology Inc. DS39582B-page 205
PIC16F87XA
FIGURE 18-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40 C TO +125 C)
FIGURE 18-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40 C TO +125 C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 5 10 15 20 25
IOH (-mA)
V
O
H

(
V
)
Max
Typ (25°C)
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
IOL (-mA)
V
O
L

(
V
)
Max (125°C)
Max (85°C)
Typ (25°C)
Min (-40°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582B-page 206  2003 Microchip Technology Inc.
FIGURE 18-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40 C TO +125 C)
FIGURE 18-20: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40 C TO +125 C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25
IOL (-mA)
V
O
L

(
V
)
Max (125°C)
Max (85°C)
Typ (25°C)
Min (-40°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
V
I
N

(
V
)
VTH Max (-40°C)
VTH Min (125°C)
VTH Typ (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
 2003 Microchip Technology Inc. DS39582B-page 207
PIC16F87XA
FIGURE 18-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40 C TO +125 C)
FIGURE 18-22: MINIMUM AND MAXIMUM VIN vs. VDD (I
2
C INPUT, -40 C TO +125 C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
V
I
N

(
V
)
VIH Max (125°C)
VIH Min (-40°C)
VIL Max (-40°C)
VIL Min (125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
V
I
N

(
V
)
VIH Max
VIH Min
VILMax
VIL Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
VIL Max
PIC16F87XA
DS39582B-page 208  2003 Microchip Technology Inc.
FIGURE 18-23: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40 C TO +125 C)
FIGURE 18-24: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40 C TO +125 C)
0
0.5
1
1.5
2
2.5
3
3.5
4
2 2.5 3 3.5 4 4.5 5 5.5
VDD and VREFH (V)
D
i
f
f
e
r
e
n
t
i
a
l

o
r

I
n
t
e
g
r
a
l

N
o
n
l
i
n
e
a
r
i
t
y

(
L
S
B
)
-40C
25C
85C
125C
-40°C
+25°C
+85°C
+125°C
0
0.5
1
1.5
2
2.5
3
2 2.5 3 3.5 4 4.5 5 5.5
VREFH (V)
D
i
f
f
e
r
e
n
t
i
a
l

o
r

I
n
t
e
g
r
a
l

N
o
n
l
i
n
e
a
r
i
l
t
y

(
L
S
B
)
Max (-40C to 125C)
Typ (25C) Typ (+25°C)
Max (-40°C to +125°C)
 2003 Microchip Technology Inc. DS39582B-page 209
PIC16F87XA
19.0 PACKAGING INFORMATION
19.1 Package Marking Information
40-Lead PDIP
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F877A/P
0310017
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
PIC16F877A
/PT
0310017
44-Lead PLCC
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
PIC16F877A
-20/L
0310017
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
PIC16F87XA
DS39582B-page 210  2003 Microchip Technology Inc.
Package Marking Information (Cont’d)
XXXXXXXXXX
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F876A/SP
0310017
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F876A/SO
0310017
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC16F876A/
SS
0310017
Example 28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
PIC16F877A
-I/ML
0310017
16F873A
-I/ML
0310017
 2003 Microchip Technology Inc. DS39582B-page 211
PIC16F87XA
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
15 10 5 15 10 5 Mold Draft Angle Bottom
15 10 5 15 10 5 Mold Draft Angle Top
17.27 16.51 15.75 .680 .650 .620 eB Overall Row Spacing §
0.56 0.46 0.36 .022 .018 .014 B Lower Lead Width
1.78 1.27 0.76 .070 .050 .030 B1 Upper Lead Width
0.38 0.29 0.20 .015 .012 .008 c Lead Thickness
3.43 3.30 3.05 .135 .130 .120 L Tip to Seating Plane
52.45 52.26 51.94 2.065 2.058 2.045 D Overall Length
14.22 13.84 13.46 .560 .545 .530 E1 Molded Package Width
15.88 15.24 15.11 .625 .600 .595 E Shoulder to Shoulder Width
0.38 .015 A1 Base to Seating Plane
4.06 3.81 3.56 .160 .150 .140 A2 Molded Package Thickness
4.83 4.45 4.06 .190 .175 .160 A Top to Seating Plane
2.54 .100
p
Pitch
40 40 n Number of Pins
MAX NOM MIN MAX NOM MIN Dimension Limits
MILLIMETERS INCHES* Units
A2
1
2
D
n
E1
c

eB
E

p
L
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
§ Significant Characteristic
PIC16F87XA
DS39582B-page 212  2003 Microchip Technology Inc.
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.14 0.89 0.64 .045 .035 .025 CH Pin 1 Corner Chamfer
1.00 .039 (F) Footprint (Reference)
(F)
A
A1 A2

E
E1
#leads=n1
p
B
D1 D
n
1
2

c

L
Units INCHES MILLIMETERS*
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 44 44
Pitch
p
.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff § A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot Angle 0 3.5 7 0 3.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 11.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c .004 .006 .008 0.09 0.15 0.20
Lead Width B .012 .015 .017 0.30 0.38 0.44
Mold Draft Angle Top 5 10 15 5 10 15
Mold Draft Angle Bottom 5 10 15 5 10 15
CH x 45
§ Significant Characteristic
 2003 Microchip Technology Inc. DS39582B-page 213
PIC16F87XA
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
CH2 x 45 CH1 x 45
10 5 0 10 5 0 Mold Draft Angle Bottom
10 5 0 10 5 0 Mold Draft Angle Top
0.53 0.51 0.33 .021 .020 .013 B
0.81 0.74 0.66 .032 .029 .026 B1 Upper Lead Width
0.33 0.27 0.20 .013 .011 .008 c Lead Thickness
11 11 n1 Pins per Side
16.00 15.75 14.99 .630 .620 .590 D2 Footprint Length
16.00 15.75 14.99 .630 .620 .590 E2 Footprint Width
16.66 16.59 16.51 .656 .653 .650 D1 Molded Package Length
16.66 16.59 16.51 .656 .653 .650 E1 Molded Package Width
17.65 17.53 17.40 .695 .690 .685 D Overall Length
17.65 17.53 17.40 .695 .690 .685 E Overall Width
0.25 0.13 0.00 .010 .005 .000 CH2 Corner Chamfer (others)
1.27 1.14 1.02 .050 .045 .040 CH1 Corner Chamfer 1
0.86 0.74 0.61 .034 .029 .024 A3 Side 1 Chamfer Height
0.51 .020 A1 Standoff §
A2 Molded Package Thickness
4.57 4.39 4.19 .180 .173 .165 A Overall Height
1.27 .050
p
Pitch
44 44 n Number of Pins
MAX NOM MIN MAX NOM MIN Dimension Limits
MILLIMETERS INCHES* Units

A2
c
E2
2
D D1
n
#leads=n1
E
E1
1

p
A3
A
35
B1
B
D2
A1
.145 .153 .160 3.68 3.87 4.06
.028 .035 0.71 0.89
Lower Lead Width
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
§ Significant Characteristic
PIC16F87XA
DS39582B-page 214  2003 Microchip Technology Inc.
44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
Lead Width
*Controlling Parameter
Drawing No. C04-103
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
B .012 .013 .013 0.30 0.33 0.35
Pitch
Number of Pins
Overall Width
Standoff
Overall Length
Overall Height
MAX
Units
Dimension Limits
A1
D
E
n
p
A
.315 BSC
.000
INCHES
.026 BSC
MIN
44
NOM MAX
.002 0
8.00 BSC
MILLIMETERS*
.039
MIN
44
0.65 BSC
NOM
0.05
1.00
.010 REF Base Thickness A3 0.25 REF
JEDEC equivalent: M0-220
0.90 .035
.001 0.02
.315 BSC 8.00 BSC
Lead Length L .014 .016 .018 0.35 0.40 0.45
E2
D2
Exposed Pad Width
Exposed Pad Length .262 .268 .274 6.65 6.80 6.95
.262 .268 .274 6.65 6.80 6.95
D2
D
A1
A3
A
TOP VIEW
n
1
L
E2
BOTTOM VIEW
B
E
2
PAD
METAL
EXPOSED
p
PIN 1
INDEX ON
EXPOSED PAD
TOP MARKING
INDEX ON
OPTIONAL PIN 1
.031 0.80
 2003 Microchip Technology Inc. DS39582B-page 215
PIC16F87XA
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
15 10 5 15 10 5 Mold Draft Angle Bottom
15 10 5 15 10 5 Mold Draft Angle Top
10.92 8.89 8.13 .430 .350 .320 eB Overall Row Spacing §
0.56 0.48 0.41 .022 .019 .016 B Lower Lead Width
1.65 1.33 1.02 .065 .053 .040 B1 Upper Lead Width
0.38 0.29 0.20 .015 .012 .008 c Lead Thickness
3.43 3.30 3.18 .135 .130 .125 L Tip to Seating Plane
35.18 34.67 34.16 1.385 1.365 1.345 D Overall Length
7.49 7.24 6.99 .295 .285 .275 E1 Molded Package Width
8.26 7.87 7.62 .325 .310 .300 E Shoulder to Shoulder Width
0.38 .015 A1 Base to Seating Plane
3.43 3.30 3.18 .135 .130 .125 A2 Molded Package Thickness
4.06 3.81 3.56 .160 .150 .140 A Top to Seating Plane
2.54 .100
p
Pitch
28 28 n Number of Pins
MAX NOM MIN MAX NOM MIN Dimension Limits
MILLIMETERS INCHES* Units
2
1
D
n
E1
c
eB

E

p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
* Controlling Parameter
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
§ Significant Characteristic
PIC16F87XA
DS39582B-page 216  2003 Microchip Technology Inc.
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Foot Angle Top 0 4 8 0 4 8
15 12 0 15 12 0 Mold Draft Angle Bottom
15 12 0 15 12 0 Mold Draft Angle Top
0.51 0.42 0.36 .020 .017 .014 B Lead Width
0.33 0.28 0.23 .013 .011 .009 c Lead Thickness
1.27 0.84 0.41 .050 .033 .016 L Foot Length
0.74 0.50 0.25 .029 .020 .010 h Chamfer Distance
18.08 17.87 17.65 .712 .704 .695 D Overall Length
7.59 7.49 7.32 .299 .295 .288 E1 Molded Package Width
10.67 10.34 10.01 .420 .407 .394 E Overall Width
0.30 0.20 0.10 .012 .008 .004 A1 Standoff §
2.39 2.31 2.24 .094 .091 .088 A2 Molded Package Thickness
2.64 2.50 2.36 .104 .099 .093 A Overall Height
1.27 .050
p
Pitch
28 28 n Number of Pins
MAX NOM MIN MAX NOM MIN Dimension Limits
MILLIMETERS INCHES* Units
2
1
D
p
n
B
E
E1
L
c

45
h

A2

A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
§ Significant Characteristic
 2003 Microchip Technology Inc. DS39582B-page 217
PIC16F87XA
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
10 5 0 10 5 0 Mold Draft Angle Bottom
10 5 0 10 5 0 Mold Draft Angle Top
0.38 0.32 0.25 .015 .013 .010 B Lead Width
203.20 101.60 0.00 8 4 0 Foot Angle
0.25 0.18 0.10 .010 .007 .004 c Lead Thickness
0.94 0.75 0.56 .037 .030 .022 L Foot Length
10.34 10.20 10.06 .407 .402 .396 D Overall Length
5.38 5.25 5.11 .212 .207 .201 E1 Molded Package Width
8.10 7.85 7.59 .319 .309 .299 E Overall Width
0.25 0.15 0.05 .010 .006 .002 A1 Standoff §
1.83 1.73 1.63 .072 .068 .064 A2 Molded Package Thickness
1.98 1.85 1.73 .078 .073 .068 A Overall Height
0.65 .026
p
Pitch
28 28 n Number of Pins
MAX NOM MIN MAX NOM MIN Dimension Limits
MILLIMETERS* INCHES Units
2
1
D
p
n
B
E1
E
L

c

A2
A1
A

§ Significant Characteristic
PIC16F87XA
DS39582B-page 218  2003 Microchip Technology Inc.
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN)
Lead Width
*Controlling Parameter
Drawing No. C04-114
Notes:
Mold Draft Angle Top
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
B

.009
12°
.011 .014 0.23
12°
0.28 0.35
Pitch
Number of Pins
Overall Width
Standoff
Molded Package Length
Overall Length
Molded Package Width
Molded Package Thickness
Overall Height
MAX
Units
Dimension Limits
A2
A1
E1
D
D1
E
n
p
A
.026
.236 BSC
.000
.226 BSC
INCHES
.026 BSC
MIN
28
NOM MAX
0.65 .031
.002 0.00
6.00 BSC
5.75 BSC
MILLIMETERS*
.039
MIN
28
0.65 BSC
NOM
0.80
0.05
1.00
.008 REF Base Thickness A3 0.20 REF
JEDEC equivalent: mMO-220
0.85 .033
.0004 0.01
.236 BSC
.226 BSC
6.00 BSC
5.75 BSC
Lead Length
Tie Bar Width
L .020 .024 .030 0.50 0.60 0.75
R .005 .007 .010 0.13 0.17 0.23
Tie Bar Length Q .012 .016 .026 0.30 0.40 0.65
Chamfer CH .009 .017 .024 0.24 0.42 0.60
E2
D2
Exposed Pad Width
Exposed Pad Length .140 .146 .152 3.55 3.70 3.85
.140 .146 .152 3.55 3.70 3.85
D
E
E1
n
1
2
D1
A
A2
EXPOSED
METAL
PADS
BOTTOM VIEW
TOP VIEW
Q
L
R
p
A1
A3

CH X 45°
B
D2
E2
 2003 Microchip Technology Inc. DS39582B-page 219
PIC16F87XA
APPENDIX A: REVISION HISTORY
Revision A (November 2001)
Original data sheet for PIC16F87XA devices. The
devices presented are enhanced versions of the
PIC16F87X microcontrollers discussed in the
“PIC16F87X Data Sheet” (DS30292).
Revision B (October 2003)
This revision includes the DC and AC Characteristics
Graphs and Tables. The Electrical Specifications in
Section 17.0 “Electrical Characteristics” have been
updated and there have been minor corrections to the
data sheet text.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
TABLE B-1: DIFFERENCES BETWEEN DEVICES IN THE PIC16F87XA FAMILY
PIC16F873A PIC16F874A PIC16F876A PIC16F877A
Flash Program Memory
(14-bit words)
4K 4K 8K 8K
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Slave Port No Yes No Yes
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Packages 28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
PIC16F87XA
DS39582B-page 220  2003 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
Considerations for converting from previous versions
of devices to the ones listed in this data sheet are listed
in Table C-1.
TABLE C-1: CONVERSION CONSIDERATIONS
Characteristic PIC16C7X PIC16F87X PIC16F87XA
Pins 28/40 28/40 28/40
Timers 3 3 3
Interrupts 11 or 12 13 or 14 14 or 15
Communication PSP, USART, SSP
(SPI, I
2
C Slave)
PSP, USART, SSP
(SPI, I
2
C Master/Slave)
PSP, USART, SSP
(SPI, I
2
C Master/Slave)
Frequency 20 MHz 20 MHz 20 MHz
Voltage 2.5V-5.5V 2.2V-5.5V 2.0V-5.5V
A/D 8-bit,
4 conversion clock selects
10-bit,
4 conversion clock selects
10-bit,
7 conversion clock selects
CCP 2 2 2
Comparator — — 2
Comparator Voltage
Reference
— — Yes
Program Memory 4K, 8K EPROM 4K, 8K Flash
(Erase/Write on
single-word)
4K, 8K Flash
(Erase/Write on
four-word blocks)
RAM 192, 368 bytes 192, 368 bytes 192, 368 bytes
EEPROM Data None 128, 256 bytes 128, 256 bytes
Code Protection On/Off Segmented, starting at end
of program memory
On/Off
Program Memory
Write Protection
— On/Off Segmented, starting at
beginning of
program memory
Other In-Circuit Debugger,
Low-Voltage Programming
In-Circuit Debugger,
Low-Voltage Programming
 2003 Microchip Technology Inc. DS39582B-page 221
PIC16F87XA
INDEX
A
A/D ................................................................................... 127
Acquisition Requirements ........................................ 130
ADCON0 Register .................................................... 127
ADCON1 Register .................................................... 127
ADIF Bit .................................................................... 129
ADRESH Register .................................................... 127
ADRESL Register .................................................... 127
Analog Port Pins .................................................. 49, 51
Associated Registers and Bits ................................. 133
Calculating Acquisition Time .................................... 130
Configuring Analog Port Pins ................................... 131
Configuring the Interrupt .......................................... 129
Configuring the Module ............................................ 129
Conversion Clock ..................................................... 131
Conversions ............................................................. 132
Converter Characteristics ........................................ 194
Effects of a Reset ..................................................... 133
GO/DONE Bit ........................................................... 129
Internal Sampling Switch (Rss) Impedance ............. 130
Operation During Sleep ........................................... 133
Result Registers ....................................................... 132
Source Impedance ................................................... 130
A/D Conversion Requirements ......................................... 195
Absolute Maximum Ratings ............................................. 173
ACKSTAT ......................................................................... 101
ADCON0 Register .............................................................. 19
ADCON1 Register .............................................................. 20
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See USART.
ADRESH Register .............................................................. 19
ADRESL Register .............................................................. 20
Analog-to-Digital Converter. See A/D.
Application Notes
AN552 (Implementing Wake-up
on Key Stroke) ................................................... 44
AN556 (Implementing a Table Read) ........................ 30
Assembler
MPASM Assembler .................................................. 167
Asynchronous Reception
Associated Registers ....................................... 118, 120
Asynchronous Transmission
Associated Registers ............................................... 116
B
Banking, Data Memory ................................................. 16, 22
Baud Rate Generator ......................................................... 97
Associated Registers ............................................... 113
BCLIF ................................................................................. 28
BF ..................................................................................... 101
Block Diagrams
A/D ........................................................................... 129
Analog Input Model .......................................... 130, 139
Baud Rate Generator ................................................. 97
Capture Mode Operation ........................................... 65
Comparator I/O Operating Modes ............................ 136
Comparator Output .................................................. 138
Comparator Voltage Reference ............................... 142
Compare Mode Operation ......................................... 66
Crystal/Ceramic Resonator Operation
(HS, XT or LP Osc Configuration) .................... 145
External Clock Input Operation
(HS, XT or LP Osc Configuration) .................... 145
Interrupt Logic .......................................................... 153
MSSP (I
2
C Mode) ...................................................... 80
MSSP (SPI Mode) ..................................................... 71
On-Chip Reset Circuit .............................................. 147
PIC16F873A/PIC16F876A Architecture ...................... 6
PIC16F874A/PIC16F877A Architecture ...................... 7
PORTC
Peripheral Output Override
(RC2:0, RC7:5) Pins .................................. 46
Peripheral Output Override (RC4:3) Pins .......... 46
PORTD (in I/O Port Mode) ......................................... 48
PORTD and PORTE (Parallel Slave Port) ................. 51
PORTE (In I/O Port Mode) ......................................... 49
RA3:RA0 Pins ............................................................ 41
RA4/T0CKI Pin .......................................................... 42
RA5 Pin ..................................................................... 42
RB3:RB0 Pins ............................................................ 44
RB7:RB4 Pins ............................................................ 44
RC Oscillator Mode .................................................. 146
Recommended MCLR Circuit .................................. 148
Simplified PWM Mode ............................................... 67
Timer0/WDT Prescaler .............................................. 53
Timer1 ....................................................................... 58
Timer2 ....................................................................... 61
USART Receive ................................................117, 119
USART Transmit ...................................................... 115
Watchdog Timer ...................................................... 155
BOR. See Brown-out Reset.
BRG. See Baud Rate Generator.
BRGH Bit ......................................................................... 113
Brown-out Reset (BOR) .................... 143, 147, 148, 149, 150
BOR Status (BOR Bit) ............................................... 29
Bus Collision During a Repeated Start Condition ............ 108
Bus Collision During a Start Condition ............................. 106
Bus Collision During a Stop Condition ............................. 109
Bus Collision Interrupt Flag bit, BCLIF ............................... 28
C
C Compilers
MPLAB C17 ............................................................. 168
MPLAB C18 ............................................................. 168
MPLAB C30 ............................................................. 168
Capture/Compare/PWM (CCP) ......................................... 63
Associated Registers
Capture, Compare and Timer1 .......................... 68
PWM and Timer2 ............................................... 69
Capture Mode ............................................................ 65
CCP1IF .............................................................. 65
Prescaler ........................................................... 65
CCP Timer Resources ............................................... 63
Compare
Special Event Trigger Output of CCP1 .............. 66
Special Event Trigger Output of CCP2 .............. 66
Compare Mode .......................................................... 66
Software Interrupt Mode .................................... 66
Special Event Trigger ........................................ 66
Interaction of Two CCP Modules (table) .................... 63
PWM Mode ................................................................ 67
Duty Cycle ......................................................... 67
Example Frequencies/Resolutions (table) ......... 68
PWM Period ...................................................... 67
Special Event Trigger and A/D Conversions ............. 66
PIC16F87XA
DS39582B-page 222  2003 Microchip Technology Inc.
Capture/Compare/PWM Requirements
(CCP1 and CCP2) .................................................... 186
CCP. See Capture/Compare/PWM.
CCP1CON Register ........................................................... 19
CCP2CON Register ........................................................... 19
CCPR1H Register ........................................................ 19, 63
CCPR1L Register ......................................................... 19, 63
CCPR2H Register ........................................................ 19, 63
CCPR2L Register ......................................................... 19, 63
CCPxM0 Bit ........................................................................ 64
CCPxM1 Bit ........................................................................ 64
CCPxM2 Bit ........................................................................ 64
CCPxM3 Bit ........................................................................ 64
CCPxX Bit .......................................................................... 64
CCPxY Bit .......................................................................... 64
CLKO and I/O Timing Requirements ............................... 183
CMCON Register ............................................................... 20
Code Examples
Call of a Subroutine in Page 1 from Page 0 ............... 30
Indirect Addressing .................................................... 31
Initializing PORTA ...................................................... 41
Loading the SSPBUF (SSPSR) Register ................... 74
Reading Data EEPROM ............................................. 35
Reading Flash Program Memory ............................... 36
Saving Status, W and PCLATH Registers
in RAM ............................................................ 154
Writing to Data EEPROM ........................................... 35
Writing to Flash Program Memory ............................. 38
Code Protection ....................................................... 143, 157
Comparator Module ......................................................... 135
Analog Input Connection
Considerations ................................................. 139
Associated Registers ............................................... 140
Configuration ............................................................ 136
Effects of a Reset ..................................................... 139
Interrupts .................................................................. 138
Operation ................................................................. 137
Operation During Sleep ............................................ 139
Outputs ..................................................................... 137
Reference ................................................................. 137
Response Time ........................................................ 137
Comparator Specifications ............................................... 180
Comparator Voltage Reference ....................................... 141
Associated Registers ............................................... 142
Computed GOTO ............................................................... 30
Configuration Bits ............................................................. 143
Configuration Word .......................................................... 144
Conversion Considerations .............................................. 220
CVRCON Register ............................................................. 20
D
Data EEPROM and Flash Program Memory
EEADR Register ........................................................ 33
EEADRH Register ...................................................... 33
EECON1 Register ...................................................... 33
EECON2 Register ...................................................... 33
EEDATA Register ...................................................... 33
EEDATH Register ...................................................... 33
Data EEPROM Memory
Associated Registers ................................................. 39
EEADR Register ........................................................ 33
EEADRH Register ..................................................... 33
EECON1 Register ...................................................... 33
EECON2 Register ...................................................... 33
Operation During Code-Protect ................................. 39
Protection Against Spurious Writes ........................... 39
Reading ..................................................................... 35
Write Complete Flag Bit (EEIF) ................................. 33
Writing ........................................................................ 35
Data Memory ..................................................................... 16
Bank Select (RP1:RP0 Bits) .................................16, 22
General Purpose Registers ....................................... 16
Register File Map ..................................................17, 18
Special Function Registers ........................................ 19
DC and AC Characteristics Graphs and Tables .............. 197
DC Characteristics ....................................................175–179
Demonstration Boards
PICDEM 1 ................................................................ 170
PICDEM 17 .............................................................. 170
PICDEM 18R PIC18C601/801 ................................. 171
PICDEM 2 Plus ........................................................ 170
PICDEM 3 PIC16C92X ............................................ 170
PICDEM 4 ................................................................ 170
PICDEM LIN PIC16C43X ........................................ 171
PICDEM USB PIC16C7X5 ...................................... 171
PICDEM.net Internet/Ethernet ................................. 170
Development Support ...................................................... 167
Device Differences ........................................................... 219
Device Overview .................................................................. 5
Direct Addressing ............................................................... 31
E
EEADR Register ...........................................................21, 33
EEADRH Register .........................................................21, 33
EECON1 Register .........................................................21, 33
EECON2 Register .........................................................21, 33
EEDATA Register .............................................................. 21
EEDATH Register .............................................................. 21
Electrical Characteristics .................................................. 173
Errata ................................................................................... 4
Evaluation and Programming Tools ................................. 171
External Clock Timing Requirements ............................... 182
External Interrupt Input (RB0/INT). See Interrupt Sources.
External Reference Signal ............................................... 137
F
Firmware Instructions ....................................................... 159
Flash Program Memory
Associated Registers ................................................. 39
EECON1 Register ...................................................... 33
EECON2 Register ...................................................... 33
Reading ..................................................................... 36
Writing ........................................................................ 37
FSR Register .......................................................... 19, 20, 31
G
General Call Address Support ........................................... 94
 2003 Microchip Technology Inc. DS39582B-page 223
PIC16F87XA
I
I/O Ports ............................................................................. 41
I2C Bus Data Requirements ............................................ 192
I
2
C Bus Start/Stop Bits Requirements ............................. 191
I
2
C Mode
Registers .................................................................... 80
I
2
C Mode ............................................................................ 80
ACK Pulse ............................................................ 84, 85
Acknowledge Sequence Timing ............................... 104
Baud Rate Generator ................................................. 97
Bus Collision
Repeated Start Condition ................................. 108
Start Condition ................................................. 106
Stop Condition ................................................. 109
Clock Arbitration ......................................................... 98
Effect of a Reset ...................................................... 105
General Call Address Support ................................... 94
Master Mode .............................................................. 95
Operation ........................................................... 96
Repeated Start Timing ..................................... 100
Master Mode Reception ........................................... 101
Master Mode Start Condition ..................................... 99
Master Mode Transmission ...................................... 101
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 105
Multi-Master Mode ................................................... 105
Read/Write Bit Information (R/W Bit) ................... 84, 85
Serial Clock (RC3/SCK/SCL) ..................................... 85
Slave Mode ................................................................ 84
Addressing ......................................................... 84
Reception ........................................................... 85
Transmission ...................................................... 85
Sleep Operation ....................................................... 105
Stop Condition Timing .............................................. 104
ID Locations ............................................................. 143, 157
In-Circuit Debugger .................................................. 143, 157
Resources ................................................................ 157
In-Circuit Serial Programming (ICSP) ...................... 143, 158
INDF Register .........................................................19, 20, 31
Indirect Addressing ............................................................ 31
FSR Register ............................................................. 16
Instruction Format ............................................................ 159
Instruction Set .................................................................. 159
ADDLW .................................................................... 161
ADDWF .................................................................... 161
ANDLW .................................................................... 161
ANDWF .................................................................... 161
BCF .......................................................................... 161
BSF .......................................................................... 161
BTFSC ..................................................................... 161
BTFSS ..................................................................... 161
CALL ........................................................................ 162
CLRF ........................................................................ 162
CLRW ...................................................................... 162
CLRWDT .................................................................. 162
COMF ...................................................................... 162
DECF ....................................................................... 162
DECFSZ ................................................................... 163
GOTO ...................................................................... 163
INCF ......................................................................... 163
INCFSZ .................................................................... 163
IORLW ..................................................................... 163
IORWF ..................................................................... 163
RETURN .................................................................. 164
RLF .......................................................................... 164
RRF ......................................................................... 164
SLEEP ..................................................................... 164
SUBLW .................................................................... 164
SUBWF .................................................................... 164
SWAPF .................................................................... 165
XORLW ................................................................... 165
XORWF ................................................................... 165
Summary Table ....................................................... 160
INT Interrupt (RB0/INT). See Interrupt Sources.
INTCON Register ............................................................... 24
GIE Bit ....................................................................... 24
INTE Bit ..................................................................... 24
INTF Bit ..................................................................... 24
PEIE Bit ..................................................................... 24
RBIE Bit ..................................................................... 24
RBIF Bit ................................................................24, 44
TMR0IE Bit ................................................................ 24
TMR0IF Bit ................................................................. 24
Inter-Integrated Circuit. See I
2
C.
Internal Reference Signal ................................................ 137
Internal Sampling Switch (Rss) Impedance ..................... 130
Interrupt Sources ......................................................143, 153
Interrupt-on-Change (RB7:RB4) ................................ 44
RB0/INT Pin, External ..................................... 9, 11, 154
TMR0 Overflow ........................................................ 154
USART Receive/Transmit Complete ....................... 111
Interrupts
Bus Collision Interrupt ................................................ 28
Synchronous Serial Port Interrupt .............................. 26
Interrupts, Context Saving During .................................... 154
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ........................24, 153
Interrupt-on-Change (RB7:RB4)
Enable (RBIE Bit) .......................................24, 154
Peripheral Interrupt Enable (PEIE Bit) ....................... 24
RB0/INT Enable (INTE Bit) ........................................ 24
TMR0 Overflow Enable (TMR0IE Bit) ........................ 24
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) .............................................. 24, 44, 154
RB0/INT Flag (INTF Bit) ............................................ 24
TMR0 Overflow Flag (TMR0IF Bit) .....................24, 154
L
Loading of PC .................................................................... 30
Low-Voltage ICSP Programming ..................................... 158
Low-Voltage In-Circuit Serial Programming ..................... 143
M
Master Clear (MCLR) ........................................................... 8
MCLR Reset, Normal Operation ............... 147, 149, 150
MCLR Reset, Sleep .................................. 147, 149, 150
Master Synchronous Serial Port (MSSP). See MSSP.
MCLR ............................................................................... 148
MCLR/VPP ......................................................................... 10
Memory Organization ........................................................ 15
Data EEPROM Memory ............................................. 33
Data Memory ............................................................. 16
Flash Program Memory ............................................. 33
Program Memory ....................................................... 15
MPLAB ASM30 Assembler, Linker, Librarian .................. 168
MPLAB ICD 2 In-Circuit Debugger .................................. 169
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator ................................................... 169
PIC16F87XA
DS39582B-page 224  2003 Microchip Technology Inc.
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator ................................................... 169
MPLAB Integrated Development
Environment Software .............................................. 167
MPLINK Object Linker/MPLIB Object Librarian ............... 168
MSSP ................................................................................. 71
I
2
C Mode. See I
2
C.
SPI Mode ................................................................... 71
SPI Mode. See SPI.
MSSP Module
Clock Stretching ......................................................... 90
Clock Synchronization and the CKP Bit ..................... 91
Control Registers (General) ....................................... 71
Operation ................................................................... 84
Overview .................................................................... 71
SPI Master Mode ....................................................... 76
SPI Slave Mode ......................................................... 77
SSPBUF ..................................................................... 76
SSPSR ....................................................................... 76
Multi-Master Mode ........................................................... 105
O
Opcode Field Descriptions ............................................... 159
OPTION_REG Register ..................................................... 23
INTEDG Bit ................................................................ 23
PS2:PS0 Bits .............................................................. 23
PSA Bit ....................................................................... 23
RBPU Bit .................................................................... 23
T0CS Bit ..................................................................... 23
T0SE Bit ..................................................................... 23
OSC1/CLKI Pin .............................................................. 8, 10
OSC2/CLKO Pin ............................................................ 8, 10
Oscillator Configuration
HS .................................................................... 145, 149
LP ..................................................................... 145, 149
RC ............................................................ 145, 146, 149
XT ..................................................................... 145, 149
Oscillator Selection .......................................................... 143
Oscillator Start-up Timer (OST) ............................... 143, 148
Oscillator, WDT ................................................................ 155
Oscillators
Capacitor Selection .................................................. 146
Ceramic Resonator Selection .................................. 145
Crystal and Ceramic Resonators ............................. 145
RC ............................................................................ 146
P
Package Information
Marking .................................................................... 209
Packaging Information ..................................................... 209
Paging, Program Memory .................................................. 30
Parallel Slave Port (PSP) ....................................... 13, 48, 51
Associated Registers ................................................. 52
RE0/RD/AN5 Pin .................................................. 49, 51
RE1/WR/AN6 Pin ................................................. 49, 51
RE2/CS/AN7 Pin .................................................. 49, 51
Select (PSPMODE Bit) ..............................48, 49, 50, 51
Parallel Slave Port Requirements
(PIC16F874A/ 877A Only) ....................................... 187
PCL Register .......................................................... 19, 20, 30
PCLATH Register ................................................... 19, 20, 30
PCON Register .................................................... 20, 29, 149
BOR Bit ...................................................................... 29
POR Bit ...................................................................... 29
PIC16F87XA Product Identification System ..................... 231
PICkit 1 Flash Starter Kit .................................................. 171
PICSTART Plus Development Programmer .................... 169
PIE1 Register ................................................................20, 25
PIE2 Register ................................................................20, 27
Pinout Descriptions
PIC16F873A/PIC16F876A ........................................... 8
PIR1 Register ...............................................................19, 26
PIR2 Register ...............................................................19, 28
POP ................................................................................... 30
POR. See Power-on Reset.
PORTA ...........................................................................8, 10
Associated Registers ................................................. 43
Functions ................................................................... 43
PORTA Register ...................................................19, 41
TRISA Register .......................................................... 41
PORTB ...........................................................................9, 11
Associated Registers ................................................. 45
Functions ................................................................... 45
PORTB Register ...................................................19, 44
Pull-up Enable (RBPU Bit) ......................................... 23
RB0/INT Edge Select (INTEDG Bit) .......................... 23
RB0/INT Pin, External ..................................... 9, 11, 154
RB7:RB4 Interrupt-on-Change ................................ 154
RB7:RB4 Interrupt-on-Change Enable
(RBIE Bit) ....................................................24, 154
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ..............................................24, 44, 154
TRISB Register .....................................................21, 44
PORTB Register ................................................................ 21
PORTC ...........................................................................9, 12
Associated Registers ................................................. 47
Functions ................................................................... 47
PORTC Register ...................................................19, 46
RC3/SCK/SCL Pin ..................................................... 85
RC6/TX/CK Pin ........................................................ 112
RC7/RX/DT Pin .................................................112, 113
TRISC Register ...................................................46, 111
PORTD .........................................................................13, 51
Associated Registers ................................................. 48
Functions ................................................................... 48
Parallel Slave Port (PSP) Function ............................ 48
PORTD Register ...................................................19, 48
TRISD Register .......................................................... 48
PORTE .............................................................................. 13
Analog Port Pins ...................................................49, 51
Associated Registers ................................................. 50
Functions ................................................................... 49
Input Buffer Full Status (IBF Bit) ................................ 50
Input Buffer Overflow (IBOV Bit) ................................ 50
Output Buffer Full Status (OBF Bit) ........................... 50
PORTE Register ...................................................19, 49
PSP Mode Select (PSPMODE Bit) ........... 48, 49, 50, 51
RE0/RD/AN5 Pin ..................................................49, 51
RE1/WR/AN6 Pin ..................................................49, 51
RE2/CS/AN7 Pin ...................................................49, 51
TRISE Register .......................................................... 49
Postscaler, WDT
Assignment (PSA Bit) ................................................ 23
Rate Select (PS2:PS0 Bits) ....................................... 23
Power-down Mode. See Sleep.
Power-on Reset (POR) ..................... 143, 147, 148, 149, 150
POR Status (POR Bit) ............................................... 29
Power Control (PCON) Register .............................. 149
Power-down (PD Bit) ..........................................22, 147
Power-up Timer (PWRT) ......................................... 143
Time-out (TO Bit) ................................................22, 147
 2003 Microchip Technology Inc. DS39582B-page 225
PIC16F87XA
Power-up Timer (PWRT) .................................................. 148
PR2 Register ................................................................ 20, 61
Prescaler, Timer0
Assignment (PSA Bit) ................................................ 23
Rate Select (PS2:PS0 Bits) ....................................... 23
PRO MATE II Universal Device Programmer .................. 169
Program Counter
Reset Conditions ...................................................... 149
Program Memory ............................................................... 15
Interrupt Vector .......................................................... 15
Paging ........................................................................ 30
Program Memory Map and Stack
(PIC16F873A/874A) ........................................... 15
Program Memory Map and Stack
(PIC16F876A/877A) ........................................... 15
Reset Vector .............................................................. 15
Program Verification ......................................................... 157
Programming Pin (VPP) ........................................................ 8
Programming, Device Instructions ................................... 159
PSP. See Parallel Slave Port.
Pulse Width Modulation. See Capture/Compare/PWM,
PWM Mode.
PUSH ................................................................................. 30
R
RA0/AN0 Pin .................................................................. 8, 10
RA1/AN1 Pin .................................................................. 8, 10
RA2/AN2/VREF-/CVREF Pin ............................................ 8, 10
RA3/AN3/VREF+ Pin ....................................................... 8, 10
RA4/T0CKI/C1OUT Pin .................................................. 8, 10
RA5/AN4/SS/C2OUT Pin ............................................... 8, 10
RAM. See Data Memory.
RB0/INT Pin ................................................................... 9, 11
RB1 Pin .......................................................................... 9, 11
RB2 Pin .......................................................................... 9, 11
RB3/PGM Pin ................................................................. 9, 11
RB4 Pin .......................................................................... 9, 11
RB5 Pin .......................................................................... 9, 11
RB6/PGC Pin ................................................................. 9, 11
RB7/PGD Pin ................................................................. 9, 11
RC0/T1OSO/T1CKI Pin ................................................. 9, 12
RC1/T1OSI/CCP2 Pin .................................................... 9, 12
RC2/CCP1 Pin ............................................................... 9, 12
RC3/SCK/SCL Pin ......................................................... 9, 12
RC4/SDI/SDA Pin .......................................................... 9, 12
RC5/SDO Pin ................................................................. 9, 12
RC6/TX/CK Pin .............................................................. 9, 12
RC7/RX/DT Pin .............................................................. 9, 12
RCREG Register ................................................................ 19
RCSTA Register ................................................................. 19
ADDEN Bit ............................................................... 112
CREN Bit .................................................................. 112
FERR Bit .................................................................. 112
OERR Bit ................................................................. 112
RX9 Bit ..................................................................... 112
RX9D Bit .................................................................. 112
SPEN Bit .......................................................... 111, 112
SREN Bit .................................................................. 112
RD0/PSP0 Pin .................................................................... 13
RD1/PSP1 Pin .................................................................... 13
RD2/PSP2 Pin .................................................................... 13
RD3/PSP3 Pin .................................................................... 13
RD4/PSP4 Pin .................................................................... 13
RD5/PSP5 Pin .................................................................... 13
RD6/PSP6 Pin .................................................................... 13
RD7/PSP7 Pin .................................................................... 13
RE0/RD/AN5 Pin ............................................................... 13
RE1/WR/AN6 Pin ............................................................... 13
RE2/CS/AN7 Pin ................................................................ 13
Read-Modify-Write Operations ........................................ 159
Register File ....................................................................... 16
Register File Map (PIC16F873A/874A) ............................. 18
Register File Map (PIC16F876A/877A) ............................. 17
Registers
ADCON0 (A/D Control 0) ......................................... 127
ADCON1 (A/D Control 1) ......................................... 128
CCP1CON/CCP2CON (CCP Control 1
and CCP Control 2) ........................................... 64
CMCON (Comparator Control) ................................ 135
CVRCON (Comparator Voltage
Reference Control) .......................................... 141
EECON1 (EEPROM Control 1) ................................. 34
FSR ........................................................................... 31
INTCON ..................................................................... 24
OPTION_REG ......................................................23, 54
PCON (Power Control) .............................................. 29
PIE1 (Peripheral Interrupt Enable 1) .......................... 25
PIE2 (Peripheral Interrupt Enable 2) .......................... 27
PIR1 (Peripheral Interrupt Request 1) ....................... 26
PIR2 (Peripheral Interrupt Request 2) ....................... 28
RCSTA (Receive Status and Control) ..................... 112
Special Function, Summary ....................................... 19
SSPCON (MSSP Control 1, I
2
C Mode) ..................... 82
SSPCON (MSSP Control 1, SPI Mode) ..................... 73
SSPCON2 (MSSP Control 2, I
2
C Mode) ................... 83
SSPSTAT (MSSP Status, I
2
C Mode) ........................ 81
SSPSTAT (MSSP Status, SPI Mode) ........................ 72
Status ........................................................................ 22
T1CON (Timer1 Control) ........................................... 57
T2CON (Timer2 Control) ........................................... 61
TRISE Register .......................................................... 50
TXSTA (Transmit Status and Control) ..................... 111
Reset ........................................................................143, 147
Brown-out Reset (BOR). See Brown-out Reset (BOR).
MCLR Reset. See MCLR.
Power-on Reset (POR). See Power-on Reset (POR).
Reset Conditions for PCON Register ...................... 149
Reset Conditions for Program Counter .................... 149
Reset Conditions for Status Register ....................... 149
WDT Reset. See Watchdog Timer (WDT).
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements .......................................................... 184
Revision History ............................................................... 219
S
SCI. See USART.
SCK ................................................................................... 71
SDI ..................................................................................... 71
SDO ................................................................................... 71
Serial Clock, SCK .............................................................. 71
Serial Communication Interface. See USART.
Serial Data In, SDI ............................................................. 71
Serial Data Out, SDO ........................................................ 71
Serial Peripheral Interface. See SPI.
Slave Select Synchronization ............................................ 77
Slave Select, SS ................................................................ 71
Sleep ................................................................. 143, 147, 156
Software Simulator (MPLAB SIM) ................................... 168
Software Simulator (MPLAB SIM30) ............................... 168
SPBRG Register ................................................................ 20
Special Features of the CPU ........................................... 143
PIC16F87XA
DS39582B-page 226  2003 Microchip Technology Inc.
Special Function Registers ................................................ 19
Special Function Registers (SFRs) .................................... 19
Speed, Operating ................................................................. 1
SPI Mode ..................................................................... 71, 77
Associated Registers ................................................. 79
Bus Mode Compatibility ............................................. 79
Effects of a Reset ....................................................... 79
Enabling SPI I/O ......................................................... 75
Master Mode .............................................................. 76
Master/Slave Connection ........................................... 75
Serial Clock ................................................................ 71
Serial Data In ............................................................. 71
Serial Data Out ........................................................... 71
Slave Select ............................................................... 71
Slave Select Synchronization ..................................... 77
Sleep Operation ......................................................... 79
SPI Clock ................................................................... 76
Typical Connection ..................................................... 75
SPI Mode Requirements .................................................. 190
SS ...................................................................................... 71
SSP
SPI Master/Slave Connection .................................... 75
SSPADD Register .............................................................. 20
SSPBUF Register .............................................................. 19
SSPCON Register .............................................................. 19
SSPCON2 Register ............................................................ 20
SSPIF ................................................................................. 26
SSPOV ............................................................................. 101
SSPSTAT Register ............................................................ 20
R/W Bit ................................................................. 84, 85
Stack .................................................................................. 30
Overflows ................................................................... 30
Underflow ................................................................... 30
Status Register
C Bit ........................................................................... 22
DC Bit ......................................................................... 22
IRP Bit ........................................................................ 22
PD Bit ................................................................. 22, 147
RP1:RP0 Bits ............................................................. 22
TO Bit ................................................................. 22, 147
Z Bit ............................................................................ 22
Synchronous Master Reception
Associated Registers ............................................... 123
Synchronous Master Transmission
Associated Registers ............................................... 122
Synchronous Serial Port Interrupt ...................................... 26
Synchronous Slave Reception
Associated Registers ............................................... 125
Synchronous Slave Transmission
Associated Registers ............................................... 125
T
T1CKPS0 Bit ...................................................................... 57
T1CKPS1 Bit ...................................................................... 57
T1CON Register ................................................................. 19
T1OSCEN Bit ..................................................................... 57
T1SYNC Bit ........................................................................ 57
T2CKPS0 Bit ...................................................................... 61
T2CKPS1 Bit ...................................................................... 61
T2CON Register ................................................................. 19
TAD ................................................................................... 131
Time-out Sequence .......................................................... 148
Timer0 ................................................................................ 53
Associated Registers ................................................. 55
Clock Source Edge Select (T0SE Bit) ....................... 23
Clock Source Select (T0CS Bit) ................................. 23
External Clock ............................................................ 54
Interrupt ..................................................................... 53
Overflow Enable (TMR0IE Bit) ................................... 24
Overflow Flag (TMR0IF Bit) ................................24, 154
Overflow Interrupt .................................................... 154
Prescaler .................................................................... 54
T0CKI ......................................................................... 54
Timer0 and Timer1 External Clock Requirements ........... 185
Timer1 ................................................................................ 57
Associated Registers ................................................. 60
Asynchronous Counter Mode .................................... 59
Reading and Writing to ...................................... 59
Counter Operation ..................................................... 58
Operation in Timer Mode ........................................... 58
Oscillator .................................................................... 59
Capacitor Selection ............................................ 59
Prescaler .................................................................... 60
Resetting of Timer1 Registers ................................... 60
Resetting Timer1 Using a CCP Trigger Output ......... 59
Synchronized Counter Mode ..................................... 58
TMR1H ...................................................................... 59
TMR1L ....................................................................... 59
Timer2 ................................................................................ 61
Associated Registers ................................................. 62
Output ........................................................................ 62
Postscaler .................................................................. 61
Prescaler .................................................................... 61
Prescaler and Postscaler ........................................... 62
Timing Diagrams
A/D Conversion ........................................................ 195
Acknowledge Sequence .......................................... 104
Asynchronous Master Transmission ........................ 116
Asynchronous Master Transmission
(Back to Back) ................................................. 116
Asynchronous Reception ......................................... 118
Asynchronous Reception with
Address Byte First ........................................... 120
Asynchronous Reception with
Address Detect ................................................ 120
Baud Rate Generator with Clock Arbitration .............. 98
BRG Reset Due to SDA Arbitration During
Start Condition ................................................. 107
Brown-out Reset ...................................................... 184
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 108
Bus Collision During Repeated
Start Condition (Case 2) .................................. 108
Bus Collision During Start Condition
(SCL = 0) ......................................................... 107
Bus Collision During Start Condition
(SDA Only) ....................................................... 106
Bus Collision During Stop Condition
(Case 1) ........................................................... 109
Bus Collision During Stop Condition
(Case 2) ........................................................... 109
Bus Collision for Transmit and Acknowledge .......... 105
Capture/Compare/PWM (CCP1 and CCP2) ............ 186
CLKO and I/O .......................................................... 183
Clock Synchronization ............................................... 91
External Clock .......................................................... 182
First Start Bit .............................................................. 99
 2003 Microchip Technology Inc. DS39582B-page 227
PIC16F87XA
I
2
C Bus Data ............................................................ 191
I
2
C Bus Start/Stop Bits ............................................. 190
I
2
C Master Mode (Reception, 7-bit Address) ........... 103
I
2
C Master Mode (Transmission,
7 or 10-bit Address) ......................................... 102
I
2
C Slave Mode (Transmission, 10-bit Address) ........ 89
I
2
C Slave Mode (Transmission, 7-bit Address) .......... 87
I
2
C Slave Mode with SEN = 1 (Reception,
10-bit Address) ................................................... 93
I
2
C Slave Mode with SEN = 0 (Reception,
10-bit Address) ................................................... 88
I
2
C Slave Mode with SEN = 0 (Reception,
7-bit Address) ..................................................... 86
I
2
C Slave Mode with SEN = 1 (Reception,
7-bit Address) ..................................................... 92
Parallel Slave Port (PIC16F874A/877A Only) .......... 187
Parallel Slave Port (PSP) Read ................................. 52
Parallel Slave Port (PSP) Write ................................. 52
Repeat Start Condition ............................................. 100
Reset, Watchdog Timer, Start-up Timer
and Power-up Timer ........................................ 184
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) ................................ 94
Slave Synchronization ............................................... 77
Slow Rise Time (MCLR Tied to VDD via
RC Network) .................................................... 152
SPI Master Mode (CKE = 0, SMP = 0) .................... 188
SPI Master Mode (CKE = 1, SMP = 1) .................... 188
SPI Mode (Master Mode) ........................................... 76
SPI Mode (Slave Mode with CKE = 0) ....................... 78
SPI Mode (Slave Mode with CKE = 1) ....................... 78
SPI Slave Mode (CKE = 0) ...................................... 189
SPI Slave Mode (CKE = 1) ...................................... 189
Stop Condition Receive or Transmit Mode .............. 104
Synchronous Reception
(Master Mode, SREN) ...................................... 124
Synchronous Transmission ...................................... 122
Synchronous Transmission (Through TXEN) .......... 122
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Case 1 .............................................................. 152
Case 2 .............................................................. 152
Time-out Sequence on Power-up (MCLR Tied
to VDD via RC Network) ................................... 151
Timer0 and Timer1 External Clock .......................... 185
USART Synchronous Receive
(Master/Slave) .................................................. 193
USART Synchronous Transmission
(Master/Slave) .................................................. 193
Wake-up from Sleep via Interrupt ............................ 157
Timing Parameter Symbology .......................................... 181
TMR0 Register ................................................................... 19
TMR1CS Bit ....................................................................... 57
TMR1H Register ................................................................ 19
TMR1L Register ................................................................. 19
TMR1ON Bit ....................................................................... 57
TMR2 Register ................................................................... 19
TMR2ON Bit ....................................................................... 61
TMRO Register .................................................................. 21
TOUTPS0 Bit ..................................................................... 61
TOUTPS1 Bit ..................................................................... 61
TOUTPS2 Bit ..................................................................... 61
TOUTPS3 Bit ..................................................................... 61
TRISA Register .................................................................. 20
TRISB Register .................................................................. 20
TRISC Register .................................................................. 20
TRISD Register .................................................................. 20
TRISE Register .................................................................. 20
IBF Bit ........................................................................ 50
IBOV Bit ..................................................................... 50
OBF Bit ...................................................................... 50
PSPMODE Bit ........................................... 48, 49, 50, 51
TXREG Register ................................................................ 19
TXSTA Register ................................................................. 20
BRGH Bit ................................................................. 111
CSRC Bit ................................................................. 111
SYNC Bit ................................................................. 111
TRMT Bit .................................................................. 111
TX9 Bit ..................................................................... 111
TX9D Bit .................................................................. 111
TXEN Bit .................................................................. 111
U
USART ............................................................................. 111
Address Detect Enable (ADDEN Bit) ....................... 112
Asynchronous Mode ................................................ 115
Asynchronous Receive (9-bit Mode) ........................ 119
Asynchronous Receive with Address Detect.
See Asynchronous Receive (9-bit Mode).
Asynchronous Receiver ........................................... 117
Asynchronous Reception ......................................... 118
Asynchronous Transmitter ....................................... 115
Baud Rate Generator (BRG) ................................... 113
Baud Rate Formula ......................................... 113
Baud Rates, Asynchronous Mode
(BRGH = 0) .............................................. 114
Baud Rates, Asynchronous Mode
(BRGH = 1) .............................................. 114
High Baud Rate Select (BRGH Bit) ................. 111
Sampling .......................................................... 113
Clock Source Select (CSRC Bit) .............................. 111
Continuous Receive Enable (CREN Bit) .................. 112
Framing Error (FERR Bit) ........................................ 112
Mode Select (SYNC Bit) .......................................... 111
Overrun Error (OERR Bit) ........................................ 112
Receive Data, 9th Bit (RX9D Bit) ............................. 112
Receive Enable, 9-bit (RX9 Bit) ............................... 112
Serial Port Enable (SPEN Bit) ..........................111, 112
Single Receive Enable (SREN Bit) .......................... 112
Synchronous Master Mode ...................................... 121
Synchronous Master Reception ............................... 123
Synchronous Master Transmission ......................... 121
Synchronous Slave Mode ........................................ 124
Synchronous Slave Reception ................................. 125
Synchronous Slave Transmit ................................... 124
Transmit Data, 9th Bit (TX9D) ................................. 111
Transmit Enable (TXEN Bit) .................................... 111
Transmit Enable, 9-bit (TX9 Bit) .............................. 111
Transmit Shift Register Status (TRMT Bit) .............. 111
USART Synchronous Receive Requirements ................. 193
V
VDD Pin ...........................................................................9, 13
Voltage Reference Specifications .................................... 180
VSS Pin ...........................................................................9, 13
PIC16F87XA
DS39582B-page 228  2003 Microchip Technology Inc.
W
Wake-up from Sleep ................................................ 143, 156
Interrupts .......................................................... 149, 150
MCLR Reset ............................................................. 150
WDT Reset ............................................................... 150
Wake-up Using Interrupts ................................................ 156
Watchdog Timer
Register Summary ................................................... 155
Watchdog Timer (WDT) ........................................... 143, 155
Enable (WDTE Bit) ................................................... 155
Postscaler. See Postscaler, WDT.
Programming Considerations ................................... 155
RC Oscillator ............................................................ 155
Time-out Period ........................................................ 155
WDT Reset, Normal Operation ................ 147, 149, 150
WDT Reset, Sleep ................................... 147, 149, 150
WCOL ................................................................ 99, 101, 104
WCOL Status Flag ............................................................. 99
WWW, On-Line Support ....................................................... 4
 2003 Microchip Technology Inc. DS39582B-page 229
PIC16F87XA
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape
®
or Microsoft
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Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web Site
The Microchip web site is available at the following
URL:
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The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
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available, including listings of Microchip sales offices,
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042003
PIC16F87XA
DS39582B-page 230  2003 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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DS39582B PIC16F87XA
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
 2003 Microchip Technology Inc. DS39582B-page 231
PIC16F87XA
PIC16F87XA PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Pattern Package Temperature
Range
Device

Device PIC16F87XA
(1)
, PIC16F87XAT
(2)
; VDD range 4.0V to 5.5V
PIC16LF87XA
(1)
, PIC16LF87XAT
(2)
; VDD range 2.0V to 5.5V
Temperature Range I = -40 C to +85 C (Industrial)
Package ML = QFN (Metal Lead Frame)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny Plastic DIP
P = PDIP
L = PLCC
S = SSOP
Examples:
a) PIC16F873A-I/P 301 = Industrial temp., PDIP
package, normal VDD limits, QTP pattern #301.
b) PIC16LF876A-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
c) PIC16F877A-I/P = Industrial temp., PDIP package,
10 MHz, normal VDD limits.
Note 1: F = CMOS Flash
LF = Low-Power CMOS Flash
2: T = in tape and reel - SOIC, PLCC,
TQFP packages only
DS39582B-page 232  2003 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

• •

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

DS39582B-page ii

 2003 Microchip Technology Inc.

PIC16F87XA
28/40/44-Pin Enhanced Flash Microcontrollers
Devices Included in this Data Sheet:
• PIC16F873A • PIC16F874A • PIC16F876A • PIC16F877A

Analog Features:
• 10-bit, up to 8-channel Analog-to-Digital Converter (A/D) • Brown-out Reset (BOR) • Analog Comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs are externally accessible

High-Performance RISC CPU:
• Only 35 single-word instructions to learn • All single-cycle instructions except for program branches, which are two-cycle • Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle • Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory • Pinout compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX microcontrollers

Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced Flash program memory typical • 1,000,000 erase/write cycle Data EEPROM memory typical • Data EEPROM Retention > 40 years • Self-reprogrammable under software control • In-Circuit Serial Programming™ (ICSP™) via two pins • Single-supply 5V In-Circuit Serial Programming • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code protection • Power saving Sleep mode • Selectable oscillator options • In-Circuit Debug (ICD) via two pins

Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep via external crystal/clock • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit • Synchronous Serial Port (SSP) with SPI™ (Master mode) and I2C™ (Master/Slave) • Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection • Parallel Slave Port (PSP) – 8 bits wide with external RD, WR and CS controls (40/44-pin only) • Brown-out detection circuitry for Brown-out Reset (BOR)

CMOS Technology:
• Low-power, high-speed Flash/EEPROM technology • Fully static design • Wide operating voltage range (2.0V to 5.5V) • Commercial and Industrial temperature ranges • Low-power consumption

Device

MSSP Data EEPROM 10-bit CCP Timers SRAM I/O USART Comparators # Single Word (Bytes) A/D (ch) (PWM) SPI Master 8/16-bit Bytes (Bytes) Instructions I2C 7.2K 7.2K 4096 4096 8192 8192 192 192 368 368 128 128 256 256 22 33 22 33 5 8 5 8 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 2/1 2/1 2/1 2/1 2 2 2 2

Program Memory

PIC16F873A PIC16F874A

PIC16F876A 14.3K PIC16F877A 14.3K

2003 Microchip Technology Inc.

DS39582B-page 1

PIC16F87XA Pin Diagrams 28-Pin PDIP. SSOP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA PIC16F873A/876A 28-Pin QFN RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT VSS OSC1/CLKI OSC2/CLKO 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB4 PIC16F873A PIC16F876A 44-Pin QFN 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 RC0/T1OSO/T1CKI RB3/PGM NC RB4 RB5 RB6/PGC RB7/PGD MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ 12 13 14 15 16 17 18 19 20 21 22 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD VDD RB0/INT RB1 RB2 1 2 3 4 5 6 7 8 9 10 11 PIC16F874A PIC16F877A 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO OSC1/CLKI VSS VSS VDD VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT DS39582B-page 2 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK 8 9 10 11 12 13 14 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT  2003 Microchip Technology Inc. SOIC. .

NC NC RB4 RB5 RB6/PGC RB7/PGD MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ 12 13 14 15 16 17 18 19 20 21 22 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3/PGM 1 2 3 4 5 6 7 8 9 10 11 PIC16F874A PIC16F877A 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKO OSC1/CLKI VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC 18 19 20 21 22 23 24 25 26 27 282 RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 MCLR/VPP NC RB7/PGD RB6/PGC RB5 RB4 NC PIC16F874A PIC16F877A DS39582B-page 3 .PIC16F87XA Pin Diagrams (Continued) 40-Pin PDIP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 PIC16F874A/877A 44-Pin PLCC RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CK1 NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 9 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT 44-Pin TQFP 44 43 42 41 40 39 38 37 36 35 34  2003 Microchip Technology Inc.

.........com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.................................................................... Most Current Data Sheet To obtain the most up-to-date version of this data sheet............................................... 71 10................................... 229 Reader Response ............ 57 7........ may exist for current devices..... 221 On-Line Support............................................................................................... 220 Index ................................. The errata will specify the revision of silicon and revision of document to which it applies..............PIC16F87XA Table of Contents 1..................................................................................................................................................................0 DC and AC Characteristics Graphs and Tables ............. 15 3.........................................................0 Master Synchronous Serial Port (MSSP) Module......................................................... We welcome your feedback...........................S.... 135 13............ (e............. 41 5................................................ The last character of the literature number is the version number..............................................0 Packaging Information ................... 173 18......0 Device Overview .................................. 5 2.............com/cn to receive the most current information on all of our products................................ please check with one of the following: • Microchip’s Worldwide Web site...................................................................................................... 61 8............................ 141 14..................................................................................................................................................... 229 Systems Information and Upgrade Hot Line ...................................0 Analog-to-Digital Converter (A/D) Module ...................................................................................... 230 PIC16F87XA Product Identification System....... 197 19............................................................... U..................................................................................0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................... 209 Appendix A: Revision History ......................................................0 I/O Ports..........0 Instruction Set Summary...... To this end..........com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center........0 Timer0 Module ........................................................ As device/documentation issues become known to us...........................0 Development Support ....... 219 Appendix C: Conversion Considerations............ 167 17......................................................................................................... 111 11............................................................................................... 143 15. 63 9.....................................................0 Timer2 Module ................................................0 Comparator Voltage Reference Module ............................0 Timer1 Module ..................0 Special Features of the CPU ........................... If you have any questions or comments regarding this publication.................................. http://www..........................................microchip.......................... revision of silicon and data sheet (include literature number) you are using.................................................................................................................................................................................................................................................................................................................................... please contact the Marketing Communications Department via E-mail at docerrors@mail............g................................ 53 6.......................................................0 Memory Organization............................................... describing minor operational differences from the data sheet and recommended workarounds.......................... ............................................... 127 12..................................................................................................microchip........................................................................... DS39582B-page 4  2003 Microchip Technology Inc........................................... we will publish an errata sheet..... FAX: (480) 792-7277 When contacting a sales office or the literature center.................................................................................. we will continue to improve our publications to better suit your needs.................... Errata An errata sheet................0 Data EEPROM and Flash Program Memory ..microchip.................................................. 231 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products.0 Capture/Compare/PWM Modules ......................0 Electrical Characteristics.......................com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150................................................0 Comparator Module ................................................................................................................................... 33 4............................................................................................................................................. To determine if an errata sheet exists for a particular device.................... Our publications will be refined and enhanced as new volumes and updates are introduced................... please register at our Worldwide Web site at: http://www.......................................................................................................................................................................................................................................... DS30000A is version A of document DS30000).................................................. 219 Appendix B: Device Differences.............microchip........................................................................................................................................................... 159 16.................. please specify which device...................................... Customer Notification System Register on our Web site at www......................................................................

Block diagrams of the PIC16F873A/876A and PIC16F874A/877A devices are provided in Figure 1-1 and Figure 1-2.PIC16F87XA 1. OST) 4K 192 128 14 Ports A. BOR (PWRT. DS39582B-page 5 . OST) 4K 192 128 15 Ports A. All devices in the PIC16F87XA family share common architecture with the following differences: • The PIC16F873A and PIC16F874A have one-half of the total on-chip memory of the PIC16F876A and PIC16F877A • The 28-pin devices have three I/O ports. USART — 5 input channels 2 35 Instructions 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN PIC16F877A DC – 20 MHz POR. USART PSP 8 input channels 2 35 Instructions 40-pin PDIP 44-pin PLCC 44-pin TQFP 44-pin QFN PIC16F876A DC – 20 MHz POR. C 3 2 MSSP. OST) 8K 368 256 15 Ports A. while the 40/44-pin devices have fifteen • The 28-pin devices have five A/D input channels. E 3 2 MSSP. USART — 5 input channels 2 35 Instructions 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN PIC16F874A DC – 20 MHz POR. while the 40/44-pin devices have five • The 28-pin devices have fourteen interrupts. BOR (PWRT. B. B. D. respectively. B. while the 40/44-pin devices have eight • The Parallel Slave Port is implemented only on the 40/44-pin devices TABLE 1-1: PIC16F87XA DEVICE FEATURES PIC16F873A DC – 20 MHz POR. B. The Reference Manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. OST) 8K 368 256 14 Ports A. while PIC16F874A/877A devices are available in 40-pin and 44-pin packages. The pinouts for these device families are listed in Table 1-2 and Table 1-3. USART PSP 8 input channels 2 35 Instructions 40-pin PDIP 44-pin PLCC 44-pin TQFP 44-pin QFN Key Features Operating Frequency Resets (and Delays) Flash Program Memory (14-bit words) Data Memory (bytes) EEPROM Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Analog Comparators Instruction Set Packages  2003 Microchip Technology Inc. which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. BOR (PWRT. BOR (PWRT. Additional information may be found in the PICmicro® Mid-Range Reference Manual (DS33023). PIC16F873A/876A devices are available only in 28-pin packages. D. C 3 2 MSSP.0 DEVICE OVERVIEW This document contains device specific information about the following devices: • • • • PIC16F873A PIC16F874A PIC16F876A PIC16F877A The available features are summarized in Table 1-1. C. C. E 3 2 MSSP.

DS39582B-page 6  2003 Microchip Technology Inc.2 Synchronous Serial Port USART Comparator Voltage Reference Device PIC16F873A PIC16F876A Program Flash 4K words 8K words Data Memory 192 Bytes 368 Bytes Data EEPROM 128 Bytes 256 Bytes Note 1: Higher order bits are from the Status register. .PIC16F87XA FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM 13 Program Counter Flash Program Memory Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT 8 Level Stack (13-bit) RAM File Registers RAM Addr(1) 9 Program Bus 14 Instruction reg Direct Addr 7 Addr MUX 8 Indirect Addr PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD FSR reg Status reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8 MUX ALU PORTC W reg RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MCLR VDD. VSS Timer0 Timer1 Timer2 10-bit A/D Data EEPROM CCP1.

DS39582B-page 7 .PIC16F87XA FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM 13 Program Counter Flash Program Memory Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8 W reg PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE MCLR VDD. VSS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 3 MUX RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 Level Stack (13-bit) RAM File Registers RAM Addr(1) 9 Program Bus 14 Instruction reg Direct Addr 7 Addr MUX 8 Indirect Addr FSR reg Status reg 8 ALU Timer0 Timer1 Timer2 10-bit A/D Parallel Slave Port Data EEPROM CCP1.  2003 Microchip Technology Inc.2 Synchronous Serial Port USART Comparator Voltage Reference Device PIC16F874A PIC16F877A Program Flash 4K words 8K words Data Memory 192 Bytes 368 Bytes Data EEPROM 128 Bytes 256 Bytes Note 1: Higher order bits are from the Status register.

Comparator 2 output. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. Master Clear (Reset) input. Oscillator crystal output. DS39582B-page 8  2003 Microchip Technology Inc. SSOP Pin# 9 QFN Pin# 6 I I I/O/P Type Buffer Type Description ST/CMOS(3) Oscillator crystal or external clock input. This pin is an active low Reset to the device. Analog input 2. External clock source input. A/D reference voltage (High) input. Analog input 4. otherwise CMOS. I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. TTL Digital I/O. ST buffer when configured in RC mode. In RC mode. Analog input 0. Comparator 1 output. Programming voltage input. Comparator VREF output. TTL Digital I/O. Connects to crystal or resonator in Crystal Oscillator mode. OSC2/CLKO pins). Always associated with pin function OSC1 (see OSC1/CLKI. Analog input 3. This buffer is a Schmitt Trigger input when used in Serial Programming mode. OSC2 pin outputs CLKO. 1 26 I P TTL Digital I/O. — Oscillator crystal or clock output. A/D reference voltage (Low) input.PIC16F87XA TABLE 1-2: Pin Name OSC1/CLKI OSC1 CLKI OSC2/CLKO OSC2 CLKO MCLR/VPP MCLR VPP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/ CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/C2OUT RA5 AN4 SS C2OUT Legend: Note 1: 2: 3: 2 27 I/O I 3 28 I/O I 4 1 I/O I I O 5 2 I/O I I 6 3 I/O I O 7 4 I/O I I O TTL Digital I/O. SPI slave select input. Analog input 1. TTL Digital I/O. Oscillator crystal input or external clock source input. Timer0 external clock input. PORTA is a bidirectional I/O port. . ST Digital I/O – Open-drain when configured as output. Master Clear (input) or programming voltage (output). SOIC. 10 7 O O ST PIC16F873A/876A PINOUT DESCRIPTION PDIP.

Digital I/O. 19 20 5. 6 17 P P I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. ST I/O O Digital I/O. Positive supply for logic and I/O pins. USART1 synchronous clock. Synchronous serial clock input/output for SPI mode. Digital I/O. External interrupt. Compare1 output. ST I/O I/O I/O Digital I/O.PIC16F87XA TABLE 1-2: Pin Name PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED) PDIP. Timer1 oscillator output. In-circuit debugger and ICSP programming data. Compare2 output. In-circuit debugger and ICSP programming clock. PORTB can be software programmed for internal weak pull-ups on all inputs. USART asynchronous receive. ST I/O I I/O Digital I/O. ST I/O O I/O Digital I/O. RB0/INT RB0 INT RB1 RB2 RB3/PGM RB3 PGM RB4 RB5 RB6/PGC RB6 PGC RB7/PGD RB7 PGD RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT VSS VDD Legend: Note 1: 2: 3: 21 18 I/O I TTL/ST(1) Digital I/O. This buffer is a Schmitt Trigger input when used in Serial Programming mode. SOIC. Timer1 oscillator input. Capture2 input. PWM1 output. ST I/O I I/O Digital I/O. Capture1 input. TTL/ST(2) I/O I/O Digital I/O. Digital I/O.  2003 Microchip Technology Inc. SSOP Pin# QFN Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. Low-voltage (single-supply) ICSP programming enable pin. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. USART synchronous data. 22 23 24 19 20 21 I/O I/O 25 26 27 22 23 24 I/O I/O 28 25 11 8 12 9 13 10 14 11 15 12 16 13 17 14 18 15 8. ST I/O I/O Digital I/O. TTL TTL TTL/ST(2) I/O I Digital I/O. PWM2 output. DS39582B-page 9 . — — Ground reference for logic and I/O pins. I2C data I/O. PORTC is a bidirectional I/O port. ST I/O I I/O Digital I/O. TTL TTL TTL I/O I Digital I/O. SPI data in. SPI data out. ST I/O O I Digital I/O. USART asynchronous transmit. Digital I/O. Synchronous serial clock input/output for I2C mode. Timer1 external clock input.

Programming voltage input. . Always associated with pin function OSC1 (see OSC1/CLKI. Timer0 external clock input. A/D reference voltage (Low) input. DS39582B-page 10  2003 Microchip Technology Inc. ST buffer when configured in RC mode. otherwise CMOS. Analog input 3. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. Master Clear (input) or programming voltage (output). This buffer is a Schmitt Trigger input when used in Serial Programming mode.PIC16F87XA TABLE 1-3: Pin Name OSC1/CLKI OSC1 PIC16F874A/877A PINOUT DESCRIPTION PDIP Pin# 13 PLCC TQFP Pin# Pin# 14 30 QFN Pin# 32 I I/O/P Type Buffer Type Description CLKI I ST/CMOS(4) Oscillator crystal or external clock input. PORTA is a bidirectional I/O port. Oscillator crystal input or external clock source input. which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Connects to crystal or resonator in Crystal Oscillator mode. 3 4 20 20 4 5 21 21 5 6 22 22 6 7 23 23 7 8 24 24 I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. Comparator 2 output. Analog input 2. Comparator 1 output. Comparator VREF output. Oscillator crystal output. ST I/O I O Digital I/O – Open-drain when configured as output. OSC2 pin outputs CLKO. — Oscillator crystal or clock output. OSC2/CLKO pins). OSC2/CLKO OSC2 14 15 31 33 O CLKO O MCLR/VPP MCLR VPP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/C2OUT RA5 AN4 SS C2OUT Legend: Note 1: 2: 3: 1 2 18 18 I P ST 2 3 19 19 I/O I TTL Digital I/O. Master Clear (Reset) input. A/D reference voltage (High) input. This pin is an active low Reset to the device. TTL I/O I Digital I/O. In RC mode. Analog input 1. Analog input 0. External clock source input. TTL I/O I I O Digital I/O. TTL I/O I I O Digital I/O. SPI slave select input. Analog input 4. TTL I/O I I Digital I/O.

Digital I/O. Digital I/O. Digital I/O. This buffer is a Schmitt Trigger input when used in Serial Programming mode. In-circuit debugger and ICSP programming clock. DS39582B-page 11 . 34 35 36 37 38 39 9 10 11 10 11 12 I/O I/O 37 38 39 41 42 43 14 15 16 14 15 16 I/O I/O 40 44 17 17 I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. TTL/ST(2) I/O I/O Digital I/O. TTL TTL TTL I/O I Digital I/O. Digital I/O. In-circuit debugger and ICSP programming data. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. External interrupt.  2003 Microchip Technology Inc. RB0/INT RB0 INT RB1 RB2 RB3/PGM RB3 PGM RB4 RB5 RB6/PGC RB6 PGC RB7/PGD RB7 PGD Legend: Note 1: 2: 3: 33 36 8 9 I/O I TTL/ST(1) Digital I/O. PORTB can be software programmed for internal weak pull-up on all inputs. Low-voltage ICSP programming enable pin. TTL TTL TTL/ST(2) I/O I Digital I/O.PIC16F87XA TABLE 1-3: Pin Name PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP Pin# PLCC TQFP Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port.

EEPGD EECON1. Bank 2 . W DATAH . therefore. This causes these two instructions immediately following the “BSF EECON1. the user must write two bytes of the address to the EEADR and EEADRH registers. memory is read in second cycle after BSF EECON1. . . . RP0 MS_PROG_EE_ADDR EEADRH LS_PROG_EE_ADDR EEADR STATUS.PIC16F87XA 3. Bank 2 MS Byte of Program Address to read LS Byte of Program Address to read Bank 3 Point to PROGRAM memory EE Read Required Sequence . W = LS Byte of Program EEDATA . . W DATAL EEDATH. Any instructions here are ignored as program .RD” instruction to be ignored. . EEDATA and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation). Once the read control bit is set. W = MS Byte of Program EEDATA . . RP0 EEDATA. it can be read as two bytes in the following instructions.5 Reading Flash Program Memory To read a program memory location. RD . set the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). DS39582B-page 36  2003 Microchip Technology Inc. .RD STATUS. . . . . EXAMPLE 3-3: BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BSF NOP NOP BCF MOVF MOVWF MOVF MOVWF FLASH PROGRAM READ STATUS. The data is available in the very next cycle in the EEDATA and EEDATH registers. RP1 STATUS. . RP0 EECON1. the program memory Flash controller will use the next two instruction cycles to read the data.

The processor will halt internal operations for the typical 4 ms. all block writes to program memory are done as erase and write operations. FIGURE 3-1: BLOCK WRITES TO FLASH PROGRAM MEMORY 7 5 EEDATH 0 7 EEDATA 0 Four words of Flash are erased. This is not Sleep mode as the clocks and peripherals will continue to run. Flash program memory must be written in four-word blocks. then AAh. The user must follow the same specific sequence to initiate the write for each word in the program block.10. the processor requires two cycles to set up the erase/write operation. the writing of the first three words of the block appears to occur immediately. Set the WR control bit (EECON1<1>). This takes the data from the program location(s) not being written and loads it into the EEDATA and EEDATH registers. the processor will resume operation with the third instruction after the EECON1 write instruction. Set the EEPGD control bit (EECON1<7>). the last word of the four-word block).01.PIC16F87XA 3. the EEADR and EEADRH must point to the last location in the four-word block (EEADR<1:0> = 11). two or three words are being written to in the block of four words. 3. Write 55h. When the write is performed on the last word (EEADR<1:0> = 11). with a lower boundary defined by an address. to EECON2 (Flash programming sequence). only during the cycle in which the erase takes place (i.. 3.11). Since data is being written to buffer registers. 2. the block of four words are automatically erased and the contents of the buffer registers are written into the program memory. After the “BSF EECON1. Set control bit WR (EECON1<1>) to begin the write operation. Then the following sequence of events must be executed: 1. where EEADR<1:0> = 00. If the sequence is performed to any other location. DS39582B-page 37 . Write 55h. Then the sequence of events to transfer data to the buffer registers must be executed. This is accomplished by first writing the destination address to EEADR and EEADRH and then writing the data to EEDATA and EEDATH. the action is ignored. A block consists of four words with sequential addresses. as defined in bits WRT1:WRT0 of the device configuration word (Register 14-1). To transfer data from the buffer registers to the program memory.e. then the following sequence of events must be executed: 1. All four buffer register locations MUST be written to with correct data.WR” instruction. it must first be loaded into the buffer registers (see Figure 3-1). After the address and data have been set up. writing each program word in sequence (00. If only one. After the write cycle. The user must place two NOP instructions after the WR bit is set. to EECON2 (Flash programming sequence). To write program data. 2. then all buffers are transferred to Flash automatically after this word is written 6 First word of block to be written 8 14 EEADR<1:0> = 00 Buffer Register EEADR<1:0> = 01 14 EEADR<1:0> = 10 14 EEADR<1:0> = 11 14 Buffer Register Buffer Register Buffer Register Program Memory  2003 Microchip Technology Inc. At the same time. then a read from the program memory location(s) not being written to must be performed. then AAh. Set the EEPGD control bit (EECON1<7>).6 Writing to Flash Program Memory Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected. The write operation is edge-aligned and cannot occur across boundaries.

WREN INTCON. . . . . EXAMPLE 3-4: . . . . . WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1.GIE 55h EECON2 AAh EECON2 EECON1. ADDRL and DATADDR are all located in shared data memory 0x70 .W FSR INDF. .F EEADR. . .W EEDATH FSR.W EEADR DATAADDR. . .RP0 EEADR.PIC16F87XA An example of the complete four-word write sequence is shown in Example 3-4. . .RP0 ADDRH. the four words of data are loaded using indirect addressing. . . .GIE STATUS.F INDF. . Continue if less than four words LOOP Required Sequence DS39582B-page 38  2003 Microchip Technology Inc. . .W EEDATA FSR.WR . The 8 bytes of data are loaded. A valid starting address (the least significant bits = ‘00’)is loaded in ADDRH:ADDRL 2. . . . . Bank 2 Load initial address Load initial data address Load first data byte into lower Next byte Load second data byte into upper Bank 3 Point to program memory Enable writes Disable interrupts (if using) Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence processor will stop here and wait for write complete after write processor continues with 3rd instruction Disable writes Enable interrupts (if using) Bank 2 Increment address Check if lower two bits of address are ‘00’ Indicates when four words have been programmed Exit if more than four words.Z LOOP STATUS.W EEADRH ADDRL.RP1 STATUS. .W 0x03 0x03 STATUS. . . .F STATUS. . . The initial address is loaded into the EEADRH:EEADR register pair. starting at the address in DATADDR 3. .0x7f BSF BCF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF INCF MOVF MOVWF INCF BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF BCF INCF MOVF ANDLW XORLW BTFSC GOTO EECON1.WREN INTCON. . . . . . .EEPGD EECON1. .RP0 EECON1. . ADDRH. .

various mechanisms have been built-in. External write access to the program memory is also disabled. WREN is cleared. read as ‘0’. power glitch or software malfunction. When program memory is code-protected. .---. q = value depends upon condition. TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND FLASH PROGRAM MEMORIES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets Address 10Ch 10Dh 10Eh 10Fh 18Ch 18Dh 0Dh 8Dh Legend: EEDATA EEADR EEDATH EEADRH EECON1 EECON2 PIR2 PIE2 EEPROM/Flash Data Register Low Byte EEPROM/Flash Address Register Low Byte — — EEPGD — — — — — CMIF CMIE EEPROM/Flash Data Register High Byte — — — — EEPROM/Flash Address Register High Byte — EEIF EEIE WRERR BCLIF BCLIE WREN — — WR — — RD CCP2IF CCP2IE xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx ---0 q000 xxxx xxxx ---. DS39582B-page 39 . When the data EEPROM is code-protected.8 Operation During Code-Protect There are conditions when the device should not write to the data EEPROM or Flash program memory.= unimplemented. u = unchanged. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out.PIC16F87XA 3. all external access to the EEPROM is disabled. However.7 Protection Against Spurious Write 3. as well as execute instructions.1 “Configuration Bits” for additional information).  2003 Microchip Technology Inc. To protect against spurious writes.---x--. External access to the memory is also disabled. Writes by the device may be selectively inhibited to regions of the memory depending on the setting of bits WR1:WR0 of the configuration word (see Section 14. the microcontroller can read and write to program memory normally. On power-up.x000 ---0 q000 ---. Also.---. the microcontroller can read and write to the EEPROM normally.----0-0 0--0 -0-0 0--0 -0-0 0--0 -0-0 0--0 EEPROM Control Register 2 (not a physical register) x = unknown. the Power-up Timer (72 ms duration) prevents an EEPROM write. Shaded cells are not used by data EEPROM or Flash program memory.

PIC16F87XA NOTES: DS39582B-page 40  2003 Microchip Technology Inc. .

PIC16F87XA 4. . . .. Other PORTA pins are multiplexed with analog inputs and the analog VREF input for both the A/D converters and the comparators. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. Bank0 Initialize PORTA by clearing output data latches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6>are always read as '0'.1 PORTA and the TRISA Register PORTA is a 6-bit wide. Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. RP0 0x06 ADCON1 0xCF TRISA 4. . Note: On a Power-on Reset. RP1 PORTA STATUS. . Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual (DS33023). Reading the PORTA register reads the status of the pins.0 I/O PORTS EXAMPLE 4-1: BCF BCF CLRF BSF MOVLW MOVWF MOVLW MOVWF INITIALIZING PORTA . whereas writing to it will write to the port latch. The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain output. In general. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i. EN RD PORTA To A/D Converter or Comparator Note 1: I/O pins have protection diodes to VDD and VSS.e.  2003 Microchip Technology Inc. .. put the corresponding output driver in a High-Impedance mode). The operation of each pin is selected by clearing/setting the appropriate control bits in the ADCON1 and/or CMCON registers. . the value is modified and then written to the port data latch. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. Therefore. . these pins are configured as analog inputs and read as ‘0’. DS39582B-page 41 . . The corresponding data direction register is TRISA. . . . bidirectional port. RP0 STATUS. that pin may not be used as a general purpose I/O pin. . All other PORTA pins have TTL input levels and full CMOS output drivers. . a write to a port implies that the port pins are read. put the contents of the output latch on the selected pin). The comparators are in the off (digital) state. when a peripheral is enabled.e. All write operations are read-modify-write operations. FIGURE 4-1: Data Bus Data Latch D Q BLOCK DIAGRAM OF RA3:RA0 PINS WR PORTA VDD CK Q P I/O pin(1) TRIS Latch D WR TRISA Q N CK Q VSS Analog Input Mode RD TRISA TTL Input Buffer Q D The TRISA register controls the direction of the port pins even when they are being used as analog inputs. STATUS.

.PIC16F87XA FIGURE 4-2: BLOCK DIAGRAM OF RA4/T0CKI PIN CMCON<2:0> = x01 or 011 C1OUT Data Bus WR PORTA Data Latch D Q CK Q 1 N VSS I/O pin(1) 0 TRIS Latch D Q WR TRISA CK Q Schmitt Trigger Input Buffer RD TRISA Q D EN EN RD PORTA TMR0 Clock Input Note 1: I/O pin has protection diodes to VSS only. DS39582B-page 42  2003 Microchip Technology Inc. FIGURE 4-3: BLOCK DIAGRAM OF RA5 PIN CMCON<2:0> = 011 or 101 C2OUT Data Bus WR PORTA Data Latch D Q CK Q 1 VDD P 0 N Analog IIP Mode VSS TTL Input Buffer I/O pin(1) TRIS Latch D Q WR TRISA CK Q RD TRISA Q D EN EN RD PORTA A/D Converter or SS Input Note 1: I/O pin has protection diodes to VDD and VSS.

Input/output or analog input or VREF+.PIC16F87XA TABLE 4-1: Name RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT PORTA FUNCTIONS Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 Buffer TTL TTL TTL TTL ST TTL Input/output or analog input. where PCFG3:PCFG0 = 0100.0000 Value on all other Resets --0u 0000 --11 1111 0000 0111 000. 0101. 1110.= unimplemented locations read as ‘0’.or CVREF. the A/D converter must be set to one of the following modes.  2003 Microchip Technology Inc. . Input/output or analog input or VREF.0000 00-. 1111. 1101. Input/output or analog input or slave select input for synchronous serial port or comparator output. DS39582B-page 43 .0000 00-. Note: When using the SSP module in SPI Slave mode and SS enabled. ST = Schmitt Trigger input TABLE 4-2: Address 05h 85h 9Ch 9Dh 9Fh Legend: Name PORTA TRISA CMCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 — — C2OUT ADFM Bit 6 — — C1OUT ADCS2 Bit 5 RA5 C2INV CVRR — Bit 4 RA4 C1INV — — Bit 3 RA3 CIS CVR3 PCFG3 Bit 2 RA2 CM2 CVR2 PCFG2 Bit 1 RA1 CM1 CVR1 PCFG1 Bit 0 RA0 CM0 CVR0 PCFG0 Value on: POR. Shaded cells are not used by PORTA. Input/output or external clock input for Timer0 or comparator output. Output is open-drain type. Function Legend: TTL = TTL input. Input/output or analog input. u = unchanged. BOR --0x 0000 --11 1111 0000 0111 000.0000 PORTA Data Direction Register CVRCON ADCON1 CVREN CVROE x = unknown. 011x.

11. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. RB7:RB4. RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>). allow easy interface to a keypad and make it possible for wake-up on key depression. any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). together with software configurable pull-ups on these four pins.e. can clear the interrupt in the following manner: a) b) Any read or write of PORTB. Polling of PORTB is not recommended while using the interrupt-on-change feature. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. DS39582B-page 44  2003 Microchip Technology Inc. Clear flag bit RBIF. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i. bidirectional port. . A single control bit can turn on all the pull-ups.PIC16F87XA 4. Refer to the application note. The alternate functions of these pins are described in Section 14. This interrupt-on-mismatch feature. A mismatch condition will continue to set flag bit RBIF. put the corresponding output driver in a High-Impedance mode). The corresponding data direction register is TRISB. Three pins of PORTB are multiplexed with the In-Circuit Debugger and Low-Voltage Programming function: RB3/PGM.. “Implementing Wake-up on Key Stroke” (DS00552). put the contents of the output latch on the selected pin)..0 “Special Features of the CPU”. This interrupt can wake the device from Sleep.e. This will end the mismatch condition. have an interrupton-change feature.e. This is performed by clearing bit RBPU (OPTION_REG<7>). AN552.. RB0/INT is discussed in detail in Section 14. FIGURE 4-4: BLOCK DIAGRAM OF RB3:RB0 PINS VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q TTL Input Buffer Q I/O pin(1) RBPU(2) Data Bus WR Port FIGURE 4-5: BLOCK DIAGRAM OF RB7:RB4 PINS VDD Weak P Pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q RBPU(2) WR TRIS CK Data Bus WR Port RD TRIS Q RD Port EN RB0/INT RB3/PGM Schmitt Trigger Buffer RD Port RD Port EN Set RBIF Q1 D WR TRIS CK TTL Input Buffer ST Buffer RD TRIS Latch Q D Note 1: I/O pins have diode protection to VDD and VSS. set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). in the Interrupt Service Routine. RB6/PGC and RB7/PGD. Four of the PORTB pins. Q From other RB7:RB4 pins RB7:RB6 In Serial Programming Mode D RD Port EN Q3 Note 1: I/O pins have diode protection to VDD and VSS. The weak pull-up is automatically turned off when the port pin is configured as an output.1 “INT Interrupt”.2 PORTB and the TRISB Register PORTB is an 8-bit wide. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB port change interrupt with flag bit RBIF (INTCON<0>). The user. The pull-ups are disabled on a Power-on Reset. set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i. Each of the PORTB pins has a weak internal pull-up. 2: To enable weak pull-ups. The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. 2: To enable weak pull-ups. Only pins configured as inputs can cause this interrupt to occur (i.

TABLE 4-4: Address SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 RB7 Bit 6 RB6 INTEDG Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 PSA Bit 2 RB2 PS2 Bit 1 RB1 PS1 Bit 0 Value on: POR. Input/output pin. Internal software programmable weak pull-up. Legend: TTL = TTL input. Input/output pin. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode or in-circuit debugger. Internal software programmable weak pull-up. Internal software programmable weak pull-up. BOR Value on all other Resets 06h. Internal software programmable weak pull-up. DS39582B-page 45 . Input/output pin (with interrupt-on-change). Serial programming clock. Input/output pin (with interrupt-on-change) or in-circuit debugger pin. 3: Low-Voltage ICSP Programming (LVP) is enabled by default which disables the RB3 I/O function. ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Internal software programmable weak pull-up. Shaded cells are not used by PORTB. 106h PORTB 86h. Internal software programmable weak pull-up. Input/output pin or programming pin in LVP mode.  2003 Microchip Technology Inc. 181h OPTION_REG RBPU Legend: x = unknown. 186h TRISB RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS0 1111 1111 1111 1111 PORTB Data Direction Register T0CS T0SE 81h. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. u = unchanged. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change) or in-circuit debugger pin.PIC16F87XA TABLE 4-3: Name RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD (3) PORTB FUNCTIONS Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer TTL/ST TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) (1) Function Input/output pin or external interrupt input. LVP must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and 40-pin mid-range devices.

Since the TRIS bit override is in effect while the peripheral is enabled. put the contents of the output latch on the selected pin). The corresponding data direction register is TRISC. by using the CKE bit (SSPSTAT<6>).e. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i. . the PORTC<4:3> pins can be configured with normal I2C levels. PORTC pins have Schmitt Trigger input buffers. should be avoided. read-modifywrite instructions (BSF.. When enabling peripheral functions. put the corresponding output driver in a High-Impedance mode). 0 Schmitt Trigger with SMBus Levels I/O pin(1) TRIS Latch FIGURE 4-6: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<2:0>. or with SMBus levels. XORWF) with TRISC as the destination. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. care should be taken in defining TRIS bits for each PORTC pin. bidirectional port. PORTC is multiplexed with several peripheral functions (Table 4-5). 3: Peripheral OE (Output Enable) is only activated if Peripheral Select is active.3 PORTC and the TRISC Register FIGURE 4-7: PORTC is an 8-bit wide. 2: Port/Peripheral Select signal selects between port data and peripheral output. BCF. while other peripherals override the TRIS bit to make a pin an input.. Some peripherals override the TRIS bit to make a pin an output. 0 VDD P Data Latch D WR TRIS CK Q Q TRIS Latch DS39582B-page 46  2003 Microchip Technology Inc. Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.PIC16F87XA 4. When the I C module is enabled. 2: Port/Peripheral Select signal selects between port data and peripheral output. 2 PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<4:3> Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port D CK Q Q 1 0 VDD P Data Latch D WR TRIS CK Q Q N VSS RD TRIS Peripheral OE(3) Schmitt Trigger Q D EN RD Port SSP Input 1 CKE SSPSTAT<6> Note 1: I/O pins have diode protection to VDD and VSS.e. 3: Peripheral OE (Output Enable) is only activated if Peripheral Select is active. RC<7:5> Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port D CK Q Q 1 I/O pin(1) N VSS RD TRIS Peripheral OE(3) Schmitt Trigger Q D EN RD Port Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS.

RC3 can also be the synchronous serial clock for both SPI and I2C modes. BOR Value on all other Resets Name PORTC TRISC xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PORTC Data Direction Register Legend: x = unknown. Legend: ST = Schmitt Trigger input TABLE 4-6: Address 07h 87h SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on: POR. u = unchanged  2003 Microchip Technology Inc. Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. Input/output port pin or USART asynchronous receive or synchronous data. Input/output port pin or Synchronous Serial Port data output. Input/output port pin or USART asynchronous transmit or synchronous clock.PIC16F87XA TABLE 4-5: Name RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTC FUNCTIONS Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. DS39582B-page 47 . RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).

DS39582B-page 48  2003 Microchip Technology Inc. u = unchanged. Input/output port pin or Parallel Slave Port bit 3. Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRIS CK Schmitt Trigger Input Buffer RD TRIS Q D EN EN RD Port Note 1: I/O pins have protection diodes to VDD and VSS. ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) Legend: ST = Schmitt Trigger input. PSPMODE (TRISE<4>). Input/output port pin or Parallel Slave Port bit 7. BOR Value on all other Resets Name PORTD TRISD TRISE xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PORTD Data Direction Register OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown. . TABLE 4-8: Address 08h 88h 89h SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 RD7 IBF Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 — Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on: POR. FIGURE 4-8: Data Bus WR Port PORTD BLOCK DIAGRAM (IN I/O PORT MODE) PORTD is an 8-bit port with Schmitt Trigger input buffers.PIC16F87XA 4. the input buffers are TTL. TABLE 4-7: Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTD FUNCTIONS Bit# bit 0 bit 1 bit2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL (1) Function Input/output port pin or Parallel Slave Port bit 0. Input/output port pin or Parallel Slave Port bit 5. Input/output port pin or Parallel Slave Port bit 1. PORTD can be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit.4 Note: PORTD and TRISD Registers PORTD and TRISD are not implemented on the 28-pin devices. TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. Input/output port pin or Parallel Slave Port bit 6. Input/output port pin or Parallel Slave Port bit 4.= unimplemented. . Shaded cells are not used by PORTD. Input/output port pin or Parallel Slave Port bit 2. read as ‘0’. Each pin is individually configurable as an input or output. In this mode.

FIGURE 4-9: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) PORTE has three pins (RE0/RD/AN5. TRISE controls the direction of the RE pins. These pins have Schmitt Trigger input buffers. DS39582B-page 49 . PORTE pins are multiplexed with analog inputs. ensure that ADCON1 is configured for digital I/O. In this mode. Value of PORTD I/O pins is latched into PORTD register (if chip selected). The PORTE pins become the I/O control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. Contents of PORTD register are output to PORTD I/O pins (if chip selected). TABLE 4-9: Name PORTE FUNCTIONS Bit# Buffer Type Function I/O port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Idle 0 = Read operation. even when they are being used as analog inputs. In this mode.  2003 Microchip Technology Inc. the input buffers are TTL. Register 4-1 shows the TRISE register which also controls the Parallel Slave Port operation. Data Bus WR Port Data Latch D Q I/O pin(1) CK TRIS Latch D Q Schmitt Trigger Input Buffer WR TRIS CK RD TRIS Q D EN EN RD Port Note 1: I/O pins have protection diodes to VDD and VSS. these pins are configured as analog inputs and read as ‘0’.5 Note: PORTE and TRISE Register PORTE and TRISE are not implemented on the 28-pin devices.PIC16F87XA 4. the user must make certain that the TRISE<2:0> bits are set and that the pins are configured as digital inputs. When selected for analog input. these pins will read as ‘0’s. I/O port pin or chip select control input in Parallel Slave Port mode or analog input: CS 1 = Device is not selected 0 = Device is selected RE0/RD/AN5 bit 0 ST/TTL(1) RE1/WR/AN6 bit 1 ST/TTL(1) RE2/CS/AN7 bit 2 ST/TTL (1) Legend: ST = Schmitt Trigger input. The user must make sure to keep the pins configured as inputs when using them as analog inputs. RE1/WR/AN6 and RE2/CS/AN7) which are individually configurable as inputs or outputs. Also. I/O port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Idle 0 = Write operation. Note: On a Power-on Reset.

. u = unchanged. . read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39582B-page 50  2003 Microchip Technology Inc.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. REGISTER 4-1: TRISE REGISTER (ADDRESS 89h) R-0 IBF bit 7 Parallel Slave Port Status/Control Bits: R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 — R/W-1 Bit 2 R/W-1 Bit 1 R/W-1 Bit 0 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = PORTD functions in Parallel Slave Port mode 0 = PORTD functions in general purpose I/O mode Unimplemented: Read as ‘0’ PORTE Data Direction Bits: Bit 2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output Bit 1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output Bit 0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend: R = Readable bit . BOR Value on all other Resets ---.= unimplemented.0000 PORTE Data Direction bits x = unknown.-xxx ---.0000 00-.-uuu 0000 -111 0000 -111 00-. read as ‘0’. Shaded cells are not used by PORTE.PIC16F87XA TABLE 4-10: Address 09h 89h 9Fh Legend: Name PORTE TRISE ADCON1 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 7 — IBF ADFM Bit 6 — OBF ADCS2 Bit 5 — IBOV — Bit 4 — PSPMODE — Bit 3 — — PCFG3 Bit 2 RE2 PCFG2 Bit 1 RE1 PCFG1 Bit 0 RE0 PCFG0 Value on: POR.

The A/D port configuration bits.PIC16F87XA 4. A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or RD pin becomes high (level triggered). OBF remains low until data is written to PORTD by the user firmware. When either the CS or WR lines become high (level triggered). The interrupt flag bit. There are actually two 8-bit latches: one for data output and one for data input. RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to be the CS (Chip Select) input. must be set to configure pins RE2:RE0 as digital I/O. it is asynchronously readable and writable by the external world through RD control input pin. the TRISD register is ignored since the external device is controlling the direction of data flow. IBF can only be cleared by reading the PORTD input latch. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. RE0/RD/AN5. the Input Buffer Full (IBF) status flag bit (TRISE<7>) is set on the Q4 clock cycle. if flag bit IBOV was previously set. In this mode. or microprocessor port. and WR control input pin. A read from the PSP occurs when both the CS and RD lines are first detected low. the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). the IBF and OBF bits are held clear. PCFG3:PCFG0 (ADCON1<3:0>).6 Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F873A or PIC16F876A. following the next Q2 cycle. the interrupt flag bit PSPIF is set on the Q4 clock cycle. Setting bit PSPMODE enables port pin RE0/RD/AN5 to be the RD input. is also set on the same Q4 clock cycle. For this functionality. following the next Q2 cycle. FIGURE 4-10: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus D WR Port Q RDx pin CK TTL Q RD Port D EN EN One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read TTL RD Chip Select TTL Write TTL Note 1: I/O pins have protection diodes to VDD and VSS. PORTD operates as an 8-bit wide Parallel Slave Port. The Input Buffer Overflow (IBOV) status flag bit (TRISE<5>) is set if a second write to the PSP is attempted when the previous byte has not been read out of the buffer. indicating that the PORTD latch is waiting to be read by the external bus. when control bit PSPMODE (TRISE<4>) is set. In Slave mode. When not in PSP mode. PSPIF (PIR1<7>). CS WR  2003 Microchip Technology Inc. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immediately (Figure 4-12). The external microprocessor can read or write the PORTD latch as an 8-bit latch. to signal the write is complete (Figure 4-11). RE1/WR/AN6. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>). However. The PSP can directly interface to an 8-bit microprocessor data bus. DS39582B-page 51 . indicating that the read is complete. The user writes 8-bit data to the PORTD data latch and reads data from the port pin latch (note that they have the same address). it must be cleared in firmware.

= unimplemented. u = unchanged.0000 00-. Port pins when read — IBF PSPIF(1) PSPIE(1) ADFM — OBF ADIF ADIE ADCS2 — IBOV RCIF RCIE — — PSPMODE TXIF TXIE — — — SSPIF SSPIE PCFG3 RE2 CCP1IF PCFG2 RE1 TMR2IF PCFG1 RE0 PORTE Data Direction bits xxxx xxxx uuuu uuuu ---.-xxx ---.-uuu 0000 -111 0000 -111 TMR1IF 0000 0000 0000 0000 PCFG0 00-. Bits PSPIE and PSPIF are reserved on the PIC16F873A/876A. BOR Value on all other Resets Port Data Latch when written.0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 ADCON1 x = unknown.PIC16F87XA FIGURE 4-11: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 4-12: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 4-11: Address 08h 09h 89h 0Ch 8Ch 9Fh Legend: Note 1: Name PORTD PORTE TRISE PIR1 PIE1 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR. Shaded cells are not used by the Parallel Slave Port. read as ‘0’. . . always maintain these bits clear. DS39582B-page 52  2003 Microchip Technology Inc.

The user can work around this by writing an adjusted value to the TMR0 register. 5. PSA. T0SE (OPTION_REG<4>). DS39582B-page 53 . Additional information on the Timer0 module is available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023). Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus M U X 8 1 0 M U X Sync 2 Cycles TMR0 Reg CLKO (= FOSC/4) 0 RA4/T0CKI pin 1 T0SE T0CS PSA PRESCALER Set Flag bit TMR0IF on Overflow 0 M U X 8-bit Prescaler 8 8-to-1 MUX PS2:PS0 Watchdog Timer 1 PSA WDT Enable bit 0 MUX 1 PSA WDT Time-out Note: T0CS.0 TIMER0 MODULE The Timer0 module timer/counter has the following features: • • • • • • 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting bit T0CS (OPTION_REG<5>). Clearing bit T0SE selects the rising edge. This overflow sets bit TMR0IF (INTCON<2>). In Timer mode. the increment is inhibited for the following two instruction cycles. Restrictions on the external clock input are discussed in detail in Section 5. The prescaler is not readable or writable.PIC16F87XA 5. Bit TMR0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. the Timer0 module will increment every instruction cycle (without prescaler). The interrupt can be masked by clearing bit TMR0IE (INTCON<5>). The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer.1 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI.2 “Using Timer0 with an External Clock”. Section 5.  2003 Microchip Technology Inc. T0SE. Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. PS2:PS0 are (OPTION_REG<5:0>).3 “Prescaler” details the operation of the prescaler. If the TMR0 register is written. The incrementing edge is determined by the Timer0 Source Edge Select bit. The TMR0 interrupt cannot awaken the processor from Sleep since the timer is shut-off during Sleep. In Counter mode.

. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count. 5.. Therefore. BSF 1. This sequence must be followed even if the WDT is disabled. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2-0 To avoid an unintended device Reset. When no prescaler is used.x.etc. When assigned to WDT. the instruction sequence shown in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. When assigned to the Timer0 module. A prescaler assignment for the REGISTER 5-1: OPTION_REG REGISTER R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0 bit 7 bit 6 bit 5 RBPU INTEDG T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 1:2 000 1:1 1:4 001 1:2 1:8 010 1:4 1 : 16 011 1:8 1 : 32 100 1 : 16 1 : 64 101 1 : 32 1 : 128 110 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit . This prescaler is not readable or writable (see Figure 5-1)..g. The prescaler is not readable or writable. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks.3 Prescaler There is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. CLRF 1. all instructions writing to the TMR0 register (e.) will clear the prescaler.PIC16F87XA 5..n = Value at POR Note: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. DS39582B-page 54  2003 Microchip Technology Inc. a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns).2 Using Timer0 with an External Clock Timer0 module means that there is no prescaler for the Watchdog Timer and vice versa. Refer to the electrical specification of the desired device. the external clock input is the same as the prescaler output. MOVWF 1. but will not change the prescaler assignment. .

8Bh. . Shaded cells are not used by Timer0. BOR Value on all other Resets TMR0 INTCON OPTION_REG Timer0 Module Register GIE RBPU PEIE INTEDG TMR0IE T0CS INTE T0SE RBIE PSA TMR0IF PS2 INTF PS1 RBIF PS0 xxxx xxxx uuuu uuuu 0000 000x 0000 000u 1111 1111 1111 1111 x = unknown. u = unchanged.18Bh 81h.PIC16F87XA TABLE 5-1: Address 01h. 10Bh.  2003 Microchip Technology Inc.181h Legend: REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR.101h 0Bh. DS39582B-page 55 .= unimplemented locations read as ‘0’.

.PIC16F87XA NOTES: DS39582B-page 56  2003 Microchip Technology Inc.

TMR1ON (T1CON<0>). read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 3 bit 2 bit 1 bit 0  2003 Microchip Technology Inc. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit . In Counter mode. That is. This Reset can be generated by either of the two CCP modules (Section 8. When the Timer1 oscillator is enabled (T1OSCEN is set). the TRISC<1:0> value is ignored and these pins read as ‘0’.0 “Capture/Compare/PWM Modules”). Timer1 can operate in one of two modes: • As a Timer • As a Counter The operating mode is determined by the clock select bit. TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable.PIC16F87XA 6. DS39582B-page 57 . Timer1 increments every instruction cycle. the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. is generated on overflow which is latched in interrupt flag bit. Timer1 also has an internal “Reset input”. In Timer mode. if enabled. TMR1CS (T1CON<1>). it increments on every rising edge of the external clock input. REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 — bit 7 U-0 — R/W-0 R/W-0 R/W-0 T1OSCEN R/W-0 R/W-0 R/W-0 bit 0 T1CKPS1 T1CKPS0 T1SYNC TMR1CS TMR1ON bit 7-6 bit 5-4 Unimplemented: Read as ‘0’ T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) T1SYNC: Timer1 External Clock Input Synchronization Control bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. Register 6-1 shows the Timer1 Control register. Timer1 can be enabled/disabled by setting/clearing control bit. TMR1IE (PIE1<0>). The TMR1 interrupt. Timer1 uses the internal clock when TMR1CS = 0. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. Additional information on timer modules is available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023).

PIC16F87XA
6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since the internal clock is always in sync. Timer1 may operate in either a Synchronous, or an Asynchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment.

FIGURE 6-1:
T1CKI (Default High)

TIMER1 INCREMENTING EDGE

T1CKI (Default Low)

Note: Arrows indicate counter increments.

6.3

Timer1 Operation in Synchronized Counter Mode

Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.

If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. In this configuration, during Sleep mode, Timer1 will not increment even if the external clock is present since the synchronization circuit is shut-off. The prescaler, however, will continue to increment.

FIGURE 6-2:

TIMER1 BLOCK DIAGRAM
Set Flag bit TMR1IF on Overflow TMR1H

TMR1 TMR1L

0 1 TMR1ON On/Off T1SYNC Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS

Synchronized Clock Input

T1OSC RC0/T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock 1

Synchronize det Q Clock

RC1/T1OSI/CCP2(2)

Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.

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 2003 Microchip Technology Inc.

PIC16F87XA
6.4 Timer1 Operation in Asynchronous Counter Mode
TABLE 6-1:
Osc Type LP

CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq. 32 kHz 100 kHz 200 kHz C1 33 pF 15 pF 15 pF C2 33 pF 15 pF 15 pF

If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt-on-overflow which will wake-up the processor. However, special precautions in software are needed to read/write the timer. In Asynchronous Counter mode, Timer1 cannot be used as a time base for capture or compare operations.

These values are for design guidance only. Crystals Tested: 32.768 kHz 100 kHz 200 kHz Note 1: Epson C-001R32.768K-A Epson C-2 100.00 KC-P STD XTL 200.000 kHz ± 20 PPM ± 20 PPM ± 20 PPM

6.4.1

READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.

2:

Higher capacitance increases the stability of oscillator but also increases the start-up time. Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

6.6

Resetting Timer1 Using a CCP Trigger Output

If the CCP1 or CCP2 module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit, TMR1IF (PIR1<0>).

6.5

Timer1 Oscillator

A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator, rated up to 200 kHz. It will continue to run during Sleep. It is primarily intended for use with a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.

Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1.

 2003 Microchip Technology Inc.

DS39582B-page 59

PIC16F87XA
6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L) 6.8 Timer1 Prescaler
The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.

TMR1H and TMR1L registers are not reset to 00h on a POR, or any other Reset, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other Resets, the register is unaffected.

TABLE 6-2:
Address

REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 GIE PSPIF(1) PSPIE(1) Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on: POR, BOR Value on all other Resets

Name

0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 8Ch 0Eh 0Fh 10h Legend: Note 1: PIR1 PIE1 TMR1L T1CON

0000 000x 0000 000u

TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register — —

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.

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 2003 Microchip Technology Inc.

Additional information on timer modules is available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023). It can be used as the PWM time base for the PWM mode of the CCP module(s). Timer2 can be shut-off by clearing control bit. PR2 is a readable and writable register. TMR2IF (PIR1<1>)). TMR2ON (T2CON<2>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 2 bit 1-0  2003 Microchip Technology Inc. The TMR2 register is readable and writable and is cleared on any device Reset. PR2. selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 — bit 7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 6-3 Unimplemented: Read as ‘0’ TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale • • • 1111 = 1:16 postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit .n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. Timer2 is an 8-bit timer with a prescaler and a postscaler. to minimize power consumption. 1:16 2 T2CKPS1: T2CKPS0 FOSC/4 Postscaler 1:1 to 1:16 4 T2OUTPS3: T2OUTPS0 EQ PR2 Reg Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.PIC16F87XA 7. The PR2 register is initialized to FFh upon Reset. 1:4. DS39582B-page 61 . The Timer2 module has an 8-bit period register. 1:4 or 1:16. The input clock (FOSC/4) has a prescale option of 1:1.0 TIMER2 MODULE Register 7-1 shows the Timer2 Control register. FIGURE 7-1: Sets Flag bit TMR2IF TMR2 Output(1) Reset TIMER2 BLOCK DIAGRAM TMR2 Reg Comparator Prescaler 1:1.

read as ‘0’. DS39582B-page 62  2003 Microchip Technology Inc. . MCLR Reset. . TABLE 7-1: Address Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 GIE PSPIF(1) PSPIE — (1) Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on: POR. 8Bh. u = unchanged. which optionally uses it to generate the shift clock.1 Timer2 Prescaler and Postscaler 7.PIC16F87XA 7. always maintain these bits clear. Bits PSPIE and PSPIF are reserved on 28-pin devices. The output of TMR2 (before the postscaler) is fed to the SSP module. WDT Reset or BOR) TMR2 is not cleared when T2CON is written. 18Bh 0Ch 8Ch 11h 12h 92h Legend: Note 1: PIR1 PIE1 TMR2 T2CON PR2 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 Timer2 Module’s Register Timer2 Period Register TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 x = unknown.= unimplemented. BOR Value on all other Resets 0Bh. INTCON 10Bh.2 Output of TMR2 The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device Reset (POR. Shaded cells are not used by the Timer2 module.

the operation of a CCP module is described with respect to CCP1. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled). CCP2 operates the same as CCP1 except where noted. Additional information on CCP modules is available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023) and in application note AN594. CCP1 Module: Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte).PIC16F87XA 8. with the exception being the operation of the special event trigger. In the following sections. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s). “Using the CCP Module(s)” (DS00594). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1. DS39582B-page 63 . The CCP2CON register controls the operation of CCP2. TABLE 8-1: CCP MODE – TIMER RESOURCES REQUIRED Timer Resource Timer1 Timer1 Timer2 CCP Mode Capture Compare PWM TABLE 8-2: Capture Capture Compare PWM PWM PWM INTERACTION OF TWO CCP MODULES Interaction Same TMR1 time base The compare should be configured for the special event trigger which clears TMR1 The compare(s) should be configured for the special event trigger which clears TMR1 The PWMs will have the same frequency and update rate (TMR2 interrupt) None None Capture Compare Compare PWM Capture Compare CCPx Mode CCPy Mode  2003 Microchip Technology Inc. Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation.0 CAPTURE/COMPARE/PWM MODULES CCP2 Module: Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte).

every falling edge 0101 = Capture mode. CCP1 resets TMR1. Compare mode: Unused. CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit . CCPx pin is unaffected) 1011 = Compare mode. clear output on match (CCPxIF bit is set) 1010 = Compare mode. every 4th rising edge 0111 = Capture mode. . every 16th rising edge 1000 = Compare mode. generate software interrupt on match (CCPxIF bit is set.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The eight MSbs are found in CCPRxL. trigger special event (CCPxIF bit is set. CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode. PWM mode: These bits are the two LSbs of the PWM duty cycle. CCPx pin is unaffected). read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 CCPxX R/W-0 CCPxY R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0 bit 3-0 DS39582B-page 64  2003 Microchip Technology Inc. every rising edge 0110 = Capture mode.PIC16F87XA REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh) U-0 — bit 7 bit 7-6 bit 5-4 Unimplemented: Read as ‘0’ CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused. set output on match (CCPxIF bit is set) 1001 = Compare mode.

4 CCP PRESCALER 8.1. Any Reset will clear the prescaler counter. FIGURE 8-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCP1IF (PIR1<2>) EXAMPLE 8-1: CLRF MOVLW MOVWF CHANGING BETWEEN CAPTURE PRESCALERS Prescaler 1.3 SOFTWARE INTERRUPT The type of event is configured by control bits.PIC16F87XA 8. When the Capture mode is changed. Also. DS39582B-page 65 . the interrupt request flag bit. 16 RC2/CCP1 pin CCPR1H and Edge Detect Capture Enable TMR1H CCP1CON<3:0> Qs CCPR1L CCP1CON . In Asynchronous Counter mode. the prescaler counter is cleared. value TMR1L  2003 Microchip Technology Inc.1. or the CCP module is not in Capture mode. CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. If another capture occurs before the value in register CCPR1 is read. Load the W reg with .1. Example 8-1 shows the recommended method for switching between capture prescalers. the prescaler counter will not be cleared. the capture operation may not work. the old captured value is overwritten by the new value. or Synchronized Counter mode. CCP1IF. Whenever the CCP module is turned off. Switching from one capture prescaler to another may generate an interrupt. the first capture may be from a non-zero prescaler. CCP1M3:CCP1M0 (CCPxCON<3:0>). a write to the port can cause a Capture condition. This example also clears the prescaler counter and will not generate the “false” interrupt. CCP1IF (PIR1<2>). In Capture mode.1 Capture Mode 8. 8. 8. Note: If the RC2/CCP1 pin is configured as an output. Load CCP1CON with this . a false capture interrupt may be generated. following any such change in operating mode. An event is defined as one of the following: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode.2 TIMER1 MODE SELECTION In Capture mode. is set. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit. move value and CCP ON CCP1CON .1.1 CCP PIN CONFIGURATION There are four prescaler settings. The interrupt flag must be cleared in software. therefore. the new prescaler . the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. 4. Turn CCP module off NEW_CAPT_PS . When a capture is made. specified by bits CCP1M3:CCP1M0. for the CCP module to use the capture feature.

When a match occurs. but not set interrupt flag bit TMR1IF (PIR1<0>) and set bit GO/DONE (ADCON0<2>). DS39582B-page 66  2003 Microchip Technology Inc. The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled).1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. if the CCP module is using the compare feature. The CCPIF bit is set. or Synchronized Counter mode. At the same time.2. Special event trigger will: reset Timer1.2. an internal hardware trigger is generated which may be used to initiate an action.PIC16F87XA 8. Special Event Trigger Set Flag bit CCP1IF (PIR1<2>) RC2/CCP1 pin Q S R TRISC<2> Output Enable Output Logic Match CCPR1H CCPR1L Comparator TMR1H TMR1L CCP1CON<3:0> Mode Select 8. the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits.2 TIMER1 MODE SELECTION In Compare mode. the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. the compare operation may not work.2 Compare Mode 8.2. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level.4 SPECIAL EVENT TRIGGER FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM In this mode. In Asynchronous Counter mode. interrupt flag bit CCP1IF is set. This is not the PORTC I/O data latch. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. the CCP1 pin is not affected. causing a CCP interrupt (if enabled).3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen. Timer1 must be running in Timer mode.2. Note: The special event trigger from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>). CCP1M3:CCP1M0 (CCP1CON<3:0>). The special event trigger output of CCP1 resets the TMR1 register pair. 8. 8. .

The postscaler could be used to have a servo update rate at a different frequency than the PWM output.1 “Timer2 Prescaler and Postscaler”) is not used in the determination of the PWM frequency.C. The PWM period can be calculated using the following formula: PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. The PWM period is specified by writing to the PR2 register. The following equation is used to calculate the PWM duty cycle in time: PWM Duty Cycle =(CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time. The frequency of the PWM is the inverse of the period (1/period). the TRISC<2> bit must be cleared to make the CCP1 pin an output. When the CCPR1H and 2-bit latch match TMR2. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. CCPR1H is a read-only register..1 PWM PERIOD In Pulse Width Modulation mode.  2003 Microchip Technology Inc. the CCP1 pin will not be cleared.3. For a step-by-step procedure on how to set up the CCP module for PWM operation. the CCP1 pin is cleared. In PWM mode. When TMR2 is equal to PR2. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. FIGURE 8-4: Period PWM OUTPUT EQUATION 8-1: Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 Resolution = FOSC log FPWM log(2) ( ) bits Note: If the PWM duty cycle value is longer than the PWM period.3 PWM Mode (PWM) 8.3. TRISC<2> PR2 Note 1: The 8-bit timer is concatenated with 2-bit internal Q clock. the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (exception: if PWM duty cycle = 0%. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. the period is complete). A PWM output (Figure 8-4) has a time base (period) and a time that the output stays high (duty cycle).e. This double-buffering is essential for glitch-free PWM operation. to create 10-bit time base. Comparator Clear Timer. the CCPx pin produces up to a 10-bit resolution PWM output. Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode. CCP1 pin and latch D. DS39582B-page 67 .3 “Setup for PWM Operation”. Since the CCP1 pin is multiplexed with the PORTC data latch. the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 7.PIC16F87XA 8. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. see Section 8. or 2 bits of the prescaler.2 PWM DUTY CYCLE CCPR1H (Slave) RC2/CCP1 Comparator R Q TMR2 (Note 1) S The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits.3. but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i. The maximum PWM resolution (bits) for a given PWM frequency is given by the following formula. This is not the PORTC I/O data latch. Up to 10-bit resolution is available. concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler. FIGURE 8-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L 8.

3. 4. read as ‘0’. BOR Value on all other Resets 0Bh. COMPARE AND TIMER1 Name Bit 7 GIE PSPIF(1) — PSPIE(1) — Bit 6 PEIE ADIF — ADIE — Bit 5 TMR0IE RCIF — RCIE — Bit 4 INTE TXIF — TXIE — Bit 3 RBIE SSPIF — SSPIE — Bit 2 TMR0IF CCP1IF — — Bit 1 INTF TMR2IF — — Bit 0 RBIF Value on: POR.3 kHz 1 0x1Fh 7 208. 2. 4.= unimplemented. 18Bh 0Ch 0Dh 8Ch 8Dh 87h 0Eh 0Fh 10h 15h 16h 17h 1Bh 1Ch 1Dh Legend: Note 1: PIR1 PIR2 PIE1 PIE2 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 CCP2IF ---. DS39582B-page 68  2003 Microchip Technology Inc. 5.8Bh. .---0 CCP2IE ---. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. always maintain these bits clear.88 kHz 4 0xFFh 10 19. Make the CCP1 pin an output by clearing the TRISC<2> bit.3 kHz 1 0x17h 5. 3.53 kHz 1 0xFFh 10 78.---0 ---.---0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PORTC Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — — Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) — — CCP1X CCP1Y Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) — — CCP2X CCP2Y T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 x = unknown.---0 ---. . Configure the CCP1 module for PWM operation. INTCON 10Bh. Set the PWM period by writing to the PR2 register. Shaded cells are not used by Capture and Timer1.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. The PSP is not implemented on 28-pin devices. 16) PR2 Value Maximum Resolution (bits) TABLE 8-4: Address REGISTERS ASSOCIATED WITH CAPTURE.12kHz 1 0x3Fh 8 156. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz 1.PIC16F87XA 8. u = unchanged.22 kHz 16 0xFFh 10 4.5 PWM Frequency Timer Prescaler (1.

PIC16F87XA TABLE 8-5: Address REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 GIE PSPIF(1) — PSPIE(1) — Bit 6 PEIE ADIF — ADIE — Bit 5 TMR0IE RCIF — RCIE — Bit 4 INTE TXIF — TXIE — Bit 3 RBIE SSPIF — SSPIE — Bit 2 TMR0IF CCP1IF — CCP1IE — Bit 1 INTF TMR2IF — TMR2IE — Bit 0 RBIF Value on: POR.8Bh. INTCON 10Bh. .---0 ---. read as ‘0’. Bits PSPIE and PSPIF are reserved on 28-pin devices. BOR Value on all other Resets 0Bh. always maintain these bits clear. DS39582B-page 69 .---0 TMR1IE 0000 0000 0000 0000 CCP2IE ---.  2003 Microchip Technology Inc. Shaded cells are not used by PWM and Timer2. u = unchanged.---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PORTC Data Direction Register Timer2 Module’s Register Timer2 Module’s Period Register — Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) — — CCP1X CCP1Y Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) — — CCP2X CCP2Y TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 x = unknown.---0 ---.= unimplemented. 18Bh 0Ch 0Dh 8Ch 8Dh 87h 11h 92h 12h 15h 16h 17h 1Bh 1Ch 1Dh Legend: Note 1: PIR1 PIR2 PIE1 PIE2 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 CCP2IF ---.

.PIC16F87XA NOTES: DS39582B-page 70  2003 Microchip Technology Inc.

16. To accomplish communication. are performed on the TRISC register while the SS pin is high. typically three pins are used: • Serial Data Out (SDO) – RC5/SDO • Serial Data In (SDI) – RC4/SDI/SDA • Serial Clock (SCK) – RC3/SCK/SCL Additionally. display drivers. Additional details are provided under the individual sections.3 “PORTC and the TRISC Register” for information on PORTC).1 The Master Synchronous Serial Port (MSSP) module is a serial interface. etc. this will cause the TRISC<5> bit to be set. When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100). the state of the SS pin can affect the state read back from the TRISC<5> bit. a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) – RA5/AN4/SS/C2OUT Figure 9-1 shows the block diagram of the MSSP module when operating in SPI mode.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. These peripheral devices may be serial EEPROMs. ( ) Edge Select RC3/SCK/SCL Prescaler TOSC 4.Full Master mode .Slave mode (with general address call) The I2C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode SSPSR reg RC4/SDI/SDA bit0 Shift Clock RC5/SDO Peripheral OE SS Control Enable RA5/AN4/ SS/C2OUT Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 TMR2 Output 2 2 9. depending on whether the MSSP module is operated in SPI or I2C mode. If Read-Modify-Write instructions. shift registers. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) . The Peripheral OE signal from the SSP module in PORTC controls the state that is read back from the TRISC<5> bit (see Section 4. useful for communicating with other peripheral or microcontroller devices. All four modes of SPI are supported. These include a status register (SSPSTAT) and two control registers (SSPCON and SSPCON2).0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview FIGURE 9-1: MSSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read SSPBUF reg Write 9.PIC16F87XA 9. 64 Data to TX/RX in SSPSR TRIS bit Note: 9. thus disabling the SDO output. A/D converters. such as BSF.2 Control Registers The MSSP module has three associated registers. The use of these registers and their individual configuration bits differ significantly. DS39582B-page 71 .  2003 Microchip Technology Inc.

the SSPBUF is not doublebuffered. D/A: Data/Address bit Used in I2C mode only. When SSPSR receives a complete byte. These are: • MSSP Control Register (SSPCON) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON and SSPSTAT are the control and status registers in SPI mode operation. SSPSR is the shift register used for shifting data in or out.PIC16F87XA 9. P: Stop bit Used in I2C mode only. BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete. SSPEN is cleared.1 REGISTERS The MSSP module has four registers for SPI mode operation.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. SSPBUF is the buffer register to which data bytes are written to or read from. The lower six bits of the SSPSTAT are read-only. SSPSR and SSPBUF together create a double-buffered receiver. SSPBUF is empty Legend: R = Readable bit . The upper two bits of the SSPSTAT are read/write. REGISTER 9-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) (ADDRESS 94h) R/W-0 SMP bit 7 R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. During transmission. . UA: Update Address bit Used in I2C mode only.3. This bit is cleared when the MSSP module is disabled. In receive operations. CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>). The SSPCON register is readable and writable. S: Start bit Used in I2C mode only. R/W: Read/Write bit information Used in I2C mode only. SSPBUF is full 0 = Receive not complete. A write to SSPBUF will write to both SSPBUF and SSPSR. it is transferred to SSPBUF and the SSPIF interrupt is set. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39582B-page 72  2003 Microchip Technology Inc.

SS can be used as I/O pin.PIC16F87XA REGISTER 9-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) (ADDRESS 14h) R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word. clock = FOSC/16 0000 = SPI Master mode. bit 4 bit 3-0 Legend: R = Readable bit . even if only transmitting data. SDI. The user must read the SSPBUF. (Must be cleared in software. clock = FOSC/64 0001 = SPI Master mode. (Must be cleared in software. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. bit 6 bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK. clock = SCK pin. CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode. Overflow can only occur in Slave mode. and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled. these pins must be properly configured as input or output. 0100 = SPI Slave mode.) 0 = No collision SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.) 0 = No overflow Note: In Master mode. 0011 = SPI Master mode. the data in SSPSR is lost. In case of overflow. clock = TMR2 output/2 0010 = SPI Master mode. SS pin control enabled. clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. SDO. the overflow bit is not set. clock = SCK pin. SS pin control disabled. DS39582B-page 73 . since each new reception (and transmission) is initiated by writing to the SSPBUF register. to avoid setting overflow.

SSPIF.No . BF (SSPSTAT<0>). If the interrupt method is not going to be used. the BF bit is cleared. the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF.Save in user RAM. W RXDATA TXDATA. will be set. if data is meaningful . Additionally. The SSPSR shifts the data in and out of the device. W SSPBUF DS39582B-page 74  2003 Microchip Technology Inc.PIC16F87XA 9. and the interrupt flag bit. indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. several options need to be specified. the MSSP Status register (SSPSTAT) indicates the various status conditions. These control bits allow the following to be specified: • • • • Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). Buffer Full bit. BF LOOP SSPBUF. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit. the MSSP interrupt is used to determine when the transmission/reception has completed. MSb first. then software polling can be done to ensure that a write collision does not occur. Example 9-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. WCOL (SSPCON<7>). The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. the Buffer Full detect bit. This data may be irrelevant if the SPI is only a transmitter.Has data been received(transmit complete)? .WREG reg = contents of SSPBUF . This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>).2 OPERATION When initializing the SPI. Once the eight bits of data have been received. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. that byte is moved to the SSPBUF register.3. When the application software is expecting to receive valid data. BF (SSPSTAT<0>). are set.New data to xmit SSPSTAT. . Then.W reg = contents of TXDATA . Generally. EXAMPLE 9-1: LOOP BTFSS BRA MOVF MOVWF MOVF MOVWF LOADING THE SSPBUF (SSPSR) REGISTER . The SSPBUF must be read and/or written.

then both controllers would send and receive data at the same time. To reset or reconfigure SPI mode. clear the SSPEN bit. SCK and SS pins as serial port pins. Whether the data is meaningful (or dummy data) depends on the application software. SSPEN (SSPCON<5>). This configures the SDI. This leads to three scenarios for data transmission: • Master sends data – Slave sends dummy data • Master sends data – Slave sends data • Master sends dummy data – Slave sends data FIGURE 9-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SDO SDI SPI Slave SSPM3:SSPM0 = 010xb Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb SDI SDO Shift Register (SSPSR) MSb LSb SCK PROCESSOR 1 Serial Clock SCK PROCESSOR 2  2003 Microchip Technology Inc.PIC16F87XA 9. SSP Enable bit.3. must be set. DS39582B-page 75 . Figure 9-2 shows a typical connection between two microcontrollers. SDO. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. For the pins to behave as the serial port function. some must have their data direction bits (in the TRIS register) appropriately programmed.4 TYPICAL CONNECTION To enable the serial port. That is: • SDI is automatically controlled by the SPI module • SDO must have TRISC<5> bit cleared • SCK (Master mode) must have TRISC<3> bit cleared • SCK (Slave mode) must have TRISC<3> bit set • SS must have TRISC<4> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.3. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Both processors should be programmed to the same Clock Polarity (CKP). re-initialize the SSPCON registers and then set the SSPEN bit.3 ENABLING SPI I/O 9.

The master determines when the slave (Processor 2.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. FIGURE 9-3: Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF SPI MODE WAVEFORM (MASTER MODE) 4 Clock Modes bit 7 bit 7 bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 bit 7 bit 0 bit 7 bit 0 Next Q4 Cycle after Q2 DS39582B-page 76  2003 Microchip Technology Inc. In Master mode. This could be useful in receiver applications as a “Line Activity Monitor” mode. it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). The time when the SSPBUF is loaded with the received data is shown. the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • FOSC/4 (or TCY) FOSC/16 (or 4 • TCY) FOSC/64 (or 16 • TCY) Timer2 output/2 This allows a maximum data rate (at 40 MHz) of 10. The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. the data is transmitted/received as soon as the SSPBUF register is written to. This then. Figure 9-2) is to broadcast data by the software protocol.PIC16F87XA 9. Figure 9-3 shows the waveforms for Master mode. the SDO output could be disabled (programmed as an input). the SDO data is valid before there is a clock edge on SCK. where the MSB is transmitted first.3. Figure 9-5 and Figure 9-6. . would give waveforms for SPI communication as shown in Figure 9-3. As each byte is received.00 Mbps. In Master mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON<4>). The change of the input sample is shown based on the state of the SMP bit. When the CKE bit is set. If the SPI is only going to receive.

When the SS pin is low.3. the data is transmitted and received as the external clock pulses appear on SCK. the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. The SPI must be in Slave mode with SS pin control enabled (SSPCON<3:0> = 04h). the slave can transmit/receive data. the SPI module will reset if the SS pin is set to VDD.6 SLAVE MODE In Slave mode. While in Sleep mode.PIC16F87XA 9. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. then the SS pin control must be enabled. External pull-up/pull-down resistors may be desirable. the SDO pin can be configured as an input. the SS pin goes high. To emulate two-wire communication. While in Slave mode.3. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100).7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode. When the last bit is latched. the SSPIF interrupt flag bit is set. the bit counter is forced to ‘0’. DS39582B-page 77 . 2: If the SPI is used in Slave Mode with CKE set. the SDO pin can be connected to the SDI pin. transmission and reception are enabled and the SDO pin is driven. The data latch must be high. This external clock must meet the minimum high and low times as specified in the electrical specifications. This disables transmissions from the SDO. When FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit 0 bit 7 bit 7 Next Q4 Cycle after Q2  2003 Microchip Technology Inc. When the SPI needs to operate as a receiver. depending on the application. When the SPI module resets. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. the device will wake-up from Sleep. 9. the external clock is supplied by the external clock source on the SCK pin. When a byte is received. The pin must not be driven low for the SS pin to function as an input.

PIC16F87XA FIGURE 9-5: SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF Next Q4 Cycle after Q2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) bit 7 bit 0 FIGURE 9-6: SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 Next Q4 Cycle after Q2 DS39582B-page 78  2003 Microchip Technology Inc. .

1 1. After the device returns to normal mode. TABLE 9-2: Name INTCON PIR1 PIE1 TRISC SSPBUF SSPCON TRISA SSPSTAT REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 GIE/ GIEH Bit 6 PEIE/ GIEL ADIF ADIE Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF Bit 1 INT0IF Bit 0 RBIF Value on POR. When all 8 bits have been received.3.3. Note 1: The PSPIF. the MSSP interrupt flag bit will be set and if enabled.  2003 Microchip Technology Inc. 0 1.3.10 BUS MODE COMPATIBILITY In Master mode. the module will continue to transmit/ receive data. . Table 9-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. PSPIE and PSPIP bits are reserved on 28-pin devices. always maintain these bits clear.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. In Slave mode.8 SLEEP OPERATION 9. There is also a SMP bit which controls when the data is sampled. read as ‘0’. u = unchanged. Shaded cells are not used by the MSSP in SPI mode. TABLE 9-1: SPI BUS MODES Control Bits State CKP 0 0 1 1 CKE 1 0 1 0 Standard SPI Mode Terminology 0.PIC16F87XA 9. 1 9. 0 0. BOR Value on all other Resets TMR0IE INT0IE RCIF RCIE TXIF TXIE 0000 000x 0000 000u PSPIF(1) PSPIE(1) CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 UA BF 0000 0000 0000 0000 PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register WCOL — SMP SSPOV SSPEN CKE D/A CKP P SSPM3 S SSPM2 R/W PORTA Data Direction Register Legend: x = unknown. will wake the device from Sleep. DS39582B-page 79 .= unimplemented.

SSPSR and SSPBUF together create a double-buffered receiver. The MSSP module implements the standard mode specifications. These are: • • • • MSSP Control Register (SSPCON) MSSP Control Register 2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible • MSSP Address Register (SSPADD) SSPCON. Two pins are used for data transfer: • Serial clock (SCL) – RC3/SCK/SCL • Serial data (SDA) – RC4/SDI/SDA The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. SSPADD reg Start and Stop bit Detect Set. Reset S.4 I2C Mode 9. LSb FIGURE 9-7: MSSP BLOCK DIAGRAM (I2C MODE) Internal Data Bus Read Write RC3/SCK/SCL Shift Clock SSPBUF reg SSPSR reg RC4/SDI/ SDA MSb Match Detect Addr Match In receive operations. When SSPSR receives a complete byte. SSPBUF is the buffer register to which data bytes are written to or read from. as well as 7-bit and 10-bit addressing. the SSPBUF is not doublebuffered. SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode.PIC16F87XA 9. The upper two bits of the SSPSTAT are read/write. The MSSP module has six registers for I2C operation.1 REGISTERS The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). it is transferred to SSPBUF and the SSPIF interrupt is set.4. the lower seven bits of SSPADD act as the baud rate generator reload value. . The lower six bits of the SSPSTAT are read-only. P bits (SSPSTAT reg) DS39582B-page 80  2003 Microchip Technology Inc. When the SSP is configured in Master mode. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPSR is the shift register used for shifting data in or out. During transmission. The SSPCON and SSPCON2 registers are readable and writable.

SSPBUF is empty In Receive mode: 1 = Data Transmit in progress (does not include the ACK and Stop bits). DS39582B-page 81 . RCEN or ACKEN will indicate if the MSSP is in Idle mode. Stop bit or not ACK bit. RSEN. PEN. SSPBUF is empty Legend: R = Readable bit . S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. UA: Update Address (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete. SSPBUF is full 0 = Data Transmit complete (does not include the ACK and Stop bits). R/W: Read/Write bit information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match.PIC16F87XA REGISTER 9-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h) R/W-0 SMP bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high-speed mode (400 kHz) CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs D/A: Data/Address bit In Master mode: Reserved. This bit is only valid from the address match to the next Start bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN. SSPBUF is full 0 = Receive not complete. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2003 Microchip Technology Inc. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.

. (Must be cleared in software. 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode.) In Master mode: Unused in this mode. (Used to ensure data setup time. SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. bit 6 bit 5 bit 4 bit 3-0 Legend: R = Readable bit . (Must be cleared in software. (Must be cleared in software.PIC16F87XA REGISTER 9-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) (ADDRESS 14h) R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started. SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables the serial port and configures these pins as I/O port pins Note: When enabled. clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. the SDA and SCL pins must be properly configured as input or output. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DS39582B-page 82  2003 Microchip Technology Inc. 10-bit address 0110 = I2C Slave mode.) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. 7-bit address Note: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch). SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode.) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word. 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode.

DS39582B-page 83 .  2003 Microchip Technology Inc. Automatically cleared by hardware. 0 = Acknowledge sequence Idle RCEN: Receive Enable bit (Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle PEN: Stop Condition Enable bit (Master mode only) 1 = Initiate Stop condition on SDA and SCL pins.PIC16F87XA REGISTER 9-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) (ADDRESS 91h) R/W-0 GCEN bit 7 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: bit 4 Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. R/W-0 ACKSTAT R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit 0 bit 6 bit 5 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. RCEN.n = Value at POR Note: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. RSEN. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is enabled for slave transmit only (PIC16F87X compatibility) Legend: R = Readable bit . Automatically cleared by hardware. SEN: If the I2C module is not in the Idle mode. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 3 bit 2 bit 1 bit 0 For bits ACKEN. PEN. 0 = Repeated Start condition Idle SEN: Start Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle RSEN: Repeated Start Condition Enabled bit (Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

SSPEN (SSPCON<5>). The I 2C Slave mode hardware will always generate an interrupt on an address match. the 8 bits are shifted into the SSPSR register.4. 3. The high and low times of the I2C specification. but bit SSPIF (PIR1<3>) is set. Following the Start condition. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. it waits for a Start condition to occur. 5. and the BF and SSPOV bits are clear. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: • • • • I2C Master mode. provided these pins are programmed to inputs by setting the appropriate TRISC bits. MSSP Interrupt Flag bit.3 SLAVE MODE In Slave mode. . BF and bit UA (SSPSTAT<1>) are set). forces the SCL and SDA pins to be open-drain. was set before the transfer was received. The address is compared on the falling edge of the eighth clock (SCL) pulse. 7. The MSSP module will override the input state with the output data when required (slave-transmitter). Through the mode select bits. 3. For a 10-bit address. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: • The buffer full bit. with the SSPEN bit set. this will clear bit UA. is set. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. 4. Receive Repeated Start condition. • The overflow bit. The SCL clock input must have a minimum high and low for proper operation. where ‘A9’ and ‘A8’ are the two MSbs of the address. pull-up resistors must be provided externally to the SCL and SDA pins. the SSPSR register value is not loaded into the SSPBUF. BF. the first byte would equal ‘11110 A9 A8 0’.4. Receive first (high) byte of address (bits SSPIF. To ensure proper operation of the module. The Buffer Full bit. The SSPCON register allows control of the I 2C operation. SSPIF (PIR1<3>).3. the user can also choose to interrupt on Start and Stop bits When an address is matched. The SSPSR register value is loaded into the SSPBUF register. Update the SSPADD register with the first (high) byte of address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. BF and UA are set). The BF bit is cleared by reading the SSPBUF register. The sequence of events for 10-bit address is as follows. SSPOV (SSPCON<6>). the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). 2. while bit SSPOV is cleared through software. are shown in timing parameter #100 and parameter #101. Selection of any I 2C mode. 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. two address bytes need to be received by the slave.4. 2. is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. All incoming bits are sampled with the rising edge of the clock (SCL) line.1 Addressing The MSSP module functions are enabled by setting MSSP Enable bit. If the addresses match. An ACK pulse is generated. Receive second (low) byte of address (bits SSPIF. was set before the transfer was received. 4.2 OPERATION 9. 8. the following events occur: 1. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. In this case. Receive first (high) byte of address (bits SSPIF and BF are set). clock = OSC/4 (SSPADD + 1) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled • I 2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled • I 2C Firmware Controlled Master mode. DS39582B-page 84  2003 Microchip Technology Inc. slave is Idle Once the MSSP module has been enabled. with steps 7 through 9 for the slave-transmitter: 1. 9. BF (SSPSTAT<0>). as well as the requirement of the MSSP module. or the data transfer after an address match is received. If match releases SCL line.PIC16F87XA 9. In 10-bit Address mode. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 6.

The SSPIF bit is set on the falling edge of the ninth clock pulse. In this case. If the SDA line was low (ACK). The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section 9. Again. which also loads the SSPSR register. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse.PIC16F87XA 9.3 Transmission When the R/W bit of the address byte is clear and an address match occurs. An MSSP interrupt is generated for each data transfer byte. The SSPSTAT register is used to determine the status of the byte. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>).4. If the SDA line is high (not ACK). then the data transfer is complete.4.4 “Clock Stretching” for more detail). the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. An MSSP interrupt is generated for each data transfer byte. then the No Acknowledge (ACK) pulse is given. Flag bit SSPIF (PIR1<3>) must be cleared in software. the next transmit data must be loaded into the SSPBUF register. the R/W bit of the SSPSTAT register is cleared. The clock must be released by setting bit CKP (SSPCON<4>). DS39582B-page 85 . RC3/SCK/SCL will be held low (clock stretch) following each data transfer. the R/W bit of the SSPSTAT register is set. When the address byte overflow condition exists. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. By stretching the clock.4.4 “Clock Stretching” for more detail. the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the Start bit. The received address is loaded into the SSPBUF register. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK).3.2 Reception 9. pin RC3/SCK/SCL must be enabled by setting bit CKP. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 9-9). when the ACK is latched by the slave.  2003 Microchip Technology Inc. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. If SEN is enabled (SSPCON<0> = 1).4. The transmit data must be loaded into the SSPBUF register.3. When the R/W bit of the incoming address byte is set and an address match occurs. See Section 9.

FIGURE 9-8: DS39582B-page 86 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 R/W = 0 Receiving Data ACK Receiving Data D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent. CKP (CKP does not reset to ‘0’ when SEN = 0) . PIC16F87XA SDA A7 A6 SCL S 1 2 SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION. 7-BIT ADDRESS)  2003 Microchip Technology Inc.

FIGURE 9-9:  2003 Microchip Technology Inc. 7-BIT ADDRESS) CKP PIC16F87XA DS39582B-page 87 . R/W = 1 Transmitting Data ACK D1 D0 D4 D3 D5 D7 D6 ACK D5 D4 D3 D2 D7 D6 D2 A1 Transmitting Data D1 D0 ACK A4 A2 A3 4 SCL held low while CPU responds to SSPIF 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software From SSPIF ISR SSPBUF is written in software SSPBUF is written in software Cleared in software From SSPIF ISR CKP is set in software CKP is set in software Receiving Address SDA A7 A6 A5 SCL 1 2 3 S Data in sampled SSPIF (PIR1<3>) BF (SSPSTAT<0>) I2C SLAVE MODE TIMING (TRANSMISSION.

CKP (CKP does not reset to ‘0’ when SEN = 0) . Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address Receive First Byte of Address PIC16F87XA SDA 1 1 1 1 SCL S 1 2 3 4 SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR SSPOV (SSPCON<6>) UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION. 10-BIT ADDRESS)  2003 Microchip Technology Inc. ACK is not sent.FIGURE 9-10: DS39582B-page 88 Clock is held low until update of SSPADD has taken place R/W = 0 ACK A7 D3 D2 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 A0 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte D1 D0 ACK Clock is held low until update of SSPADD has taken place 0 A9 A8 5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full.

10-BIT ADDRESS) CKP (SSPCON<4>) PIC16F87XA DS39582B-page 89 . Clock is held low until update of SSPADD has taken place R/W = 0 Receive Second Byte of Address Receive First Byte of Address ACK 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 1 0 A9 A8 Clock is held low until update of SSPADD has taken place 4 Sr 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address CKP is set in software CKP is automatically cleared in hardware holding SCL low Receive First Byte of Address SDA 1 1 1 SCL S 1 2 3 SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated I2C SLAVE MODE TIMING (TRANSMISSION.FIGURE 9-11: Bus master terminates transfer Clock is held low until CKP is set to ‘1’ R/W=1 ACK Transmitting Data Byte D7 D6 D5 D4 D3 D2 D1 D0 ACK  2003 Microchip Technology Inc.

only occurs during a data sequence. the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 9-11). The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address.4. Clock stretching. the CKP bit in the SSPCON register is automatically cleared. The CKP bit must be set in the user’s ISR before reception is allowed to continue.4. The release of the clock line occurs upon updating SSPADD.4. if the BF bit is set. if the BF bit is clear.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode. 2: The CKP bit can be set in software regardless of the state of the BF bit.4. 9.4. the CKP bit will not be cleared and clock stretching will not occur.4 CLOCK STRETCHING 9. 9. clock stretching is controlled during the first two address sequences by the state of the UA bit. with the R/W bit cleared to ‘0’. The first two addresses are followed by a third address sequence. The CKP bit being cleared to ‘0’ will assert the SCL line low. then the CKP bit will still NOT be asserted low. forcing the SCL output to be held low. Clock stretching will occur on each data receive sequence as described in 7-bit mode. just as it is in 10-bit Slave Receive mode.1 Clock Stretching for 7-bit Slave Receive Mode (SEN = 1) In 7-bit Slave Receive mode. 2: The CKP bit can be set in software regardless of the state of the BF bit. Note 1: If the user loads the contents of SSPBUF. not an address sequence. This occurs regardless of the state of the SEN bit.4.PIC16F87XA 9.4. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. clock stretching automatically takes place but CKP is not cleared. During this time.3 Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. 9. on the falling edge of the ninth clock at the end of the ACK sequence. By holding the SCL line low. . thus clearing the BF bit. which contains the high order bits of the 10-bit address and the R/W bit set to ‘1’. the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. Clock Stretching for 7-bit Slave Transmit Mode 7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock. DS39582B-page 90  2003 Microchip Technology Inc. By holding the SCL line low. during the address sequence.4 Clock Stretching for 10-bit Slave Transmit Mode In 10-bit Slave Transmit mode. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition. the CKP bit will not be cleared and clock stretching will not occur. Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock. clock stretching is initiated. the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 9-9). Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. the UA bit is not set. The user’s ISR must set the CKP bit before transmission is allowed to continue. This will prevent buffer overruns from occurring (see Figure 9-13).4. on the basis of the state of the BF bit. After the third address sequence is performed. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by reading the SSPBUF register before that time. if the UA bit is set after the ninth clock. setting the BF bit before the falling edge of the ninth clock.

The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. FIGURE 9-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL Master device asserts clock Master device deasserts clock WR SSPCON CKP  2003 Microchip Technology Inc. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 9-12). the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line.PIC16F87XA 9. setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore. DS39582B-page 91 .4.4. the SCL output is forced to ‘0’. however.5 Clock Synchronization and the CKP Bit When the CKP bit is cleared.

CKP will not be reset to ‘0’ and no clock stretching will occur .FIGURE 9-13: DS39582B-page 92 Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is held low until CKP is set to ‘1’ ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 R/W = 0 Receiving Data Clock is not held low because ACK = 1 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. 7-BIT ADDRESS)  2003 Microchip Technology Inc. ACK is not sent. CKP is reset to ‘0’ and clock stretching occurs I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION. PIC16F87XA SDA A7 A6 SCL S 1 2 SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) CKP CKP written to ‘1’ in software BF is set after falling edge of the 9th clock. If BF is cleared prior to the falling edge of the 9th clock.

10-BIT ADDRESS) CKP PIC16F87XA DS39582B-page 93 . 6 1 2 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Bus master terminates transfer Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. SDA 1 1 1 1 0 SCL S 1 2 3 4 5 SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR SSPOV (SSPCON<6>) UA (SSPSTAT<1>) UA is set indicating that SSPADD needs to be updated I2C SLAVE MODE TIMING SEN = 1 (RECEPTION.FIGURE 9-14: Clock is held low until update of SSPADD has taken place Clock is held low until CKP is set to ‘1’ Receive Data Byte D1 D0 D7 D6 D5 D4 ACK D3 D2 R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 Receive Second Byte of Address Receive Data Byte Clock is held low until update of SSPADD has taken place Clock is not held low because ACK = 1 ACK D1 D0 Receive First Byte of Address A9 A8  2003 Microchip Technology Inc. and UA will remain set. Cleared by hardware when SSPADD is updated with high byte of address after falling edge of ninth clock CKP written to ‘1’ in software Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA. Cleared by hardware when SSPADD is updated with low byte of address after falling edge of ninth clock UA is set indicating that SSPADD needs to be updated Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. ACK is not sent.

The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7> set). the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit). while the slave is configured in 10-bit Address mode.4. When the interrupt is serviced. the SSPIF interrupt flag bit is set. the source for the interrupt can be checked by reading the contents of the SSPBUF. If the general call address is sampled when the GCEN bit is set. in theory.PIC16F87XA 9.5 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. R/W = 0 ACK D7 Receiving Data D6 D5 D4 D3 D2 D1 D0 ACK SDA SCL S SSPIF BF (SSPSTAT<0>) 1 General Call Address 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Cleared in software SSPBUF is read SSPOV (SSPCON<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS39582B-page 94  2003 Microchip Technology Inc. all devices should. If the general call address matches. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. 8 bits are shifted into the SSPSR and the address is compared against the SSPADD. The value can be used to determine if the address was device specific or a general call address. After ACK. respond with an Acknowledge. the SSPADD is required to be updated for the second half of the address to match and the UA bit is set (SSPSTAT<1>). set interrupt. The exception is the general call address which can address all devices. the SSPSR is transferred to the SSPBUF. the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 9-15). Following a Start bit detect. It is also compared to the general call address and fixed in hardware. When this address is used. In 10-bit mode. then the second half of the address is not necessary. It consists of all ‘0’s with R/W = 0. FIGURE 9-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to general call address. .

WCOL (SSPSTAT) Set SSPIF. user code conducts all I 2C bus operations based on Start and Stop bit conditions. Once Master mode is enabled. S. with both the S and P bits clear. BCLIF Reset ACKSTAT. 4. Acknowledge Generate . In Firmware Controlled Master mode. the user has six options. 1. Configure the I2C port to receive data. Assert a Repeated Start condition on SDA and SCL.PIC16F87XA 9. 6. 3. The MSSP module. Generate an Acknowledge condition at the end of a received byte of data. does not allow queueing of events. Stop bit. 5. initiating transmission of data/address. For instance. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Clock Cntl Start bit. SSPIF. 2. indicating that a write to the SSPBUF did not occur. when configured in I2C Master mode.6 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. the SCL and SDA lines are manipulated by the MSSP hardware. the SSPBUF will not be written to and the WCOL bit will be set. In Master mode. P. In this case. PEN (SSPCON2)  2003 Microchip Technology Inc. to be set (SSP interrupt if enabled): • • • • • Start condition Stop condition Data transfer byte transmitted/received Acknowledge transmit Repeated Start FIGURE 9-16: MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal Data Bus Read SSPBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source) DS39582B-page 95 Shift Clock SSPSR Receive Enable MSb LSb SSPM3:SSPM0 SSPADD<6:0> SDA SDA In SCL SCL In Bus Collision Start bit Detect Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV Set/Reset. Control of the I 2C bus may be taken when the P bit is set or the bus is Idle. The following events will cause SSP Interrupt Flag bit. Write to the SSPBUF register.4. the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. Generate a Stop condition on SDA and SCL. Assert a Start condition on SDA and SCL.

SEN (SSPCON2<0>). Data is shifted out the SDA pin until all 8 bits are transmitted. . 3. The MSSP module will wait the required Start time before any other operation takes place. an Acknowledge bit is received.7 “Baud Rate Generator” for more detail. 11. the I2C bus will not be released. The user generates a Stop condition by setting the Stop Enable bit. Since the Repeated Start condition is also the beginning of the next serial transfer. In this case. In Master Receive mode. 2. PEN (SSPCON2<2>).1 I2C Master Mode Operation A typical transmit sequence would go as follows: 1. serial data is output through SDA while SCL outputs the serial clock. 12. 7. A transfer is ended with a Stop condition or with a Repeated Start condition. 10. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). See Section 9. 4. After each byte is transmitted. Thus. Serial data is transmitted 8 bits at a time. 400 kHz or 1 MHz I2C operation. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. Interrupt is generated once the Stop condition is complete. the R/W bit will be logic ‘1’.4. 6. an Acknowledge bit is transmitted. DS39582B-page 96  2003 Microchip Technology Inc. SSPIF is set.4. The baud rate generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz. the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit.PIC16F87XA 9. In this case.6. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). The master device generates all of the serial clock pulses and the Start and Stop conditions. In Master Transmitter mode. The user generates a Start condition by setting the Start Enable bit. After each byte is received. 5. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. the R/W bit will be logic ‘0’. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. Address is shifted out the SDA pin until all 8 bits are transmitted. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. Serial data is received 8 bits at a time. 8. Serial data is received via SDA while SCL outputs the serial clock. Start and Stop conditions indicate the beginning and end of transmission. 9. The user loads the SSPBUF with eight bits of data. The user loads the SSPBUF with the slave address to transmit.

PIC16F87XA
9.4.7
2

BAUD RATE GENERATOR

In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 9-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.

Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. Table 9-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD.

FIGURE 9-17:

BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0 SSPADD<6:0>

SSPM3:SSPM0 SCL

Reload Control CLKO

Reload

BRG Down Counter

FOSC/4

TABLE 9-3:
FCY

I2C CLOCK RATE W/BRG
FCY*2 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz I2C BRG Value 19h 20h 3Fh 0Ah 0Dh 28h 03h 0Ah 00h FSCL (2 Rollovers of BRG) 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100 kHz 1 MHz(1)

10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz Note 1: I2C

The interface does not conform to the 400 kHz specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application.

 2003 Microchip Technology Inc.

DS39582B-page 97

PIC16F87XA
9.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure 9-17).

FIGURE 9-18:
SDA

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DX DX-1 SCL allowed to transition high

SCL deasserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off)

03h

02h

SCL is sampled high, reload takes place and BRG starts its count BRG Reload

DS39582B-page 98

 2003 Microchip Technology Inc.

PIC16F87XA
9.4.8 I2C MASTER MODE START CONDITION TIMING 9.4.8.1 WCOL Status Flag
To initiate a Start condition, the user sets the Start condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag (BCLIF) is set, the Start condition is aborted and the I2C module is reset into its Idle state. If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete.

FIGURE 9-19:

FIRST START BIT TIMING
Set S bit (SSPSTAT<3>) SDA = 1, SCL = 1 At completion of Start bit, hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st Bit SDA TBRG 2nd Bit

Write to SEN bit occurs here

TBRG

SCL S

TBRG

 2003 Microchip Technology Inc.

DS39582B-page 99

4. When the Baud Rate Generator times out. the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). hardware clears RSEN bit and sets SSPIF TBRG 1st Bit SDA Falling edge of ninth clock. the S bit (SSPSTAT<3>) will be set. When SCL is sampled high. Note: Because queueing of events is not allowed. SCL = 1 At completion of Start bit. if SDA is sampled high. 9. leaving the SDA pin held low. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low to high. After the first eight bits are transmitted and an ACK is received. When the SCL pin is sampled low. When the RSEN bit is set. FIGURE 9-20: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. • SCL goes low before SDA is asserted low. end of Xmit Write to SSPBUF occurs here TBRG TBRG Sr = Repeated Start TBRG TBRG SCL DS39582B-page 100  2003 Microchip Technology Inc.9. Note 1: If RSEN is programmed while any other event is in progress. As soon as a Start condition is detected on the SDA and SCL pins. the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG).4. Following this. the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded. the SCL pin will be deasserted (brought high). the user may write the SSPBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. SDA and SCL must be sampled high for one TBRG.PIC16F87XA 9. . This may indicate that another master is attempting to transmit a data ‘1’. the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.1 WCOL Status Flag If the user writes the SSPBUF when a Repeated Start sequence is in progress. The SSPIF bit will not be set until the Baud Rate Generator has timed out.9 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. Immediately following the SSPIF bit getting set. it will not take effect. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. SDA = 1. the SCL pin is asserted low. SCL (no change) SDA = 1.

SCL is held low for one Baud Rate Generator rollover count (TBRG). The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place. ACKEN (SSPCON2<4>).11.4. the bit is set.. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock.e. If not.. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded.4. the Acknowledge Status bit.4.10.1 BF Status Flag In receive operation. It is cleared when the SSPBUF register is read. Data should be valid before SCL is released high (see data setup time specification.10. 9. the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF. parameter #106). the BF flag bit is automatically cleared. allowing the slave to respond with an Acknowledge. and allow the Baud Rate Generator to begin counting and start the next transmission.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i. ACKSTAT. parameter #107). In Transmit mode.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i. the BF flag bit is set.11. 9. a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register.4. DS39582B-page 101 .2 SSPOV Status Flag In receive operation. if an address match occurred or if data was received properly. the receive enable flag is automatically cleared. The MSSP is now in Idle state. RCEN (SSPCON2<3>). the master will sample the SDA pin to see if the address was recognized by a slave.  2003 Microchip Technology Inc. the state of the SCL pin changes (high to low/ low to high) and data is shifted into the SSPSR. the master will deassert the SDA pin.e.3 ACKSTAT Status Flag Transmission of a data byte. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting.4. awaiting the next command. After the ninth clock. After the falling edge of the eighth clock. the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. is cleared. holding SCL low. 9. After the write to the SSPBUF. holding SCL low and allowing SDA to float.PIC16F87XA 9. it is held that way for TBRG. WCOL must be cleared in software. the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does Not Acknowledge (ACK = 1). 9. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit. until all seven address bits and the R/W bit are completed. the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all eight bits are shifted out. the BF flag is cleared and the master releases SDA.1 BF Status Flag In Transmit mode. After the eighth bit is shifted out (the falling edge of the eighth clock). This action will set the Buffer Full flag bit. On the falling edge of the ninth clock. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification. When the SCL pin is released high. the contents of the SSPSR are loaded into the SSPBUF. SSPSR is still shifting in a data byte). each bit of address will be shifted out on the falling edge of SCL. leaving SCL low and SDA unchanged (Figure 9-21). the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). If the master receives an Acknowledge.4.4. the SSPIF is set. the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). SSPSR is still shifting out a data byte). On the falling edge of the eighth clock. BF. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time.4.11 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit. 9.11. A slave sends an Acknowledge when it has recognized its address (including a general call) or when the slave has properly received its data. the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception.10 I2C MASTER MODE TRANSMISSION 9. Following the falling edge of the ninth clock transmission of the address.10. The Baud Rate Generator begins counting and on each rollover. 9. When the buffer is read by the CPU.

Start transmit.FIGURE 9-21: DS39582B-page 102 Write SSPCON2<0> SEN = 1 Start condition begins From Slave. SEN cleared by hardware SSPBUF is written in software PEN PIC16F87XA I 2C MASTER MODE WAVEFORM (TRANSMISSION. R/W . 7 OR 10-BIT ADDRESS)  2003 Microchip Technology Inc. SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 ACKSTAT in SSPCON2 = 1 SSPIF Cleared in software Cleared in software service routine from SSP interrupt Cleared in software BF (SSPSTAT<0>) SSPBUF written SEN After Start condition. clear ACKSTAT bit SSPCON2<6> R/W = 0 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 Transmitting Data or Second Half of 10-bit Address D0 ACK SEN = 0 Transmit Address to Slave SDA A7 SSPBUF written with 7-bit address and R/W.

begin Start condition ACK from master SDA = ACKDT = 0 RCEN = 1. Receiving Data from Slave D7 D6 D5 D4 D3 D2 D1 ACK is not sent 4 5 1 2 3 4 5 1 2 3 4 6 8 6 7 8 9 7 9 5 6 7 8 9 Bus master terminates transfer P Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK Set SSPIF at end of receive Set SSPIF interrupt at end of receive Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software Cleared in software Cleared in software Set P bit (SSPSTAT<4>) and SSPIF Last bit is shifted into SSPSR and contents are unloaded into SSPBUF SSPOV is set because SSPBUF is still full Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) SEN = 0 Write to SSPBUF occurs here. SDA = ACKDT = 1 PEN bit = 1 written here  2003 Microchip Technology Inc.FIGURE 9-22: Write to SSPCON2<0> (SEN = 1). 7-BIT ADDRESS) ACKEN PIC16F87XA DS39582B-page 103 . start next receive RCEN cleared automatically D0 Receiving Data from Slave D0 ACK D7 D6 D5 D4 D3 D2 D1 ACK Write to SSPCON2<4> to start Acknowledge sequence. SDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN. start Acknowledge sequence. SCL = 1 while CPU responds to SSPIF Cleared in software BF (SSPSTAT<0>) SSPOV I 2C MASTER MODE WAVEFORM (RECEPTION. RCEN cleared start XMIT automatically ACK from Slave SDA Transmit Address to Slave R/W = 1 A7 A6 A5 A4 A3 A2 A1 ACK SCL S 1 2 3 SSPIF SDA = 0.

FIGURE 9-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here. the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. the Baud Rate Generator is reloaded and counts down to 0. the Baud Rate Generator counts for TBRG. If the user writes the SSPBUF when a Stop sequence is in progress. A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit.13. When this bit is set. At the end of a receive/ transmit. . then the ACKDT bit should be cleared. If the user wishes to generate an Acknowledge. DS39582B-page 104  2003 Microchip Technology Inc.PIC16F87XA 9. When the PEN bit is set. When the SDA line is sampled low. PEN (SSPCON2<2>). ACKEN (SSPCON2<4>).13 STOP CONDITION TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit. then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). the master will assert the SDA line low.1 WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress. 9. set PEN Falling edge of 9th clock SCL = 1 for TBRG. the SCL line is held low after the falling edge of the ninth clock. the ACKEN bit is automatically cleared. the SDA pin will be deasserted. The SCL pin is then pulled low.12.4. When the Baud Rate Generator times out.4. the PEN bit is cleared and the SSPIF bit is set (Figure 9-24). If not. followed by SDA = 1 for TBRG after SDA sampled high. the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later. the P bit (SSPSTAT<4>) is set. the baud rate generator is turned off and the MSSP module then goes into Idle mode (Figure 9-23). FIGURE 9-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2. the user should set the ACKDT bit before starting an Acknowledge sequence.12 ACKNOWLEDGE SEQUENCE TIMING 9. When the SDA pin is sampled high while SCL is high. ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared SCL 8 9 SSPIF Set SSPIF at the end of receive Cleared in software Set SSPIF at the end of Acknowledge sequence Cleared in software Note: TBRG = one Baud Rate Generator period.4. A TBRG later. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur).1 WCOL Status Flag 9. P bit (SSPSTAT<4>) is set. When the SCL pin is sampled high (clock arbitration). Following this. write to SSPCON2 ACKEN = 1.4.

with both the S and P bits clear. data doesn’t match what is driven by the master.14 SLEEP OPERATION 2 9. the I C module can receive addresses or data and when an address match or complete byte transfer occurs. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.16 MULTI-MASTER MODE In Multi-Master mode. DS39582B-page 105 . the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the master outputs address/data bits onto the SDA pin. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register or the bus is Idle and the S and P bits are cleared. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0. the user can resume communication by asserting a Start condition.PIC16F87XA 9. data should be stable. In Multi-Master mode. If a transmit was in progress when the bus collision occurred. then a bus collision has taken place. This check is performed in hardware with the result placed in the BCLIF bit. 9. The master will set the Bus Collision Interrupt Flag. the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. and reset the I2C port to its Idle state (Figure 9-25). arbitration takes place when the master outputs a ‘1’ on SDA by letting SDA float high and another master asserts a ‘0’. the SDA line must be monitored for arbitration to see if the signal level is at the expected output level. Bus collision has occurred. When the SCL pin floats high. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free. the transmission is halted. the BF flag is cleared. If a Start. the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. BCLIF.4. The Master will continue to monitor the SDA and SCL pins.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. Repeated Start. Stop or Acknowledge condition was in progress when the bus collision occurred. the user can resume communication by asserting a Start condition. the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. FIGURE 9-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. When the bus is busy. If a Stop condition occurs. enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition Multi-Master mode support is achieved by bus arbitration. the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. While SCL is high. SDA SCL Set bus collision interrupt (BCLIF) BCLIF  2003 Microchip Technology Inc. or the bus is Idle.4. In multi-master operation. Control of the I 2C bus may be taken when the P bit (SSPSTAT<4>) is set. BUS COLLISION AND BUS ARBITRATION 9. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free. wake the processor from Sleep (if the MSSP interrupt is enabled). the condition is aborted. MULTI -MASTER COMMUNICATION.4.17 While in Sleep mode.4.

BCLIF SSPIF SSPIF and BCLIF are cleared in software DS39582B-page 106  2003 Microchip Technology Inc. Note: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. however.4.PIC16F87XA 9. a ‘1’ is sampled on the SDA pin. one master will always assert SDA before the other. At the end of the BRG count. SCL = 1. Repeated Start or Stop conditions. SSPIF and BCLIF are cleared in software S SEN cleared automatically because of bus collision. If. the Baud Rate Generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high. SCL is sampled low before SDA is asserted low (Figure 9-27). a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. the SDA pin is asserted low at the end of the BRG count. SCL = 1 SEN SDA sampled low before Start condition. a bus collision does not occur. SDA SCL Set SEN. then all of the following occur: • the Start condition is aborted. Set BCLIF. both the SDA and the SCL pins are monitored. SCL = 1. the BRG is reset and the SDA line is asserted early (Figure 9-28). the SCL pin is asserted low. if the SCL pin is sampled as ‘0’. S bit and SSPIF set because SDA = 0. Set BCLIF. If the address is the same. or the SCL pin is already low. The Baud Rate Generator is then reloaded and counts down to 0 and during this time. FIGURE 9-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set.17. If the SDA pin is sampled low during this count.1 Bus Collision During a Start Condition During a Start condition. SSP module reset into Idle state. enable Start condition if SDA = 1. Therefore. The Start condition begins with the SDA and SCL pins deasserted. If the SDA pin is already low. • the BCLIF flag is set and • the MSSP module is reset to its Idle state (Figure 9-26). S bit and SSPIF set because SDA = 0. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. During a Start condition. When the SDA pin is sampled high. a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 9-26). . arbitration must be allowed to continue into the data portion.

SCL = 1 TBRG SDA TBRG SCL Set SEN.PIC16F87XA FIGURE 9-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0. bus collision occurs. DS39582B-page 107 . set SSPIF Interrupts cleared in software  2003 Microchip Technology Inc. SEN BCLIF Interrupt cleared in software S SSPIF ‘0’ ‘0’ ‘0’ ‘0’ FIGURE 9-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0. SCL = 1. TBRG Set SSPIF SCL S SCL pulled low after BRG time-out SEN Set SEN. Set BCLIF. bus collision occurs. SCL = 0 before BRG time-out. SCL = 1 Set S Less than TBRG SDA SDA pulled low by other master. enable Start sequence if SDA = 1. SCL = 1 SCL = 0 before SDA = 0. enable Start sequence if SDA = 1. Set BCLIF. SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0. Reset BRG and assert SDA.

If SDA is sampled high. If at the end of the BRG time-out. reloaded and begins counting. set BCLIF.e. When the user deasserts SDA and the pin is allowed to float high. At the end of the count.. SCL goes low before SDA is asserted low. Interrupt cleared in software RSEN S SSPIF ‘0’ DS39582B-page 108  2003 Microchip Technology Inc. If SCL goes from high to low before the BRG times out and SDA has not already been asserted. RSEN BCLIF Cleared in software S SSPIF ‘0’ ‘0’ FIGURE 9-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA. indicating that another master is attempting to transmit a data ‘1’. both SCL and SDA are still high. If SDA is low. a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. If SDA goes from high to low before the BRG times out. The SCL pin is then deasserted and when sampled high. If SDA = 0. another master is attempting to transmit a data ‘1’ during the Repeated Start condition (Figure 9-30).4. regardless of the status of the SCL pin. In this case. a bus collision has occurred (i. the SDA pin is driven low and the BRG is reloaded and begins counting. the SDA pin is sampled. the SCL pin is driven low and the Repeated Start condition is complete. the BRG is FIGURE 9-29: SDA BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SCL Sample SDA when SCL goes high. see Figure 9-29).17. set BCLIF and release SDA and SCL. a bus collision occurs. the BRG is loaded with SSPADD<6:0> and counts down to 0.PIC16F87XA 9. no bus collision occurs because no two masters can assert SDA at exactly the same time. Release SDA and SCL. .2 Bus Collision During a Repeated Start Condition During a Repeated Start condition. another master is attempting to transmit a data ‘0’.

DS39582B-page 109 . If SDA is sampled low. set BCLIF SDA SDA asserted low SCL PEN BCLIF P SSPIF ‘0’ ‘0’ FIGURE 9-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL goes low before SDA goes high. a bus collision occurs.17. This is another case of another master attempting to drive a data ‘0’ (Figure 9-32). When the pin is sampled high (clock arbitration).PIC16F87XA 9. SDA is sampled. After the SCL pin is deasserted.4. a bus collision has occurred. SCL is sampled low before SDA goes high. SDA is sampled low after the BRG has timed out. When SDA is sampled low. the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out. If the SCL pin is sampled low before SDA is allowed to float high. set BCLIF SCL PEN BCLIF P SSPIF ‘0’ ‘0’  2003 Microchip Technology Inc.3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: a) After the SDA pin has been deasserted and allowed to float high. The Stop condition begins with SDA asserted low. b) FIGURE 9-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG. the SCL pin is allowed to float. This is due to another master attempting to drive a data ‘0’ (Figure 9-31).

PIC16F87XA NOTES: DS39582B-page 110  2003 Microchip Technology Inc. .

etc. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2003 Microchip Technology Inc.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices. or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices. such as A/D or D/A integrated circuits.PIC16F87XA 10.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data. serial EEPROMs. REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 — R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as ‘0’ BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. such as CRT terminals and personal computers. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. (USART is also known as a Serial Communications Interface or SCI. can be Parity bit Legend: R = Readable bit . DS39582B-page 111 . The USART module also has a multi-processor communication capability using 9-bit address detection. The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules.

read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39582B-page 112  2003 Microchip Technology Inc. . enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection. Synchronous mode – Slave: Don’t care.PIC16F87XA REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don’t care.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection. all bytes are received and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware) Legend: R = Readable bit .

= unimplemented.1. In Synchronous mode. The BRG supports both the Asynchronous and Synchronous modes of the USART. . Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared).1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. Shaded cells are not used by the BRG. the nearest integer value for the SPBRG register can be calculated using the formula in Table 10-1. TABLE 10-1: SYNC 0 1 BAUD RATE FORMULA BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64 (X + 1)) (Synchronous) Baud Rate = FOSC/(4 (X + 1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16 (X + 1)) N/A Legend: X = value in SPBRG (0 to 255) TABLE 10-2: Address 98h 18h 99h REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 CSRC SPEN Bit 6 TX9 RX9 Bit 5 Bit 4 Bit 3 — Bit 2 BRGH FERR Bit 1 TRMT Bit 0 Value on: POR. In Asynchronous mode. From this. Table 10-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock). 10. It is a dedicated 8-bit baud rate generator. DS39582B-page 113 . Given the desired baud rate and FOSC. BOR Value on all other Resets Name TXSTA RCSTA TXEN SYNC TX9D 0000 -010 0000 -010 0000 0000 0000 0000 SREN CREN ADDEN OERR RX9D 0000 000x 0000 000x SPBRG Baud Rate Generator Register Legend: x = unknown. bit BRGH (TXSTA<2>) also controls the baud rate. This is because the FOSC/(16 (X + 1)) equation can reduce the baud rate error in some cases. the error in baud rate can be determined.1 USART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks.  2003 Microchip Technology Inc. read as ‘0’. The SPBRG register controls the period of a free running 8-bit timer.PIC16F87XA 10. This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. bit BRGH is ignored.

16 0.766 19.250 FOSC = 3.2 28.4 9.17 0.17 0.17 0.531 31.2 28.833 31.16 3.500 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz % ERROR 1.72 1.4 9.13 SPBRG value (decimal) 103 51 33 29 16 255 0 FOSC = 10 MHz % ERROR 1.4 9.17 0.404 8.34 8.6 19.6 19.778 35.824 3.94 0.16 0.2 2.231 27.000 KBAUD 1.2 28.51 3.6 19.34 FOSC = 4 MHz % ERROR 0.51 SPBRG value (decimal) 207 103 25 12 8 6 3 255 0 FOSC = 10 MHz % ERROR 0.2 2.929 20.51 FOSC = 4 MHz % ERROR 0 0.6 19.714 62.722 62.083 0.895 56.6 TABLE 10-4: BAUD RATE (K) 0.300 1.615 19.4 DS39582B-page 114  2003 Microchip Technology Inc.818 2.977 250.6 57.000 KBAUD 2.500 1.55 6.000 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz % ERROR 0.55 6.17 6.8 32.221 312.500 0.PIC16F87XA TABLE 10-3: BAUD RATE (K) 0.55 3.58 SPBRG value (decimal) 129 64 15 7 4 4 2 255 0 KBAUD 1.714 62.73 1.51 SPBRG value (decimal) 207 51 25 6 2 1 0 255 0 SPBRG value (decimal) 255 129 31 15 9 8 4 255 0 FOSC = 16 MHz % ERROR 0.404 9.231 29.16 1.6 0.2 2.8 33.17 0.404 9.333 58.202 2.2 28.17 1.500 KBAUD 1.906 1000.2 2.17 1.8 57.000 FOSC = 3.6 57.4 9.070 33.250 34.2 28.99 9.615 19.16 2.798 35.250 31.4 9.531 28.16 3.6 HIGH LOW BAUD RATE (K) KBAUD 0.202 2.883 1250.3 1.977 250.9 230.16 0.6 HIGH LOW 0.412 33.4 9.04 0 SPBRG value (decimal) 191 95 23 11 7 6 3 255 0 KBAUD 1.6 19.2 2.409 32.441 9.6 19.615 19.10 1.202 2.72 8.404 9.615 19.13 0.250 62.6 HIGH LOW BAUD RATE (K) KBAUD 0.6 57.36 2.6864 MHz % ERROR 0 0 0 0 0 2.3 1.8 33.51 6.531 31.784 59.9 57.221 2.225 57.500 0.244 62.766 19.29 8.2 28.72 8.3 1.8 33.441 625.6 0.73 1.610 156. .000 KBAUD 9.29 8.3 1.51 SPBRG value (decimal) 207 103 25 12 8 6 3 255 0 SPBRG value (decimal) 129 64 42 36 20 255 0 FOSC = 16 MHz % ERROR 0.500 0.17 0.524 4.79 2.3 1.6 HIGH LOW 1.99 8.2 2.231 29.75 0.16 0.250 52.231 27.6864 MHz % ERROR 0 0 0 0 0 0 0 SPBRG value (decimal) 191 47 23 5 2 1 0 255 0 KBAUD 0.51 8.71 0.6 57.202 2.404 9.51 8.16 0.8 33.36 SPBRG value (decimal) 255 64 31 21 18 10 255 0 KBAUD 9.615 19.

As soon as the Stop bit is transmitted. TXIF is cleared by loading TXREG. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. The transmitter and receiver are functionally independent but use the same data format and baud rate. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). an incorrect ninth data bit may be loaded in the TSR register. While flag bit TXIF indicates the status of the TXREG register. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). Transmission is enabled by setting enable bit. DS39582B-page 115 . shows the status of the TSR register. 10. depending on bit BRGH (TXSTA<2>). The actual transmission will not occur until the TXREG register has been loaded with data and the Baud Rate Generator (BRG) has produced a shift clock (Figure 10-2). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. TXIF (PIR1<4>). the TSR is loaded with new data from the TXREG register (if available). TRMT (TXSTA<1>). transfer to the TXREG register will result in an immediate transfer to TSR. Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The shift register obtains its data from the Read/Write Transmit Buffer. TXIE (PIE1<4>). The most common data format is 8 bits. As a result. the TXREG register is empty and flag bit. Note 1: The TSR register is not mapped in data memory so it is not available to the user. is set. The baud rate generator produces a clock. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR).2 USART Asynchronous Mode In this mode. This interrupt can be FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register 8 MSb (8) TSR Register LSb 0 Pin Buffer and Control RC6/TX/CK pin TXIE Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN  2003 Microchip Technology Inc. Parity is not supported by the hardware but can be implemented in software (and stored as the ninth data bit). In order to select 9-bit transmission. Once the TXREG register transfers the data to the TSR register (occurs in one TCY). resulting in an empty TXREG. A back-to-back transfer is thus possible (Figure 10-3). An on-chip. the RC6/TX/CK pin will revert to high-impedance. The ninth bit must be written before writing the 8-bit data to the TXREG register. TXEN (TXSTA<5>).PIC16F87XA 10. Status bit TRMT is a read-only bit which is set when the TSR register is empty. eight or nine data bits and one Stop bit). The USART Asynchronous module consists of the following important elements: • • • • Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver enabled/disabled by setting/clearing enable bit. The TXREG register is loaded with data in software. 2: Flag bit TXIF is set when enable bit TXEN is set. In such a case. Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. At that point. Normally. Asynchronous mode is stopped during Sleep. the USART uses standard Non-Returnto-Zero (NRZ) format (one Start bit. either x16 or x64 of the bit shift rate. dedicated. It will reset only when new data is loaded into the TXREG register. when transmission is first started.2. 8-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. TXREG.1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 10-1. The USART transmits and receives the LSb first. the TSR register is empty. another bit. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty.

. which will also set bit TXIF. 5. 7. Empty Flag) Note: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Word 1 Word 2 Start Bit Bit 0 Bit 1 Word 1 Bit 7/8 Stop Bit Start Bit Word 2 Bit 0 Word 1 Transmit Shift Reg. 4.18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA TXREG PIE1 TXSTA USART Transmit Register SPBRG Baud Rate Generator Register x = unknown. Word 2 Transmit Shift Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) ASYNCHRONOUS MASTER TRANSMISSION Word 1 Start Bit Bit 0 Bit 1 Word 1 Bit 7/8 Stop Bit TRMT bit (Transmit Shift Reg. the ninth bit should be loaded in bit TX9D. If using interrupts. Bits PSPIE and PSPIF are reserved on 28-pin devices. Enable the transmission by setting bit TXEN. FIGURE 10-2: Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Reg. ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. Initialize the SPBRG register for the appropriate baud rate. set bit BRGH (Section 10. 8. Load data to the TXREG register (starts transmission). DS39582B-page 116  2003 Microchip Technology Inc.= unimplemented locations read as ‘0’. then set transmit bit TX9. INTCON 10Bh. If 9-bit transmission is selected. If a high-speed baud rate is desired. 3. Shaded cells are not used for asynchronous transmission. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.1 “USART Baud Rate Generator (BRG)”). 8Bh. BOR 0000 000x 0000 0000 0000 -00x 0000 0000 SSPIE CCP1IE — BRGH 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 Name 0Bh. Empty Flag) Word 1 Transmit Shift Reg FIGURE 10-3: Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. TABLE 10-5: Address REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF — Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR TMR2IE TRMT Bit 0 R0IF TMR1IF RX9D TMR1IE TX9D Value on: POR. . If interrupts are desired. This timing diagram shows two consecutive transmissions. always maintain these bits clear. then set enable bit TXIE.PIC16F87XA When setting up an Asynchronous Transmission. 6. follow these steps: 1. If 9-bit transmission is desired. 2.

2. Once Asynchronous mode is selected. flag bit. operating at x16 times the baud rate. is set if a Stop bit is detected as clear. therefore. reception is enabled by setting bit CREN (RCSTA<4>). OERR (RCSTA<1>). it is essential for the user to read the RCSTA register before reading the RCREG register in order not to lose the old FERR and RX9D information. transfers from the RSR register to the RCREG register are inhibited and no further data will be received. Bit FERR and the 9th receive bit are buffered the same way as the receive data. It is. RCIF (PIR1<5>). The RCREG is a double-buffered register (i. essential to clear error bit OERR if it is set. whereas the main receive serial shifter operates at the bit rate or at FOSC. if the RCREG register is still full. The word in the RSR will be lost. The actual interrupt can be enabled/disabled by setting/clearing enable bit. Framing error bit. Reading the RCREG will load bits RX9D and FERR with new values. DS39582B-page 117 .2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 10-4.PIC16F87XA 10.e. the received data in the RSR is transferred to the RCREG register (if it is empty). it is a two-deep FIFO). Overrun bit OERR has to be cleared in software. Flag bit RCIF is a read-only bit which is cleared by the hardware.. therefore. will be set. the Overrun Error bit. The data recovery block is actually a high-speed shifter. FERR (RCSTA<2>). The data is received on the RC7/RX/DT pin and drives the data recovery block. The heart of the receiver is the Receive (Serial) Shift Register (RSR). It is cleared when the RCREG register has been read and is empty. If the transfer is complete. is set. RCIE (PIE1<5>). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. The RCREG register can be read twice to retrieve the two bytes in the FIFO. If bit OERR is set. After sampling the Stop bit. This is done by resetting the receive logic (CREN is cleared and then set). FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK CREN OERR FERR FOSC SPBRG Baud Rate Generator 64 or 16 MSb Stop (8) 7 RSR Register 1 0 LSb Start RC7/RX/DT Pin Buffer and Control Data Recovery RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF RCIE Data Bus  2003 Microchip Technology Inc. On the detection of the Stop bit of the third byte.

18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA PIE1 TXSTA SPBRG CCP1IF TMR2IF TMR1IF FERR OERR RX9D RCREG USART Receive Register Baud Rate Generator Register x = unknown. BOR 0000 000x 0000 0000 0000 -00x 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE — BRGH TRMT TX9D 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 Name 0Bh. then set bit RX9.1 “USART Baud Rate Generator (BRG)”). If a high-speed baud rate is desired. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. set bit BRGH (Section 10. Bits PSPIE and PSPIF are reserved on 28-pin devices. causing the OERR (Overrun Error) bit to be set. The RCREG (Receive Buffer) is read after the third word. 4. INTCON 10Bh. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. clear the error by clearing enable bit CREN. ASYNCHRONOUS RECEPTION Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 1 RCREG Word 2 RCREG When setting up an Asynchronous Reception. TABLE 10-6: Address REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF — Bit 2 TMR0IF Bit 1 INTF Bit 0 R0IF Value on: POR. follow these steps: 1. always maintain these bits clear. then set enable bit RCIE. If interrupts are desired. Initialize the SPBRG register for the appropriate baud rate. Shaded cells are not used for asynchronous reception. DS39582B-page 118  2003 Microchip Technology Inc. . ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. 9. If 9-bit reception is desired. 10. Enable the reception by setting bit CREN.PIC16F87XA FIGURE 10-5: RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. 2. If any error occurred. 8. 5. 7.= unimplemented locations read as ‘0’. . If using interrupts. 8Bh. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. Read the 8-bit received data by reading the RCREG register. 6. 3.

If a high-speed baud rate is desired. FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK CREN OERR FERR FOSC SPBRG 64 or 16 MSb Stop (8) 7 RSR Register 1 0 LSb Start Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery RX9 8 SPEN RX9 ADDEN RX9 ADDEN RSR<8> Enable Load of Receive Buffer 8 RX9D RCREG Register FIFO 8 Interrupt RCIF RCIE Data Bus  2003 Microchip Technology Inc. clear the ADDEN bit to allow data bytes and address bytes to be read into the receive buffer and interrupt the CPU. • Set ADDEN to enable address detect. • If interrupts are desired. DS39582B-page 119 . • Flag bit RCIF will be set when reception is complete. • Set bit RX9 to enable 9-bit reception. • Read the 8-bit received data by reading the RCREG register to determine if the device is being addressed. • If any error occurred. • Enable the reception by setting enable bit CREN. set bit BRGH. then set enable bit RCIE. and an interrupt will be generated if enable bit RCIE was set.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT When setting up an Asynchronous Reception with address detect enabled: • Initialize the SPBRG register for the appropriate baud rate.PIC16F87XA 10. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • If the device has been addressed. • Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. clear the error by clearing enable bit CREN.2.

BOR 0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000 0Bh.PIC16F87XA FIGURE 10-7: RC7/RX/DT (pin) Load RSR Bit 8 = 0. TABLE 10-7: Address REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 GIE PSPIF(1) SPEN PSPIE (1) Name Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 TMR0IF Bit 1 INTF Bit 0 R0IF Value on: POR. Data Byte Word 1 RCREG RCIF Note: This timing diagram shows a data byte followed by an address byte. Bits PSPIE and PSPIF are reserved on 28-pin devices. 8Bh. Shaded cells are not used for asynchronous reception. Address Byte Read Bit 8 = 0. Data Byte Read Bit 8 = 1. The data byte is not read into the RCREG (Receive Buffer) because ADDEN = 1.= unimplemented locations read as ‘0’. INTCON 10Bh. The data byte is not read into the RCREG (Receive Buffer) because ADDEN was not updated and still = 0.18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG CCP1IF TMR2IF TMR1IF FERR OERR RX9D CREN ADDEN TXIE SYNC SSPIE — USART Receive Register CCP1IE TMR2IE TMR1IE BRGH TRMT TX9D CSRC Baud Rate Generator Register x = unknown. . FIGURE 10-8: RC7/RX/DT (pin) Load RSR ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST Start bit bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit Bit 8 = 1. DS39582B-page 120  2003 Microchip Technology Inc. always maintain these bits clear. . Address Byte Word 1 RCREG ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT Start bit bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit RCIF Note: This timing diagram shows a data byte followed by an address byte.

While flag bit TXIF indicates the status of the TXREG register. If either bit CREN or bit SREN is set during a transmission. The actual transmission will not occur until the TXREG register has been loaded with data. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The CK pin will remain an output if bit CSRC is set (internal clock). The ninth bit must be written before writing the 8-bit data to the TXREG register. is not reset. bit TXEN should be cleared. If interrupts are desired. Setting enable bit TXEN will start the BRG. As soon as the last bit is transmitted. 3. The Master mode indicates that the processor transmits the master clock on the CK line. 4. It will reset only when new data is loaded into the TXREG register. resulting in an empty TXREG. when transmission is first started.1 USART SYNCHRONOUS MASTER TRANSMISSION The USART transmitter block diagram is shown in Figure 10-6. the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). then after the single word is received. the “present” value of bit TX9D is loaded. If the TSR was empty and the TXREG was written before writing the “new” TX9D. TXIF (PIR1<4>). bit SREN will be cleared and the serial port will revert back to transmitting since bit TXEN is still set. the TSR is loaded with new data from the TXREG (if available). is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines. another bit. The Master mode is entered by setting bit. enable bit. Back-to-back transfers are possible. When transmitting data. The transmitter logic.e. Enable the transmission by setting bit TXEN. Initialize the SPBRG register for the appropriate baud rate (Section 10. 8. TRMT (TXSTA<1>).. SYNC (TXSTA<4>). however. Data out is stable around the falling edge of the synchronous clock (Figure 10-9). Transmission is enabled by setting enable bit. set enable bit TXIE. In addition. TXREG. If bit SREN is set (to interrupt an on-going transmission and receive a single word). Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 10-10). ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. TXEN (TXSTA<5>). CSRC (TXSTA<7>). 2. DS39582B-page 121 . The shift register obtains its data from the Read/Write Transmit Buffer register. SPEN and CSRC. CREN and SREN are clear. Normally. The DT line will immediately switch from HighImpedance Receive mode to transmit and start driving. Synchronous mode is entered by setting bit. If using interrupts. Enable the synchronous master serial port by setting bits SYNC. although it is disconnected from the pins. the TXREG is empty and interrupt bit. the data is transmitted in a half-duplex manner (i. 7. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). 5. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). set bit TX9. TRMT is a readonly bit which is set when the TSR is empty. The TSR register is not loaded until the last bit has been transmitted from the previous load. the transmission is aborted and the DT pin reverts to a high-impedance state (for a reception). In order to reset the transmitter. In order to select 9-bit transmission. Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software.  2003 Microchip Technology Inc. shows the status of the TSR register. Start transmission by loading data to the TXREG register. 6. the user has to clear bit TXEN. the TSR register is empty so a transfer to the TXREG register will result in an immediate transfer to TSR. is set. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. To avoid this. the reception is inhibited and vice versa. transmission and reception do not occur at the same time). 10. This is advantageous when slow baud rates are selected since the BRG is kept in Reset when bits TXEN. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. the ninth bit should be loaded in bit TX9D. respectively. If 9-bit transmission is desired. Steps to follow when setting up a Synchronous Master Transmission: 1.3 USART Synchronous Master Mode Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. SPEN (RCSTA<7>). In Synchronous Master mode.3. If 9-bit transmission is selected. creating a shift clock immediately. The TSR is not mapped in data memory so it is not available to the user. The DT and CK pins will revert to highimpedance. The TXREG register is loaded with data in software.1 “USART Baud Rate Generator (BRG)”).PIC16F87XA 10.

read as ‘0’. always maintain these bits clear.18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA TXREG PIE1 TXSTA SPBRG USART Transmit Register Baud Rate Generator Register x = unknown. INTCON 10Bh. FIGURE 10-9: SYNCHRONOUS TRANSMISSION Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2Q3 Q4Q1Q2Q3 Q4Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg Write Word 1 TXIF bit (Interrupt Flag) TRMT bit ‘1’ bit 0 bit 1 bit 2 Word 1 bit 7 bit 0 bit 1 Word 2 bit 7 Write Word 2 TXEN bit ‘1’ Note: Sync Master mode. . BOR 0000 000x 0000 0000 0000 -00x 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 Name 0Bh. FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) bit 0 bit 1 bit 2 bit 6 bit 7 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit DS39582B-page 122  2003 Microchip Technology Inc. 8Bh.= unimplemented.PIC16F87XA TABLE 10-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF — SSPIE — Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF TMR1IF RX9D Value on: POR. Shaded cells are not used for synchronous master transmission. Bits PSPIE and PSPIF are reserved on 28-pin devices. . Continuous transmission of two 8-bit words. SPBRG = 0.

Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Bit OERR has to be cleared in software (by clearing bit CREN). If a single reception is required. then set bit RX9. SPEN and CSRC. set bit SREN. the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). 10. In this case. then only a single word is received. When setting up a Synchronous Master Reception: 1. Flag bit RCIF is a read-only bit which is reset by the hardware. it is reset when the RCREG register has been read and is empty. 11. If any error occurred. After clocking the last bit. set bit CREN. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Initialize the SPBRG register for the appropriate baud rate (Section 10.e. SREN (RCSTA<5>).= unimplemented. For continuous reception. 9. OERR (RCSTA<1>). interrupt flag bit. If enable bit SREN is set. then Overrun Error bit. reception is enabled by setting either enable bit. 5. 8Bh. Data is sampled on the RC7/RX/DT pin on the falling edge of the clock.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected. The actual interrupt can be enabled/ disabled by setting/clearing enable bit.. INTCON 10Bh. Read the 8-bit received data by reading the RCREG register. The ninth receive bit is buffered the same way as the receive data. Shaded cells are not used for synchronous master reception. is set. Reading the RCREG register will load bit RX9D with a new value. If bit OERR is set. if the RCREG register is still full. If interrupts are desired. transfers from the RSR to the RCREG are inhibited so it is essential to clear bit OERR if it is set. CREN takes precedence. It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. clear the error by clearing bit CREN. If enable bit CREN is set. ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. DS39582B-page 123 . RCIF (PIR1<5>).1 “USART Baud Rate Generator (BRG)”). If 9-bit reception is desired. the reception is continuous until CREN is cleared. or enable bit.3. 4. is set. If using interrupts. RCIE (PIE1<5>). it is a twodeep FIFO). always maintain these bits clear. 8. Enable the synchronous master serial port by setting bits SYNC. The word in the RSR will be lost. 7. Ensure bits CREN and SREN are clear. On the clocking of the last bit of the third byte. When the transfer is complete. CREN (RCSTA<4>). TABLE 10-9: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF — SSPIE — Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF TMR1IF RX9D Value on: POR. it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. read as ‘0’.PIC16F87XA 10. therefore. .  2003 Microchip Technology Inc. then set enable bit RCIE. 2. 3. BOR 0000 000x 0000 0000 0000 -00x 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000 Name 0Bh. The RCREG register can be read twice to retrieve the two bytes in the FIFO. The RCREG is a double-buffered register (i. Bits PSPIE and PSPIF are reserved on 28-pin devices.18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG USART Receive Register Baud Rate Generator Register x = unknown. If both bits are set. 6.

4. e) DS39582B-page 124  2003 Microchip Technology Inc.4 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). The second word will remain in TXREG register. If interrupts are desired. Start transmission by loading data to the TXREG register. then set enable bit TXIE. the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. CSRC (TXSTA<7>). 8. the program will branch to the interrupt vector (0004h). When setting up a Synchronous Slave Transmission. If 9-bit transmission is selected. follow these steps: 1. 6. 2. then set bit TX9. . 3. Clear bits CREN and SREN. If two words are written to the TXREG and then the SLEEP instruction is executed. If enable bit TXIE is set. 10. Enable the transmission by setting enable bit TXEN. This allows the device to transfer or receive data while in Sleep mode. 7. 5. 4. Slave mode is entered by clearing bit. If 9-bit transmission is desired. the ninth bit should be loaded in bit TX9D. the interrupt will wake the chip from Sleep and if the global interrupt is enabled. When the first word has been shifted out of TSR. the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit.PIC16F87XA FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE. If using interrupts. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Flag bit TXIF will not be set.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes is identical. SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG ‘0’ bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ‘0’ Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0. ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. except in the case of the Sleep mode. 10.

BOR 0000 000x Value on all other Resets 0000 000u 0Bh. Shaded cells are not used for synchronous slave reception.18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 USART Receive Register BRGH TRMT TX9D CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 Baud Rate Generator Register x = unknown. If receive is enabled by setting bit CREN prior to the SLEEP instruction. clear the error by clearing bit CREN. 9. Bits PSPIE and PSPIF are reserved on 28-pin devices.  2003 Microchip Technology Inc.PIC16F87XA TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE — Bit 2 TMR0IF Bit 1 INTF Bit 0 R0IF Value on: POR.= unimplemented. always maintain these bits clear. 6. The operation of the Synchronous Master and Slave modes is identical. . set enable bit RCIE. 8. Read the 8-bit received data by reading the RCREG register. 3. INTCON 10Bh. If the global interrupt is enabled. If 9-bit reception is desired. 2. set enable bit CREN. INTCON 10Bh. set bit RX9.= unimplemented. BOR 0000 000x Value on all other Resets 0000 000u 0Bh. 7.4. Bits PSPIE and PSPIF are reserved on 28-pin devices. To enable reception. Bit SREN is a “don't care” in Slave mode. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. read as ‘0’. follow these steps: 1. the interrupt generated will wake the chip from Sleep. read as ‘0’. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. If using interrupts. ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE — Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF Value on: POR. the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set.18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA TXREG PIE1 TXSTA SPBRG CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 USART Transmit Register Baud Rate Generator Register x = unknown. Shaded cells are not used for synchronous slave transmission. On completely receiving the word. . 10. except in the case of the Sleep mode.2 USART SYNCHRONOUS SLAVE RECEPTION When setting up a Synchronous Slave Reception. the program will branch to the interrupt vector (0004h). If any error occurred. 8Bh. 5. DS39582B-page 125 . always maintain these bits clear. 8Bh. 4. then a word may be received during Sleep. If interrupts are desired. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set.

.PIC16F87XA NOTES: DS39582B-page 126  2003 Microchip Technology Inc.

RA2 or RA3.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The ADCON0 register.PIC16F87XA 11. The port pins can be configured as analog inputs (RA3 can also be the voltage reference) or as digital I/O. controls the operation of the A/D module. The A/D module has high and low-voltage reference input that is software selectable to some combination of VDD. GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress Unimplemented: Read as ‘0’ ADON: A/D On bit 1 = A/D converter module is powered up 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit . To operate in Sleep. VSS. The ADCON1 register. the A/D clock must be derived from the A/D’s internal RC oscillator. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. the unimplemented selections are reserved. DS39582B-page 127 . The conversion of an analog input signal results in a corresponding 10-bit digital number. shown in Register 11-1.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. Additional information on using the A/D module can be found in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023). These registers are: • • • • A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the 40/44-pin devices. shown in Register 11-2. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Note: bit 2 bit 1 bit 0  2003 Microchip Technology Inc. configures the functions of the port pins. Do not select any unimplemented channels with these devices. REGISTER 11-1: ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 ADCS1 bit 7 R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 — R/W-0 ADON bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold) ADCON1 <ADCS2> 0 0 0 0 1 1 1 1 ADCON0 <ADCS1:ADCS0> 00 01 10 11 00 01 10 11 Clock Conversion FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from the internal A/D RC oscillator) FOSC/4 FOSC/16 FOSC/64 FRC (clock derived from the internal A/D RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (AN0) 001 = Channel 1 (AN1) 010 = Channel 2 (AN2) 011 = Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5) 110 = Channel 6 (AN6) 111 = Channel 7 (AN7) The PIC16F873A/876A devices only implement A/D channels 0 through 4.

PIC16F87XA REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh) R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.n = Value at POR Note: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. . Six (6) Most Significant bits of ADRESH are read as ‘0’. DS39582B-page 128  2003 Microchip Technology Inc. ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in shaded area and in bold) ADCON1 ADCON0 <ADCS2> <ADCS1:ADCS0> 0 0 0 0 1 1 1 1 bit 5-4 bit 3-0 00 01 10 11 00 01 10 11 Clock Conversion FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from the internal A/D RC oscillator) FOSC/4 FOSC/16 FOSC/64 FRC (clock derived from the internal A/D RC oscillator) R/W-0 ADCS2 U-0 — U-0 — R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 bit 6 Unimplemented: Read as ‘0’ PCFG3:PCFG0: A/D Port Configuration Control bits PCFG <3:0> 0000 0001 0010 0011 0100 0101 011x 1000 1001 1010 1011 1100 1101 1110 1111 AN7 A A D D D D D A D D D D D D D AN6 A A D D D D D A D D D D D D D AN5 A A D D D D D A A A A D D D D AN4 A A A A D D D A A A A A D D D AN3 A VREF+ A VREF+ A VREF+ D VREF+ A VREF+ VREF+ VREF+ VREF+ D VREF+ AN2 A A A A D D D VREFA A VREFVREFVREFD VREFAN1 A A A A A A D A A A A A A D D AN0 A A A A A A D A A A A A A A A VREF+ VDD AN3 VDD AN3 VDD AN3 — AN3 VDD AN3 AN3 AN3 AN3 VDD AN3 VREFVSS VSS VSS VSS VSS VSS — AN2 VSS VSS AN2 AN2 AN2 VSS AN2 C/R 8/0 7/1 5/0 4/1 3/0 2/1 0/0 6/2 6/0 5/1 4/2 3/2 2/2 1/0 1/2 A = Analog input D = Digital I/O C/R = # of analog input channels/# of A/D voltage references Legend: R = Readable bit . 0 = Left justified. the port pins that are multiplexed with analog functions (ANx) are forced to be an analog input. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown On any device Reset.

When the A/D conversion is complete. 5. go to step 1 or step 2 as required. 2. see Section 11. The analog input channels must have their corresponding TRIS bits selected as inputs. the A/D conversion can be started. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit Wait the required acquisition time. follow these steps: 1.PIC16F87XA The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. the result is loaded into this A/D Result register pair. 3. 4. OR • Waiting for the A/D interrupt Read A/D Result register pair (ADRESH:ADRESL). To do an A/D Conversion. FIGURE 11-1: A/D BLOCK DIAGRAM CHS2:CHS0 111 110 101 100 VAIN (Input Voltage) 011 010 001 000 VREF+ (Reference Voltage) PCFG3:PCFG0 VREF(Reference Voltage) VSS PCFG3:PCFG0 RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) RA5/AN4 RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 A/D Converter VDD Note 1: Not available on 28-pin devices. 7. After the A/D module has been configured as desired. The block diagram of the A/D module is shown in Figure 11-1. After this acquisition time has elapsed. the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set.1 “A/D Acquisition Requirements”. the selected channel must be acquired before the conversion is started. DS39582B-page 129 . To determine sample time. Start conversion: • Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete by either: • Polling for the GO/DONE bit to be cleared (interrupts disabled).  2003 Microchip Technology Inc. Configure the A/D module: • Configure analog pins/voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) 6. clear bit ADIF if required. For the next conversion. The A/D conversion time per bit is defined as TAD.

To calculate the minimum acquisition time. TACQ. This is required to meet the pin leakage specification. the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. After the analog input channel is selected (changed).6V RIC Sampling Switch 1K SS RSS CHOLD = DAC Capacitance = 120 pF VSS VT = 0. this acquisition must be done before the conversion can be started. The source impedance (RS) and the internal sampling switch impedance (RSS) directly affect the time required to charge the capacitor CHOLD.PIC16F87XA 11.0004885) 16. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 2.5 k .6V ILEAKAGE ± 500 nA Legend: CPIN = input capacitance = threshold voltage VT ILEAKAGE = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k ) DS39582B-page 130  2003 Microchip Technology Inc.120 pF (1 k + 7 k + 10 k ) In(0. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The analog input model is shown in Figure 11-2. To calculate the minimum acquisition time. As the impedance is decreased. see the PICmicro® Mid-Range MCU Family Reference Manual (DS33023). . Equation 11-1 may be used.05 s/ C) 19.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy. the acquisition time may be decreased. The maximum recommended impedance for analog sources is 2.05 s/°C)] CHOLD (RIC + RSS + RS) In(1/2047) . FIGURE 11-2: ANALOG INPUT MODEL VDD RS VA ANx CPIN 5 pF VT = 0.5 k .47 s + [(50°C – 25 C)(0.72 s TC TACQ Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out. The sampling switch (RSS) impedance varies over the device voltage (VDD).47 s 2 s + 16. EQUATION 11-1: TACQ ACQUISITION TIME = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = = = = = = = TAMP + TC + TCOFF 2 s + TC + [(Temperature – 25°C)(0. see Figure 11-2. The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution.

PIC16F87XA 11. When the device frequencies are greater than 1 MHz. any pin configured as an analog input channel will read as cleared (a low level). The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input).2 Selecting the A/D Conversion Clock 11. The seven possible options for TAD are: • • • • • • • 2 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal A/D module RC oscillator (2-6 s) TOSC For correct A/D conversions. DS39582B-page 131 .5 MHz 5 MHz 10 MHz 20 MHz 20 MHz (Note 1) The RC source has a typical TAD time of 4 s but can vary between 2-6 s. Analog levels on a digitally configured input will not affect the conversion accuracy. please refer to Section 17.0 “Electrical Characteristics”. the RC A/D conversion clock source is only recommended for Sleep operation. 2. the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1. For extended voltage devices (LF).6 s. 3) Note 1: 2: 3: ADCS2:ADCS1:ADCS0 000 100 001 101 010 110 x11 1. Table 11-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. The source of the A/D conversion clock is software selected.3 Configuring Analog Port Pins The ADCON1 and TRIS registers control the operation of the A/D port pins. the digital output level (VOH or VOL) will be converted. The A/D conversion requires a minimum 12 TAD per 10-bit conversion. Pins configured as digital inputs will convert an analog input. If the TRIS bit is cleared (output). The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits.25 MHz 2. 2: Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins) may cause the input buffer to consume current that is out of the device specifications. TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (F)) AD Clock Source (TAD) Maximum Device Frequency Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC(1. The A/D conversion time per bit is defined as TAD.  2003 Microchip Technology Inc. Note 1: When reading the port register.

PIC16F87XA 11. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. these registers may be used as two general purpose 8-bit registers. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. FIGURE 11-3: A/D CONVERSION TAD CYCLES TAD2 b9 Conversion starts TAD3 b8 TAD4 b7 TAD5 b6 TAD6 b5 TAD7 b4 TAD8 b3 TAD9 TAD10 TAD11 b2 b1 b0 TCY to TAD TAD1 Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit ADRES is loaded GO bit is cleared ADIF bit is set Holding capacitor is connected to analog input 11. In Figure 11-3. the first time segment has a minimum of TCY and a maximum of TAD.4 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. FIGURE 11-4: A/D RESULT JUSTIFICATION 10-bit Result ADFM = 1 ADFM = 0 7 0000 00 2107 0 7 0765 0000 00 0 ADRESH ADRESL 10-bit Result ADRESH 10-bit Result ADRESL Right Justified Left Justified DS39582B-page 132  2003 Microchip Technology Inc. That is. after the GO bit is set. The A/D Format Select bit (ADFM) controls this justification. After the A/D conversion is aborted. . the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). Figure 11-4 shows the operation of the A/D result justification. the next acquisition on the selected channel is automatically started.4. When an A/D result will not overwrite these locations (A/D disable). This register pair is 16 bits wide.1 A/D RESULT REGISTERS The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. The extra bits are loaded with ‘0’s. The GO/DONE bit can then be set to start the conversion. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register.

Shaded cells are not used for A/D conversion. The value that is in the ADRESH:ADRESL registers is not modified for a Power-on Reset. For the A/D module to operate in Sleep. the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). the GO/DONE bit will be cleared and the result loaded into the ADRES register.PIC16F87XA 11. the A/D module waits one instruction cycle before starting the conversion. u = unchanged. Turning off the A/D places the A/D module in its lowest current consumption state. This allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conversion. This forces the A/D module to be turned off and any conversion is aborted. .0000 --11 1111 --11 1111 --0x 0000 --0u 0000 0000 -111 0000 -111 ---.-xxx ---. the A/D module will then be turned off. TABLE 11-2: Address REGISTERS/BITS ASSOCIATED WITH A/D Bit 7 GIE PSPIF(1) PSPIE(1) Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF Bit 0 RBIF Value on Value on POR. although the ADON bit will remain set. These registers are not available on 28-pin devices. WDT 0000 000x 0000 000u Name 0Bh. When the RC clock source is selected.  2003 Microchip Technology Inc. a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off. the device will wake-up from Sleep.6 Effects of a Reset A device Reset forces all registers to their Reset state.-uuu PORTA Data Direction Register PORTA Data Latch when written: PORTA pins when read IBOV — PSPMODE — — — PORTE Data Direction bits RE2 RE1 RE0 x = unknown. To allow the conversion to occur during Sleep. read as ‘0’. When the conversion is completed. If the A/D interrupt is enabled. All A/D input pins are configured as analog inputs.5 A/D Operation During Sleep Note: The A/D module can operate during Sleep mode.8Bh. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. 11. BOR MCLR. When the A/D clock source is another clock option (not RC). INTCON 10Bh. DS39582B-page 133 . though the ADON bit will remain set. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11).= unimplemented. ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit. If the A/D interrupt is not enabled.18Bh 0Ch 8Ch 1Eh 9Eh 1Fh 9Fh 85h 05h 89h(1) 09h(1) Legend: Note 1: PIR1 PIE1 TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 ADCON1 TRISA PORTA TRISE PORTE ADCS1 ADCS0 ADFM — — IBF — ADCS2 — — OBF — CHS2 — CHS1 — CHS0 PCFG3 GO/DONE PCFG2 — PCFG1 ADON PCFG0 0000 00-0 0000 00-0 00-.0000 00-.

PIC16F87XA NOTES: DS39582B-page 134  2003 Microchip Technology Inc. .

The on-chip voltage reference (Section 13. The CMCON register (Register 12-1) controls the comparator input and output multiplexers. Legend: R = Readable bit .connects to RA0/AN0 C2 VIN. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2  2003 Microchip Technology Inc. while the outputs are multiplexed to pins RA4 and RA5.connects to RA1/AN1 CM2:CM0: Comparator Mode bits Figure 12-1 shows the Comparator modes and CM2:CM0 bit settings.0 COMPARATOR MODULE The comparator module contains two analog comparators. A block diagram of the various comparator configurations is shown in Figure 12-1.PIC16F87XA 12.n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.connects to RA3/AN3 C2 VIN.connects to RA2/AN2 0 = C1 VIN. DS39582B-page 135 . REGISTER 12-1: CMCON REGISTER R-0 C2OUT bit 7 R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-1 CM2 R/W-1 CM1 R/W-1 CM0 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN. The inputs to the comparators are multiplexed with I/O port pins RA0 through RA3.0 “Comparator Voltage Reference Module”) can also be an input to the comparators.

1 Comparator Configuration There are eight modes of operation for the comparators. CIS (CMCON<3>) is the Comparator Input Switch. The CMCON register is used to select these modes. the comparator output level may not be valid for the specified mode change delay shown in Section 17. The TRISA register controls the data direction of the comparator pins for each mode.PIC16F87XA 12. If the Comparator mode is changed. Note: Comparator interrupts should be disabled during a Comparator mode change. .0 “Electrical Characteristics”. a false interrupt may occur. port reads zeros always. Figure 12-1 shows the eight possible modes. D = Digital Input. Otherwise. FIGURE 12-1: Comparators Reset CM2:CM0 = 000 RA0/AN0 RA3/AN3 A A COMPARATOR I/O OPERATING MODES Comparators Off (POR Default Value) CM2:CM0 = 111 VINVIN+ RA0/AN0 C1 Off (Read as ‘0’) RA3/AN3 D D VINVIN+ C1 Off (Read as ‘0’) RA1/AN1 RA2/AN2 A A VINVIN+ RA1/AN1 C2 Off (Read as ‘0’) RA2/AN2 D D VINVIN+ C2 Off (Read as ‘0’) Two Independent Comparators CM2:CM0 = 010 RA0/AN0 RA3/AN3 A A VINVIN+ Two Independent Comparators with Outputs CM2:CM0 = 011 RA0/AN0 A A VINVIN+ C1 C1OUT RA3/AN3 C1 C1OUT RA4/T0CKI/C1OUT RA1/AN1 RA2/AN2 A A VINVIN+ C2 C2OUT RA1/AN1 RA2/AN2 A A VINVIN+ C2 C2OUT RA5/AN4/SS/C2OUT Two Common Reference Comparators CM2:CM0 = 100 RA0/AN0 RA3/AN3 A A VINVIN+ Two Common Reference Comparators with Outputs CM2:CM0 = 101 RA0/AN0 A A VINVIN+ C1 C1OUT RA3/AN3 C1 C1OUT RA4/T0CKI/C1OUT RA1/AN1 RA2/AN2 A D VINVIN+ C2 C2OUT RA1/AN1 RA2/AN2 A D VINVIN+ C2 C2OUT RA5/AN4/SS/C2OUT One Independent Comparator with Output CM2:CM0 = 001 RA0/AN0 RA3/AN3 A A VINVIN+ Four Inputs Multiplexed to Two Comparators CM2:CM0 = 110 RA0/AN0 A A CIS = 0 CIS = 1 VINVIN+ C1 C1OUT RA3/AN3 RA1/AN1 RA2/AN2 C1 C1OUT RA4/T0CKI/C1OUT D D VINVIN+ A A CIS = 0 CIS = 1 VINVIN+ RA1/AN1 RA2/AN2 C2 C2OUT C2 Off (Read as ‘0’) CVREF From Comparator VREF Module A = Analog Input. DS39582B-page 136  2003 Microchip Technology Inc.

multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator.PIC16F87XA 12. However. When the analog input at VIN+ is less than the analog input VIN-. threshold detector applications may require the same reference.3. the output of the comparator is a digital high level. The internal reference signal is used when comparators are in mode.0 “Electrical Characteristics”). The comparator outputs may also be directly output to the RA4 and RA5 I/O pins.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 12-2 along with the relationship between the analog input levels and the digital output. Section 13. These bits are read-only. the maximum delay of the comparators should be used (Section 17.4 Comparator Response Time An external or internal reference signal may be used depending on the comparator operating mode. 12. When the analog input at VIN+ is greater than the analog input VIN-. If the internal reference is changed. a pull-up resistor is required. 3: RA4 is an open collector I/O pin. FIGURE 12-2: SINGLE COMPARATOR Response time is the minimum time. Note 1: When reading the Port register. the maximum delay of the internal voltage reference must be considered when using the comparator outputs. the internal voltage reference is applied to the VIN+ pin of both comparators. the output of the comparator is a digital low level.3 Comparator Reference 12. Figure 12-3 shows the comparator output block diagram. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). When used as an output. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s). before the comparator output has a valid level.  2003 Microchip Technology Inc.3. Otherwise. The TRISA bits will still function as an output enable/ disable for the RA4 and RA5 pins while in this mode. The comparator module also allows the selection of an internally generated voltage reference for the comparators. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. Output Output 12. after selecting a new reference voltage or input source.is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly (Figure 12-2). When enabled. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. In this mode. CM<2:0> = 110 (Figure 12-1). DS39582B-page 137 . The shaded areas of the output of the comparator in Figure 12-2 represent the uncertainty due to input offsets and response time.0 “Comparator Voltage Reference Module” contains a detailed description of the Comparator Voltage Reference module that provides this signal.5 + – Output Comparator Outputs VININ– VVIN+ VIN+ The comparator outputs are read through the CMCON register.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used. the comparator module can be configured to have the comparators operate from the same or different reference sources. all pins configured as analog inputs will read as a ‘0’. The analog signal present at VIN.2 Comparator Operation 12. VIN+ VIN- 12. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification.

The CMIF bit must be reset by clearing it (‘0’). If any of these bits are clear. the GIE bit must also be set. DS39582B-page 138  2003 Microchip Technology Inc. then the CMIF (PIR registers) interrupt flag may not get set. Software will need to maintain information about the status of the output bits. A mismatch condition will continue to set flag bit CMIF. in the Interrupt Service Routine. The user. Clear flag bit CMIF. Since it is also possible to write a ‘1’ to this register. a simulated interrupt may be initiated. The CMIF bit (PIR registers) is the Comparator Interrupt Flag. to determine the actual change that occurred. .6 Comparator Interrupts Note: The comparator interrupt flag is set whenever there is a change in the output value of either comparator.PIC16F87XA FIGURE 12-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + CxINV To RA4 or RA5 Pin Bus Data Read CMCON Q EN D Set CMIF bit Q From Other Comparator D EN CL Read CMCON Reset 12. though the CMIF bit will still be set if an interrupt condition occurs. as read from CMCON<7:6>. can clear the interrupt in the following manner: a) b) Any read or write of CMCON will end the mismatch condition. If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle). The CMIE bit (PIE registers) and the PEIE bit (INTCON register) must be set to enable the interrupt. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. the interrupt is not enabled. In addition.

6 V RIC VA CPIN 5 pF VT = 0. FIGURE 12-4: ANALOG INPUT MODEL VDD RS < 10K AIN VT = 0. turn off the comparators. higher Sleep currents than shown in the power-down current specification will occur. This ensures compatibility to the PIC16F87X devices. therefore.6V in either direction. Since the analog pins are connected to a digital output.9 Analog Input Connection Considerations When a comparator is active and the device is placed in Sleep mode. This interrupt will wake-up the device from Sleep mode when enabled.7 Comparator Operation During Sleep 12.8 Effects of a Reset A device Reset forces the CMCON register to its Reset state. A maximum source impedance of 10 k is recommended for the analog sources. DS39582B-page 139 . To minimize power consumption while in Sleep mode. A simplified circuit for an analog input is shown in Figure 12-4. causing the comparator module to be in the Comparator Off mode. they have reverse biased diodes to VDD and VSS. If the input voltage deviates from this range by more than 0. While the comparator is powered up. the contents of the CMCON register are not affected. should have very little leakage current. such as a capacitor or a Zener diode. Any external component connected to an analog input pin. 12. Each operational comparator will consume additional current as shown in the comparator specifications. must be between VSS and VDD. one of the diodes is forward biased and a latch-up condition may occur. the comparator remains active and the interrupt is functional if enabled. The analog input. before entering Sleep. CM<2:0> = 111. If the device wakes up from Sleep.PIC16F87XA 12. CM<2:0> = 111.6 V ILEAKAGE ±500 nA VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage  2003 Microchip Technology Inc.

0000 --0x 0000 --0u 0000 --11 1111 --11 1111 CVRCON CVREN 0Bh.= unimplemented. .0000 -0-.0000 0000 000x 0000 000u -0-. u = unchanged.0000 -0-.0000 000.18Bh 0Dh 8Dh 05h 85h Legend: PIR2 PIE2 PORTA TRISA TMR3IF CCP2IF TMR3IE CCP2IE RA1 RA0 PORTA Data Direction Register x = unknown. . DS39582B-page 140  2003 Microchip Technology Inc.0000 -0-.PIC16F87XA TABLE 12-1: Address 9Ch 9Dh REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 C2OUT GIE/ GIEH — — — — Bit 6 C1OUT CVROE PEIE/ GIEL CMIF CMIE — — Bit 5 C2INV CVRR TMR0IE — — RA5 Bit 4 C1INV — INTIE — — RA4 Bit 3 CIS CVR3 RBIE BCLIF BCLIE RA3 Bit 2 CM2 CVR2 TMR0IF LVDIF LVDIE RA2 Bit 1 CM1 CVR1 INTIF Bit 0 CM0 CVR0 RBIF Value on POR Value on all other Resets Name CMCON 0000 0111 0000 0111 000. 8Bh. Shaded cells are unused by the comparator module. INTCON 10Bh. read as ‘0’.

The output of the reference generator may be connected to the RA2/AN2/VREF-/CVREF pin.25 CVRSRC to 0. It should be noted. with CVRSRC/32 step size Unimplemented: Read as ‘0’ CVR3:CVR0: Comparator VREF Value Selection bits 0 When CVRR = 1: CVREF = (VR<3:0>/ 24) (CVRSRC) When CVRR = 0: CVREF = 1/4 (CVRSRC) + (VR3:VR0/ 32) (CVRSRC) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. the resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. with CVRSRC/24 step size 0 = 0. DS39582B-page 141 .PIC16F87XA 13. This reference will only be as accurate as the values of CVRSRC and VSAT. Register 13-1 lists the bit functions of the CVRCON register.75 CVRSRC. A programmable register controls the function of the reference generator. This can be used as a simple D/A function by the user if a very highimpedance load is used.75 CVRSRC. where VSAT is the saturation voltage of the power switch transistor. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown VR3:VR0 15 bit 6 bit 5 bit 4 bit 3-0  2003 Microchip Technology Inc. The Comparator Voltage Reference Generator is a 16-tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode ‘110’. that the voltage at the top of the ladder is CVRSRC – VSAT. The comparator reference REGISTER 13-1: CVRCON CONTROL REGISTER (ADDRESS 9Dh) R/W-0 CVREN bit 7 R/W-0 CVROE R/W-0 CVRR U-0 — R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.0 COMPARATOR VOLTAGE REFERENCE MODULE supply voltage (also referred to as CVRSRC) comes directly from VDD. however. The primary purpose of this function is to provide a test path for testing the reference generator function. As shown in Figure 13-1.

0000 000. read as ‘0’.0000 CM0 0000 0111 0000 0111 C2OUT C1OUT C2INV C1INV Legend: x = unknown. Shaded cells are not used with the comparator voltage reference. .= unimplemented.PIC16F87XA FIGURE 13-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VDD 16 Stages CVREN 8R R R R R 8R CVRR RA2/AN2/VREF-/CVREF CVROE CVREF Input to Comparator 16:1 Analog MUX CVR3 CVR2 CVR1 CVR0 TABLE 13-1: Address Name REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets 9Dh 9Ch CVRCON CVREN CVROE CVRR CMCON — CVR3 CIS CVR2 CM2 CVR1 CM1 CVR0 000. u = unchanged. DS39582B-page 142  2003 Microchip Technology Inc. .

most applications need no external Reset circuitry. The erased or unprogrammed value of the Configuration Word register is 3FFFh. These bits are mapped in program memory location 2007h. The user can wake-up from Sleep through external Reset.Oscillator Start-up Timer (OST) . The other is the Power-up Timer (PWRT).1 Configuration Bits The configuration bits can be programmed (read as ‘0’). which provides a fixed delay of 72 ms (nominal) on power-up only. DS39582B-page 143 .0 SPECIAL FEATURES OF THE CPU Sleep mode is designed to offer a very low current power-down mode.  2003 Microchip Technology Inc. Watchdog Timer wake-up or through an interrupt. With these two timers on-chip. intended to keep the chip in Reset until the crystal oscillator is stable. One is the Oscillator Start-up Timer (OST).PIC16F87XA 14. minimize cost through elimination of external components. It is important to note that address 2007h is beyond the user program memory space which can be accessed only during programming. or left unprogrammed (read as ‘1’) to select various device configurations. It runs off its own RC oscillator for added reliability. 14. It is designed to keep the part in Reset while the power supply stabilizes.Power-up Timer (PWRT) . The RC oscillator option saves system cost while the LP crystal option saves power. All PIC16F87XA devices have a host of features intended to maximize system reliability.Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Sleep • Code Protection • ID Locations • In-Circuit Serial Programming • Low-Voltage In-Circuit Serial Programming • In-Circuit Debugger PIC16F87XA devices have a Watchdog Timer which can be shut-off only through configuration bits. Several oscillator options are also made available to allow the part to fit the application.Power-on Reset (POR) . A set of configuration bits is used to select various options. Additional information on special features is available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023). There are two timers that offer necessary delays on power-up. These are: • Oscillator Selection • Reset . provide power saving operating modes and offer code protection.

PIC16F87XA
REGISTER 14-1:
R/P-1 CP bit 13 bit 13 CP: Flash Program Memory Code Protection bit 1 = Code protection off 0 = All program memory code-protected Unimplemented: Read as ‘1’ DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger WRT1:WRT0 Flash Program Memory Write Enable bits For PIC16F876A/877A: 11 = Write protection off; all program memory may be written to by EECON control 10 = 0000h to 00FFh write-protected; 0100h to 1FFFh may be written to by EECON control 01 = 0000h to 07FFh write-protected; 0800h to 1FFFh may be written to by EECON control 00 = 0000h to 0FFFh write-protected; 1000h to 1FFFh may be written to by EECON control For PIC16F873A/874A: 11 = Write protection off; all program memory may be written to by EECON control 10 = 0000h to 00FFh write-protected; 0100h to 0FFFh may be written to by EECON control 01 = 0000h to 03FFh write-protected; 0400h to 0FFFh may be written to by EECON control 00 = 0000h to 07FFh write-protected; 0800h to 0FFFh may be written to by EECON control CPD: Data EEPROM Memory Code Protection bit 1 = Data EEPROM code protection off 0 = Data EEPROM code-protected LVP: Low-Voltage (Single-Supply) In-Circuit Serial Programming Enable bit 1 = RB3/PGM pin has PGM function; low-voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as ‘1’ PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 — R/P-1

CONFIGURATION WORD (ADDRESS 2007h)(1)
R/P-1 R/P-1 R/P-1 R/P-1 CPD LVP R/P-1 BOREN U-0 — U-0 — R/P-1 R/P-1 R/P-1 R/P-1 bit0 PWRTEN WDTEN FOSC1 FOSC0

DEBUG WRT1 WRT0

bit 12 bit 11

bit 10-9

bit 8

bit 7

bit 6

bit 5-4 bit 3

bit 2

bit 1-0

Note 1: The erased (unprogrammed) value of the Configuration Word is 3FFFh.

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PIC16F87XA
14.2
14.2.1

Oscillator Configurations
OSCILLATOR TYPES

FIGURE 14-2:

EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)

The PIC16F87XA can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator Resistor/Capacitor

Clock from Ext. System
Open

OSC1 PIC16F87XA OSC2

14.2.2

CRYSTAL OSCILLATOR/CERAMIC RESONATORS

TABLE 14-1:

CERAMIC RESONATORS
Ranges Tested:

In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKI and OSC2/CLKO pins to establish oscillation (Figure 14-1). The PIC16F87XA oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKI pin (Figure 14-2).

Mode XT

Freq. 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz

OSC1 68-100 pF 15-68 pF 15-68 pF 10-68 pF 10-22 pF

OSC2 68-100 pF 15-68 pF 15-68 pF 10-68 pF 10-22 pF

HS

FIGURE 14-1:

CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 To Internal Logic Sleep PIC16F87XA

These values are for design guidance only. See notes following Table 14-2. Resonators Used: 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX – 0.5% – 0.5% – 0.5% – 0.5%

C1(1)

XTAL OSC2 C2(1) Rs(2)

RF(3)

All resonators used did not have built-in capacitors.

Note 1: See Table 14-1 and Table 14-2 for recommended values of C1 and C2. 2: A series resistor (Rs) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen.

 2003 Microchip Technology Inc.

DS39582B-page 145

PIC16F87XA
TABLE 14-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF

14.2.3

RC OSCILLATOR

Osc Type LP XT

Crystal Freq. 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz

HS

4 MHz 8 MHz 20 MHz

For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 14-3 shows how the R/C combination is connected to the PIC16F87XA.

These values are for design guidance only. See notes following this table. Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C ± 20 PPM ± 20 PPM ± 50 PPM ± 50 PPM ± 30 PPM ± 30 PPM

FIGURE 14-3:
VDD REXT

RC OSCILLATOR MODE

OSC1 CEXT VSS FOSC/4 OSC2/CLKO

Internal Clock PIC16F87XA

Recommended values:

3k REXT 100 k CEXT > 20 pF

Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: When migrating from other PICmicro® devices, oscillator performance should be verified.

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 2003 Microchip Technology Inc.

Most other registers are reset to a “Reset  2003 Microchip Technology Inc.51. Their status is unknown on POR and unchanged in any other Reset.3(3(c0.3 Reset The PIC16F87XA differentiates between various kinds of Reset: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset (during normal operation) WDT Wake-up (during Sleep) Brown-out Reset (BOR) state” on Power-on Reset (POR).1( o Some registers are not affected in any Reset condition. DS39582B-page 147 .PIC16F87XA 14.0035 Tck)10.6(noco)12. on the MCLR and WDT Reset. on MCL3(3(3(3(30.

For example.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. Destination select. For literal and control operations. or the program counter is changed as a result of an instruction. a “CLRF PORTB” instruction will read PORTB. ‘f’ represents a file register designator and ‘d’ represents a destination designator. ‘b’ represents a bit field designator which selects the bit affected by the operation. If ‘d’ is zero. All instructions are executed within a single instruction cycle.  2003 Microchip Technology Inc. The destination designator specifies where the result of the operation is to be placed. Table 15-2 lists the instructions recognized by the MPASM™ Assembler. The formats for each of the categories is presented in Figure 15-1. For bit-oriented instructions. The file register designator specifies which file register is to be used by the instruction. do not use the OPTION and TRIS instructions. for an oscillator frequency of 4 MHz. The register is read. then write the result back to PORTB. ‘k’ represents an eight or eleven-bit constant or literal value One instruction cycle consists of four oscillator periods. Note: To maintain upward compatibility with future PIC16F87XA products. A read operation is performed on a register even if the instruction writes to that register. 15. the result is placed in the file register specified in the instruction. constant data or label Don't care location (= 0 or 1). k = 11-bit immediate value DS39582B-page 159 .1 READ-MODIFY-WRITE OPERATIONS CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. Program Counter Time-out bit Power-down bit d PC TO PD FIGURE 15-1: GENERAL FORMAT FOR INSTRUCTIONS 0 Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value 8 7 k (literal) 0 All instruction examples use the format ‘0xhh’ to represent a hexadecimal number. this gives a normal instruction execution time of 1 s. while the various opcode fields are summarized in Table 15-1. When this occurs. unless a conditional test is true. For byte-oriented instructions. the data is modified. TABLE 15-1: Field f W b k x OPCODE FIELD DESCRIPTIONS Description Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field. If ‘d’ is one. Default is d = 1. A complete description of each instruction is also available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023).PIC16F87XA 15. the execution takes two instruction cycles with the second cycle executed as a NOP. and the result is stored according to either the instruction or the destination designator ‘d’. where ‘h’ signifies a hexadecimal digit. This example would have the unintended result that the condition that sets the RBIF flag would be cleared. while ‘f’ represents the address of the file in which the bit is located. d = 0: store result in W. clear all the data bits. It is the recommended form of use for compatibility with all Microchip software tools. the result is placed in the W register. The assembler will generate code with x = 0. d = 1: store result in file register f.

b k k k k k k k k k Bit Clear f Bit Set f Bit Test f. Skip if 0 Increment f Increment f.PD Z LITERAL AND CONTROL OPERATIONS TO. b f.Z Z TO. .2 1. For example. d f f. the prescaler will be cleared if assigned to the Timer0 module.2 1. d f.DC.2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f..2.PIC16F87XA TABLE 15-2: Mnemonic. d f.2 1. d f.2 1.3 1. the data will be written back with a ‘0’. Skip if Set Add Literal and W AND Literal with W Call Subroutine Clear Watchdog Timer Go to Address Inclusive OR Literal with W Move Literal to W Return from Interrupt Return with Literal in W Return from Subroutine Go into Standby mode Subtract W from Literal Exclusive OR Literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 1.2 1. d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f.2 1. the value used will be that value present on the pins themselves.2.Z Z 2: 3: When an I/O register is modified as a function of itself ( e.Z Z 1. Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 01 01 11 11 10 00 10 11 11 00 11 00 00 11 11 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 00bb 01bb 10bb 11bb 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff bfff bfff bfff bfff kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff ffff kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C. d f. The second cycle is executed as a NOP.2 1. d = 1).DC.2 C C C.2 2 1.3 1. if the data latch is ‘1’ for a pin configured as input and is driven low by an external device.2 1.g. d f. MOVF PORTB.2 3 3 C. 1). Skip if Clear Bit Test f. If Program Counter (PC) is modified. d f.DC.2 1. or a conditional test is true. Operands PIC16F87XA INSTRUCTION SET 14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f. d f. d f. DS39582B-page 160  2003 Microchip Technology Inc.2 1.DC. d f. If this instruction is executed on the TMR0 register (and where applicable. b f. Note: Additional information on the mid-range instruction set is available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023).PD C. d f f. b f. the instruction requires two cycles.Z Z Z Z Z Z Z Z Z 1. d f. d f.

Z None Bit ‘b’ in register ‘f’ is set. making this a 2 TCY instruction. the result is stored back in register ‘f’. k 255 (W) (W) . If bit ‘b’ in register ‘f’ is ‘0’. If ‘d’ is ‘0’. the next instruction is executed.d BTFSC Syntax: Operands: Operation: Status Affected: Description: Bit Test. the result is stored back in register ‘f’.b 0 0 f 127 b 7 (W) .AND. If ‘d’ is ‘1’.2 ADDLW Syntax: Operands: Operation: Status Affected: Description: Instruction Descriptions Add Literal and W [ label ] ADDLW 0 k 255 (W) Operation: Status Affected: Description: (W) + k C.b (W) + (f) C.1] (destination) f.  2003 Microchip Technology Inc. (k) k BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f. If bit ‘b’ is ‘1’.d BSF Syntax: Operands: Operation: Status Affected: Description: Bit Set f [ label ] BSF 0 0 1 f 127 b 7 (f<b>) f. The result is placed in the W register. Skip if Clear [ label ] BTFSC f. DC. then the next instruction is discarded and a NOP is executed instead.PIC16F87XA 15. If ‘d’ is ‘0’. Add the contents of the W register with register ‘f’.1] (destination) f.b 0 0 f 127 b<7 skip if (f<b>) = 1 None If bit ‘b’ in register ‘f’ is ‘0’. DC. the result is stored in the W register. k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 0 0 f 127 b 7 (f<b>) f. Skip if Set [ label ] BTFSS f. If ‘d’ is ‘1’. (f) skip if (f<b>) = 0 None If bit ‘b’ in register ‘f’ is ‘1’. the result is stored in the W register. DS39582B-page 161 . the next instruction is executed. f 127 [0. making this a 2 TCY instruction. the next instruction is discarded and a NOP is executed instead. ANDLW Syntax: Operands: Operation: Status Affected: Description: AND Literal with W [ label ] ANDLW 0 Z The contents of W register are AND’ed with the eight-bit literal ‘k’. ADDWF Syntax: Operands: Operation: Status Affected: Description: Add W and f [ label ] ADDWF 0 d f 127 [0. Z The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register.b None Bit ‘b’ in register ‘f’ is cleared.AND. ANDWF Syntax: Operands: Operation: Status Affected: Description: AND W with f [ label ] ANDWF 0 d Z AND the W register with register ‘f’.

Status Affected: Description: CLRF Syntax: Operands: Operation: Status Affected: Description: Clear f [ label ] CLRF 0 f 127 00h (f) 1 Z Z The contents of register ‘f’ are cleared and the Z bit is set. Status Affected: Description: CLRWDT Syntax: Operands: Operation: PC<12:11> Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler. the result is stored in W. TO and PD. f 127 [0. First. k PC<10:0>. Zero bit (Z) is set. If ‘d’ is ‘1’.1] (destination) (f) . the result is stored back in register ‘f’. the result is stored in the W register. If ‘d’ is ‘1’.d 0 d Z Decrement register ‘f’. are set. . return address (PC+1) is pushed onto the stack. If ‘d’ is ‘0’.PIC16F87XA CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS.1 DS39582B-page 162  2003 Microchip Technology Inc.d CLRW Syntax: Operands: Operation: Status Affected: Description: Clear W [ label ] CLRW None 00h (W) 1 Z Z W register is cleared. 1 TO 1 PD TO. f COMF Syntax: Operands: Operation: Status Affected: Description: Complement f [ label ] COMF 0 d (f) Z The contents of register ‘f’ are complemented. Status bits. It also resets the prescaler of the WDT. DECF Syntax: Operands: Operation: Status Affected: Description: Decrement f [ label ] DECF f. The upper bits of the PC are loaded from PCLATH. If ‘d’ is ‘0’. The eleven-bit immediate address is loaded into PC bits <10:0>. the result is stored back in register ‘f’.1] (destination) f. (PCLATH<4:3>) None Call Subroutine. PD CLRWDT instruction resets the Watchdog Timer. f 127 [0. CALL is a two-cycle instruction.

INCF f. the next instruction is executed. the result is placed back in register ‘f’. (f)  2003 Microchip Technology Inc.1] (destination) f 127 [0. The result is placed in the W register. If ‘d’ is ‘1’. DS39582B-page 163 . making it a 2 TCY instruction.PIC16F87XA DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f. the result is placed in the W register. If ‘d’ is ‘1’. If ‘d’ is ‘0’. the result is placed back in register ‘f’. If ‘d’ is ‘0’.1] INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f. the result is placed in the W register. (f) + 1 (destination). IORWF f.d f 127 [0.1 (destination). If the result is ‘0’.OR. k IORLW k 255 (W) k PC<10:0> PCLATH<4:3> None (W) . the result is placed back in register ‘f’. GOTO is a two-cycle instruction. If ‘d’ is ‘1’.d IORWF Syntax: Operands: Operation: Status Affected: Description: Inclusive OR W with f [ label ] 0 d Z Inclusive OR the W register with register ‘f’. Skip if 0 [ label ] DECFSZ f.d 0 d f 127 [0. making it a 2 TCY instruction. If ‘d’ is ‘0’. Skip if 0 [ label ] 0 d INCFSZ f. If ‘d’ is ‘1’. a NOP is executed instead. If the result is ‘0’. skip if result = 0 None The contents of register ‘f’ are incremented. The eleven-bit immediate value is loaded into PC bits <10:0>. skip if result = 0 None The contents of register ‘f’ are decremented. If ‘d’ is ‘0’. k GOTO is an unconditional branch.1] (destination) (f) + 1 (W) .1] (f) .d f 127 [0. the next instruction is executed. the result is placed in the W register.OR. then a NOP is executed instead. the result is placed back in register ‘f’. the result is placed in the W register. INCF Syntax: Operands: Operation: Status Affected: Description: Increment f [ label ] 0 d Z The contents of register ‘f’ are incremented. If the result is ‘1’. The upper bits of PC are loaded from PCLATH<4:3>. GOTO Syntax: Operands: Operation: Status Affected: Description: Unconditional Branch [ label ] 0 k GOTO k 2047 PC<12:11> IORLW Syntax: Operands: Operation: Status Affected: Description: Inclusive OR Literal with W [ label ] 0 Z The contents of the W register are OR’ed with the eight-bit literal ‘k’. If the result is ‘1’.

is set. the result is placed back in register ‘f’. RRF Syntax: Operands: Operation: Status Affected: Description: Rotate Right f through Carry [ label ] 0 d C The contents of register ‘f’ are rotated one bit to the right through the Carry flag. Time-out status bit. TO.PIC16F87XA RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF 0 d C The contents of register ‘f’ are rotated one bit to the left through the Carry flag. the result is stored in the W register. DC. If ‘d’ is ‘0’.1] See description below (f) . If ‘d’ is ‘1’. Z Subtract (2’s complement method) W register from register ‘f’.d f 127 [0.(W) C. the result is placed in the W register. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. If ‘d’ is ‘0’. f. The processor is put into Sleep mode with the oscillator stopped. If ‘d’ is ‘1’. C Register f SUBWF Syntax: Operands: Operation: Status Affected: Description: Subtract W from f [ label ] SUBWF f. DS39582B-page 164  2003 Microchip Technology Inc.(W) Status Affected: C.1] (destination) RRF f. If ‘d’ is ‘0’. 1 TO. If ‘d’ is ‘1’. The result is placed in the W register. DC. the result is placed in the W register. PD. PC RETURN SUBLW Syntax: Operands: Operation: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 (W) k . PD The power-down status bit.d 0 d f 127 [0. 0 WDT prescaler. Z The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. C Register f SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT. This is a two-cycle instruction. Watchdog Timer and its prescaler are cleared. the result is stored back in register ‘f’. the result is stored back in register ‘f’. .1] See description below Status Affected: Description: RETURN Syntax: Operands: Operation: Status Affected: Description: Return from Subroutine [ label ] None TOS None Return from subroutine. is cleared. 0 PD TO.d f 127 [0.

If ‘d’ is ‘1’. k 255 (W) (W) . f 127 [0. DS39582B-page 165 .XOR. k  2003 Microchip Technology Inc. the result is stored in the W register.XOR. (destination<3:0>) XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF 0 d Z Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’.d 0 d f 127 [0.d (f<3:0>) (f<7:4>) (W) .PIC16F87XA SWAPF Syntax: Operands: Operation: Swap Nibbles in f [ label ] SWAPF f.1] (destination<7:4>). the result is placed in the W register. (f) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. The result is placed in the W register. XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR Literal with W [ label ] XORLW k 0 Z The contents of the W register are XOR’ed with the eight-bit literal ‘k’. If ‘d’ is ‘1’. the result is placed in register ‘f’.1] (destination) f. the result is stored back in register ‘f’. If ‘d’ is ‘0’.

.PIC16F87XA NOTES: DS39582B-page 166  2003 Microchip Technology Inc.

MPLAB C17 and MPLAB C18 C Compilers .2 MPASM Assembler The MPASM assembler is a full-featured.PICDEM USB Demonstration Board • Evaluation Kits .absolute listing file (mixed assembly and C) . universal macro assembler for all PICmicro MCUs.PRO MATE® II Universal Device Programmer . 16.PICDEM 3 Demonstration Board . DS39582B-page167 . The MPASM assembler generates relocatable object files for the MPLINK object linker.1 The PICmicro® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment . The MPLAB IDE is a Windows® based application that contains: • An interface to debugging tools .emulator (sold separately) .PICSTART® Plus Development Programmer • Low Cost Demonstration Boards . Intel® standard HEX files.MPLAB dsPIC30 Software Simulator • Emulators .PICDEM 18R Demonstration Board . This eliminates the learning curve when upgrading to tools with increasing flexibility and power. to full-featured emulators.PICDEM 4 Demonstration Board .CAN .MPLAB® IDE Software • Assemblers/Compilers/Linkers .PICDEMTM 1 Demonstration Board .microID® .programmer (sold separately) .PIC16F87XA 16.machine code MPLAB IDE supports multiple debugging tools in a single development paradigm.PICDEM 2 Plus Demonstration Board .source files (assembly or C) .simulator . The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process 2003 Microchip Technology Inc.MPLAB ASM30 Assembler/Linker/Library • Simulators .PICDEM 17 Demonstration Board .MPLAB ICE 4000 In-Circuit Emulator • In-Circuit Debugger .MPLAB C30 C Compiler .PowerSmart® .KEELOQ® . MAP files to detail memory usage and symbol reference. through low cost in-circuit debuggers. from the cost effective simulators.MPLAB SIM Software Simulator .PICDEM LIN Demonstration Board .netTM Demonstration Board . absolute LST files that contain source lines and generated machine code and COFF files for debugging.PICDEM MSC .in-circuit debugger (sold separately) • A full-featured editor with color coded context • A multiple project manager • Customizable data windows with direct edit of contents • High level source code debugging • Mouse over variable inspection • Extensive on-line help The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) • Debug using: .MPLINKTM Object Linker/ MPLIBTM Object Librarian .Analog MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market.PICDEM.MPLAB ICE 2000 In-Circuit Emulator .0 DEVELOPMENT SUPPORT 16.MPASMTM Assembler .MPLAB ICD 2 • Device Programmers .

. as well as the MPASM assembler. replacement. Linker. or Trace mode. MPLAB C30 compiler uses the assembler to produce it’s object file. The MPLIB object librarian manages the creation and modification of library files of pre-compiled code. and math functions (trigonometric. For easy source level debugging.5 MPLAB C30 C Compiler 16. ANSI compliant. On any given instruction. The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. dynamic memory allocation. The simulator runs in either a Command Line mode for automated tasks. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. timekeeping. the data areas can be examined or modified and stimuli can be applied from a file. the data areas can be examined or modified and stimuli can be applied from a file.7 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level.8 MPLAB SIM30 Software Simulator The MPLAB C30 C compiler is a full-featured.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. When a routine from a library is called from a source file. MPLAB C30 is distributed with a complete ANSI C standard library. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing. superior code optimization and ease of use not found with other compilers. 16. It can link relocatable objects from precompiled libraries. DS39582B-page 168 2003 Microchip Technology Inc. The execution can be performed in Single-Step. only the modules that contain that routine will be linked in with the application. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. These compilers provide powerful integration capabilities. Notable features of the assembler include: • • • • • • Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 16. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment. data conversion. to any of the pins. MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. analyze and optimize time intensive DSP routines. Execute Until Break. The compiler provides symbolic information for high level source debugging with the MPLAB IDE. and afford fine control of the compiler code generator. to any pin. This allows large libraries to be used efficiently in many different applications. deletion and extraction 16.6 MPLAB ASM30 Assembler.PIC16F87XA 16. exponential and hyperbolic). economical software development tool. This high speed simulator is designed to debug. using directives from a linker script. The compiler also supports many commandline options and language extensions to take full advantage of the dsPIC30F device hardware capabilities. the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The library includes functions for string manipulation. or user defined key press. or from MPLAB IDE.3 MPLAB C17 and MPLAB C18 C Compilers 16. making it an excellent. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers. All library functions have been validated and conform to the ANSI C library standard. or user defined key press. optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. and Librarian The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. On any given instruction.

Its advanced emulator features include complex triggering and timing.12 PRO MATE II Universal Device Programmer The PRO MATE II is a universal. building.13 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use. downloading and source debugging from a single environment. but with increased emulation memory and high speed performance for dsPIC30F and PIC18XXXX devices. which allows editing. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. It can also set code protection in this mode. 16. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. and the ability to view variables in real-time. 16. may be supported with an adapter socket. and program PICmicro devices without a PC connection. verify. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices. downloading and source debugging from a single environment. the PRO MATE II device programmer can read. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows 32-bit operating system were chosen to best make these features available in a simple. offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints. unified application. CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. which allows editing. up to 2 Mb of emulation memory. It connects to the PC via a COM (RS-232) port. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. DS39582B-page169 . run-time development tool. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. The PICSTART Plus development programmer is CE compliant. trigger and data monitoring features. is a powerful. prototype programmer. building. MPLAB ICD 2.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple. connecting to the host PC via an RS-232 or high-speed USB interface. 2003 Microchip Technology Inc.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator 16. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. providing the features of MPLAB ICE 2000. low-cost. Larger pin count devices. along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol. such as the PIC16C92X and PIC17C76X. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment. single-stepping and watching variables. unified application. The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types.10 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. In Stand-Alone mode. CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. 16. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. This feature. low-cost.PIC16F87XA 16. The MPLAB ICD 4000 is a premium emulator system.

including PIC17C752. Some of the features include an RS-232 interface. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. or MPLAB ICD 2 with a Universal Programmer Adapter. PCB footprints for H-Bridge motor driver. an Ethernet interface. including PIC16F87X and PIC18FXX2 devices.18 PICDEM 4 8/14/18-Pin Demonstration Board The PICDEM 4 can be used to demonstrate the capabilities of the 8. and a 16 x 2 LCD display. This kit features a user friendly TCP/IP stack. eight LEDs. 28-. 16.19 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers. 16.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. an on-board temperature sensor. PICSTART Plus development programmer. A prototype area extends the circuitry for additional application components. DB-9 RS-232 interface. four LEDs. four potentiometers. PIC16C71. PIC17C756A. PIC16C8X. or a PICSTART Plus development programmer. three push buttons and a prototyping area. ICD connector for programming via ICSP and development with MPLAB ICD 2. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer. PIC16C61. PIC16F87/88. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer. 16. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. and sample PIC18F452 and PIC16F877 Flash microcontrollers. All the necessary hardware and software is included to run the demonstration programs. Also included is the book and CD-ROM “TCP/IP Lean. Included with the kit is a PIC16F627A and a PIC18F1320. a five volt regulator for use with a nine volt wall adapter or battery.net Internet/Ethernet Demonstration Board The PICDEM. RC or Canned Oscillator modes. LIN transceiver and EEPROM. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. including LIN and Motor Control using ECCP. ICSP/MPLAB ICD 2 interface connector. Features include an RS-232 interface. a potentiometer for simulated analog input. Included on the demo board are provisions for Crystal. web server with HTML. 2x16 liquid crystal display. Special provisions are made for low power operation with the supercapacitor circuit. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing.PIC16F87XA 16.15 PICDEM. 16.14 PICDEM 1 PICmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A). Web Servers for Embedded Systems. a piezo speaker.16 PICDEM 2 Plus Demonstration Board The PICDEM 2 Plus demonstration board supports many 18-. PICDEM 4 is intended to showcase the many features of these low pin count parts. and 40-pin microcontrollers. A prototype area extends the circuitry for additional application components. a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM.” by Jeremy Bentham. push button switches and eight LEDs. PIC17C762 and PIC17C766. All the necessary hardware and software is included to run the demonstration programs. The PRO MATE II device programmer. or the PICSTART Plus development programmer. A programmed sample is included. including the PIC16F818/819. PIC17C42. PIC16F62XA and the PIC18F1320 family of microcontrollers. 16. and 18-pin PIC16XXXX and PIC18XXXX MCUs. A generous prototype area is available for user hardware expansion. PIC16C62X. . All necessary hardware and software is included to run basic demo programs. Tutorial firmware is included along with the User’s Guide. RS-232 interface. Also included are: header for expansion. DS39582B-page 170 2003 Microchip Technology Inc. PIC17C43 and PIC17C44. can be used to reprogram the device for user tailored application development. a 2 x 16 LCD display. and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. 14.17 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package.

high power IR driver.24 Evaluation and Programming Tools In addition to the PICDEM series of circuits. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory. 2003 Microchip Technology Inc. • KEELOQ evaluation and programming tools for Microchip’s HCS Secure Data Products • CAN developers kit for automotive network applications • Analog design boards and filter design software • PowerSmart battery charging evaluation/ calibration kits • IrDA® development kit • microID development and rfLabTM development software • SEEVAL® designer kit for memory evaluation and endurance calculations • PICDEM MSC demo boards for Switching mode power supply. evaluation and development of 8/14-pin Flash PIC® microcontrollers. the board operates under a simple Windows GUI. This board provides the basis for future USB products. Supports all current 8/14-pin Flash PIC microcontrollers. delta sigma ADC. the PICkit Flash Starter Kit includes a convenient multi-section board for programming. 16. software and hardware “Tips 'n Tricks for 8-pin Flash PIC® Microcontrollers” Handbook and a USB Interface Cable. 16. 16. and flow rate sensor Check the Microchip web page and the latest Product Line Card for the complete list of demonstration and evaluation kits. as well as serial EEPROM. 16. PICkit 1 tutorial software and code for various applications.PIC16F87XA 16. All three microcontrollers are programmed with firmware to provide LIN bus communication.22 PICkitTM 1 Flash Starter Kit A complete “development system in a box”. allowing access to the wide range of memory types supported by the PIC18C601/801. Microchip has a line of evaluation kits and demonstration software for these products. A PIC16F874 Flash microcontroller serves as the master. DS39582B-page171 .21 PICDEM LIN PIC16C43X Demonstration Board The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers.20 PICDEM 18R PIC18C601/801 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. Also included are MPLAB® IDE (Integrated Development Environment) software. as well as many future planned devices. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. The PICkit 1 Starter Kit includes the user's guide (on CD ROM). Powered via USB.

PIC16F87XA NOTES: DS39582B-page 172 2003 Microchip Technology Inc. .

.........................................................PIC16F87XA 17.............. may cause latch-up.................................................................................-55 to +125°C Storage temperature .......................................................0 to +14V Voltage on RA4 with respect to Vss ............................................................... ......300 mA Maximum current into VDD pin ................................... Exposure to maximum rating conditions for extended periods may affect device reliability..3V) Voltage on VDD with respect to VSS ..............................................................................................................................................................................................0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias........... -0............................................................................................. MCLR.................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3) ................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD...................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD ...25 mA Maximum output current sourced by any I/O pin .... PORTB and PORTE (combined) (Note 3)..................................................................................1...5V Voltage on MCLR with respect to VSS (Note 2) ................3V to (VDD + 0.......... – 20 mA Output clamp current......................................................250 mA Input clamp current.........0W Maximum current out of VSS pin ....VOH) x IOH} + ∑(VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin.................................................................. a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS..............................................................................................25 mA Maximum current sunk by PORTA.... DS39582B-page 173 .....................................∑ IOH} + ∑ {(VDD ........................................... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied.... IOK (VO < 0 or VO > VDD) ..................... -0........................................................0 to +8................. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.......... – 20 mA Maximum output current sunk by any I/O pin.......................... inducing currents greater than 80 mA..... 3: PORTD and PORTE are not implemented on PIC16F873A/876A devices............. and RA4) ...... IIK (VI < 0 or VI > VDD).................................. Thus.................... PORTB and PORTE (combined) (Note 3) .............................................  2003 Microchip Technology Inc.................200 mA Maximum current sourced by PORTA...........................................................................................5V Total power dissipation (Note 1) .............200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) ............................3 to +7..................................................................................

0 MHz/V) (VDDAPPMIN – 2.0V 3.0V 2.0V Voltage 4.5V 3. Note 2: FMAX has a maximum frequency of 10 MHz.5V 2. DS39582B-page 174  2003 Microchip Technology Inc.5V 4.PIC16F87XA FIGURE 17-1: PIC16F87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL. EXTENDED) 6. .5V 5.5V 5.0V 2.0V PIC16LF87XA 4 MHz 10 MHz Frequency FMAX = (6.0V 5.0V 20 MHz Frequency FIGURE 17-2: PIC16LF87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 3.5V 4.5V 3.0V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.0V PIC16F87XA Voltage 4.0V 5.5V 2.

PIC16F87XA 17. Other factors. These parameters are for design guidance only and are not tested.5 “Power-on Reset (POR)” for details V BODEN bit in configuration word enabled D005 VBOR 3.0 VBOR — — — — 1.65 4. MCLR = VDD.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial. internal code execution pattern and temperature.0 4. FMAX = 14 MHz(7) See Section 14. 3: The power-down current in Sleep mode does not depend on the oscillator type. all I/O pins tri-stated. 4: For RC osc configuration. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k . DS39582B-page 175 . 6: The current is the additional current consumed when this peripheral is enabled. such as I/O pin loading. † Data in “Typ” column is at 5V.  2003 Microchip Technology Inc.35 Legend: Rows with standard voltage device data only are shaded for improved readability.0 4.05 — — V/ms See Section 14. the device will operate correctly until the VBOR voltage trip point is reached. 2: The supply current is mainly a function of the operating voltage and frequency. 25°C. Power-down current is measured with the part in Sleep mode. unless otherwise stated. WDT enabled/disabled as specified. D001 D001 D001A D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Symbol VDD Characteristic/ Device Supply Voltage 16LF87XA 16F87XA 2. 7: When BOR is enabled. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. also have an impact on the current consumption. This value is from characterization and is for design guidance only. This current should be added to the base IDD or IPD measurement. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave. with all I/O pins in high-impedance state and tied to VDD and VSS. Extended) Param No.5 VSS 5.5 5. switching rate.5 “Power-on Reset (POR)” for details D004 SVDD 0. This is not tested. Extended) PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ† Max Units Conditions PIC16LF873A/874A/876A/877A (Industrial) PIC16F873A/874A/876A/877A (Industrial. oscillator type.5 — — V V V V V All configurations (DC to 10 MHz) All configurations BOR enabled. pulled to VDD. from rail-to-rail.5 5. Note 1: This is the limit to which VDD can be lowered without losing RAM data. current through REXT is not included.

Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ† Max Units Conditions PIC16LF873A/874A/876A/877A (Industrial) PIC16F873A/874A/876A/877A (Industrial. .PIC16F87XA 17. † Data in “Typ” column is at 5V.0V. MCLR = VDD. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave. 3: The power-down current in Sleep mode does not depend on the oscillator type. RC osc configurations. 4: For RC osc configuration. Note 1: This is the limit to which VDD can be lowered without losing RAM data. pulled to VDD. 7: When BOR is enabled.5) 16LF87XA 16F87XA 16LF87XA — — — 0. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. VDD = 5. VDD = 3. This value is from characterization and is for design guidance only.0V D013 D015 IBOR 16F87XA Brown-out Reset Current(6) — — 7 85 15 200 mA A Legend: Rows with standard voltage device data only are shaded for improved readability. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k .6 1. Extended) Param No. the device will operate correctly until the VBOR voltage trip point is reached. VDD = 3. from rail-to-rail.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial. unless otherwise stated. WDT disabled HS osc configuration. also have an impact on the current consumption.0 4 35 mA mA A XT. This current should be added to the base IDD or IPD measurement. with all I/O pins in high-impedance state and tied to VDD and VSS. FOSC = 20 MHz. RC osc configurations. Power-down current is measured with the part in Sleep mode.0V XT. DS39582B-page 176  2003 Microchip Technology Inc. 6: The current is the additional current consumed when this peripheral is enabled.5V LP osc configuration. all I/O pins tri-stated. FOSC = 32 kHz. FOSC = 4 MHz. such as I/O pin loading. Other factors.5V BOR enabled. 25°C. current through REXT is not included. VDD = 5. internal code execution pattern and temperature.6 20 2. These parameters are for design guidance only and are not tested. switching rate. 2: The supply current is mainly a function of the operating voltage and frequency. oscillator type. This is not tested. FOSC = 4 MHz. WDT enabled/disabled as specified. Symbol IDD D010 D010 D010A Characteristic/ Device Supply Current(2. VDD = 5.

VDD = 5.5) 16LF87XA 16F87XA — — 7. 7: When BOR is enabled.0V. WDT enabled/disabled as specified. 2: The supply current is mainly a function of the operating voltage and frequency. pulled to VDD. DS39582B-page 177 . WDT disabled.0V. current through REXT is not included. WDT enabled. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. MCLR = VDD.  2003 Microchip Technology Inc. WDT enabled.0V. Extended) Param No. switching rate. 3: The power-down current in Sleep mode does not depend on the oscillator type. also have an impact on the current consumption. WDT enabled. -40 C to +85 C VDD = 4. Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ† Max Units Conditions PIC16LF873A/874A/876A/877A (Industrial) PIC16F873A/874A/876A/877A (Industrial.0V D021 D021 16LF87XA 16F87XA — — 0. 25°C. oscillator type. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave. with all I/O pins in high-impedance state and tied to VDD and VSS. Power-down current is measured with the part in Sleep mode. -40 C to +85 C BOR enabled.0V. -40 C to +85 C VDD = 4. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 4: For RC osc configuration.9 1. This value is from characterization and is for design guidance only. all I/O pins tri-stated. WDT disabled. -40 C to +85 C VDD = 4. internal code execution pattern and temperature. -40 C to +125 C (extended) VDD = 3. Other factors. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k . -40 C to +125 C (extended) VDD = 3. WDT disabled. the device will operate correctly until the VBOR voltage trip point is reached. -40 C to +85 C VDD = 4.0V. This current should be added to the base IDD or IPD measurement.PIC16F87XA 17.0V.5 85 5 19 200 Legend: Rows with standard voltage device data only are shaded for improved readability.5 30 42 60 A A A A A A A A A VDD = 3.0V. 0 C to +70 C VDD = 4.9 1. WDT disabled. These parameters are for design guidance only and are not tested. 6: The current is the additional current consumed when this peripheral is enabled. This is not tested. † Data in “Typ” column is at 5V.5 5 16 20 D021A D021A D023 IBOR 16LF87XA 16F87XA Brown-out Reset Current(6) — 0. WDT disabled. such as I/O pin loading.0V. from rail-to-rail. Symbol IPD D020 D020 Characteristic/ Device Power-down Current(3.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial.5 10. unless otherwise stated.

15 VDD 0.3 VDD 0.2 VDD 0.6V 0. RA4/T0CKI OSC1 — — — — — — –1 –5 –5 A A A VSS VPIN VDD.5V VDD 5. † Data in “Typ” column is at 5V. -40°C TO +85°C with Schmitt Trigger buffer with SMBus Input High Voltage I/O ports: with TTL buffer 2.8 VDD 1.1) Characteristic Input Low Voltage I/O ports: D030 D030A D031 D032 D033 with Schmitt Trigger buffer MCLR. 25°C unless otherwise stated.5 with TTL buffer VSS VSS VSS VSS VSS VSS — — — — — — — — — 0. pin at high-impedance VSS VPIN VDD VSS VPIN VDD.5 to 5.0 0. Sym VIL * These parameters are characterized but not tested.5V 0.8V 0.5V VDD 5.5V Min Typ† Max Units Conditions DC CHARACTERISTICS Param No.5V For entire VDD range For entire VDD range VSS -0. It is not recommended that the PIC16F87XA be driven with external clock in RC mode. the OSC1/CLKI pin is a Schmitt Trigger input.7 VDD 1.3 VDD V V V V V V (Note 1) For entire VDD range 4.5 to 5.4 50 — — 250 VDD 5.2 VDD 0.8V 0. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level.8 VDD 0.5V VDD = 5V. HS and LP osc configuration 0.25 VDD + 0. Higher leakage current may be measured at different input voltages. DS39582B-page 178  2003 Microchip Technology Inc.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial. The specified levels represent normal operating conditions. Extended) PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Operating voltage VDD range as described in DC specification (Section 17. OSC1 (in RC mode) OSC1 (in XT and LP modes) OSC1 (in HS mode) Ports RC3 and RC4: D034 D034A VIH D040 D040A D041 D042 D042A D043 D044 D044A D070 IPURB IIL D060 D061 D063 with Schmitt Trigger buffer MCLR OSC1 (in XT and LP modes) OSC1 (in HS mode) OSC1 (in RC mode) Ports RC3 and RC4: with Schmitt Trigger buffer with SMBus PORTB Weak Pull-up Current Input Leakage Current(2.5 400 V V A For entire VDD range For VDD = 4. 3: Negative current is defined as current sourced by the pin. These parameters are for design guidance only and are not tested.6 V V For entire VDD range For VDD = 4.9 VDD — — — — — — — — VDD VDD VDD VDD VDD VDD VDD V V V V V V V (Note 1) 4. .7 VDD 0. XT. Note 1: In RC oscillator configuration.3V 0. VPIN = VSS.PIC16F87XA 17. 3) I/O ports MCLR.

5 mA. Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Operating voltage VDD range as described in DC specification (Section 17. -40 C to +85 C RA4 pin — — — — 0.7 VDD – 0. DS39582B-page 179 . -40 C to +85 C IOH = -1. † Data in “Typ” column is at 5V. VDD = 4. HS and LP modes when external clock is used to drive OSC1 VDD – 0. VMIN = min. -40 C to +85 C Min Typ† Max Units Conditions DC CHARACTERISTICS Param No.5V. VDD = 4.5V. It is not recommended that the PIC16F87XA be driven with external clock in RC mode.5 5. operating voltage Using EECON to read/write.5V. VDD = 4.6 V V IOL = 8. Sym VOL D080 D083 D101 D102 D120 D121 D122 D130 D131 D132A D133 CIO CB ED VDRW TDEW EP VPR All I/O pins and OSC2 (RC mode) SCL.0 mA.1) Characteristic Output Low Voltage I/O ports OSC2/CLKO (RC osc config) VOH D090 D092 D150* VOD Output High Voltage I/O ports(3) OSC2/CLKO (RC osc config) Open-Drain High Voltage Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial. VMIN = min. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level.3 mA.5 8 pF pF E/W -40 C to +85 C V ms E/W -40 C to +85 C V V ms VMIN = min. 25°C unless otherwise stated. VDD = 4.6 0. the OSC1/CLKI pin is a Schmitt Trigger input. SDA (I2C mode) Data EEPROM Memory Endurance VDD for read/write Erase/write cycle time Program Flash Memory Endurance VDD for read VDD for erase/write — — 100K VMIN — 10K VMIN VMIN — — — 1M — 4 100K — — 4 50 400 — 5.5V. Higher leakage current may be measured at different input voltages.7 — — — — — — 8.PIC16F87XA 17. -40 C to +85 C IOL = 1. These parameters are for design guidance only and are not tested. operating voltage TPEW Erase/Write cycle time * These parameters are characterized but not tested.6 mA. operating voltage Using EECON to read/write. 3: Negative current is defined as current sourced by the pin.  2003 Microchip Technology Inc.5 V V V IOH = -3. Note 1: In RC oscillator configuration.5 8 — 5. The specified levels represent normal operating conditions.

TABLE 17-2: VOLTAGE REFERENCE SPECIFICATIONS 3. -40°C < TA < +125°C (unless otherwise stated) Characteristics Resolution Absolute Accuracy Unit Resistor Value (R)* Settling Time*(1) Min VDD/24 — — — — Typ — — — 2k — Max VDD/32 1/2 1/2 — 10 s Units LSb LSb LSb Low Range (VRR = 1) High Range (VRR = 0) Comments Operating Conditions: Spec No. -40°C < TA < +85°C (unless otherwise stated) 4.5V. D300 D301 D302 300 300A 301 * Note 1: Sym VIOFF VICM CMRR TRESP TMC2OV These parameters are characterized but not tested.5 — 400 600 10 Units mV V dB ns ns s PIC16F87XA PIC16LF87XA Comments Operating Conditions: Param No. DS39582B-page 180  2003 Microchip Technology Inc. .0V < VDD < 5.PIC16F87XA TABLE 17-1: COMPARATOR SPECIFICATIONS 3.0V < VDD < 5. D310 D311 D312 310 * Note 1: Sym VRES VRAA VRUR TSET These parameters are characterized but not tested.5V.0V < VDD < 5.5V. Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.0 150 — Max ± 10 VDD – 1.0V < VDD < 5.5V. Response time measured with one comparator input at (VDD – 1. -40°C < TA < +125°C (unless otherwise stated) Characteristics Input Offset Voltage Input Common Mode Voltage* Common Mode Rejection Ratio* Response Time*(1) Comparator Mode Change to Output Valid* Min — 0 55 — — Typ ± 5. -40°C < TA < +85°C (unless otherwise stated) 4.5)/2 while the other input transitions from VSS to VDD.

TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low I2C only AA BUF output access Bus free T Time 3. 15 pF for OSC2 output Note: PORTD and PORTE are not implemented on PIC16F873A/876A devices. DS39582B-page 181 . TppS2ppS 2. TCC:ST 4.  2003 Microchip Technology Inc. but including PORTD and PORTE outputs as ports.PIC16F87XA 17.3 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. Ts (I2C specifications only) (I2C specifications only) osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z High Low Period Rise Valid High-impedance High Low TCC:ST (I2C specifications only) CC HD Hold ST DAT Data input hold STA Start condition SU STO Setup Stop condition FIGURE 17-3: LOAD CONDITIONS Load Condition 1 VDD/2 Load Condition 2 RL Pin VSS RL CL = 464 CL Pin VSS CL = 50 pF for all pins except OSC2.

These parameters are for design guidance only and are not tested. .5 15 — — — 4 TOSR. TOSF External Clock in (OSC1) Rise or Fall Time † Data in “Typ” column is at 5V.” values with an external clock applied to the OSC1/CLKI pin. All devices are tested to operate at “min. with the device executing code.25 Oscillator Period (Note 1) 2 3 TCY TOSL.1 4 5 Typ† — — — — — — — — — — — — — — — TCY — — — — — — Max 1 20 32 4 4 20 200 — — — — 1 250 250 — DC — — — 25 50 15 Units Conditions Symbol FOSC MHz XT and RC Osc mode MHz HS Osc mode kHz LP Osc mode MHz RC Osc mode MHz XT Osc mode MHz HS Osc mode kHz LP Osc mode ns ns s ns s ns ns s ns ns s ns ns ns ns XT and RC Osc mode HS Osc mode LP Osc mode RC Osc mode XT Osc mode HS Osc mode HS Osc mode LP Osc mode TCY = 4/FOSC XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator 1 TOSC External CLKI Period (Note 1) 1000 50 5 250 250 100 50 31. All specified values are based on characterization data for that particular oscillator type. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS39582B-page 182  2003 Microchip Technology Inc. TOSH Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time 200 100 2. under standard operating conditions. the “max. EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic External CLKI Frequency (Note 1) Min DC DC DC Oscillator Frequency (Note 1) DC 0. When an external clock input is used.” cycle time limit is “DC” (no clock) for all devices.PIC16F87XA FIGURE 17-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 2 CLKO 3 3 4 4 TABLE 17-3: Param No. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. 25°C unless otherwise stated.

DS39582B-page 183 . These parameters are asynchronous events not related to any internal clock edges. 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22††* 23††* Symbol CLKO AND I/O TIMING REQUIREMENTS Characteristic to CLKO to CLKO Min — — — — — TOSC + 200 0 — 100 200 0 — — — — TCY TCY Standard (F) Extended (LF) Standard (F) Extended (LF) Standard (F) Extended (LF) Typ† 75 75 35 35 — — — 100 — — — 10 — 10 — — — Max 200 200 100 100 0. 25°C unless otherwise stated.5 TCY + 20 — — 255 — — — 40 145 40 145 — — Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) TOSH2CKL OSC1 TOSH2CKH OSC1 TCKR TCKF TCKL2IOV TCKH2IOI TOSH2IOI CLKO Rise Time CLKO Fall Time CLKO to Port Out Valid TIOV2CKH Port In Valid before CLKO Port In Hold after CLKO (Q1 cycle) to Port Out Valid OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) TOSH2IOV OSC1 TIOV2OSH Port Input Valid to OSC1 TIOR TIOF TINP TRBP * † Port Output Rise Time Port Output Fall Time INT pin High or Low Time (I/O in setup time) RB7:RB4 Change INT High or Low Time †† Note 1: These parameters are characterized but not tested. 21 Note: Refer to Figure 17-3 for load conditions. TABLE 17-4: Param No.PIC16F87XA FIGURE 17-5: CLKO AND I/O TIMING Q4 OSC1 10 CLKO 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 15 New Value 19 18 12 16 11 Q1 Q2 Q3 20. Measurements are taken in RC mode where CLKO output is 4 x TOSC. These parameters are for design guidance only and are not tested.  2003 Microchip Technology Inc. Data in “Typ” column is at 5V.

DS39582B-page 184  2003 Microchip Technology Inc. . WATCHDOG TIMER. OSCILLATOR START-UP TIMER. These parameters are for design guidance only and are not tested. Data in “Typ” column is at 5V. -40°C to +85°C VDD = 5V. 25°C unless otherwise stated. OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O pins Note: Refer to Figure 17-3 for load conditions.PIC16F87XA FIGURE 17-6: RESET. 32 30 31 34 FIGURE 17-7: BROWN-OUT RESET TIMING VDD VBOR 35 TABLE 17-5: Param No.1 — Units s ms — ms s s VDD VBOR (D005) Conditions VDD = 5V. 30 31* 32 33* 34 35 * † RESET. -40°C to +85°C Symbol TMCL TWDT TOST TPWRT TIOZ TBOR These parameters are characterized but not tested. POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Min 2 7 — 28 — 100 Typ† — 18 1024 TOSC 72 — — Max — 33 — 132 2. -40°C to +85°C TOSC = OSC1 period VDD = 5V. WATCHDOG TIMER.

25°C unless otherwise stated. 40* 41* 42* Symbol TT0H TT0L TT0P TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0. 4.. 2.5 TCY + 20 10 0. 2. 8) 48 Standard(F) — — ns Extended(LF) — — ns FT1 Timer1 Oscillator Input Frequency Range — 200 kHz (oscillator enabled by setting bit T1OSCEN) TCKEZTMR1 Delay from External Clock Edge to Timer Increment 2 TOSC — 7 TOSC — * These parameters are characterized but not tested. 48 TABLE 17-6: Param No. These parameters are for design guidance only and are not tested. 8 Extended(LF) Asynchronous Standard(F) Extended(LF) T1CKI Input Synchronous Standard(F) Period Extended(LF) T1CKI High Time — — — — — — — — — — — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns Must also meet parameter 47 N = prescale value (1. Standard(F) Prescaler = 2. Standard(F) Prescaler = 2.5 TCY + 20 15 25 30 50 Greater of: 30 or TCY + 40 N Greater of: 50 or TCY + 40 N 60 100 DC Typ† — — — — — — Max — — — — — — Units ns ns ns ns ns ns Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2.PIC16F87XA FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 TMR0 or TMR1 Note: Refer to Figure 17-3 for load conditions. 4. 4.. Asynchronous  2003 Microchip Technology Inc. DS39582B-page 185 .5 TCY + 20 15 25 30 50 0. 256) Must also meet parameter 47 45* TT1H 46* TT1L 47* TT1P Synchronous. † Data in “Typ” column is at 5V. 8 Extended(LF) Asynchronous Standard(F) Extended(LF) T1CKI Low Time Synchronous..5 TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0. 4. Prescaler = 1 Synchronous. Prescaler = 1 Synchronous.. 8) N = prescale value (1. 4.

50* TCCL CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Characteristic CCP1 and CCP2 Input Low Time No Prescaler With Prescaler Standard(F) Extended(LF) Standard(F) Extended(LF) Min 0. These parameters are for design guidance only and are not tested. Data in “Typ” column is at 5V.5 TCY + 20 10 20 0.5 TCY + 20 10 20 3 TCY + 40 N Standard(F) Extended(LF) Standard(F) Extended(LF) — — — — Typ† Max Units — — — — — — — 10 25 10 25 — — — — — — — 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1. . DS39582B-page 186  2003 Microchip Technology Inc. 4 or 16) Conditions 51* TCCH CCP1 and CCP2 Input High Time No Prescaler With Prescaler 52* 53* 54* TCCP TCCR TCCF * † CCP1 and CCP2 Input Period CCP1 and CCP2 Output Rise Time CCP1 and CCP2 Output Fall Time These parameters are characterized but not tested. 25°C unless otherwise stated.PIC16F87XA FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 52 51 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 Note: Refer to Figure 17-3 for load conditions. 54 TABLE 17-7: Param Symbol No.

64 TABLE 17-8: Param No. Data in “Typ” column is at 5V. These parameters are for design guidance only and are not tested. 25°C unless otherwise stated. 62 63* 64 65 * † PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/877A ONLY) Characteristic Data In Valid before WR WR or CS (hold time) RD RD and CS or CS or CS (setup time) Standard(F) Extended(LF) to Data–out Valid to Data–out Invalid Min 20 20 35 — 10 Typ† — — — — — Max — — — 80 30 Units ns ns ns ns ns Conditions Symbol TDTV2WRH TWRH2DTI TRDL2DTV TRDH2DTI to Data–in Invalid These parameters are characterized but not tested.  2003 Microchip Technology Inc.PIC16F87XA FIGURE 17-10: RE2/CS PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY) RE0/RD RE1/WR 65 RD7:RD0 62 63 Note: Refer to Figure 17-3 for load conditions. DS39582B-page 187 .

76 Bit 6 . DS39582B-page 188  2003 Microchip Technology Inc.. 76 SDI MSb In 74 73 Note: Refer to Figure 17-3 for load conditions..-1 LSb LSb In FIGURE 17-12: SPI MASTER MODE TIMING (CKE = 1...-1 LSb SDI MSb In 74 Bit 6 . SMP = 1) SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79 SDO MSb 75. Bit 6 ... .....-1 Bit 6 .PIC16F87XA FIGURE 17-11: SS 70 SCK (CKP = 0) 71 72 78 79 SPI MASTER MODE TIMING (CKE = 0.. SMP = 0) SCK (CKP = 1) 79 78 80 SDO MSb 75..-1 LSb In Note: Refer to Figure 17-3 for load conditions.

-1 LSb In Note: Refer to Figure 17-3 for load conditions. DS39582B-page 189 . 76 Bit 6 ..PIC16F87XA FIGURE 17-13: SS 70 SCK (CKP = 0) 71 72 78 79 83 SPI SLAVE MODE TIMING (CKE = 0) SCK (CKP = 1) 79 MSb 75. 76 SDI MSb In 74 73 Note: Refer to Figure 17-3 for load conditions...-1 LSb 77 SDI MSb In 74 Bit 6 ..  2003 Microchip Technology Inc...-1 LSb 77 FIGURE 17-14: SS SPI SLAVE MODE TIMING (CKE = 1) 82 SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb 75. Bit 6 .....-1 LSb In 78 80 SDO Bit 6 ...

Data in “Typ” column is at 5V.PIC16F87XA TABLE 17-9: Param No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83* Symbol TSSL2SCH. 25°C unless otherwise stated. Stop Condition DS39582B-page 190  2003 Microchip Technology Inc. These parameters are for design guidance only and are not tested. TDOV2SCL TSSL2DOV TSCH2SSH. FIGURE 17-15: I2C BUS START/STOP BITS TIMING SCL 90 SDA 91 92 93 Start Condition Note: Refer to Figure 17-3 for load conditions. TSCL2DIL TDOR TDOF TSSH2DOZ TSCR TSCF TSCH2DOV. TSCL2DOV TDOV2SCH. TSSL2SCL TSCH TSCL TDIV2SCH.5 TCY + 40 Standard(F) Extended(LF) Typ† — — — — — 10 25 10 — 10 25 10 — — — — — Max — — — — — 25 50 25 50 25 50 25 50 145 — 50 — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions SCK Input High Time (Slave mode) SCK Input Low Time (Slave mode) Setup Time of SDI Data Input to SCK Edge Hold Time of SDI Data Input to SCK Edge SDO Data Output Rise Time SDO Data Output Fall Time SS to SDO Output High-Impedance SCK Output Rise Time (Master mode) SCK Output Fall Time (Master mode) SDO Data Output Valid after SCK Edge Standard(F) Extended(LF) SDO Data Output Setup to SCK Edge SDO Data Output Valid after SS SS after SCK Edge Edge These parameters are characterized but not tested. TDIV2SCL TSCH2DIL. TSCL2SSH * † SS to SCK SPI MODE REQUIREMENTS Characteristic or SCK Input Min TCY TCY + 20 TCY + 20 100 100 — — — 10 — — — Standard(F) Extended(LF) — — TCY — 1. .

the first clock pulse is generated FIGURE 17-16: I2C BUS DATA TIMING 103 100 101 102 SCL 90 91 106 107 92 SDA In 110 109 SDA Out Note: Refer to Figure 17-3 for load conditions. 109  2003 Microchip Technology Inc. 90 91 92 93 Symbol TSU:STA THD:STA TSU:STO THD:STO Characteristic Start condition Setup time Start condition Hold time Stop condition Setup time Stop condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Typ — — — — — — — — Max — — — — — — — — ns ns ns Units ns Conditions Only relevant for Repeated Start condition After this period. DS39582B-page 191 .PIC16F87XA TABLE 17-10: I2C BUS START/STOP BITS REQUIREMENTS Param No.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. before the SCL line is released.1 CB — 20 + 0.6 0 0 250 100 4.7 0. TR MAX.3 — Max — — — — — — 1000 300 300 300 — — — — — 0.0 0.5 TCY 4.5 TCY — 20 + 0.7 1.7 1. must then be met.6 0.0 0.6 4. it must output the next data bit to the SDA line. but the requirement that. TSU:DAT 250 ns.6 — — 4. .9 — — — — 3500 — — — 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification).7 0. DS39582B-page 192  2003 Microchip Technology Inc. the first clock pulse is generated Cb is specified to be from 10 to 400 pF s s Units s s Conditions 103 TF 90 91 106 TSU:STA THD:STA THD:DAT As a transmitter.1 CB 4. the device must provide this internal minimum delay time to bridge the undefined region (min. If such a device does stretch the LOW period of the SCL signal. A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system. 100 Sym THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode SSP Module 101 TLOW Clock Low Time 100 kHz mode 400 kHz mode SSP Module 102 TR SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Setup Time Start Condition Hold Time Data Input Hold Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 107 92 109 110 TSU:DAT TSU:STO TAA TBUF CB Note 1: 2: Data Input Setup Time 100 kHz mode 400 kHz mode Stop Condition Setup Time Output Valid from Clock Bus Free Time Bus Capacitive Loading 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4.PIC16F87XA TABLE 17-11: I2C BUS DATA REQUIREMENTS Param No.3 0.

PIC16F87XA FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 121 121 120 122 Note: Refer to Figure 17-3 for load conditions. These parameters are for design guidance only and are not tested. 25 C unless otherwise stated. TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param No. DS39582B-page 193 . 125 126 Symbol TDTV2CKL TCKL2DTL Characteristic SYNC RCV (MASTER & SLAVE) Data Setup before CK (DT setup time) Data Hold after CK (DT hold time) Min Typ† Max Units Conditions 15 15 — — — — ns ns † Data in “Typ” column is at 5V. 25 C unless otherwise stated.  2003 Microchip Technology Inc. TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120 Symbol Characteristic Min Typ† Max Units Conditions TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid TCKRF TDTRF Clock Out Rise Time and Fall Time (Master mode) Data Out Rise Time and Fall Time Standard(F) Extended(LF) Standard(F) Extended(LF) Standard(F) Extended(LF) — — — — — — — — — — — — 80 100 45 50 45 50 ns ns ns ns ns ns 121 122 † Data in “Typ” column is at 5V. FIGURE 17-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 17-3 for load conditions. These parameters are for design guidance only and are not tested.

PIC16F87XA TABLE 17-14: A/D CONVERTER CHARACTERISTICS:PIC16F873A/874A/876A/877A (INDUSTRIAL) PIC16LF873A/874A/876A/877A (INDUSTRIAL) Param No. it will not consume any current other than minor leakage current. DS39582B-page 194  2003 Microchip Technology Inc. VSS VAIN VREF VREF = VDD = 5. These parameters are for design guidance only and are not tested.12V. VSS VAIN VREF VREF = VDD = 5.12V.5 — — 5 Units bit LSb LSb LSb LSb — V V V V k A A A (Note 4) Average current consumption when A/D is on (Note 1) During VAIN acquisition. VSS VAIN VREF VSS VAIN VREF VREF+ Reference Voltage High VREF.Reference Voltage Low VAIN ZAIN IAD Analog Input Voltage Recommended Impedance of Analog Voltage Source A/D Conversion Current (VDD) PIC16F87XA PIC16LF87XA A50 IREF VREF Input Current (Note 2) — * † Note 1: 2: 3: 4: — 150 A These parameters are characterized but not tested.3V VREF+ – 2. whichever is selected as reference input. VSS VAIN VREF VREF = VDD = 5. VSS VAIN VREF VREF = VDD = 5.12V.3V VSS – 0. When A/D is off. During A/D conversion cycle Conditions VREF = VDD = 5.1 “A/D Acquisition Requirements”. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A30 A40 Sym NR EIL EDL EOFF EGN — VREF Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity Reference Voltage (VREF+ – VREF-) Min — — — — — — 2.12V. see Section 11. This requires higher acquisition time. Based on differential of VHOLD to VAIN to charge CHOLD.12V. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.3 AVDD + 0. . VREF current is from RA3 pin or VDD pin. 25°C unless otherwise stated.5V AVSS – 0.3V — — — — — — 220 90 — Typ† — — — — — guaranteed(3) — Max 10-bits <±1 <±1 <±2 <±1 — VDD + 0.0 AVDD – 2.0V VREF + 0. Maximum allowed impedance for analog voltage source is 10 k .3V 2. Data in “Typ” column is at 5V. The power-down current spec includes any such leakage from the A/D module.

0 3. Conditions TOSC based.6 3.0 12 — — Units s s s s TAD s s The minimum time is the amplifier settling time. 25°C unless otherwise stated. 2 1 0 NEW_DATA 131 BSF ADCON0. If the A/D clock source is selected as RC.. GO OLD_DATA SAMPLE Note: If the A/D clock source is selected as RC.0 2..0 9. This specification ensured by design.e.0V 2.12V) from the last sampled voltage (as stated on CHOLD). a time of TCY is added before the A/D clock starts. VREF TOSC based. This may be used if the “new” input voltage has not changed by more than 1 LSb (i. .  2003 Microchip Technology Inc.0 Typ† — — 4.0 6.PIC16F87XA FIGURE 17-19: A/D CONVERSION TIMING 1 TCY (TOSC/2)(1) Q4 130 A/D CLK A/D DATA ADRES ADIF GO Sampling Stopped DONE 132 9 8 7 . These parameters are for design guidance only and are not tested.0 — 40 — Max — — 6. This allows the SLEEP instruction to be executed. 20. TABLE 17-15: A/D CONVERSION REQUIREMENTS Param Symbol No. This allows the SLEEP instruction to be executed.0V 134 TGO Q4 to A/D Clock Start — TOSC/2 § — — * † § Note 1: 2: These parameters are characterized but not tested. See Section 11. a time of TCY is added before the A/D clock starts.0 mV @ 5. ADRES register may be read on the following TCY cycle.. Data in “Typ” column is at 5V...1 “A/D Acquisition Requirements” for minimum conditions. 130 TAD Characteristic A/D Clock Period PIC16F87XA PIC16LF87XA PIC16F87XA PIC16LF87XA 131 132 TCNV TACQ Conversion Time (not including S/H time) (Note 1) Acquisition Time (Note 2) 10* Min 1. DS39582B-page 195 . VREF A/D RC mode A/D RC mode 3.

.PIC16F87XA NOTES: DS39582B-page 196  2003 Microchip Technology Inc.

over the whole temperature range. “Typical” represents the mean of the distribution at 25 C.0V 1 3 0 4 6 8 10 12 FOSC (MHz) 14 16 18 20 FIGURE 18-2: 8 MAXIMUM IDD vs. where is a standard deviation.0V 3 2.5V 3. In some graphs or tables. the data presented may be outside the specified operating range (e.g..0V 2 2.PIC16F87XA 18. “Maximum” or “minimum” represents (mean + 3 ) or (mean – 3 ) respectively.0 Note: DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only.0V 4. DS39582B-page 197 .0V 3.5V IDD (mA) 4 4. FOSC OVER VDD (HS MODE) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.0V 5 IDD (mA) 4.5V 3. The performance characteristics listed herein are not tested or guaranteed.5V 2.5V 2 2.0V 4 3. FIGURE 18-1: 7 TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 6 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 4.0V 1 0 4 6 8 10 12 FOSC (MHz) 14 16 18 20  2003 Microchip Technology Inc.5V 5 5. outside the warranted range. outside specified power supply range) and therefore.5V 7 6 5.

5V 1.0V 0.5 IDD (mA) 4.0V IDD (mA) 1.5V 5.0V 1.5 MAXIMUM IDD vs.0V 0. FOSC OVER VDD (XT MODE) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2. FOSC OVER VDD (XT MODE) 1.0 5.8 TYPICAL IDD vs.PIC16F87XA FIGURE 18-3: 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 0.5V 4.4 0.0 3.2 0.5 0.0V 3.5V 5.8 3.5V 0.0 3.0V 2.0 0 500 1000 1500 2000 FOSC (MHz) 2500 3000 3500 4000 FIGURE 18-4: 2.6 2.4 1.2 4.5V 4.0 0 500 1000 1500 2000 FOSC (MHz) 2500 3000 3500 4000 DS39582B-page 198  2003 Microchip Technology Inc.0V 1. .0V 2.5V 2.

5V 5.0V 2.0V 20 0 20 30 40 50 60 FOSC (kHz) 70 80 90 100  2003 Microchip Technology Inc. DS39582B-page 199 .0V 3.5V 20 2.5V 40 IDD (uA) 4.0V 80 4. FOSC OVER VDD (LP MODE) 60 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 4.5V 30 3.PIC16F87XA FIGURE 18-5: 70 TYPICAL IDD vs.5V 3.0V 4.0V IDD (uA) 60 3.5V 50 5.5V 40 2.0V 10 0 20 30 40 50 60 FOSC (kHz) 70 80 90 100 FIGURE 18-6: 120 MAXIMUM IDD vs.0V 2. FOSC OVER VDD (LP MODE) 100 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.

0 3. +25 C) 2. C = 20 pF.5 10 kOhm 2.5 3.0 3.5 3. +25 C) 3.5 2.0 2.5 100 kOhm 0.0 5.0 0. VDD FOR VARIOUS VALUES OF R (RC MODE.5 VDD (V) 4.1 kOhm 1.5 5.0 2.0 4.5 AVERAGE FOSC vs.5 VDD (V) 4.0 2.0 2.0 5. VDD FOR VARIOUS VALUES OF R (RC MODE.1 kOhm 3.0 1.3 kOhm 1.5 5.0 10 kOhm 0.5 FIGURE 18-8: AVERAGE FOSC vs.0 4.5 100 kOhm 0. . C = 100 pF.PIC16F87XA FIGURE 18-7: 4.0 5.0 3.5 Freq (MHz) 5.5 DS39582B-page 200  2003 Microchip Technology Inc.5 Operation above 4 MHz is not recommended 4.5 1.0 Freq (MHz) 2.

PIC16F87XA
FIGURE 18-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, +25 C)

0.9

0.8 3.3 kOhm 0.7

0.6 5.1 kOhm Freq (MHz) 0.5

0.4 10 kOhm 0.3

0.2

0.1 100 kOhm 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5

FIGURE 18-10:
100

IPD vs. VDD, -40 C TO +125 C (SLEEP MODE, ALL PERIPHERALS DISABLED)

Max (125°C) 10

Max (85°C) 1 IPD (uA) 0.1 0.01 Typ (25°C)

Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C)

0.001 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5

 2003 Microchip Technology Inc.

DS39582B-page 201

PIC16F87XA
FIGURE 18-11: TYPICAL AND MAXIMUM ITMR1 vs. VDD OVER TEMPERATURE (-10 C TO +70 C, TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF)

14

12

Typical: statistical mean @ 25°C Maximum: mean + 3 (-10°C to +70°C) Minimum: mean – 3 (-10°C to +70°C) Max (+70°C) Max (70C)

10

8

( A) IPD (uA)

Typ (+25°C) Typ (25C)
6

4

2

0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5

FIGURE 18-12:
100

TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)

Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C)

10

Max (+125°C)

Max (+85°C)
IPD (uA)

Typ (+25°C)

1

0.1 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5

DS39582B-page 202

 2003 Microchip Technology Inc.

PIC16F87XA
FIGURE 18-13:
1,000

IBOR vs. VDD OVER TEMPERATURE

Max (125°C)

Typ (25°C) Indeterminant State Device in Reset 100 Device in Sleep

IDD ( A)

Note:

Device current in Reset depends on oscillator mode, frequency and circuit.

Max (125°C)

Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C)
10 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5

Typ (25°C)

5.0

5.5

FIGURE 18-14:
50

TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40 C TO +125 C)

45

40

Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C)

35 Max (125°C) WDT Period (ms) 30

25 Typ (25°C)

20

15

Min (-40°C)

10

5

0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5

 2003 Microchip Technology Inc.

DS39582B-page 203

5 5.0 1.5 Min 2.0 4.5 3.0 0 5 10 IOH (-mA) 15 20 25 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) DS39582B-page 204  2003 Microchip Technology Inc. . VDD OVER TEMPERATURE (-40 C TO +125 C) 45 40 125°C 35 85°C WDT Period (ms) 30 25°C 25 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 20 -40°C 15 10 5 0 2. -40 C TO +125 C) Max 3.0 3. MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V.5 4.0 TYPICAL.5 1.0 2.0 2.0 4.5 0.5 5.0 5.5 FIGURE 18-16: 5.5 VDD (V) 4.0 0.PIC16F87XA FIGURE 18-15: 50 AVERAGE WDT PERIOD vs.5 Typ (25°C) VOH (V) 3.

6 VOL (V) 0. DS39582B-page 205 .5 TYPICAL.0 0 5 10 IOH (-mA) 15 20 25 FIGURE 18-18: 1.PIC16F87XA FIGURE 18-17: 3.0 VOH (V) Typ (25°C) 1.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.0 0 5 10 IOL (-mA) 15 20 25  2003 Microchip Technology Inc.9 Max (125°C) 0. MINIMUM AND MAXIMUM VOL vs.4 0. -40 C TO +125 C) 0. -40 C TO +125 C) 3.7 Max (85°C) 0.3 Min (-40°C) 0.5 Max 2. IOH (VDD = 3V.5 Min 1. IOL (VDD = 5V.5 0.8 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0. MINIMUM AND MAXIMUM VOH vs.5 Typ (25°C) 0.1 0.0 0.0 TYPICAL.2 0.

VDD (TTL INPUT.3 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) VTH Max (-40°C) 1.5 MINIMUM AND MAXIMUM VIN vs. IOL (VDD = 3V.5 2.0 5.5 Max (85°C) 1.0 2.0 3. .0 4.5 3. -40 C TO +125 C) 1.2 1. -40 C TO +125 C) Max (125°C) 2.1 VTH Typ (25°C) VIN (V) 1. MINIMUM AND MAXIMUM VOL vs.5 5.PIC16F87XA FIGURE 18-19: 3.0 0 5 10 IOL (-mA) 15 20 25 FIGURE 18-20: 1.5 Min (-40°C) 0.6 0.0 Typ (25°C) 0.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.8 0.0 VOL (V) 1.7 0.5 DS39582B-page 206  2003 Microchip Technology Inc.0 0.4 1.5 VDD (V) 4.0 TYPICAL.9 VTH Min (125°C) 0.

0 2.5 VDD (V) 4.0 2.5 3.0 VIL Max (-40°C) 1.5 2.5 3.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) VIH Max (125°C) 3.0 4. -40 C TO +125 C) 3. DS39582B-page 207 .0 5.0 4.5 VDD (V) 4.PIC16F87XA FIGURE 18-21: 4.5 FIGURE 18-22: 3.0 3.5 5. VDD (I2C INPUT.0 5.5 VIN (V) VIH Min (-40°C) 2.5 MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.0 3.5 0.0 VIL Min (125°C) 0.0 VIL Min 0.0 2. -40 C TO +125 C) VIH Max 3.0 MINIMUM AND MAXIMUM VIN vs.5 5.5 0.0 2.5  2003 Microchip Technology Inc.5 1.5 1.0 2.0 VIN (V) VIL Max VIL Max VIH Min 1.

VREFH (VDD = 5V. -40 C TO +125 C) 3.5 3 3.5 1 0.5 Differential or Integral Nonlinearilty (LSB) 2 1.5 5 5.PIC16F87XA FIGURE 18-23: 4 A/D NONLINEARITY vs.5 DS39582B-page 208  2003 Microchip Technology Inc.5 5 5.5 Max (-40°Cto 125C) Max (-40C to +125°C) 1 Typ (+25°C) Typ (25C) 0.5 +125°C 125C 0 2 2. -40 C TO +125 C) 2.5 VREFH (V) 4 4.5 0 2 2.5 3 3. VREFH (VDD = VREFH.5 -40°C -40C Differential or Integral Nonlinearity (LSB) 3 +25°C 25C 2.5 +85°C 85C 2 1.5 4 4.5 VDD and VREFH (V) FIGURE 18-24: 3 A/D NONLINEARITY vs. .

* Standard PICmicro device marking consists of Microchip part number.X Y YY WW NNN Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line.PIC16F87XA 19. it will be carried over to the next line thus limiting the number of available characters for customer specific information.1 PACKAGING INFORMATION Package Marking Information 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F877A/P 0310017 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16F877A /PT 0310017 44-Lead PLCC Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16F877A -20/L 0310017 Legend: XX. For PICmicro device marking beyond this. year code. week code..0 19.  2003 Microchip Technology Inc. and traceability code. DS39582B-page 209 . certain price adders apply.. Please check with your Microchip Sales Office. For QTP devices. any special marking adders are included in QTP price.

.PIC16F87XA Package Marking Information (Cont’d) 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16F877A -I/ML 0310017 28-Lead PDIP (Skinny DIP) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F876A/SP 0310017 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F876A/SO 0310017 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC16F876A/ SS 0310017 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 16F873A -I/ML 0310017 DS39582B-page 210  2003 Microchip Technology Inc.

010” (0.070 Lower Lead Width B .015 A1 Shoulder to Shoulder Width E .680 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions.058 2.600 .012 .38 1.625 Molded Package Width E1 .545 .29 0.05 3.160 .620 .595 .190 Molded Package Thickness A2 .27 0.045 2. DS39582B-page 211 .PIC16F87XA 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) E1 D n E 2 1 A c A1 eB Units Dimension Limits n p INCHES* NOM 40 .530 .51 5 10 5 10 A2 L MIN MAX MIN MAX Number of Pins Pitch Top to Seating Plane A .76 1.150 B1 B p MILLIMETERS NOM 40 2.36 0.46 15.06 4.160 Base to Seating Plane .650 .022 Overall Row Spacing § eB .22 52.175 .100 .065 Tip to Seating Plane L .84 51.75 16.54 4.45 3.94 52.56 3. Mold flash or protrusions shall not exceed . C04-016 4.43 0.030 .38 15.018 .015 Upper Lead Width B1 .11 15.014 .27 15 15  2003 Microchip Technology Inc.30 0.050 .88 14.24 13.120 .45 3.83 4.26 3.008 .56 17.135 c Lead Thickness .140 .46 13.81 0.254mm) per side.20 0.06 15.130 . JEDEC Equivalent: MO-011 Drawing No.560 Overall Length D 2.78 0.

15 0.015 . C04-076 DS39582B-page 212  2003 Microchip Technology Inc.463 .10 0.00 9.041 .10 0.00 11.035 10 10 MAX MIN .10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D B n 2 1 CH x 45 A c L A1 (F) A2 Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff § Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH MIN .PIC16F87XA 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body.20 1.254mm) per side.037 .472 .25 10.472 .30 0.64 0.002 .75 12.5 11.0/0.00 9. .00 1.390 .463 .38 0.010” (0.030 7 .006 .018 0 .45 0. 1.10 0.25 12.80 11 1.039 . JEDEC Equivalent: MS-026 Drawing No.00 0.05 0.394 .017 .89 5 10 5 10 MAX 1.09 0.00 0 3.10 10.006 .398 .039 .043 .05 0. Mold flash or protrusions shall not exceed .15 0.390 .024 .008 .95 1.039 3.004 .012 .75 7 12.75 12.5 .031 11 .60 1.394 .44 1.20 0.482 .045 15 15 MILLIMETERS* NOM 44 0.025 5 5 INCHES NOM 44 .90 10.90 10.398 .004 .14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions.482 .047 .00 0.

53 16.685 .39 3.035 A3 Side 1 Chamfer Height .53 17.59 16.034 Corner Chamfer 1 CH1 .89 0.653 .045 .40 17.656 Molded Package Length D1 .650 .590 .59 14.011 .66 0.75 14.013 Upper Lead Width B1 .010 Overall Width E .165 .27 11 4.029 .40 17.14 0.75 0.153 .53 10 10  2003 Microchip Technology Inc.99 15.06 0.630 D2 c Lead Thickness .008 .653 .021 Lower Lead Width Mold Draft Angle Top 10 Mold Draft Angle Bottom 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions.87 0.99 15.026 .19 4.032 B .51 16.65 16.51 16. DS39582B-page 213 .000 .010” (0.33 0.013 .630 Footprint Length .690 .PIC16F87XA 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3 A2 35 A B1 B p c A1 E2 Units Dimension Limits n p INCHES* NOM 44 .685 .86 1. Mold flash or protrusions shall not exceed .13 17. C04-048 4.74 1.02 1.27 0.690 .00 16.695 Overall Length D .050 11 .050 Corner Chamfer (others) CH2 .51 0. JEDEC Equivalent: MO-047 Drawing No.20 0.024 .81 0.57 4.590 .00 0.040 .65 17.650 .25 17.029 .020 0 5 0 5 D2 MILLIMETERS NOM 44 1.656 Footprint Width E2 .66 16.254mm) per side.51 0 5 0 5 MIN MAX MIN MAX Number of Pins Pitch Pins per Side n1 Overall Height A .173 .66 16.160 Molded Package Thickness A2 Standoff § A1 .74 0.620 .695 Molded Package Width E1 .33 0.620 .180 .005 .27 0.61 0.68 3.71 0.020 .00 0.028 .145 .

05 6.35 0.010 REF .262 .274 . JEDEC equivalent: M0-220 Drawing No.80 8.016 MAX MIN .013 .45 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions.02 0 0.002 .262 .PIC16F87XA 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) E EXPOSED METAL PAD p D D2 2 1 n OPTIONAL PIN 1 INDEX ON TOP MARKING PIN 1 INDEX ON EXPOSED PAD E2 L B TOP VIEW BOTTOM VIEW A A1 A3 Number of Pins Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length Units Dimension Limits n p A A1 A3 E E2 D D2 B L MIN .40 MAX 1.031 .00 0.30 0.268 .000 .00 BSC 6.65 6.95 0.014 INCHES NOM 44 .315 BSC .274 .012 .95 6.33 0.010" (0.026 BSC .25 REF 8.80 0.65 6.039 .80 0.268 .65 BSC 0.001 .254mm) per side. Mold flash or protrusions shall not exceed .013 .018 MILLIMETERS* NOM 44 0.90 0.315 BSC .35 0.00 BSC 6.035 . C04-103 DS39582B-page 214  2003 Microchip Technology Inc. .

56 3.019 .38 7.49 35.015 .275 1.48 8.125 .18 0.125 .62 6.310 .87 7.16 3.33 0.135 MAX MIN MILLIMETERS NOM 28 2.99 34.430 15 15 . C04-070  2003 Microchip Technology Inc.30 4. JEDEC Equivalent: MO-095 Drawing No.92 15 15 3.325 .24 34.30 0.54 3.67 3.254mm) per side.016 .295 1.140 .38 1.56 10.053 .015 .285 1.20 1. DS39582B-page 215 .350 10 10 .130 .43 MAX * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions.010” (0.130 .160 .385 .65 0.150 .365 .26 7.13 5 5 7.022 . Mold flash or protrusions shall not exceed .89 10 10 8.06 3.43 0.29 1.PIC16F87XA 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) E1 D 2 n 1 E A2 A L A1 B1 B p c eB Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom § Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN INCHES* NOM 28 .065 .18 3.008 .02 0.300 .040 .41 8.012 .100 .320 5 5 .18 0.81 3.345 .135 .

74 1.014 0 0 .254mm) per side.08 0.87 0.050 8 .27 8 0.299 .712 .23 0.39 0.012 .31 0.008 .59 18.013 . .010 .28 0.010” (0.009 .088 .49 17. C04-052 DS39582B-page 216  2003 Microchip Technology Inc.020 .33 0.094 .093 .67 7.091 .42 0 12 0 12 MIN MAX MIN MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic .394 .01 10.24 2.36 2.695 .099 .65 17.50 0. Mold flash or protrusions shall not exceed . 300 mil (SOIC) E E1 p D B n h 45 c A A2 2 1 L Units Dimension Limits n p A A2 A1 E E1 D h L c B A1 INCHES* NOM 28 .016 0 .288 .011 .104 . JEDEC Equivalent: MS-013 Drawing No.704 .51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions.PIC16F87XA 28-Lead Plastic Small Outline (SO) – Wide.004 .84 0 4 0.36 0.407 .020 15 15 2.32 7.50 2.27 2.029 .10 0.017 12 12 MILLIMETERS NOM 28 1.295 .033 4 .41 0.20 10.30 10.25 0.34 7.050 .64 2.420 .

60 203.75 0.83 0.11 5.25 5.026 .94 0.010 0 0 INCHES NOM 28 .037 .85 1.309 .38 10. C04-073  2003 Microchip Technology Inc.05 0.407 .18 0.013 5 5 MAX MIN .064 .PIC16F87XA 28-Lead Plastic Shrink Small Outline (SS) – 209 mil.59 7.212 . Mold flash or protrusions shall not exceed .38 0 5 10 0 5 10 Notes: Dimensions D and E1 do not include mold flash or protrusions.15 0.10 0.10 5.06 10.004 0 .010 8 .98 1.015 10 10 MILLIMETERS* NOM MAX 28 0.34 0.201 .20 0.56 0.32 0.030 .006 .25 0.73 1.73 1.207 .299 .319 .63 1.25 7.65 1.078 .007 4 .00 101.072 . DS39582B-page 217 .396 .25 0.20 10. 5.022 .85 8.068 .30 mm (SSOP) E E1 p D B n 2 1 A c A2 A1 L Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B MIN .002 .010 . JEDEC Equivalent: MS-150 Drawing No.068 .402 .073 .010” (0.254mm) per side.

236 BSC .75 BSC 3.002 .17 0.024 .30 0.80 0.PIC16F87XA 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body.140 .254mm) per side.024 12° MILLIMETERS* NOM 28 0.75 BSC 3.50 0.009 .026 .85 0.65 BSC 0.152 . C04-114 DS39582B-page 218  2003 Microchip Technology Inc.008 REF .70 0.28 0.23 0.026 .40 0. .05 3.85 0.23 0.152 .026 BSC .146 .039 .13 0.009 INCHES NOM 28 .65 0.016 .011 .55 3.226 BSC .85 3.65 0.01 0.60 0.010" (0.140 .00 0.010 .033 .005 .226 BSC .00 BSC 5.012 .030 .42 MAX 1.020 .031 .20 REF 6.60 12° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions.75 0.35 0.014 . JEDEC equivalent: mMO-220 Drawing No.146 .007 .00 0.0004 .017 MAX MIN .55 3.24 0.000 .236 BSC .70 6. Mold flash or protrusions shall not exceed . Punch Singulated (QFN) E E1 EXPOSED METAL PADS Q D1 2 1 n R CH X 45° E2 L B D D2 p TOP VIEW BOTTOM VIEW A2 A1 A3 A Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Width Molded Package Width Exposed Pad Width Overall Length Molded Package Length Exposed Pad Length Lead Width Lead Length Tie Bar Width Tie Bar Length Chamfer Mold Draft Angle Top Units Dimension Limits n p A A2 A1 A3 E E1 E2 D D1 D2 B L R Q CH MIN .00 BSC 5.

B. B. TABLE B-1: DIFFERENCES BETWEEN DEVICES IN THE PIC16F87XA FAMILY PIC16F873A PIC16F874A 4K 192 128 15 Ports A. USART Yes 8 input channels 40-pin PDIP 44-pin PLCC 44-pin TQFP 44-pin QFN PIC16F876A 8K 368 256 14 Ports A. D. E MSSP. C MSSP. DS39582B-page 219 . C. USART No 5 input channels 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN PIC16F877A 8K 368 256 15 Ports A. E MSSP. USART Yes 8 input channels 40-pin PDIP 44-pin PLCC 44-pin TQFP 44-pin QFN Flash Program Memory (14-bit words) Data Memory (bytes) EEPROM Data Memory (bytes) Interrupts I/O Ports Serial Communications Parallel Slave Port 10-bit Analog-to-Digital Module Packages 4K 192 128 14 Ports A.PIC16F87XA APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (November 2001) Original data sheet for PIC16F87XA devices. The differences between the devices in this data sheet are listed in Table B-1. The devices presented are enhanced versions of the PIC16F87X microcontrollers discussed in the “PIC16F87X Data Sheet” (DS30292). C. Revision B (October 2003) This revision includes the DC and AC Characteristics Graphs and Tables. B. USART No 5 input channels 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN  2003 Microchip Technology Inc. D.0 “Electrical Characteristics” have been updated and there have been minor corrections to the data sheet text. The Electrical Specifications in Section 17. C MSSP. B.

I2C Slave) 20 MHz 2. SSP (SPI.0V-5.5V 10-bit. I2C Master/Slave) 20 MHz 2.5V 10-bit. SSP (SPI.2V-5. 256 bytes Segmented. TABLE C-1: Pins Timers Interrupts Communication Frequency Voltage A/D CCP Comparator CONVERSION CONSIDERATIONS PIC16C7X 28/40 3 11 or 12 PSP. USART. I2C Master/Slave) 20 MHz 2. Low-Voltage Programming DS39582B-page 220  2003 Microchip Technology Inc.PIC16F87XA APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.5V 8-bit. 8K EPROM PIC16F87X 28/40 3 13 or 14 PSP. 4 conversion clock selects 2 — — 4K. Low-Voltage Programming Characteristic Comparator Voltage Reference Program Memory RAM EEPROM Data Code Protection Program Memory Write Protection Other 192. USART. 368 bytes 128. . 368 bytes 128. 256 bytes On/Off Segmented. 368 bytes None On/Off — In-Circuit Debugger. starting at end of program memory On/Off PIC16F87XA 28/40 3 14 or 15 PSP. 7 conversion clock selects 2 2 Yes 4K. 4 conversion clock selects 2 — — 4K. starting at beginning of program memory In-Circuit Debugger. SSP (SPI.5V-5. USART. 8K Flash (Erase/Write on single-word) 192. 8K Flash (Erase/Write on four-word blocks) 192.

............. See USART............................................................................... 138 Comparator Voltage Reference ...... 65 CCP Timer Resources .............. 168 MPLAB C18 ................................................. See Brown-out Reset..................................................... 155 BOR................................. 97 Associated Registers ................................................................... 153 MSSP (I2C Mode) ............................... 131 Conversions ............................................................... BCLIF ................... 118... 67 Duty Cycle ......... 30 Assembler MPASM Assembler ................. 7 PORTC Peripheral Output Override (RC2:0............................... 130 Operation During Sleep ........................................... 49................... 101 Block Diagrams A/D ....................... 194 Effects of a Reset .... 19 ADRESL Register ..... 130 Configuring Analog Port Pins .................... 28 C C Compilers MPLAB C17 ......................................................... 129 ADRESH Register ..................................................... 42 RB3:RB0 Pins ............................ 167 Asynchronous Reception Associated Registers ....... 127 Analog Port Pins ..................... 71 On-Chip Reset Circuit ......... 129 Internal Sampling Switch (Rss) Impedance .................. BRG............. RC7:5) Pins ...................... 113 Brown-out Reset (BOR) .... Application Notes AN552 (Implementing Wake-up on Key Stroke) ......................................... 150 BOR Status (BOR Bit) .............. ADRESH Register ........... 68 PWM and Timer2 ........................................................... 195 Absolute Maximum Ratings ................................................................................................... Compare and Timer1 ................................................................................. 19 ADCON1 Register ............................................................................ 115 Watchdog Timer ........................................................ 139 Baud Rate Generator ........... 127 ADIF Bit ..................................................... 66 Compare Mode ...................... 143....................... 65 Prescaler ............................................ 22 Baud Rate Generator . 148 Simplified PWM Mode ........................ 48 PORTD and PORTE (Parallel Slave Port) ................... 133 Calculating Acquisition Time ............................................................................................................................................................................................................... See Baud Rate Generator................ DS39582B-page 221 ............................................................ 42 RA5 Pin ......................................... 173 ACKSTAT .............................................................. 29 Bus Collision During a Repeated Start Condition ..................... 41 RA4/T0CKI Pin .......... 116 Interrupt Logic ................................. 66 Special Event Trigger .......... 130 ADCON0 Register ..... 46 PORTD (in I/O Port Mode) ............................................ 113 BCLIF ............................................ 63 Associated Registers Capture................................. 147 PIC16F873A/PIC16F876A Architecture ............................................................................................................................................................................................................................ 66 Software Interrupt Mode ............................... 132 Source Impedance ...................................................................... 80 MSSP (SPI Mode) .................................................. XT or LP Osc Configuration) ...... 129 Analog Input Model ................................................................................. 16.... 130 A/D Conversion Requirements ................... 46 Peripheral Output Override (RC4:3) Pins .......................... 97 Capture Mode Operation ..................... 136 Comparator Output .................................................................................. 66 Crystal/Ceramic Resonator Operation (HS.......................... BRGH Bit ....... 20 Analog-to-Digital Converter..... 61 USART Receive .. 129 Conversion Clock ........................... 131 Configuring the Interrupt ................................................. 119 USART Transmit .......................... 127 ADRESL Register ................ 132 Converter Characteristics ............................................................ 51 Associated Registers and Bits ............................................................................... 133 Result Registers ......................................... See A/D.. 44 RC Oscillator Mode ................................ 53 Timer1 ................................. 148. 28 BF ...... 65 Comparator I/O Operating Modes .............. 108 Bus Collision During a Start Condition ........................ 142 Compare Mode Operation ................................................................................ 44 AN556 (Implementing a Table Read) ............................................................. 67 Timer0/WDT Prescaler ......... 149..................................................... 51 PORTE (In I/O Port Mode) ........................................ 65 CCP1IF ............................................................................... 66 Interaction of Two CCP Modules (table) .......................................................... 147........................................................................................................... 129 Configuring the Module ..........117............................. 145 External Clock Input Operation (HS..................................... 109 Bus Collision Interrupt Flag bit............. XT or LP Osc Configuration) .............. 168 Capture/Compare/PWM (CCP) ............................................................. 68 PWM Period ................... 63 PWM Mode ............................... 20 Addressable Universal Synchronous Asynchronous Receiver Transmitter................................................................................................. 58 Timer2 ....................... 168 MPLAB C30 ......................................................................... 145  2003 Microchip Technology Inc........................................................................... Data Memory ............................... 106 Bus Collision During a Stop Condition . 63 Compare Special Event Trigger Output of CCP1 .................... 127 Acquisition Requirements ......... 127 ADCON1 Register ........................................................... 146 Recommended MCLR Circuit ................................................... 49 RA3:RA0 Pins ................................................................................................. 66 Special Event Trigger Output of CCP2 ........................... 101 ADCON0 Register ...........................................................PIC16F87XA INDEX A A/D ............... 130.... 6 PIC16F874A/PIC16F877A Architecture ........................ 44 RB7:RB4 Pins .............................. 120 Asynchronous Transmission Associated Registers ............................................... 67 Special Event Trigger and A/D Conversions ................................................... 66 B Banking................. 69 Capture Mode ................................................... 133 GO/DONE Bit ........................................................ 67 Example Frequencies/Resolutions (table) ......................

......................net Internet/Ethernet .................................. 36 Writing .......... 35 Writing to Flash Program Memory ........... 143 Configuration Word .................. 139 Outputs ...................... 16 Bank Select (RP1:RP0 Bits) ........................................................................................ 171 PICDEM.......................................... 21 Electrical Characteristics ......................... 4 Evaluation and Programming Tools ................................ 143................................... 170 PICDEM 4 .............................................................................................................................. 31 D Data EEPROM and Flash Program Memory EEADR Register ............................ 63 CCPR2H Register . 19 DC and AC Characteristics Graphs and Tables ................................................................................................................................................................................................. 33 EECON2 Register ......... 41 Loading the SSPBUF (SSPSR) Register ............................................. 135 Analog Input Connection Considerations ..................................................................... 33 Reading ........................................................................................ 64 CCPxM1 Bit .................... 64 CCPxY Bit ............................................. External Reference Signal .... 20 Data EEPROM Memory Associated Registers .................................. 35 Write Complete Flag Bit (EEIF) ........................PIC16F87XA Capture/Compare/PWM Requirements (CCP1 and CCP2) ................................. 30 Configuration Bits ... 64 CLKO and I/O Timing Requirements .......................................................................... 142 Computed GOTO ...................... 170 PICDEM LIN PIC16C43X ................................. 33 Operation During Code-Protect ............. 171 PICDEM 2 Plus ....................... CCP1CON Register .................... 33 EEDATA Register .............................................. 16 Register File Map .......... 154 Writing to Data EEPROM ................... 137 F Firmware Instructions ........................................................ 33 EECON2 Register ............................... 21 EEDATH Register ....21................................... 140 Configuration ....................................................................................................................................................................................................................... 64 CCPxM2 Bit ...................... 33 EECON1 Register . 170 PICDEM 17 .............. 33 EEADRH Register ............................... 141 Associated Registers ....................................................... 63 CCPR1L Register .................................................................... 33 EEDATA Register ...................................................... 157 Comparator Module ......................................................................................................................... 186 CCP...... 19................................... 33 EEADRH Register ......................... 18 Special Function Registers ............................................ 33 Writing .......................................................................... 63 CCPxM0 Bit ........ 30 Indirect Addressing ........................... 20 Code Examples Call of a Subroutine in Page 1 from Page 0 ..... 180 Comparator Voltage Reference ............................................................................................................................................................. 33 EECON1 Register ....... 170 PICDEM 3 PIC16C92X .............................. W and PCLATH Registers in RAM ......................................... See Capture/Compare/PWM...................................... 19 CCPR1H Register ............................................ 35 Data Memory ............................................................................. 64 CCPxX Bit ... 5 Direct Addressing ....... 38 Code Protection ........................................................................................................................................................................ 39 Reading ......................... 33 EECON2 Register ................................................. 138 Operation .......................... 171 PICDEM USB PIC16C7X5 .............................. 36 Saving Status.................... 137 Reference . 197 DC Characteristics ...................... 159 Flash Program Memory Associated Registers ........... See Interrupt Sources..........................175–179 Demonstration Boards PICDEM 1 .............. 144 Conversion Considerations . 19 CCP2CON Register . 182 External Interrupt Input (RB0/INT).................................................................................................................................................................................. 137 Response Time ........... 39 EECON1 Register ....... 39 EEADR Register ..... 171 External Clock Timing Requirements ............................................... 33 EEADRH Register ............19......................................... 137 Comparator Specifications ............................................... 33 EECON2 Register ......................................... 37 FSR Register ............................................................. 19..................................................... 183 CMCON Register ................................... 20......................17...............................................................16........................................... 22 General Purpose Registers ............................................... 167 Device Differences ....................................................... 63 CCPR2L Register ............................................. 170 Development Support ........................... 19................................ 39 Protection Against Spurious Writes .........................................................................................................................21.................. 33 G General Call Address Support . 220 CVRCON Register .............. 64 CCPxM3 Bit ............... 219 Device Overview .....................................................................................................................................................................................................................................................................................................................21...... ............................... 94 DS39582B-page 222  2003 Microchip Technology Inc............................ 31 Initializing PORTA ....................................... 139 Interrupts ................... 74 Reading Data EEPROM ........................ 31 E EEADR Register ............................................... 173 Errata .................................................... 170 PICDEM 18R PIC18C601/801 ..................... 35 Reading Flash Program Memory ........................................... 33 EEDATH Register .......................................... 137 Operation During Sleep ......................................................................................................................................................21......................................................................................................................................................... 19............................................................................................................. 136 Effects of a Reset ............................................................ 33 EECON1 Register .................... 139 Associated Registers ..........

.... 100 Master Mode Reception .................................... Sleep ............................................................ 162 DECFSZ ............... 24 INTF Bit .................................................................................................................. Context Saving During ................................................ 84 Addressing ........ 24 TMR0 Overflow Flag (TMR0IF Bit) .......... 154 TMR0 Overflow ............................................................. 26 Interrupts............................................. 44..........................................................24....................................................................................................................................... 163 RETURN .........................................24........................... 30 Low-Voltage ICSP Programming ........ 143.........................................................................................................................19................................................................ 164 SWAPF ...... Librarian ........... 149............................................................................................................ 16 Flash Program Memory .................................................. 96 Repeated Start Timing ....... 105 General Call Address Support ................................143.......................................................................................... 24............................................................................................................ 44 TMR0IE Bit ............... 24 RBIE Bit ........................................ 162 COMF .............................................................. 33 Data Memory .............24........................................................ 24 PEIE Bit ............................................................................................ 31 Indirect Addressing ...................... Bus Collision and Arbitration ..................................................................................... 163 INCFSZ .................................................. 108 Start Condition ........... 191 I2C Mode Registers ...................... 24 Inter-Integrated Circuit................................ 101 Master Mode Start Condition ...... 154 RB0/INT Flag (INTF Bit) ............................. 84............ 104 Baud Rate Generator ................................ See MSSP........................ 158 INDF Register .......................... External ........... 169  2003 Microchip Technology Inc.................................................................... 164 SLEEP ............................................................. 15 MPLAB ASM30 Assembler............ 159 ADDLW .. 164 RLF ................................................................... 33 Program Memory ................... 109 Clock Arbitration .............................................. 85 Sleep Operation ........................................... 153 Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit) ....... 165 XORLW ............................................................................................. 161 ANDLW .......................................................... 80 I2C Mode ................................... 85 Transmission .............. 162 CLRWDT ............... 161 BTFSC ........... 85 Slave Mode ............................................................................................ 150 Master Synchronous Serial Port (MSSP)....................................................... 85 Serial Clock (RC3/SCK/SCL) .......... 154 USART Receive/Transmit Complete ............................................................................................................................................................................................ 24 INTE Bit ................... 164 SUBWF .............................................................................................................. 105 Multi-Master Mode .................. 154 L Loading of PC ................................................................. Normal Operation ........................ 147.................... 143............................. 161 BTFSS ...................................................................................................................PIC16F87XA I I/O Ports .................... 24 GIE Bit .............. 85 Acknowledge Sequence Timing ............................................. 98 Effect of a Reset ....................................................................... 10 Memory Organization . 41 I2C Bus Data Requirements ................................... 165 XORWF ............................................ Internal Reference Signal . 24 TMR0IF Bit ......... 163 GOTO .. 111 Interrupts Bus Collision Interrupt ..................................................................................................................................................................................... 161 CALL ......................... 24 RBIF Bit ............ 95 Operation ......... 16 Instruction Format . 9. 24 TMR0 Overflow Enable (TMR0IE Bit) .......... 154 Peripheral Interrupt Enable (PEIE Bit) .... 97 Bus Collision Repeated Start Condition ...... 163 IORLW ............................................................................................ 31 FSR Register ........................... 161 ADDWF ..... 104 ID Locations .......... 162 DECF ...... 105 Read/Write Bit Information (R/W Bit) ....................................................................... MCLR .................................... 168 MPLAB ICD 2 In-Circuit Debugger ................................................................................................................................................................................................. See Interrupt Sources........................ 164 RRF ............................................ INTCON Register ......................................................................24.................... See I2C..... 84 Reception ............. 84....... 157 In-Circuit Debugger ............. 149................................................................................ 153 Interrupt-on-Change (RB7:RB4) .................... 28 Synchronous Serial Port Interrupt ........................................... 105 Stop Condition Timing .... 24 Interrupts.................................................. 137 Internal Sampling Switch (Rss) Impedance ......................................................................................................................................................................................... 143 M Master Clear (MCLR) .................................................................... 159 Instruction Set ................................. 163 IORWF ................................................ 161 BSF .................................................................................................................. 154 Interrupts......... 162 CLRW ...... 164 SUBLW .................. 165 Summary Table . 150 MCLR Reset.......................... 24 RB0/INT Enable (INTE Bit) ........................................... 160 INT Interrupt (RB0/INT)....... Linker........................................... 20.......................................................................................................... 94 Master Mode ................................................................................................................................... 157 In-Circuit Serial Programming (ICSP) ..................................................................................................................... 99 Master Mode Transmission ............................................................................................................................................................................ 101 Multi-Master Communication.......... 157 Resources .... DS39582B-page 223 ............ 106 Stop Condition ................... 80 ACK Pulse ........................... 11....................... 148 MCLR/VPP ............ Enable Bits Global Interrupt Enable (GIE Bit) ........................................................................ 44 RB0/INT Pin..... 147.................. 161 ANDWF .......... 161 BCF .. 162 CLRF ...... 15 Data EEPROM Memory ............. 192 I2C Bus Start/Stop Bits Requirements ...... 163 INCF .......... 158 Low-Voltage In-Circuit Serial Programming ...... Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .......... 143................ 169 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ............................................................... 8 MCLR Reset............................................ 130 Interrupt Sources .............................................

............................................................................................................................................49...... 143 Time-out (TO Bit) ........................19........................ 47 PORTC Register ................ 41 TRISA Register .................. 29 PIC16F87XA Product Identification System ....................................................................... 30 POR............... 26 PIR2 Register ................................................................................. 51 Associated Registers ........... 84 Overview ......................................................................................................................................49................................... 29 POR Bit ........ 51 Select (PSPMODE Bit) ................................................................................ See I2C.... 154 TRISB Register ................... 8................................... 13................................................................ 71 SPI Mode.......................... 77 SSPBUF ....................................... 49.............................................................................................................................................. 41 PORTB .............................. 187 PCL Register .................... SPI Mode .......................................................... 50 Output Buffer Full Status (OBF Bit) ......................................... 76 SSPSR ............................................. 154 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ...................22...... 148................... 48................. 47 Functions ............. 48 Functions ...................... 30 PCLATH Register ........................ 10 OSC2/CLKO Pin ................................ 149 RC ................................24............................... 50 Functions .... 49....... 20............... 23 RBPU Bit ..........................................13............... 23 RB0/INT Pin............ 23 PSA Bit ..... 149 XT ............................................... 50........................................................................ 149 Power-down (PD Bit) .......................................... 23 OSC1/CLKI Pin ............................... 23 Rate Select (PS2:PS0 Bits) .. 154 RB7:RB4 Interrupt-on-Change ......... 44......................112............................................................... 49......................... 48 Parallel Slave Port (PSP) Function .............................................................. 209 Paging....................... 143 Oscillator Start-up Timer (OST) .........19....... 171 DS39582B-page 224  2003 Microchip Technology Inc............................................. 20..................................... 113 TRISC Register ........................................ 71 Operation ...........21............................................................ 111 PORTD ........... 143................................................................... 147............................... 10 Associated Registers ......PIC16F87XA MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator ......... 43 PORTA Register ... 19....................... PORTA .......................................................... 149 LP ............................................................................. 51 RE1/WR/AN6 Pin ..... 51 RE2/CS/AN7 Pin ......................................................... 51 Parallel Slave Port Requirements (PIC16F874A/ 877A Only) ..................................................................................................................................... 50.............................. 76 SPI Slave Mode ............. 50 PORTE Register ..............................................8....................................... 168 MSSP .......... 85 RC6/TX/CK Pin ............ 19.................................... 49.......................................... 23 T0CS Bit ............................................................... 146 P Package Information Marking .22.............. 27 Pinout Descriptions PIC16F873A/PIC16F876A ........................... Program Memory ........................................................................ 231 PICkit 1 Flash Starter Kit ......................... 49.................................................. 10 Oscillator Configuration HS ........................... 23 RB0/INT Edge Select (INTEDG Bit) .................. 44 Pull-up Enable (RBPU Bit) ........................49........................ 147 O Opcode Field Descriptions ......................................................19..............................19.......... 28 POP ................................................ 46 RC3/SCK/SCL Pin .......................... 167 MPLINK Object Linker/MPLIB Object Librarian ................................................ 11.......................................................................... 51 RE1/WR/AN6 Pin ....................................49