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ISSCC 2007 / SESSION 17 / ANALOG TECHNIQUES AND PLLs /173

17.7
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time Daniel Schinkel, Eisse Mensink, Eric Klumperink, Ed van Tuijl,
Bram Nauta
in the inset of the chip micrograph in Fig. 17.7.7. An SR-latch is connected to the output of the SA to create static output signals without loss of timing information from the core of the SA. When required, more advanced 'slave' stages could be used in applications [3].

input and output pads (for probe station measurement) was placed on the same die. The layout of the double-tail SA is shown

University of Twente, Enschede, The Netherlands Latch-type sense amplifiers, or sense amplifier based flip-flops, Figure 17.7.4 shows the measured relative delay under different are very effective comparators. They achieve fast decisions due to conditions (the absolute delay is not measurable due to additiona strong positive feedback and their differential input enables a al delay from the output drivers). As intended, the minimal delay low offset. Sense amplifiers (SA) are hence widely applied in, for is found at V.,, = l.lV At a Vc, of 0.6V, there is still only a 20ps example, memories, A/D converters, data receivers and lately also increase in delay. The delay versus AV,, is 44ps/decade under in on-chip transceivers [1,2]. Voltage-mode SA's, as shown in Fig. nominal conditions. In comparison, measurements in [4] on a con17.7.1, have become especially popular [3-5] because of their high ventional topology in 0.13Rtm CMOS with VDD= 1.5V show a delay input impedance, full-swing output and absence of static power versus AVi7, of 100 to 170ps/dec and a 250ps increase in delay consumption. when V17< is lowered to 0.6V However, the stack of transistors in Fig. 17.7.1 requires a large The offset in [4] is also very dependent on the V17>. and rises from voltage headroom, which is problematic in low-voltage deep-sub- 8.5 to l9mV when the V>,, changes from 1.05 to 1.5V. For our micron CMOS technologies. Furthermore, the speed and offset of design, measurements on 20 samples gave an offset of a,,= 8mV this circuit are very dependent on the common-mode voltage of at both V., = 1.1V and Vc,, = 0.75V. If desired, area upscaling could the input V,,,, [4], which is a problem in applications with wide further reduce the offset at the expense of power (P 2) common-mode ranges, for example A/D converters. Offset compensation schemes [5] are a good alternative if the As an alternative, a double-tail sense amplifier is presented here, application allows for the added complexity. The power consumed which uses one tail for the input stage and another for the latch- by the SA is 113fJ/decision when AVi is 5OmV (f[1k = 1GHz, VDD = ing stage, as shown in Fig. 17.7.2. This topology has less stack- 1.2V, P = 113gtW f 1GHz, or 225gW @ 2 GHz), which drops to ing and can therefore operate at lower supply voltages. The dou- 92fJ/decision for full-swing inputs. ble tail enables both a large current in the latching stage (wide The SAs equivalent input noise was extracted, by measuring the M12), for fast latching independent of the V,,,, and a small cur- average number of positive decisions versus AV,, as shown in Fig. rent in the input stage (small M9), for low offset. 17.7.5. Fitting the measurements to a Gaussian cumulative disThe signal behavior of the double-tail SA is also shown in Fig. tribution gives an RMS noise voltage of V,,,,= 1.5mV. 17.7.2. During the reset phase (Clk = 0V), transistors M7 and M8 Setup and hold times are extracted from BER measurements pre-charge the Di nodes to VDD, which in turn causes M10 and around the zero crossings of the full-swing input patterns, as Mll to discharge the output nodes to ground (so there is no need shown in Fig. 17.7.6. No bit errors are measured outside an interfor dedicated reset transistors at the output nodes), After the val of 18ps, so the required setup+hold time is smaller than 18ps reset phase, the tail transistors M9 and M12 turn on (Clk = VDD). (as input jitter is part of the 18ps). A conventional circuit in At the Di nodes, the common-mode voltage then drops monotoni- 0.18gm CMOS [3] achieves 80ps, which would still be 40ps in cally with a rate defined by ITMICDi and on top of this, an input 9Onm CMOS according to scaling theory. In the double-tail topoldependent differential voltage AVDi will build up. The intermedi- ogy, the setup+hold time could be further reduced with a wider ate stage formed by Mi10 and Mll passes AVDi to the cross-coupled tail transistor M9, but at the expense of increased offset and inverters and also provides additional shielding between the noise due to a shortening of the time that M5/M6 operate in satinput and output, with less kickback noise as a result. The invert- uration. Simulations predict that the current aperture time is ers start to regenerate the voltage difference as soon as the com- already fast enough to sample data patterns of 4OGb/s, provided mon-mode voltage at the Di nodes is no longer high enough for that interleaving is used to enable a suitably long regeneration M10 and Mll to clamp the outputs to ground. The ideal operat- phase. ing point (V'>,) and the timing of the various phases can be tuned with the transistor sizes. In conclusion, the double-tail topology has an added degree of freedom that enables better optimization of the balance between To compare the conventional and double-tail SAs, both circuits speed, offset, power and common-mode voltage. The circuit also are simulated, with transistor dimensions scaled to get an offset has better isolation between input and output and is well suited standard deviation of a,, = 13mV. The operating conditions are to operate at low supply voltages. VDD = 1.2V and f,, = 3GHz, and the input has VC11= 1.1V. At this high V>,, (found, for example, in memories), the conventional Acknowledgements: Philips Research for chip fabrication, the Dutch authors thank topology topology needs reset tranLsistors at the Di nodes [1,5] to rettniosthDThe ensure Technology Foundation (STW, project TCS.5791) for funding and Gerard that M5 and M6 at least start in saturation. The power consumed Wienk for assistance. by both circuits is similar, about 40fJ/bit. Figure 17.7.3 shows the delays of both circuits versus the differential input voltage. The References: [1] I. Zhang, V. George and J. Rabaey, "Low-Swing On-Chip Signaling feedback gives a logarithmic relation between the delay Techniques: Effectiveness and Robustness," IEEE T VLSI Systems, pp. and Al">: 37ps per decade for the double-tail SA anLd 37 to '264-272, June, 2000. . 43ps/dec for the conventional SA. The double-tail SA is both [2] D. Schinkel et al., "A 3Gb/s/ch Transceiver for 10-mm Uninterrupted faster in general and the delay increases by only 7ps when V,,. RC-Limited Global On-Chip Interconnects," IEEE J. Solid-State Circuits, 297-306, Jan,, 2006. drops to 0.7V, instead of the 25 to 60ps increase for the conven- pp. B. Nikolic et al., "Improved Sense-Amplifier-Based Flip-Flop: Design tional topology. When tional topology. When simulated at VDD= 1Vthe delay of the doU- and Measurements," IEEE J. Solid-State Circuits, pp. 876-884, June, st,1imulatedt at VDD = 1 V, the delay of thedou [31
ne

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ble-tail SA is lps larger versus 29ps for the conventional SA.

2000

nology, as part of a low-swing on-chip data transceiver that operatesU aound1 V. = 1.1V. The 1, can hae, large variations due to, for examnple, crosstalk effects. A double-tail SA with dedicated

Thne dLouble-tail SA was implementedt in a 1.2 V CMOSlU OOnm tech-

[41 B. Wicht at at., 'Yield anld Speed Optimnization of a Latch-Type Voltage Sense Amplifier," IEEE J. Solid-Stnte circuits, pp. 1148-1158, JulLy, 2004. [51 K.-Lid. Wong and C.-K.K. Yang, "Offset CompensatDion inl Comparators with Minimum Input-Referred Supply Noise," IEEE J. Solid-State circuits, pp. 837- 840, May, 2004.

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1 V Vdd=1. I 0.7V 180 180 Conventional SA. Vdd0 Vcm=0._.t .8 I 0.2 -6 -4 081 . Vcm=l .4r - 0~~~~~~~~~~~~~~~i1 0.2V] IF. 250 Conventional SA.75V..-------- ~~~~~~~~~~~~~~~~~-0.2n In+-I 5 M6 n0 In+- -0. at tcIk= 1GHiz.. --l Covntoa SAVcDD7 800..~~~~~~~~~~1 l -610 -605 1 8ps setup + hold time I/ -2 0 2 AVin ...1V1k0 180 Dela.7.6 1.2 Clk~~~~~~ Clk-.Ot Ou_tn I 1n . M Out- M12 1. The dotted transistors Figure 17.Voffset (mV) 4 6 1 10 -600 -595 Clock skew (ps) -590 -585 Figure 17. Conztinued onz Patge 605 DIGEST OFTECHNICAL PAPERS * 315 .8 Gaussian. Vdd=1 .2V 140 --Vcm=0.. cy =1 . 27 12 80 ----------------2V------------------------ cn CZ 120 120 CZ.Op t (s) are Figure 17.1 10.5mV I~~ measured ' .7.71: Conventional latch-type voltage sense amplitier.Vcm=0..7V 16 200 -------E Double-Tail SA..4: Measured relative delay versus differential and common-mode input delay is the time between the clock edge and the instant when AOut crosses 1/2 VDD..4 0ConvetionalSA.00 >f> 1 CZ T0 001 1 -6 -- -4 20 -50 00 10 -20 - 103 E ~~~~~Vn (V) 102 AVin (V) 0 0 t18 2 0 io 100 101 AVin-Voffset (mV) 102 0.ISSCC 2007 1 February 13..4 AVIN: I\A8 200.72: Double-tail latch-type voltage sense amplitier and signal behavior.. voltages.-2 10 / f 0 1 0 P attern PRBS Pattern . Vcm=0.7.OmV 1O.2________n__.5: Measured cumulative noise distribution and tit to Gaussian distribution.3: Simulated sense amplifier delays versus differential input voltage.75V..5 Figure 17.+.6: Bit error rate versus clock skew. Xia ~ ~ ~ ~~~~~ 1 CD~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~C. Vcm=l1 lV AVin=5OmV. Vdd=1 V -+-Double-Tail SA. examples ot common variations.6V. Figure 17.5 Vcm (V) 1 1.1 ~ ~ EE ~~~~ -6 ~~~~~~~~~~~~~ /11 0..OmV Out+u+ MIO Ot Mlr M3 L Mu 1. 2007 /4:15 PM VDD VDD M7 L Cl.2 -__ - -----------~~~~~~~~~~~~~~ M7 M8 VM il M5 M6 I Di 0':'D 1 1.0.. The Figure 17.. Vcm=0..7.Vcm=1 -&.

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