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Analysis of First-Order Anti-Aliasing Integration Sampler

Ahmad Mirzaei, Saeed Chehrazi, Rahim Bagheri, and Asad A. Abidi, Fellow, IEEE
AbstractPerformance of the rst-order anti-aliasing integration sampler used in software-dened radio (SDR) receivers is analyzed versus all practical nonidealities. The nonidealities that are considered in this paper are transconductor nite output resistance, switch resistance, nonzero rise and fall times of the sampling clock, charge injection, clock jitter, and noise. It is proved that the lter is quite robust to all of these nonidealities except for transconductor nite output resistance. Furthermore, linearity and noise performances are all limited to design of a low-noise and highly linear transconductor. Index TermsAnti-aliasing, charge sampling, impulse sampler, integration sampler, jitter, noise, receiver, software-dened radio (SDR).

the ADC for such a receiver is at dBm. This quantization noise in terms of ADC parameters is [4] (1) where is the ADC full scale in dBm, and are the ADC effective number of bits and the sampling frequency, respecis the signal bandwidth. If the ADC full scale is tively, and dBm with a sampling 3 dBm, in order to lower the QN to frequency of 12 GHz, the resolution of the ADC must be at least 12 b. This ADC is far beyond realization with a power consumption suitable for portable devices in the foreseeable future [5]. Other approaches such as subsampling or undersampling have their own fundamental limitations, making them not useful for SDR [6], [7]. Therefore, realizing the SDR receiver in todays technology needs a new approach. We visualize the SDR receiver as a programmable receiver without any RF pre-lter. It is comprised of a wideband frontend, including a low-noise amplier (LNA) and a downconversion mixer, and a sampler before the ADC. The desired channel along with nearby and faraway blockers, with vastly different powers, enters the front-end, is amplied by the LNA, and is downconverted to zero-IF by the mixer [6]. After downconversion, discrete samples of the zero-IF desired channel should be delivered to the ADC. The traditional way is to use an impulse sampler, which is deeply rooted in the electronics tradition, but it samples all of the frequencies with equal delity and gain [8]. Since the receiver does not have a pre-lter and the front-end is broadband, the downconverted channel is accompanied by unwanted adjacent channels as well as far away blockers. After impulse sampling, the unwanted adjacent channels and the far-away blockers alias either in the IF signal band or somewhere away from it in the Nyquist band. The aliasing channels directly degrade the quality of the wanted channel and the large, far-away blockers might exceed the dynamic range of the ADC; therefore, an anti-aliasing lter must precede the sampler. This lter is ideally a brick-wall low-pass lter with a cut-off conservatively at the Nyquist frequency, but more aggressively at the sampling frequency minus half of the wanted channel bandwidth. Its bandwidth should be programmed according to the bandwidth of the received channel, which can be anywhere from 200 kHz for GSM [3] to 16 MHz for IEEE 802.11g [9]. As long as the desired channel gets to the ADC with a good signal-to-noise ratio (SNR), and the blockers are within the dynamic range, the rest of ltering, detection, and demodulation can be done by DSP. However, it is not easy to realize

I. INTRODUCTION HE proliferation of bands, standards, and modulation formats has motivated the communications industry to look for a single wireless receiver that can tune to any band and receive any modulation across a wide range of frequencies (for example, 0.86 GHz to cover all of the standards in use to date). One way to realize such a radio, which is often called a software-dened radio (SDR) receiver, was proposed by Mitola [1]. He denes the SDR as one where the only analog components are an RF A/D converter (ADC) at the receiver front-end and an RF D/A converter (DAC) at the transmitter front-end, where the rest of the receiver functions have to be realized in a programmable digital signal processor (DSP), which is clocked at RF. With the rapid progress in CMOS scaling and advances in data converters, this looks like a good approach. However, in order to cover the frequency band in use to date and to detect the smallest available signal, an extraordinary ADC with a 12-GHz conversion rate and 12 bits of resolution is needed. We assume that the receiver covers up to 6 GHz; therefore, if no subsampling technique is utilized, the minimum sampling rate has to be at 12 GHz to avoid aliasing [2]. The weakest signal which must be detected determines the resolution of this ADC. The Global System for Mobiles (GSM) standard demands one of the most sensitive receivers which has to detect a minimum dBm [3]. With a 15-dB signal-to-quantisignal of about zation-noise ratio (SQNR), the quantization noise (QN) level of
Manuscript received October 3, 2007; revised February 10, 2008. First published April 30, 2008; current version published November 21, 2008. This paper was recommended by Associate Editor B. Zhao. A. Mirzaei is with Broadcom Corporation, Irvine, CA 92617 USA. S. Chehrazi and A. A. Abidi are with the Department of Electrical Engineering, University of California, Los Angeles, CA 90095 USA. R. Bagheri is with Wilinx Inc., Calrsbad, CA 92008 USA. Digital Object Identier 10.1109/TCSI.2008.924127

1549-8328/$25.00 2008 IEEE



the programmable anti-aliasing lter, particularly at todays low supply voltages, if it is to meet the low noise and high linearity requirements. Therefore, the impulse sampler offers the wrong paradigm for such a wireless receiver. A sampler is needed that nulls the aliasing blockers, and intrinsically de-emphasizes adjacentparticularly far-awayunwanted channels. The integration sampler [10], [11] provides all of the above-mentioned requirements. The input waveform is integrated over a xed time window, and the resulting integral is taken as a sample. The window can be as wide as the sample period, and its repetition rate denes the sampling frequency. A simple rectangular integration sampler has nulls at the sampling frequency which, if clocked at a sufciently high frequency, attenuate every possible aliasing channel. Away from the aliasing frequencies, lter side-lobes which roll off at 20 dB/dec attenuate adjacent channels. In order to achieve a sufciently wide null bandwidth, the lter has to be driven with a high-frequency clock. Since a low-power ADC cannot easily digitize at this sample rate, the integration sampler can be followed by discrete-time anti-aliasing decimation lters [6]. In this paper, we completely analyze the rst-order integration samplerthe SDR receiver enabler [6]versus all practical implementation imperfections. We will show that it is exceptionally robust to many nonidealities such as clock jitter, charge injection, nonzero rise/fall times of the clock, and switch resistance. As we will see, linearity and noise performances are all limited by the low-noise and highly linear transconductor. Moreover, there is no need to have a special clocking scheme such as bootstrapped driving [12] and dummy switches [13]. We have carried out a similar performance analysis for a secondorder anti-aliasing integration sampler presented in [14]. In spite of having some similarities, such as being robust to clock jitter, the second-order lter behaves differently to some nonidealities. For instance, unlike the rst-order integration sampler, the IIP3 of the second-order integration sampler is a function of clock frequency. The interested reader is referred to [15]. In Section II, we introduce the integration sampler and a compact realization of an anti-aliasing FIR+IIR lter. Section III analyzes the impact of various nonidealities on performance of the lter. Jitter and noise analyses are carried out in Sections IV and V, respectively. Section VI concludes the paper.

Fig. 1. (a), (b) First-order windowed integration sampler and its transfer function. (c), (d) FIR+IIR integration sampler and its transfer function.

gration lasts for a clock period , after which the capacitor is disconnected. The sampled voltage on the capacitor is

(2) While this sample is read through charge transfer, the transconover the next clock ductor charges the second capacitor period. The two time-interleaved capacitors keep the overall sampling throughput at . Equation (2) is the convolution integral [2] of the input signal and a rectangular window whose and its width is [Fig. 1(b)]. Therefore, the height is input signal passes through a continuous-time FIR lter with a rectangular impulse response prior to sampling. The -domain transfer function of this lter is (3)

II. FIRST-ORDER INTEGRATION SAMPLER Here, we will explain the operation of two different integration sampler-based anti-aliasing lters: a nite impulse response (FIR) lter based on direct implementation of the concept and a modied version which offers the FIR lter cascaded with an inherent innite impulse response (IIR) discrete-time lter. A. Integration Sampler: FIR Fig. 1(a) shows the rst-order integration sampler. The input through the transconvoltage is integrated into the capacitor and the switch, which is clocked by . The inteductor

which is a sinc function if it is evaluated on the imaginary axis (4) Equation (4) denes a low-pass lter with nulls at sampling frequency and all of its integer multiples , a main-lobe at dc , and a set of side-lobes rolling off at with a dc gain of 20 dB/dec. The narrowband wanted signal is centered at dc (zero IF). Those unwanted blockers that reside at are attenuated by the nulls before they are aliased on top of the desired signal



at dc. Unwanted adjacent channels located in the side-lobes are also aliased into the main-lobe, but, away from dc, therefore, they can be suppressed in DSP using a sharp channel selection lter. The lter passband can be scaled by orders of magnitude simply by changing the clock frequency . This makes it specially suitable for SDR receivers in which the zero-IF bandwidth of the downconverted channel vastly changes from 100 kHz, when receiving the GSM signal, to 8 MHz, when it receives the IEEE 802.11g signal. The nulls are only at discrete frequencies. The skirts of side-lobes adjacent to a null determine how much a wideband channel is suppressed. If the edge of the aliasing channel lies at from the th null it will be attenuated by an offset (5) Therefore, the higher the clock rate is, the wider is the bandwidth over which a minimum attenuation can be obtained around a null. Changing the clock frequency does not change the shape of the transfer function, it only stretches or shrinks it in frequency domain. B. Integration Sampler: FIR+IIR The FIR lter of Fig. 1(a) is modied to a more useful lter shown in Fig. 1(c). This is done by removing one of the time-interleaved channels and adding a continuously connected capacto the output of the transconductor. In this lter, right itor to yield before the th sampling moment (6) and are the sample of the output voltage where and the voltage across capacitor , respectively. Over the time interval when the sampling switch is off, the sampled voltage over capacitor C is read and then it is reset with no . During the same interval, the transconductor charge at current is integrated into . Therefore, the voltage across at is (7) , the charge-free capacitor C is connected to Right after , which causes an immediate charge-sharing between them. As a result, the output voltage is

clock duty cycle [second term in (9)]. Second, a discrete-time (DT) rst-order IIR low-pass lter with a real pole at cascades the windowed integrator [rst term in (9)]. This IIR lter attenuates adjacent blockers located in the side-lobes. Although these are not aliasing blockers, they increase ADC dynamic range requirements if not attenuated suf[6], the 3-dB bandwidth ciently. Since in most cases of the IIR lter is approximated to , which is controlled by the capacitor ratio and sampling frequency. The capacitor ratio and clock frequency are very well controlled in todays CMOS technologies. This allows to accurately compensate the droop and delay of this IIR lter in DSP if required. inAdditionally, having larger integration capacitor ( stead of C in the FIR lter of Section II-A) lowers the swing, relaxing the transconductor design especially in low-voltage ap, which is indeplications. The dc gain of this lter is pendent of the nonswitched capacitor . This is utilized to implement a programmable gain in this anti-aliasing lter by using switch-selectable capacitors [6]. III. IMPLEMENTATION NONIDEALITIES AND THEIR IMPACT ON NULL-DEPTH Practical nonidealities limit the depth of nulls. Finite transconductor output impedance, nite transconductance of switches, nonzero rise and fall times of sampling clock, and charge injection can be numbered as important implementation nonidealities that can adversely affect the null-depth. A. Transconductor Finite Output Resistance So far we assumed that the transconductance stage, , which supplies the integration current has an innite output resistance, (or equivalently an innite DC gain, ). This is not true for a practical transconductor which has a limited output resistance due to the channel length modulation of its comprising FETs [16]. This nite output resistance limits the depth of the nulls and, as a result, lowers attenuation of aliasing channels. Lets start with the FIR integration sampler which was introduced in Section II-A, and is redrawn in Fig. 2(a). Since steals away some of the transconducor current, the integration over is lossy. Therefore, the lter impulse response is (10) where is the time constant of the circuit. Equation (10) as gets larger. approaches the ideal impulse response The transfer function of the lter is (11) Comparing this new transfer function with the ideal one in (3), it is evident that the zeros of the FIR lter move off the -axis by . As a consequence, the lter transfer function is no longer from the th aliasing an ideal sinc [Fig. 2(c)]. At an offset , the magnitude of the transfer function is approxfrequency imated by (12)

(8) For the remainder of the clock cycle, the transconductor is charging the two capacitors in parallel, therefore, the nal is equation expressing the sampled voltage (9) which is mapped to the equivalent system in Fig. 1(d). Equation (9) reveals some interesting properties of this lter. First, the modied integration sampler is independent of the



Therefore, a required null-depth determines the minimum tolerable time-constant or the smallest possible capacitor. This, of course, dictates maximum achievable dc gain. also impacts the transfer funcThe transconductor nite tion of the FIR+IIR lter in Fig. 1(c). With a similar approach and assuming the previously mentioned practical assumption of , it is readily shown that the transfer function is now obtained from the equivalent system of Fig. 3(a). The continuous-time input passes through a lossy windowed integration, and is ltered with a DT-IIR after which it is sampled at lter. Finite not only shifts the zeros of the FIR lter off of the -axis by , it also scales down the DT-IIR pole by , increasing its 3-dB bandwidth. In this circuit, the time constant is (16)
Fig. 2. Effect of transconductor nite output resistance on null-depth.

which indicates that the transfer function is no longer zero at . On the other hand, away from the nulls, it can be shown is simplied to that (13) Comparing this equation with (4) shows that the side-lobes are the same as those of the ideal circuit but they are scaled by . In order to get sufciently wide nulls, the initial sampling frequency has to be large [(5)]. This guarantees that the lter has enough suppression over the entire bandwidth of the desired channel around the nulls. For example, in [6], the initial sample rate when receiving IEEE 802.11g signal is 480 MHz, which is much larger than the 8-MHz zero-IF bandwidth of that is channel. However, because the lter transfer function at no longer zero [see (12)], the magnitude of the transfer function remains relatively at across 8 MHz around the aliasing frequencies. Thus, the null-depth, which is an indication of how , is the magnitude much attenuation the lter offers around divided by the dc gain. From (12) of the transfer function at and (13), it is Null-depth at (14)

factor compared with the which is boosted by the FIR integration sampler lter. This boost factor, which is a large number, results in a large time constant. This signicantly reof the laxes the null-depth limitation due to nite output transconductor [see (14)]. Fig. 3(b) compares the transfer function of the system in Fig. 3(a) with SPECTRE-RF simulation, which are in good agreement. Also, the ideal transfer function with innite is drawn to emphasize the effect of nite in reducing the gain and limiting null-depth. In conclusion, transconductor output resistance needs to be designed to be as high as possible. , this gain Although the dc gain of the transconductor is drops at higher frequencies due to the parasitic capacitances. If the only parasitic capacitance is that which is at the output, it can and all of the previous analysis will sufce. be lumped with However, the gain transfer function can have higher order poles which cause a second, third, or even higher order roll off at high frequencies. Therefore, the most general form of the gain across all frequencies is (17) is the output impedance of the transconductor in where Fig. 4(b). The -domain transfer function can be written in terms of the total output impedance , which is a parallel combination of the transconductor output impedance and the two capacand C [Fig. 4(a)]. The analysis carried out for the imitors, pact of can be readily generalized to any given transconductor output impedance . This leads to the equivalent system of Fig. 4(b), for which the new transfer function before sampling is (18) and is dened as , and are the total output resistance and cawhere pacitance at dc and can be found as (19) (20)

For narrowband signals like GSM with a zero-IF bandwidth of kHz, (12) suggests that can be a limiting factor in achievable null-depth over the desired bandwidth unless it is designed to be very large ( ). However, this may not be the case for wideband signals like the IEEE 802.11g with an 8-MHz zero-IF channel bandwidth. Since, for a transconductor topology in a certain CMOS technology, tends to be a constant, equal to, say, , the maximum null-depth in (14) can be reformatted to (15) which suggests a fundamental tradeoff between the lters dc-gain ( ) and the largest achievable null-depth.



Fig. 4. Effect of transconductor frequency-dependent output impedance in FIR+IIR lter.

Fig. 3. Impact of nite r on FIR+IIR. (a) Equivalent system. (b) Simulation against prediction.

This emphasizes the importance of having the highest possible transconductor output resistance at dc in order to have . In fact, beyond the desired signal bandwidth, maximum helps in suppressing adjacent blocker faster roll-off in even more aggressively. Equation (18) and the equivalent system of Fig. 4(b) have been validated by SPECTRE-RF simulations on different examples of transconductor output [15]. impedance, Finally, from Fig. 4(b), it can be shown that the total dc gain . This is easy to undertstand, of the lter is because the switched capacitor C manifests itself as a resistor at dc. of size B. Switch Resistance So far, we have assumed ideal switches. In practice, an MOS switch has a nonzero ON resistance which is a function of its gate, drain, and source voltages [16]. However, for simplicity, we assume that the ON resistance is constant, independent of or [Fig. 5(a)]. This assumption introduces a negligible error. Here, we analyze the effect of this nonzero switch resistance

on the performance of the FIR+IIR lter in Fig. 5(a). When and C are connected together with the switch during , because of its nonzero resistance , cannot track perfectly. At the sampling moment when the switch turns off, the sampled voltage is not the ideal value in the previous analysis. We assume that C has enough time to be completely discharged in the reset phase. Furthermore, we asis long enough to have a complete sume that and C for the charge stored on charge sharing between at the moment . Having those assumptions, at , and can be written as


(22) in which and are impulse responses relating and for a current input , respectively, and are given by (23) (24)



Fig. 6. Effect of nonzero switch resistance on the transfer function: simulation versus prediction together with ideal transfer function.

Fig. 5. Effect of nonzero switch resistance on the FIR+IIR transfer function.

The time-constant is equal to (21) and (22) can be simplied to

. Equations


unwanted signals around dc before they are added to the desired DT signal. Thus, with practical values of switch resistance the overall transfer function doesnt alter around nulls. This model holds true against SPECTRE-RF simulations (Fig. 6). Compared to the case of the ideal switch, in the main-lobe and frequencies around the nulls, there is no signicant change observed in the transfer function. The side-lobes are slightly lowered, However the exact accuracy of side-lobes is not important. This is because blockers that lie in the side-lobes alias into the main-lobe but away from the desired channel and eventually are ltered out by the following decimation stages or in DSP. Thus, in todays submicron CMOS technology with excellent switches, switch resistance is not harmful at all. The work of [17] has also analyzed the switch resistance and ended up a recursive expression which is not that instructive. In fact the existence of the high-pass lter was overlooked. C. Nonzero Rise and Fall Times of the Clock

(26) in which the error expression: is dened by the following

(27) From (25) and (26) and with straightforward mathematics, the effect is easily modeled as an undesired path in the signal ow diagram of Fig. 5(b). In the parasitic path, the input signal passes through a CT-FIR lter [with impulse response in Fig. 5(b)] which doesnt have any null at the sampling fre, is a wideband low-pass lter quency. Since with a dc gain that is times that of . When the output is sampled at , those blockers at alias to the of desired signal band with equal delity. However, DT samples go through a high-pass DT-IIR lter. This DT lter nulls the

So far, we have assumed zero rising and falling transition edges for . From the FIR+IIR lter structure it is easily recognized that only the falling edge of the clock, when the capacitor C is disconnected from , can affect the transfer function. For simplicity, we model the switch with a conductance linearly varying from innity to zero during the falling time of the clock. when As a result, as shown in Fig. 7(a), at the moment the switch is completely turned off, a charge which was supposed to be stored on C, wrongly remains on . This error charge not only corrupts the current sample, but also propagates through future samples as well. The following equations describe this situation:




Fig. 7. Impact of nonzero rise and fall times of clock.

switch is turned off, depending on different impedances seen at its drain and source and the clock slope, this channel charge divides unevenly between the source and drain impedances [18], [19]. If fully differential circuits are used, the constant portion of the channel charge and those due to even-order nonlinearities will cancel out and therefore are not important. There are always mismatches and offsets between the transistors in differential circuits. As a result of those, error signals due to even-order nonlinearities leak through but this is a second-order effect which is negligible here. Sometimes bootstrapping technique is used in which the gate voltage tracks the voltage at the source and drain terminals of the switch. This results in a constant voltage-independent switch transconductance which stores a constant channel charge [20], [21]. To understand the impact of charge-injection in the rst-order integration sampler, let us focus on Fig. 1(c). Only the switch can introduce error, because the reset switch clocked by leaves a signal-independent charge on the capacitor C. In addition to that, it can be proved that the linear portion of the stored doesnt have any impact on the nullcharge in the switch depth, only slightly changes the dc gain and the IIR pole. Also, since the actual implementation is differential, ideally there is no even-order term and the impact of mismatch is assumed to be negligible. Thus, only the channel charge due to the third-order , can introduce nonlinearity. Let us assume that the term, portion of this charge goes into the capacitor C, and the rest , discharges into . It can be written of it, indicated by

(29) (30) (31) where , . Equations (28) and (29) are similar to (25) and (26), hence once again the impact is presented by the block diagram in Fig. 7(b). In the parasitic path, the sampled signal has to pass through a DT-IIR highpass lter. The zeros of this highpass lter suppresses the unwanted components at dc before they add to the desired channel. Thus, like the nonzero switch resistance, this effect doesnt degrade the performance of FIR+IIR lter. We can also describe this phenomenon intuitively. The length of integration window is set with two adjacent falling edges of . Since falling edges are all identically shifted by the nonzero fall-time of the clock, the effective window length remains unchanged. D. Charge Injection An MOS switch conducting a voltage stores a channel charge which approximately is . and are the width and length of the switch, reand are its gate and threshold voltages, respectively, spectively, and and are constant coefcients representing nonlinear terms stemming from different sources such as body effect. Therefore, part of this channel charge is a function of . This charge can be positive or negthe transferred voltage ative based on the P- or N-type of the switch. Now, when the

(32) Since the impact of this injected charge is very small, we can write (33) (34) . By replacing these where and are found. new variables and simplifying, Ultimately, the charge injection is modeled with a parasitic path shown in Fig. 8. From the model it is deduced that nonlinearity operates effectively after the discrete-time IIR lter where the strong blockers have sufciently been ltered out. Therefore, it mainly introduces self-distortion rather than aliasing, relaxing



Fig. 8. Charge injection effect on FIR+IIR transfer function.

Fig. 9. Charge injection effect for a DT-FIR lter.

the effect. This suggests us to use a simplest clocking scheme without worrying about charge-injection. Almost for all practical cases, this FIR+IIR lter is followed by chains of anti-aliasing decimating discrete-time sinc functions [6], [22], [23]. Fig. 9(a) explains an implementation of a discrete-time decimation by 4, simply by shorting together four identical capacitors which hold four consecutive samples. For simplicity, the input and related clocks are not shown, and only those clock phases required for the decimation are shown ). The impact of charge injection on this decimation lter ( is accurately modeled in Fig. 9(b), in which nonlinearity appears after decimation. Again, it causes self-distortion. This explains the robustness of these DT-FIR lters to charge-injection. IV. CLOCK JITTER It has been reported that for certain frequency ranges of input the integration sampler outperforms the impulse sampler when it comes to clock jitter [24][26]. In these reports, the input is sinusoidal whose frequency is swept from dc up to a few times the sampling clock and SNR is calculated as the signal power to the total noise power from dc up to the Nyquist frequency. This might be suitable for some applications, but denitely not for an SDR receiver in which only noise components interfering with the signal band is important. First, self-distortion is not detrimental and reciprocal downconversion of the blockers is typically the main concern. Second, only that portion of the aliased noise that lies in the desired signal band is harmful. We will now show, that the integration sampler is exceptionally robust to the clock jitter.

Fig. 10. Clock jitter analysis. (a) Integration sampler. (b) Impulse sampler.

To prove this, let us dene the following system with input and output , where,

(35) This continuous-time integration over a window of length , denes a linear time-invariant system (LTI) with a dc gain of unity. Outputs of the rst-order integration sampler are uniform samples of this lter. However, clock jitter disturbs this uniformity as such (36) in which is the clock jitter as a function of time. This integral is approximated using Taylors series expansion to

(37) or, in terms of power spectral density, can be rewritten as




those that are in the side-lobes. First, let us consider a blocker of at the sampling frequency . With a jitter-free clock, power such a blocker is completely nulled. However, as explained in Fig. 11(a), because of jitter it is reciprocally aliased into the signal band. Using (38) and after some simplications, the noise power aliased on top of the signal is

(42) where is the wanted signal bandwidth at zero IF.1 is proportional to the blocker energy and is a function of phasenoise prole. With a Lorentzian prole2 and, for practical values of the phase noise, this energy is much smaller than the case or when the same sinusoidal blocker at is aliased on top of the desired signal with a jitter-free clock, . Even for the most pessimistic value of which is over and zero at phase-noise, other points, the aliased noise is which is still smaller than . Consequently, if with a noiseless clock a blocker around a null is tolerable, a very relaxed phase noise for the clock can deliver the same good performance. Now, let us turn our attention to a blocker residing at sidelobes [Fig. 11(b)], and without loss of generality let us assume . The total noise power aliased to the signal it is located at band after sampling is

Fig. 11. Reciprocal downconversion of the blocker due to clock jitter.

is the power spectral density of the clock jitter and is related to the phase noise as (39) Equations (37) and (38) are represented by a block diagram in Fig. 10(a). Interestingly, the impact of the jitter is modeled as an extra undesired path, whereby the input signal is modulated by the jitter and then passes through a comb lter. Consequently, before sampling, all possible aliasing components are nulled by the zeros of the comb lter. This comb lter makes the integration sample-and-hold more rigid to the clock phase noise than the conventional impulse sampler. To understand this, let us turn our attention to the impulse sampler. In an impulse sampler, the sampled value in the presence of jitter is equal to (40) or, in the frequency domain, is (41) Equation (41) indicates that the skirt of phase noise modulated with strong blockers can create components at dc and integer multiples of the clock frequency, which are aliased on top of the desired channel at around dc after sampling [Fig. 10(b)]. Specially, those blockers located at higher offset frequencies can be more harmful, because of the term in (41). This reciprocal downconversion due to phase noise degrades the SNR of the desired signal. In order to see the effect of blockers on the integration sampler, we consider two kinds of blockers: those that are located around the sampling frequency or its harmonics and

(43) For a given blocking prole, (43) dictates the required phase . Similarly, the phase-noise requirenoise at the offset of ment of the clock at other offset frequencies is found. To verify the foregoing conclusions, we use a brute force simulation setup in MATLAB, implementing an integration sampler with a clock of a given phase-noise prole. The clock frequency is 50 MHz and has a phase-noise of dBc Hz at 100 kHz rolling off at 20 dB/dec. In order to have a reasonable length of simulation time, phase-noise is assumed to be zero at [0,100 kHz] interval. The desired zero-IF signal bandwidth is assumed to be 10 MHz. A sinusoidal blocker whose frequency is swept from 10 to 120 MHz is sampled by the integration sampler using this jittery clock. The noisy clock reciprocally downconverts the blocker into the desired channel. The normalized noise power inside [0, 10 MHz] bandwidth is a function of the blocker frequency, . Fig. 12(a) plots this normalized noise power as a function of the blocker frequency and compares the results of the simulation setup (discrete

S (f )) sin (T f ) around other nulls, i.e., 2f ; 3f ; . . .


approximation comes from ignoring those portions of (S (f ) 3

2The Lorentzian prole is the phase-noise spectrum of any oscillator perturbed by white noise sources which is given by S (f ) / 1=(f + f ). This means that the phase noise at zero is not innite [27].



Fig. 12. Impact of clock jitter in windowed integration sampler. (a) A single tone blocker with a constant amplitude whose frequency swept from 10 to 120 MHz is sampled using a 50-MHz jittery clock. (b) Jitter is important only for the blockers in the side-lobes.

Fig. 13. Switch noise analysis.

points) against the prediction obtained from (38) which are well matched. From Fig. 12(a), it appears that some blockers in the vicinity of the nulls are aliased to the desired signal band with larger gains than those in the side-lobes, and as a result can be more serious. However, these blockers are aliased to the desired signal band even using a noiseless clock and from Fig. 12(b) this aliased component has much bigger power compared with the one reciprocally downconverted by jitter. Therefore, in the presence of the jitter the receiver performance is not jeopardized from the blockers close to a null. Another way, that jitter can degrade the SNR is its inevitable distortion to the desired signal itself even in the absence of the blocker [(38)] [15]. The SNR of sampled signal is still far better than what is typically needed at the end of the receiver chain. Thus, this effect is negligible in an SDR receiver and is not discussed further. V. NOISE ANALYSIS A. Switch Noises Lets start with the resetting switch [Fig. 1(c)]. After the reset phase a noise voltage with of or equivalently a noise charge with of is stored on the capacitor C. When this capacitor is shorted to , charge-sharing equalizes

the two capacitor voltages and each capacitor holds its charge till the sampling moment. This leads us to seek for an equivalent white noise at the input which would cause the same impact. It is readily shown that such a white noise would possess a . This PSD is inspectral density of . Compared to the versely proportional to the dc gain transconductor input referred noise, , for a DC gain larger than , the noise of the reset switch is negligible3. Let us now consider the noise of the sampling switch. As described in Fig. 13(a), for the rst sample a noise voltage of with an of is stored on C. At the same time, the stored voltage on is which affects all future samples as follows: (44) (45) (46) is The -transformation of the signal , where . This amounts to the model shown in Fig. 13(a), in which a discrete-time white noise
3 is the transconductors noise factor, accounting for all its noise contributors.



Of course, since the wanted signal occupies a narrow band around dc, the sinc lter can be treated as a constant over the desired signal bandwidth. We can generalize this concept as a general theorem apis any time-limited plicable for time-limited signals. If signal over a time interval of , where , and if is its Fourier transform, then has the following mathematical property: dicing over intervals of followed by shifting to dc and then summation [Fig. 14(b)], results in a constant PSD independent of frequency . In other words, we have (48) This can be proved either using the concept of sampling and properties of white noise similar to the foregoing method, or using a direct mathematical approach. The reverse of this theis a complex function in the freorem also holds true: if quency domain, in which (48) holds true for a given , then is time-limited in a time interval of length at least . VI. CONCLUSION We explained the operation of the rst-order integration sampler which is suitable for use in SDR receivers. It was shown that with minor circuit modications, the circuit can be used either as a time-interleaved continuous-time analog FIR lter or an analog FIR lter followed by a discrete-time IIR lter without interleaving. The effect of all implementation nonidealities on the performance of the circuit was analyzed. These nonidealities include transconductor nite output resistance, switch on resistance, nite rise and fall time of the clock, and charge injection. We proved that only nite output resistance of the transconductor limits the null-depth and the linearity and noise are limited to those of the transconductor. Therefore, the transconductor determines the performance of the whole lter. We also analyzed the effect of the clock jitter on the lter noise performance in presence of blockers and proved that it has a superior robustness compared to the widely used impulse sampler. The analysis is conrmed with SPECTRE-RF simulations. REFERENCES
[1] J. Mitola, The software radio architecture, IEEE Commun. Mag., vol. 33, no. 5, pp. 2638, May 1995. [2] A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signals and Systems, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1996. [3] Digital Cellular Telecommunications System (Phase 2+): Radio Transmission and Reception, Rev. 8.15.0, European Telecommunication Standard Inst. (ETSI), 1999. [4] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1996. [5] R. H. Walden, Analog-to-digital converter survey and analysis, IEEE J. Sel. Areas Commun., vol. 17, no. 4, pp. 539550, Apr. 1999. [6] R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M. Mikhemar, W. Tang, and A. A. Abidi, An 800-MHz6-GHz software-dened wireless receiver in 90-nm CMOS, IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 28602876, Dec. 2006. [7] A. A. Abidi, Evolution of a software-dened radio receivers RF frontend, in Proc. IEEE RFIC Symp., San Francisco, CA, 2006, pp. 1720. [8] S. J. Orfanidis, Introduction to Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1995. [9] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specication, Further Higher-Speed Physical Layer Extension in the 2.4 GHz Band, IEEE Std. 802.11g, 2002.

Fig. 14. Property of time-limited signals explained using sampling of ltered white noise.

with of is high-pass ltered and then added to the desired samples. Consequently, noise components around dc are nulled out and the SNR is not degraded. Fig. 13(b) compares SPECTRE-RF simulation results with this prediction, which agree well. In conclusion, for the high-gain mode of the lter where higher SNR is demanded, noise contribution from the switches is negligible. B. White Noise at the Input Let us assume a white noise passes through a sinc lter and then sampled at a period of equal to integration time [Fig. 14(a)]. Since each sample is originated via integration over a time-interval nonoverlapped with others, the result is a discrete-time white noise. When interpreted using mathematical concepts, the continuous-time white noise goes through the sinc lter and is shaped to the colored power spectrum at the output. As a result of sampling, the discrete sampled data possesses a periodic spectrum over , in which the spectrum over frequency intervals of are added up after shifting to the main interval [Fig. 14(a)]. Independence of the discrete-time samples mandates this summation to be white, that is a constant PSD over . Indeed, mathematically it is proved that this summation is white. Therefore, including aliasing the equivalent input referred noise (IRN) is colored and is equal to (47)



[10] J. Yuan, A charge sampling mixer with embedded lter function for wireless applications, in Proc. 2nd Int. Conf. Microw. Millimeter Wave Technol., Beijing, China, 2000, pp. 315318. [11] Y. Poberezhskiy and G. Poberezhskiy, Sampling and signal reconstruction structures performing internal antialiasing ltering and their inuence on the design of digital recievers and transmitters, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 118129, Jan. 2004. [12] T. L. Brooks, D. H. Robertson, D. F. Kelly, A. D. Muro, and S. W. Harston, A 16 b sigma-delta pipeline ADC with 2.5 MHz output data-rate, in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 1997, pp. 208209. [13] C. Eichenberger and W. Guggenbuhl, On charge injection in analog MOS switches and dummy switch compensation techniques, IEEE Trans. Circuits Syst., vol. 37, no. 2, pp. 256264, Feb. 1990. [14] A. Mirzaei, R. Bagheri, S. Chehrazi, and A. A. Abidi, A second-order anti-aliasing prelter for an SDR receiver, in Proc. IEEE Custom Integrated Circuits Conf., Sep. 1821, 2005, pp. 629632. [15] A. Mirzaei, Clock programmable IF circuits for CMOS software dened radio receiver and precise quadrature oscillators, Ph.D. dissertation, Dept. of Elect. Eng., Univ. of California, Los Angeles, 2006. [16] B. Razavi, Design of Analog CMOS Integrated Circuit. New York: McGraw-Hill, 2000. [17] D. Chen, W. Wang, and T. Kwasniewski, Design considerations for a direct RF sampling mixer, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 11, pp. 934938, Nov. 2007. [18] A. Dei and M. Valle, Modelling charge injection in MOS analogue switches using a compact model in a deep submicron technology, in Proc. IEE Circuits, Devices Syst., Jun. 2006, vol. 153, pp. 268272. [19] G. Wegmann, E. A. Vittoz, and F. Rahali, Charge injection in analog MOS switches, IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 10911097, Dec. 1987. [20] J. Steensgaard, Bootstrapped low-voltage analog switches, in Proc. Int. Symp. Circuits Syst., Orlando, FL, May 30-Jun. 2 1999, vol. 2, pp. 2932. [21] A. M. Abo, Design for reliability of low-voltage switched capacitor circuits, Ph.D. dissertation, Dept. Elect. Eng and Comput. Sci., Univ. of California, Berkeley, 1999. [22] R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de Obaldia, and P. T. Balsara, All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 22782291, Dec. 2004. [23] K. Muhammad, Y. C. Ho, T. Mayhugh, C. M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M. C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, A discrete time quad-band GSM/GPRS receiver in a 90 nm digital CMOS process, in Proc. IEEE Custom Integrated Circuits Conf., Sep. 2005, pp. 809812. [24] G. Xu and J. Yuan, Performance analysis of general charge sampling, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 2, pp. 107111, Feb. 2005. [25] L. R. Cenkeramaddi and T. Ytterdal, Jitter analysis of general charge sampling ampliers, in Proc. Int. Symp. Circuits Syst., May 2006, pp. 52675270. [26] S. Karvonen, T. Riley, and J. Kostamovaara, On the effects of timing Jitter in charge sampling, in Proc. Int. Symp. Circuits Syst., May 2003, vol. 1, pp. 737740. [27] A. Demir, A. Mehrotra, and J. Roychowdhury, Phase noise in oscillators: A Unifying theory and numerical methods for characterization, IEEE Trans. Circuits Syst. I, Analog Digit. Signal Process., vol. 47, no. 5, pp. 655674, May 2000. Ahmad Mirzaei received the B.Sc. and M.Sc. degrees from Sharif University of Technology, Tehran, Iran, in 2000 and 2002, respectively, and the Ph.D. degree from the University of California, Los Angeles, in 2006, all in electrical engineering. He is currently a Senior Staff Scientist with Broadcom Corporation, Irvine, CA. His interests include analog and RF IC design for wireless communications.

Saeed Chehrazi received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 2001 and the M.Sc. and Ph.D. degrees from the University of California, Los Angeles (UCLA), in 2004 and 2008, respectively. Since joining UCLA, he has been involved in designing and modeling RF front-end circuits for software-dened radios. His research interests are RF, analog, and mixed-signal circuit design and modeling.

Rahim Bagheri received the B.Sc. and M.Sc. degrees (both with honors) from Sharif University of Technology, Tehran, Iran, in 1997 and 1999, respectively, and the Ph.D. degree from the University of California, Los Angeles (UCLA), in 2007, all in electrical engineering. His Ph.D. research team delivered the rst portable software-dened radio (SDR) receiver. From 1999 to 2000, he was with UCLAs MOSFET Research Laboratory, where he worked on sub-100-nm MOSFET design. He was with Valence Semiconductor Inc., Irvine, CA, from 2000 to 2001 as a Design Engineer working on 802.11a CMOS radio. He was with JAALAA Inc., Irvine, in 2003 as an RFIC Team Leader developing high-speed wireless CMOS chips with proprietary communication schemes. He cofounded WiLinx Inc., Los Angeles, developing CMOS wireless-communication chips for universal-UWB and Bluetooth over UWB systems in 2003. Since then, he has been with WiLinx, Inc., as CTO and President. He holds 12 patent applications in the eld of RF-CMOS design. Dr. Bagheri was the recipient of the Gold Medal in National Physics Olympiad and Honorable Mention Diploma in the XXIV International Physics Olympiad (1993). He was a recipient of the UCLA ICSRR Best Student Presentation Award (2006), the Analog Devices Outstanding Student Designer Award (2003), the UCLA Graduate Division Fellowship (2000), and the UCLA Regent Stipend Fellowship (1999).

Asad A. Abidi (S75M80SM95F96) received the B.Sc. (with honors) degree from the Imperial College, London, U.K., in 1976 and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1978 and 1981, respectively. From 1981 to 1984, he was with Bell Laboratories, Murray Hill, NJ, as a Member of Technical Staff with the Advanced LSI Development Laboratory. Since 1985, he has been with the Electrical Engineering Department, University of California, Los Angeles (UCLA), where he is a Professor. He was a Visiting Faculty Researcher with Hewlett-Packard Laboratories in 1989. His research interests are in CMOS RF design, high-speed analog integrated circuit design, data conversion, and other techniques of analog signal processing. Dr. Abidi was the Program Secretary for the IEEE International Solid-State Circuits Conference (ISSCC) from 1984 to 1990 and the General Chairman of the Symposium on VLSI Circuits in 1992. He was the Secretary of the IEEE Solid-State Circuits Council from 1990 to 1991. From 1992 to 1995, he was the Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He received an IEEE Millennium Medal, the 1988 TRW Award for Innovative Teaching, and the 1997 IEEE Donald G. Fink Award and is corecipient of the Best Paper Award at the 1995 European Solid-State Circuits Conference, the Jack Kilby Best Student Paper Award at the 1996 ISSCC, the Jack Raper Award for Outstanding Technology Directions Paper at the 1997 ISSCC, the Design Contest Award at the 1998 Design Automation Conference, an Honorable Mention at the 2000 Design Automation Conference, and the 2001 ISLPED Low Power Design Contest Award. He was named one of the top ten contributors to the ISSCC. He has been elected to the National Academy of Engineering, which is the highest professional lifetime distinction accorded to American engineers.