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K. Saravanan and K. Padmanathan

Abstract---This paper proposes a new circuit topology for a multilevel pulse width modulation (PWM) rectier. The proposed method forms a new circuit by combining a diode clamp-type topology with a ying capacitor-type topology. The proposed circuit uses only 12 switches, despite the use of a ve-level three-phase PWM rectier. Further, the proposed circuit can obtain good performance, same as a conventional multilevel circuit. This paper describes about the features of the proposed topology; the control strategy. In addition, the basic operation of the proposed method is conrmed by simulation results. The proposed converter achieved total harmonic distortion of 9.6% for the input current and efciency of 84.4% is simulated with Matlab /Simulink model. Keywords---AC-DC Power Conversion, Multilevel Systems, Harmonics, Pulse Width Modulated Converters, Rectifier. I. INTRODUCTION the cascaded type requires a large transformer and many switching devices. However, for the multilevel converters that are more than three-level, the DCLP type requires balance circuits in the dc part, in order to control the clamping capacitor voltage [10], [11]. And as for the FC type, it requires several capacitors for the clamping capacitors. In addition, both methods needed to use a high amount of switching devices. For example, in the case of a ve-level three-phase rectier, 24 switching devices are required. In conclusion, the problems of the multilevel converters would be number of switching devices and the control of clamping capacitors. This paper proposes a novel ve-level three-phase rectier topology, which combines the DCLP- and FC-type converters, and discusses about the control strategy. The proposed converter requires only half of the number of switches in comparison to the DCLP and FC types, that is, only 12 switches are used for the ve-level rectier. The point of the proposed topology is that high-voltage diodes can be more easily utilized than the high voltage switching devices. The features of the proposed circuit are described, and the space vector modulation is used as a control strategy. The use of space vector modulation can result in a good sinusoidal current of the power grid. II. CONVECTIONAL METHODS

HE harmonic current in the power grid causes various problems such as line voltage distortion and heating in power factor correction capacitors. The harmonic current in power grids is mainly generated by a diode rectier that is used as a front converter of an inverter. In order to reduce the harmonic current of the power grid, power factor correction (PFC) rectier still stands for a very important technology. A pulse width modulation (PWM) rectier, which is consisted of three switching legs, remains one of the popular PFC rectiers. A PWM rectier can reduce the harmonic current dramatically because the grid current is able to control. A PWM rectier requires high-voltage rating devices in order to be applied into the medium voltage applications. The high-voltage rating devices have known problems, such as low switching speed and large saturation voltage between the collector and the emitter. The low switching speed requires a large volume of a boost reactor and lter since the high switching frequency cannot be achieved For a medium voltage power grid, multilevel converter technology is one of the solutions for high-voltage rectication application [1][3]. In general, an n-level converter can reduce the voltage stress of a switching device to 1/(n 1) of the dc output voltage. There are many circuit congurations for a multilevel converter, such as the diode clamp (DCLP) type [4], [5] that uses clamp diodes and capacitors for the dc output voltage, the ying capacitor (FC) type [6], [7] that uses clamping capacitors oating on the dc output voltage, and the cascaded h-bridge type [8], [9] that uses isolated power supplies to clamp each level. In terms of cost reduction and downsizing, the DCLP and FC types are better solutions than the cascaded type, since

K. Saravanan, PG Student/Department of EEE, Adhiparasakthi Engineering College, Melamaruvathur, India. E-Mail: spksme@gmail.com K. Padmanathan, Assistant Professor/Department of EEE, Adhiparasakthi Engineering College, Melamaruvathur, India. E-Mail: padmanathankm@gmail.com

Fig. 1(a) and (b) shows the DCLP- and FC-type ve-level PWM rectier topology, respectively. The switching devices of both topologies are of the same voltage rating. Both converters can use a voltage rating of 1/4 for the dc output voltage; however, these converters use 24 switching devices. As a result, the cost will be increased and the control strategy is complicated. For example, the control strategy for the FCtype ve-level PWM rectier is described in the following. The FC-type ve-level PWM rectier has 16 switching patterns. The switching patterns and its rectier input voltage, which is the voltage point between the rectier and the boost up reactor, are based on the neutral point of the power grid. There are many switching patterns that can charge or discharge the FC disregards of the same voltage level. These switching patterns should be selected in order to control the voltage of each FC as constant. When the phase shift PWM is applied, the FC voltage will be kept constant [14], [15]. However, many voltage sensors are required to detect the voltage of the FC s in terms of the voltage protection of power devices. On the other hand, for the DCLP type, the clamping capacitor voltage cannot be controlled without an auxiliary circuit except for specic circumstances [12]. Additional voltage regulators, such as dc choppers, are required to

2nd International Conference on Advances in Engineering and Technology (ICAET2012), March 28 & 29, 2012 maintain each clamping capacitor voltage at quarter of the dc output voltage. III. PROPOSED CIRCUIT

TABLE I Comparison of Proposed Topology with DCLP, FC. DCLP Switch Diode Capacitor Control of the capacitor voltage 24 60 4 Impossible FC 24 24 22 Possible PROPOSED 12 24 8 Possible

in a medium voltage application, high-voltage rating (1/2Vdc) diodes are required. However, it costs lower than the high-voltage rating insulated gate bipolar transistors.

Fig. 2 shows the proposed ve-level PWM rectier using only12 switches. The proposed converter combines both the DCLP and FC types into one circuit. The voltage stress of the switch is 1/4Vdc, same as that of the conventional circuits. The voltage stress for diodes requires 1/2Vdcin the proposed circuit. The current waveform of the diode is PWM waveforms. However, the diode voltage does not receive reverse voltage for half period of the power grid frequency. As a result, there is no recovery mode in the high voltage diode. Thus, the cost of the high-voltage low speed Switching devices, such as a thyristor or a gate turn-off thyristor, can be applied, because the high-voltage switching devices do not switch at high frequency, but only switch at the same frequency of the power grid. The proposed topology can be applied for both low-voltage (200 V, 400 V) application and medium voltage (3.3 kV, 6.6 kV) application. In the lowvoltage application, the low-voltage rating MOSFETs can be used to improve the switching frequency. On the other hand,

Table I shows a comparison among the DCLP, FC, and proposed rectier. The largest advantage of the proposed circuit is that the number of components in the proposed circuit could be used by using high-voltage diodes. The number of switching devices in the proposed circuit is reduced to 12, which is half of the conventional circuits. It should be noted that if the proposed concept is applied for n-level rectier topology, then the number of switching devices can always be reduced to half of that conventional n-level converter topology, because the outer diode can absorb half of the dc output voltage. The other large advantage of the proposed circuit is that the proposed circuit can control each of the clamping capacitor voltage. The voltage of the inner clamping capacitor C1can be controlled at 1/4Vdc, because the structure of the inside part is the same as that to the FC type. The voltage of the middle capacitors (C2and C3) can also be controlled at 1/2Vdc, because this part is the same as the three-level rectier. Note that the proposed circuit cannot run an invert operation where the reverse energy will ow into the circuit because the diodes are used instead of switches.

Fig-1: Conventional Five-Level PWM Rectier Topologies (Single Leg). (a) Diode Clamp (DCLP). (b) Flying Capacitor (FC)

.

Fig-3: Rectifier Input Voltage

Fig. 3 shows the voltage waveform of the rectier input voltage. It is noted that the zero level of the rectier input voltage is dened as the neutral point voltage of the dc output part. Five-step stair waveform is obtained as the rectier input voltage, which is divided into six sectors by the voltage levels. In principle, the proposed circuit can output seven voltage levels to the ac side of the converter. However, in order to control the inner clamping capacitor (C1 ) voltage Vc , two switching patterns for the charge or discharge mode are required. Table II indicates the switching pattern table of the proposed rectifier. The inner clamping capacitor voltage is controlled by selecting the switching patterns, where it will appear as the same voltage to the rectifier input voltage but the inner clamping capacitor is controlled to either being charged

2nd International Conference on Advances in Engineering and Technology (ICAET2012), March 28 & 29, 2012 or discharged. For example, in the Sector II, when the rectifier input voltage is +Vdc/2 or +Vdc/4, if the inner clamping capacitor voltage Vc is lower than its command V c, the charge mode (S2 and S4 are turned ON) will be selected. On the other hand, if Vc is higher than V c , the discharge mode (S1 and S3 are turned ON) will be selected. Thus, the inner clamping capacitor voltage can be controlled constantly at all sectors. The switching pattern including the zero-phase sequence component is selected according to the input voltage polarity due to the limitation of the current path that is caused by the clamping diodes. For example, when the input voltage is positive, the switching pattern 0 in Table II will be selected for the zero level to increase the neutral point voltage. On the other hand, when the switching pattern 0 is selected where the input voltage is negative, the neutral point voltage will be decreased. As a result, the dc part capacitor (C3) voltage can be balanced.

TABLE II Switching Table for the Proposed Rectifier SECTOR I II III IV V VI VOLTAGE LEVEL +Vdc/4 , 0 +Vdc/2, +Vdc/4 +Vdc/4 , +0 -0 , -Vdc/4 -Vdc/4, -Vdc/2 -0 , -Vdc/4 TURN-ON SWITCHES S1-S3 , S3-S4 S1-S2 , S2-S4 S2-S4 , S3-S4 S1-S2 , S2-S4 S1-S3 , S3-S4 S1-S2 , S2-S4 vector V0 (000) V1 (100) V2 (110) P P N N N P Point A Point B A=B=C=0 N P P P N N A=B=C=0 N N N P P P Point C VAB 0 +V0 0 -V0 -V0 0 +V0 0 VBC 0 0 +V0 +V0 0 -V0 -V0 0 VCA 0 -V0 -V0 0 +V0 +V0 0 0

To implement space vector modulation as show in fig.4, a reference signal Vref is sampled with a frequency fs (Ts = 1/fs). The reference signal may be generated from three separate phase references using the abc transform. The reference vector is then synthesized using a combination of the two adjacent active switching vectors and one or both of the zero vectors. Various strategies of selecting the order of the vectors and which zero vector to use exist. Strategy selection will affect the harmonic content and the switching losses.

IV.

Fig. 4 shows the space vector for the proposed five-level rectifier, where x represents the top of the voltage vector. In the case of the proposed rectifier, there are 61 kinds of the voltage vectors, except for the charge or discharge switching patterns to the inner clamping capacitor in the proposed circuit. First, the nearest three space vectors surrounding at the top of the output voltage vector of the rectifier are selected. Second, the output time ratio of each of the voltage vector is calculated. Finally, the charge or discharge mode vector is selected according to the inner clamping capacitor voltage and the neutral point voltage of the dc output part.

From the analysis of the rectifier topologies, eight available vectors are defined, as shown in Table I. non null vectors are represented by the potential of points A, B, and C, and the null vector represents the situation where the three points are connected. The determination of switching instant may be achieved using space vector modulation technique based on the representation of switching vector in plane. V. SIMULATION RESULTS

The SVM has six symmetrical operation intervals, where the current sectors are defined for one full cycle period: C, A+, B, C+, A, and B+, as shown in Fig. 6. Each sector has an interval. I t is defined by the current that has the greatest value and its respective signal.

Fig 7 shows the simulation of the proposed rectifier at 50 Hz input frequency done by using MATLAB/Simulink. Clean sinusoidal input current waveform is obtained, and the total harmonic distortion (THD) for the input current is 9.6%. However, there is a distortion at the zero-cross point of the input current. The reason of the distortion is a phase shift of the input current depends on the input inductor.

2nd International Conference on Advances in Engineering and Technology (ICAET2012), March 28 & 29, 2012 In the angle calculation sub-model, the interval test is carried out between two angles and the corresponding vector is chosen. The vector location sub model is shown in the figure 11.

Then, the switching vectors are given as a input for the switching look-up table to get a multilevel converted rectifier input. The generated gate pulses are shown in the figure 12

After that, the angle calculation is done by taking interval test for five-level space vector diagram which is shown in the figure 10.

Figure 13 shows the simulation results of the proposed rectifier. The input voltage 220V, 50Hz supply is given to the proposed topology, the rectifier input voltage is converted into five levels and its given as a input of the rectifier. The proposed rectifier also acts as a boost converter because of the circuit topology. The inner clamping voltage is balanced for a variable switching sequence at the range of 200V DC. The THD achieves by the proposed rectifier is 9.6% and power factor is 0.83 for the output power of 2KW. Figure 14, shows the Output voltage and current of the proposed rectifier is 400V, 5A.

2nd International Conference on Advances in Engineering and Technology (ICAET2012), March 28 & 29, 2012

[6] [7] A. Sneineh, M. Wang, Novel Hybrid Flying-Capacitor -Half- Bridge 9Level Inverter, TENCON 2006. X. Kou, K. A. Corzine, and Y. L. Familiant, A Unique Fault-Tolerant Design for Flying Capacitor Multilevel Inverter, IEEE Transactions on power electronics, vol.19, no.4, pp. 979-987, 2004. D. Kang, Y. Lee, B. Suh, C. Choi, and D. Hyun, An Improved CarrierBased SVPWM Method Using Leg Voltage Redundancies in Generalized Cascaded Multilevel Inverter Topology, IEEE Transactions on power electronics, vol.18, no.1, pp. 180-187, 2003. F. Z. Peng, J, W. McKeever, and D. J. Adams, A Power Line Conditioner Using Cascade Multilevel Inverters for Distribution Systems, IEEE Transactions on industry applications, vol.34, no.6, pp. 1293-1298, 1998. F. Z. Peng, A Generalized Multilevel Inverter Topology with Self Voltage Balancing, IEEE Transactions on industry applications vol.37, no.2, pp. 2024-2031, 2001. N. Hatti, K. Hasegawa, and H. Akagi, A 6.6-kV transformerless motor drive using a five-level diode-clamped PWM inverter for energy savings of pumps and blowers, IEEE Trans. Power Electron., vol. 24, no. 3, pp. 796803, Mar. 2009. M. Saeedifard, R. Iravani, and J. Pou, A space vector modulation strategy for a back-to-back five-level HVDC converter system, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 452466, Feb. 2009. J.-I. Itoh, T. Iida, and A. Odaka, Realization of high efficiency ac link converter system based on ac/ac direct conversion techniques with RBIGBT, presented at the Ind. Electron. Conf., Paris, France, 2006. D.-W. Kang, B.-K. Lee, J.-H. Jeon, T.-J. Kim, and D.-S. Hyun, A symmetric carrier technique of CRPWM for voltage balance method of flying capacitor multilevel inverter, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 879888, Jun. 2005. C. Feng, J. Liang, and V.G.Agelidis, Modified phase-shifted PWM control for flying capacitor multilevel converters, IEEE Trans. Power Electron., vol. 22, no. 1, pp. 178185, Jun. 2007.

[8]

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[10]

[11]

[12]

[13]

[14]

[15]

VI.

CONCLUSION

A novel multi-level PWM rectifier and its control strategy have been proposed. The rectifier also works as a boost converter and its simulated with DC motor Load. Features of the proposed circuit are the reduction in the number of switching devices, and a controllable clamping capacitor voltage. The proposed converter achieves THD of 9.6% for the input current at a 2 kW load. Also, the efficiency of the proposed rectifier reaches 84.4% and the power factor of 0.83. The output voltage of the proposed rectifier is 400V DC. REFERENCES

[1] B. Singh, B. N. Singh, and A. Chandra, et al, A Review of Three Phase Improved Power Quality AC-DC Converters, IEEE Transactions on industrial electronics, vol.51, no.3, pp.641-660, 2004. J. Rodrguez, J. Lai, and F. Z. Peng: Multilevel Inverters: A Survey of Topologies, Controls, and Applications, IEEE Transactions on industrial electronics, vol.49, no.4, pp.724-738, 2002 U. Drofenic, J. W. Kolar, Y. Nishida, Y. Okuma, and J. Sun, Three Phase PFC Rectifier Systems, PCC-Osaka 2002 Tutorials, pp.293,2002. X. Yuan, I. Barbi, Fundamentals of a New Diode Clamping Multilevel Inverter, IEEE Transactions on power electronics, vol.15, no.4, pp.711718, 2000. Z. Pan, F. Z. Peng, and K. A. Corzine, et al, Voltage Balancing Control of Diode-Clamped Multilevel Rectifier/Inverter Systems, IEEE Transactions on industry applications, vol.41, no.6, pp.1698-1706, 2005.

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