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OBSERVATION NOTE BOOK

FOR

DIGITAL ELECTRONICS

LABORATORY

Name of the Student : ……………………………………………….. Reg. No. / Roll No. : ………………………………………………... Degree & Branch : ………………………………………………...

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VIDYAA VIKAS COLLEGE OF ENGG & TECH

DIGITAL ELECTRONICS LAB

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VIDYAA VIKAS COLLEGE OF ENGG & TECH

DIGITAL ELECTRONICS LAB

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INSTRUCTIONS

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The students are required to get the approval from the lab in charge within the first 15 minutes.

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The approval is given for the students who have recorded the Aim of the Experiment, Apparatus required, Theory, Procedure, Circuit diagram and the Truth Table in the Observation.

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The students can proceed with the Experiment only after the above approval.

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Verification is required from the Lab In Charge after the completion of the experiment.

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Verified Experiments are to be recorded in the record file and can be submitted in the next class.

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VIDYAA VIKAS COLLEGE OF ENGG & TECH

DIGITAL ELECTRONICS LAB 4 4 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

Full adder and Subtractors using NAND Gates. 6 7 8 Design of Parity generator. &BCD). &BCD). 1’s complement b. Down.g. Design of Synchronous Counters (Up. 4 Design of RS and JK Flip flops using NAND Gates. 10 11 12 Shift Registers (all types). Design of Decoders and Encoders. 2’s complement 14 Memories.NO SIGNATURE 5 VIDYAA VIKAS COLLEGE OF ENGG & TECH . 3 Design of Half adder. 9 Design of Asynchronous Counters (Up. a. Multiplexer and Demultiplexer and extensions(e. PAGE. 4 to 8) 13 Binary Addition/Subtraction. Design of Ring Counters.NO 1 NAME OF THE EXPERIMENT Transfer characteristics and specifications of TTL & MOS gates. excess-3 code etc). 2 Verification of Laws & Theorems and realization of circuits for Boolean expression after simplification.DIGITAL ELECTRONICS LAB 5 CONTENTS S. 5 Design of code converters (GREY to BCD & vice versa. Down.

DIGITAL ELECTRONICS LAB 6 6 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

To prevent this. With Q2 open. Since Q3 acts as an emitter follower. we can simplify its analysis by using the diode equivalent of the multiple-emitter transistor Q1. The input voltages A and B are either LOW (ideally grounded) or HIGH (ideally +5volts). APPARATUS REQUIRED: SPECIFICATION/ RANGE IC7400 1k. the Y output is pulled up to a HIGH voltage. 130. If either A or B or both are low. Q4 goes into cutoff. Diodes D2 and D3 represent the two E-B junctions of Q1 and D4 is the collector-base (C-B) junction. Therefore. one for each input to the gate. 1 2 3 4 5 COMPONENTS NAND GATE Resisters Qty 2 1 Digital Trainer Kit Digital Power Supply (0 – 12) V (0 – 5) V 1 1 THEORY: TTL can be noticed that Q1 is an NPN transistor having two emitters.DIGITAL ELECTRONICS LAB 7 EX. 7 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Without diode D1. the emitter diodes of Q1 are reversed biased making them off. and the Q3 base is pulled HIGH.7v. On the other hand. 4k. This reduces the base voltage of Q2 to almost zero. In this way. This causes the collector diode D4 to go into forward conduction. 1. when A and B both are HIGH. its voltage drop keeps the base-emitter diode of Q3 reverse-biased. in the circuit. the corresponding diode conducts and the base of Q1 is pulled down to approximately 0. producing a low output. the diode is inserted. Sl. Q2 cuts off. Q3 will conduct slightly when the output is low.NO: 1 TRANSFER CHARACTERISTICS AND SPECIFICATIONS OF TTL & MOS GATE DATE: AIM: To find the Transfer characteristics and Specifications of TTL & MOS Gates. In turn.No. Q4 goes into saturation.6k. This forces Q2 base to go HIGH. only Q4 conducts when the output is low. Although this circuit looks complex. Table summarizes all input and output conditions.

Since 8 VIDYAA VIKAS COLLEGE OF ENGG & TECH . since the sources are connected to + VDD . Since the gate-tosource voltages of Q3 and Q4 (N-channel MOSFETs) are both 0v. Q1 is on because + VGS1=. P-channel MOSFET is ON when its gate voltage is negative with respect to its source whereas N-channel MOSFET is ON when its gate voltage is positive with respect to its source. It consists of two P-channel MOSFETs. MOSFETs Q2 and Q3 are off because their gate-to-source voltages are 0v. The equivalent switching circuit when both inputs are low.VDD and Q4 is ON because + VGS4=+ VDD. Thus Q1 and Q2 are both ON. The output is therefore connected to + VDD (HIGH) through Q1 and Q2 and is disconnected from ground. connected in parallel and two N-channel MOSFETs. Here. the gates of both P-channel MOSFETs are negative with respect to their courses. those MOSFETs are OFF. Q1 and Q2. the equivalent switching circuit when A=0 and B=+ VDD .DIGITAL ELECTRONICS LAB CIRCUIT DIAGRAM: 8 TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 CMOS NAND Gate: CMOS 2 input NAND gate. In this case. Q1 and Q4 connected in series.

Thus. when both inputs are high (A=B=+ VDD). MOSFETs Q1 and Q2 are both OFF and Q3 and Q4 are both ON. the output is connected to the ground through Q3 and Q4 and it is disconnected from + VDD. the output is connected to + VDD and it is disconnected from ground. When a=+ VDD and B=0v. Connect the components as per the given circuit. Check for the output as given in the characteristics table by the glowing of LED. The table summarizes the operation of 2-input CMOS NAND gate. 3. CIRCUIT DIAGRAM TRUTH TABLE: A 0 0 1 1 B Q1 Q2 Q3 Q4 Output 0 ON ON OFF OFF 1 1 ON OFF OFF ON 1 0 OFF ON ON OFF 1 1 OFF OFF ON ON 0 PROCEDURE: 1. Apply the bits as per the truth table. the output is connected to + VDD through Q2 and it is disconnected from ground because Q4 is OFF. Finally.DIGITAL ELECTRONICS LAB 9 Q1 is ON and Q3 is OFF. the situation is similar (not shown). 2. Result: 9 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

The resulting reduced expression can then be readily tested with a Truth Table. reduces the number of gates needed. The simpler expression can then be implemented with a smaller.DIGITAL ELECTRONICS LAB 10 Ex. The rules of Boolean Algebra are simple and straightforward. introduced by George Boole in 1854 and known today as Boolean Algebra. simpler circuit. 10 VIDYAA VIKAS COLLEGE OF ENGG & TECH . to verify that the reduction was valid. APPARATUS REQUIRED: Sl.No. and can be applied to any logical expression. AIM: To Verify the Boolean theorem using logic gates. which in turn saves the price of the unnecessary gates. and reduces the power and the amount of space required by those gates. This constantly requires that complex logical expressions be reduced to simpler expressions that nevertheless produce the same results under all possible conditions. One tool to reduce logical expressions is the mathematics of logical expressions. No: 2 DATE: VERIFICATION OF LAWS & THEOREMS AND REALIZATION OF CIRCUITS FOR BOOLEAN EXPRESSION AFTER SIMPLIFICATION . 1 2 3 4 5 COMPONENTS AND Gate OR Gate NOT Gate Digital IC Trainer Digital Power Supply SPECIFICATION/ RANGE IC7408 IC7432 IC7404 IC 7486 IC 7400 Qty 1 1 1 1 1 THEORY: One of the primary requirements when dealing with digital circuits is to find ways to make them as simple as possible.

PQ = W.PQ = W.DIGITAL ELECTRONICS LAB The rules of Boolean Algebra are: AND Operations (·) 0·0 = 0 1·0 = 0 0·1 = 0 1·1 = 1 0+0 = 0 1+0 = 1 0+1 = 1 1+1 = 1 0' = 1 1' = 0 Associative Law (A·B)·C = A· (B·C) = A·B·C (A+B)+C = A+ (B+C) = A+B+C Distributive Law A· (B+C) = (A·B) + (A·C) A+ (B·C) = (A+B) · (A+C) Commutative Law A·B = B·A A+B = B+A Precedence AB = A·B A·B+C = (A·B) + C A+B·C = A + (B·C) DeMorgan's Theorem (A·B)' = A' + B' (NAND) A·0 = 0 A·1 = A A·A = A A·A' = 0 A+0 = A A+1 = 1 A+A = A A+A' = 1 A’’ = A 11 OR Operations (+) NOT Operations (') (A+B)' = A' · B' (NOR) Expression => X=W+PQ X= W+PQ = W.PQ 11 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

DIGITAL ELECTRONICS LAB 12 CIRCUIT DIAGRAM 12 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

B 0 0 0 1 7408 3 Y = A.B 0 1 1 PIN DIAGRAM VCC 14 13 12 11 10 9 8 12 11 13 9 8 10 IC7408 1 3 2 5 4 6 1 2 3 4 5 6 7 GND 13 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB 13 OR GATE SYMBOL A B 1 3 2 TRUTH TABLE A B 0 1 0 1 Y= A+B 0 1 1 1 7432 Y= A+B 0 0 1 1 PINDIAGRAM VCC 14 13 12 11 10 9 8 12 11 13 9 8 10 IC7432 1 3 2 5 4 6 1 2 3 4 5 6 7 GND AND GATE TRUTH TABLE SYMBOL A B 1 2 A 0 B 0 1 0 1 Y = A.

B A 0 0 1 1 B 0 1 0 1 _____ Y= A.DIGITAL ELECTRONICS LAB 14 NOT GATE SYMBOL ___ Y= A A 0 1 PINDIAGRAM VCC 14 13 12 11 10 9 8 TRUTH TABLE __ Y= A 1 0 A 1 7404 2 13 12 11 10 9 8 IC7404 1 2 3 4 5 6 1 2 3 4 5 6 7 GND NAND GATE SYMBOL A B 1 2 TRUTH TABLE ____ Y= A.B 1 1 1 0 7400 3 PINDIAGRAM VCC 14 13 12 11 10 9 8 12 11 13 9 8 10 IC7400 1 3 2 5 4 6 1 2 3 4 5 6 7 GND 14 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

DIGITAL ELECTRONICS LAB NOR GATE SYMBOL A B 2 1 3 15 7402 ______ Y= A+B A 0 0 1 1 TRUTH TABLE B 0 1 0 1 _____ Y= A+B 1 0 0 0 PINDIAGRAM VCC 14 13 12 11 10 9 8 12 13 11 10 9 8 7402 3 1 2 4 5 6 1 2 3 4 5 6 7 GND EXOR GATE TRUTH TABLE 7486 3 A B 1 2 Y= A + B A 0 0 1 1 B 0 1 0 1 Y= A + B 0 1 1 0 PINDIAGRAM VCC 14 13 12 11 10 9 8 12 11 13 9 8 10 IC7486 1 3 2 5 4 6 1 2 3 4 5 6 7 GND 15 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

4. 16 RESULT: QUESTIONS: 1. Define Boolean Algebra. 16 VIDYAA VIKAS COLLEGE OF ENGG & TECH . For the above given functions form the truth table. 2.DIGITAL ELECTRONICS LAB PROCEDURE: 1. Using basic Gate implements the function. Verify the truth table. 2. State the Boolean theorems State the Duality theorem State the Boolean Law. 3. 3.

These are two inputs to the half adder designated sum and carry . APPARATUS REQUIRED: Sl. The function of half adder is adding two binary digits producing a sum and carry. No: 3 Date: DESIGN HALF ADDER. The relationship can be written as Sum = A⊕B AB Carry = TRUTH TABLE A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1 17 VIDYAA VIKAS COLLEGE OF ENGG & TECH .No. Full adder.DIGITAL ELECTRONICS LAB Ex. If both the inputs are 1’s then the output on the C will be 1 . 1 2 3 COMPONENTS NAND Gate Digital Trainer Kit Digital Power Supply SPECIFICATION/ RANGE IC 7400 (0 – 12) V (0 – 5) V Qty 10 1 1 HALF ADDER THEORY: A basic module used in binary arithmetic elements is the half adder.for other states. there will be a ‘0’ output on the carry line. not logical and Boolean addition. Half subtractor and Full subtractor using Logic gates and verify the truth table. This is Arithmetic addition.The half adder performs binary addition operation for two binary inputs. If either of the inputs is a ‘1’ but not both. the output on the Sum will be ‘1’. FULL ADDER AND SUBTRACTORS USING NAND GATES 17 AIM: To design and construct Half adder.

DIGITAL ELECTRONICS LAB CIRCUIT DIAGRAM: 18 A⊕B 18 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

The relationship can be written as Sum = (A ⊕ B) ⊕ C AB + (A + B) C Carry = The full Adder can be constructed using two Half Adders and an AND Gate TRUTH TABLE: C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1 CIRCUIT DIAGRAM: A⊕B A⊕B⊕C 19 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB FULL ADDER: THEORY: 19 A full adder is the combinational circuit that forms the arithmetic sum of three input bits. The full adder accepts three inputs and generates a sum output and carries output.

It also has an output to specify if a 1 has been borrowed.Y. The result is called difference bit .To perform X .1 X 0 0 1 1 Y 0 1 0 1 D 0 1 1 0 B 0 1 0 0 20 VIDYAA VIKAS COLLEGE OF ENGG & TECH .2. we have to check the relative magnitude of X and Y. The second output. Designate the minuend bit by X and the subtrahend bit by Y.One output generates the difference and will be designated by the symbol D.The half subtractor needs two outputs .DIGITAL ELECTRONICS LAB HALF SUBTRACTOR: THEORY: 20 A Half Subtractor is a combinational circuit that subtracts two bits and produces their difference . generates the binary signal that informs the next stage that a 1 has been borrowed CIRCUIT DIAGRAM: TRUTH TABLE x y 1 1 2 3 D=X+Y 1 2 1 2 3 B=X'Y HALF-SUBTRACTOR Truth Table 3. designated B for borrow.

taking into account that 1 has been borrowed by a lower significant stage. Y. The circuit has three inputs and two outputs .The three inputs X. Z denotes the minuend.The two outputs D and B represents the difference and output borrow respectively TRUTH TABLE: Input Z 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 Y 0 1 0 1 0 1 0 1 Output D 0 1 1 0 1 0 0 1 B 0 1 1 1 0 0 0 1 21 VIDYAA VIKAS COLLEGE OF ENGG & TECH . subtrahend and previous borrow respectively .DIGITAL ELECTRONICS LAB 21 X Y D= X ⊕ Y B=X’• Y FULL SUBTRACTOR THEORY A full subtractor is a combinational circuit that performs the subtraction between two bits.

DIGITAL ELECTRONICS LAB 22 CIRCUIT DIAGRAM: x 1 1 y z 2 1 1 2 4 5 9 10 AND2 AND2 AND2 3 1 2 6 5 OR2 OR2 3 4 7432 6 B=X'Y+X'Z+YZ 8 4 5 1 2 3 XOR2 6 D=X+Y+Z X Y X⊕Y D Z B D=X⊕Y⊕Z B=(X⊕Y)Z+X’Y 22 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

Show by Boolean Function how a Full Adder can be constructed by two Half Adder and an OR gate.DIGITAL ELECTRONICS LAB 23 PROCEDURE: 1. 2. 4. What is a Half Adder? Design and implement it using NOR gate. Show by Boolean Function how a Full Subtractor can be constructed by two Half Subtractor and an OR gate? 23 VIDYAA VIKAS COLLEGE OF ENGG & TECH . RESULT: . 4. Connect the components as per the given circuit. 3. QUESTIONS: 1. Apply the bits as per the truth table. 3. 2. Check for the output as given in the characteristics table by the glowing of LED. Define Combinational circuit. What is a Half Subtractor? Design and implement it using NOR gate? 5. Draw the conclusion.

1 2 3 4 5 6 7 COMPONENTS NAND GATE 3 INPUT AND GATE 2 INPUT AND GATE NOT GATE NOR GATE Digital Trainer Kit Digital Power Supply SPECIFICATION/ RANGE IC7400 IC7411 IC7408 IC7404 IC7402 (0 – 12) V (0 – 5) V Qty 1 2 1 1 1 1 1 RS FLIP FLOP THEORY • A flip-flop circuit can maintain a binary state indefinitely (as long as the power is delivered to the circuit) until directed by the input signal to switch states .At the starting point assume the set input is 1 and the reset input is 0.the outputs remain the same .which puts both inputs of gate 1at 0. we must remember that output of an NOR Gate is0 if any input is 1 .its output Q’ must be 0 .JK flip-flop to verify their truth table. and two inputs. No: 4 Date: AIM: To construct flip-flops like RS flip-flop.DIGITAL ELECTRONICS LAB Ex.Since gate 2 has an input of 1 .the major differences among various types of flip flops are in number of inputs they possess and in the manner in which the inputs affects the binary state • A flip-flop can be constructed from two NAND gates or two OR gates .for this reason the circuits are called as asynchronous sequential circuits each flip-flop has two outputs. Q and Q’. 24 DESIGN OF RS AND JK FLIP FLOPS USING NAND GATES APPARATUS REQUIRED: Sl.To analyze the operation of the circuit. set and reset This type of flip-flop is sometimes called direct coupled RS flip-flop or SR latch .because the output Q remains a 1 .When the set input is returned to 0.The cross coupled connection from the output of one gate to the input of other gate constitutes a feedback path .No.this causes output Q’ to stay at 24 VIDYAA VIKAS COLLEGE OF ENGG & TECH .so that output Q is 1 .leaving one input of gate 2 at 1.and the output is 1 only when all the inputs are 0 .

this condition must be avoided by making sure that 1’s are not applied to both inputs simultaneously. In normal operation. PINDIAGRAM: TRUTH TABLE: S 1 0 0 0 1 R 0 0 1 0 1 Q 1 1 0 0 0 Q’ 0 0 1 1 0 25 VIDYAA VIKAS COLLEGE OF ENGG & TECH . When the reset input returns to 0 the output do not change. both Q and Q’ outputs go to 0. In the same manner it is possible to show that a 1 in the reset input changes Q to 0 and Q’ to 1. This condition violates the fact that outputs Q and Q’ are the complements of each other. • When a 1 is applied to both the set and the reset inputs.DIGITAL ELECTRONICS LAB 25 0 which leaves both inputs of gates number 1 at 0 .so the output Q is a1 .

The input marked J is for set and the input marked k is for Reset. Inputs J and K behave like inputs S and R to set and clear the flip-flop respectively . that is if Q=1 it switches to Q=0 and vice versa. PINDIAGRAM 26 VIDYAA VIKAS COLLEGE OF ENGG & TECH . When both inputs J and K are equal to 1.DIGITAL ELECTRONICS LAB CIRCUIT DIAGRAM: 26 JK FLIP-FLOP THEORY A JK flip flop is a refinement of the RS flip flop in that the indeterminate state of the RS type is defined in the JK type. the flip-flop switches to its complement state.

2. 4. Check for the output as given in the characteristics table by the glowing of LED.DIGITAL ELECTRONICS LAB TRUTH TABLE: 27 J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q’(t) CIRCUIT DIAGRAM: PROCEDURE: 1. Draw the conclusion. 27 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Connect the components as per the given circuit. Apply the bits as per the truth table. 3.

Give the difference between positive and negative edge triggering? 28 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB 28 RESULT: QUESTIONS: 1. 5. Define sequential circuit. What is a flip-flop? 3. What is the difference in the implementation of RS flip-flop using NAND and NOR gate? 4. Explain triggering. Define characteristic table. 2.

No: 5 DESIGN OF CODE CONVERTERS (GREY to BCD & Vice versa.NO 1 2 3 4 5 6 COMPONENTS OR GATE EXOR GATE AND GATE NOT GATE DIGITAL TRAINER KIT DIGITAL POWER SUPPLY SPECIFICATION/RANGE IC7432 IC7486 IC 7408 IC7404 (0-12) V (0-5) V QUANTITY 1 1 1 1 1 1 THEORY: The communication systems requires various types of data codes for security purposes. it is a number system rages from the decimal values 0 and 9. This circuit accepts a 4-bit binary code input and converts into its equivalent 4 bit gray code. 3d) to the original data.. Excess-3 code etc) DATE: AIM: To design and verify the operations of Binary to Gray code converter. so we need some code converters to convert the actual data into some other form. Gray to Binary code converter. BCD code to Excess-3 code converter: Excess – 3 code means adding the binary value 011(i.e. This circuit accepts the 4-bit BCD value and converts into its equivalent 4 bit Excess-3 code. The commonly used code converters are binary code to gray code and BCD to Excess 3 code and vice versa converters.DIGITAL ELECTRONICS LAB 29 Ex. APPARATUS REQUIRED: S. BCD stands for Binary Coded Decimal. 29 VIDYAA VIKAS COLLEGE OF ENGG & TECH . BCD to Excess 3 code converter and Excess 3 to BCD code converter using Logic gates. Binary code to Gray code converter: Gray code is a one bit change code which is used in many decoding applications like Optical shaft encoders.

DIGITAL ELECTRONICS LAB CIRCUIT DIAGRAM: 1. BINARY TO GRAY CODE CONVERTER: 30 TRUTH TABLE: Input Binary Code B4 B2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Output Gray Code G1 G2 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 B8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G3 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 30 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

GRAY TO BINARY CODE CONVERTER: 31 TRUTH TABLE: Input Gray Code G1 G2 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 Output Binary Code B4 B2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 G0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G3 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 B8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 31 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB 2.

DIGITAL ELECTRONICS LAB 32 3. BCD TO EXCESS-3 CODE CONVERTER: TRUTH TABLE: Output Excess-3 code B0 0 0 0 0 0 0 0 0 1 1 B1 0 0 0 0 1 1 1 1 0 0 B2 0 0 1 1 0 0 1 1 0 0 B3 0 1 0 1 0 1 0 1 0 1 E0 0 0 0 0 0 1 1 1 1 1 E1 0 1 1 1 1 0 0 0 0 1 E2 1 0 0 1 1 0 0 1 1 0 E3 1 0 1 0 1 0 1 0 1 0 32 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

DIGITAL ELECTRONICS LAB 33 4. EXCESS-3 TO BCD CODE CONVERTER: TRUTH TABLE: Input Excess-3 code E8 E4 E2 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 E1 1 0 1 0 1 0 1 0 1 0 B8 0 0 0 0 0 0 0 0 1 1 Output BCD Code B4 B2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 B1 0 1 0 1 0 1 0 1 0 1 33 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

**DIGITAL ELECTRONICS LAB
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PROCEDURE: 1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table.

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3. Check for the output as given in the characteristics table by the glowing of LED.

RESULT:

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VIDYAA VIKAS COLLEGE OF ENGG & TECH

DIGITAL ELECTRONICS LAB

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EX. NO: 6

DATE: AIM:

DESIGN OF PARITY GENERATOR

To design and verify the operation of 16 bit odd / even parity checker generator using IC74180

APPARATUS REQUIRED: Sl.No. 1 2 3 THEORY: 16 BIT ODD/EVEN PARITY CHECKER/GENERATOR: IC74180 is a monolithic, 8 bit parity checker / generator which features control inputs and even/odd outputs to enhance operation in either odd or even parity applications. Cascading these circuits allows unlimited word length expansion. Typical application would be to generate and check parity on data being transmitted from one register to another.16 bit circuit could be designed by cascading two IC74180. TRUTH TABLE: COMPONENTS 8 bit odd/parity checker Digital Trainer Kit Digital Power Supply SPECIFICATION/R ANGE IC74180 (0 – 12) V (0 – 5) V Qty 2 1 1

L – Logic low, H – Logic High X – Don’t care

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VIDYAA VIKAS COLLEGE OF ENGG & TECH

DIGITAL ELECTRONICS LAB

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PIN DESCRIPTION:

CIRCUIT DIAGRAM:

PIN DIAGRAM:

LOGICAL SYMBOL:

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VIDYAA VIKAS COLLEGE OF ENGG & TECH

Apply the bits as per the truth table. 2. RESULT: 37 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Connect the components as per the given circuit. 3.DIGITAL ELECTRONICS LAB 37 PROCEDURE: 1. Check for the output as given in the characteristics table by the glowing of LED.

The output is 10 (binary 2) if D2 is equal to 1. 2. the X ‘s are don’t care conditions that designate the fact that binary value may be equal to 1 or 0 • Input D3 has the highest priority level.The priority Encoder is an Encoder Circuit that includes the priority function. D2 has the next priority level . 38 DESIGN OF ENCODERS AND DECODERS APPARATUS REQUIRED: S.DIGITAL ELECTRONICS LAB Ex.The output lines generates the binary code corresponding to the input value • The above circuit shows the operation of Priority Encoder . designated by Z is set to 1 only when one or more of the inputs are equal to 1 . 3. so regardless of the value of other inputs. provided D3=0.the output of xy is 11 (binary 3).7 Date: AIM: To design and construct a combinational circuit for Encoder and Decoder using Logic Gates. and the other two outputs of the circuits are not used 38 VIDYAA VIKAS COLLEGE OF ENGG & TECH . when this input is 1. • The operation of the priority encoder is such that if two or more inputs are equal to one at the same time. regardless of the value of other two lower priority inputs . the input have the highest priority will take precedence • In the truth table. Components Require RPS Resistor LED IC’S Range +5V 330Ω --7432 7408 7404 7421 Quantity 1 4 4 1 1 1 2 ENCODER THEORY • • An Encoder is a digital circuit that performs the inverse operation of a decoder An Encoder has 2n input lines and n output lines . A valid output indicator. 4. No.Z is equal to 0.the output o for D1 is generated only if higher priority inputs are 0 and so on down the priority level.No 1.If all the inputs are 0.

DIGITAL ELECTRONICS LAB PINDIAGRAM 39 CIRCUIT DIAGRAM: D0 39 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

The 2 inverters provide complement of the inputs.The two inputs are decoded into 4 outputs. and each of the 4 AND gates generate one of the minterms TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 D0 1 0 0 0 D1 0 1 0 0 D2 0 0 1 0 D3 0 0 0 1 40 VIDYAA VIKAS COLLEGE OF ENGG & TECH . each output representing one of the minterms of the 2 input variables.DIGITAL ELECTRONICS LAB 40 X = D2 + D3 Y = D1D2’ + D3 Z = D0 + D1+ D2 + D3 TRUTH TABLE: D0 0 1 X X X D1 0 0 1 X X D2 0 0 0 1 X D3 0 0 0 0 1 X X 0 0 1 1 Y X 0 1 0 1 Z 0 1 1 1 1 DECODER THEORY • Discrete quantities of information are represented in digital systems with binary codes. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n • output lines The decoder presented here is called 2 to 4 line decoder .

41 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Connect the components as per the given circuit. Verification of glowing LED confirms the required data in the truth table. Apply the bits as per the truth table. . 2.DIGITAL ELECTRONICS LAB CIRCUIT DIAGRAM 41 D0 = A’B’ D1 = A’B D2 = AB’ D3 = AB PROCEDURE: 1. 3.

How many select lines are needed to construct a 1x8 Demultipexer? Design it. Realise a simple Boolean function of your choice using 4x1 MUX constructed by you. 2. What is an Encoder? 42 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Realise 3 input AND gate and 3 input OR gate using 4x1 MUX and 2 input AND function using 2x1 MUX.DIGITAL ELECTRONICS LAB 42 RESULT: QUESTIONS: 1. 9. 3. What is Multiplexing? 4 What is the difference between Multiplexing and Demultiplexing? 5What are different types of Multiplexing techniques? 6. What is a Demultiplexer? 7. What is the difference between Demultipexer and Decoder? 8.

No.DIGITAL ELECTRONICS LAB 43 EX. To design and construct the following synchronous counter and to verify its truth table. APPARATUS REQUIRED: SPECIFICATION/ RANGE IC7476 IC7408 IC7432 (0 – 12) V (0 – 5) V Sl. 1 2 3 4 5 COMPONENTS JK FLIP-FLOP AND GATE OR GATE Digital Trainer Kit Digital Power Supply Qty 2 1 1 1 1 PIN DIAGRAM OF IC7476 43 VIDYAA VIKAS COLLEGE OF ENGG & TECH . &BCD). DOWN.NO :8 Date: AIM: DESIGN OF SYNCHRONOUS COUNTERS (UP.

the binary count indicates that next higher order bit be complemented .In Synchronous binary counter.the counter is called Synchronous counter QA changes on each clock pulse as we progress from its original state to its final stack and then back to its original state .Synchronous binary counters have a regular pattern and can be easily constructed with complementing flip-flops and gates .DIGITAL ELECTRONICS LAB 44 3 BIT SYNCHRONOUS COUNTER THEORY When a Counter is Clocked such that each Flip flop in the Counter is Triggered at the same time . the flip-flop in the lowest –order position is complemented with every pulse A flip-flop in any other position is complemented with a pulse provided all the bits in the lower order positions are equal to 1 .The counter could also be triggered on the positive edge of the pulse CIRCUIT DIAGRAM: Q1 Q2 Q3 HIGH 1 2 J1 4 > 1 K1 16 FF1 K2 3 2 15 J2 9 7 11 FF2 J1 4 > 1 K1 16 FF3 2 15 3 PRESET +5V >6 12 8 3 CP CLEAR +5V 44 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

Because of return to 0 after count 9 .BCD counter does not have a regular pattern as in a straight binary count .The excitation for T flip-flops is obtained from present and next states Synchronous BCD Counters can be cascaded to form a counter for Decimal numbers of any length 45 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB TRUTH TABLE 45 CLK 0 1 2 3 4 5 6 7 8 Q3 0 0 0 0 1 1 1 1 0 Q2 0 0 1 1 0 0 1 1 0 Q1 0 1 0 1 0 1 0 1 0 SYNCHRONOUS DOWN COUNTER BCD SYNCHRONOUS COUNTER THEORY A BCD Synchronous counter counts in binary coded decimal from 0000 to 1001 and back to 0000.

DIGITAL ELECTRONICS LAB 46 CIRCUIT DIAGRAM Q4 Q1 Q2 Q3 PRESET 12 HIGH 4 5 1 J1 4 > 1 K1 16 FF1 2 3 15 2 >6 K2 3 FF2 J2 9 7 11 4 >1 2 J1 15 FF1 6 13 9 10 11 1 2 8 J2 7 11 Q FF2 +5V 3 9 >6 K2 12 8 K1 16 12 3 8 10 Q' CP CLEAR +5V TRUTH TABLE CLK 0 1 2 3 4 5 6 7 8 9 10 Q4 0 0 0 0 0 0 0 0 1 1 0 Q3 0 0 0 0 1 1 1 1 0 0 0 Q2 0 0 1 1 0 0 1 1 0 0 0 Q1 0 1 0 1 0 1 0 1 0 1 0 46 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

The output is indicated by the LED display. What is Ripple counter? 2. 2. What is other name for Ripple Counter? 6. 3. Apply the clock pulse.DIGITAL ELECTRONICS LAB PROCEDURE: 1. The counter is set initially in the reset position. RESULT: . What is the difference between Synchronous Counter and Asynchronous Counter? 5. The components are connected as shown in the circuit diagram. QUESTIONS: 1. The glowing of LED’s confirming to required data in the truth table is verified and the conclusion is drawn. 47 4. What are the Applications of Counters? 47 VIDYAA VIKAS COLLEGE OF ENGG & TECH . What is the difference between Binary Ripple Counter and BCD Ripple Counter? 4. Continue giving the clock pulse and check for the output as given in the truth table. It starts counting. 5. What are preset and clear lines? 3.

&BCD). Date: AIM: To design and construct the following asynchronous counter and to verify its truth table. APPARATUS REQUIRED: SPECIFICATION/ RANGE IC7476 IC7408 IC7432 (0 – 12) V (0 – 5) V Sl. DOWN. NO:9 DESIGN OF ASYNCHRONOUS COUNTERS (UP.No. 1 2 3 4 5 COMPONENTS JK FLIP-FLOP AND GATE OR GATE Digital Trainer Kit Digital Power Supply Qty 2 1 1 1 1 PIN DIAGRAM OF IC7476 48 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB 48 EX.

Negative Edge Triggering is used.The flip-flop changes one at a time propagates through the counter in a ripple fashion .DIGITAL ELECTRONICS LAB 49 3 BIT RIPPLE UPCOUNTER THEORY Three JK flip-flops are used with their inputs connected to Vcc. The small circle in the CP input indicates that the flip-flop complements during a Negative going transition or when the output to which is connected goes from 1 to 0 .Ripple counter are called as Asynchronous Counter CIRCUIT DIAGRAM TRUTH TABLE CLK 0 1 2 3 4 5 6 7 8 49 Q3 0 0 0 0 1 1 1 1 0 Q2 0 0 1 1 0 0 1 1 0 Q1 0 1 0 1 0 1 0 1 0 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

DIGITAL ELECTRONICS LAB 50 ASYNCHRONUS DOWN COUNTER: TRUTH TABLE CLK 8 7 6 5 4 3 2 1 0 Q3 0 1 1 1 1 0 0 0 0 Q2 0 1 1 0 0 1 1 0 0 Q1 0 1 0 1 0 1 0 1 0 PROCEDURE: 1. The glowing of LED’s confirming to required data in the truth table is verified and the conclusion is drawn. 4.The counter is set initially in the reset position.Continue giving the clock pulse and check for the output as given in the truth table. 3.The components are connected as shown in the circuit diagram.The output is indicated by the LED display.Apply the clock pulse. It starts counting. 5. 50 VIDYAA VIKAS COLLEGE OF ENGG & TECH . 2.

DIGITAL ELECTRONICS LAB RESULT: 51 QUESTIONS: 1.What are the Applications of Counters? 7.What are preset and clear lines? 3.What is the difference between Synchronous Counter and Asynchronous Counter? 5.How many states does a modulus-14 counter has? 51 VIDYAA VIKAS COLLEGE OF ENGG & TECH .What is other name for Ripple Counter? 6.What is Ripple counter? 2.What is the difference between Binary Ripple Counter and BCD Ripple Counter? 4.

in general is used for temporary storing and shifting data in Digital systems. The basic difference between a register and counter is that a register has no specified sequence of states. No: 10 Date: AIM: To construct the following Shift Registers i. A register. one bit at a time on a single line . 52 VIDYAA VIKAS COLLEGE OF ENGG & TECH .No. This type of Shift Register enters data serially that is. 1 2 3 COMPONENTS D FLIP-FLOP Digital Trainer Kit Digital Power Supply Qty 2 1 1 SERIAL-IN SERIAL OUT THEORY Shift Register is very important in applications involving the storage and transfer of data in Digital Systems.It produces the stored information on its output also in serial form.DIGITAL ELECTRONICS LAB Ex.)Serial in Serial out Shift left Register Ii) Serial in Serial out Shift Right Register Iii) Serial in Parallel out IV) Parallel in Serial out V) Parallel in Parallel out Shift register 52 SHIFT REGISTERS (All Types) APPARATUS REQUIRED: SPECIFICATION/ RANGE IC7474 (0 – 12) V (0 – 5) V Sl.

SERIAL IN SERIAL OUT SHIFT LEFT REGISTER TRUTH TABLE CLK 1 2 3 4 D3 0 0 0 1 D2 0 0 1 1 D1 0 1 1 1 D0 1 1 1 1 CIRCUIT DIAGRAM .SERIAL IN SERIAL OUT SHIFT RIGHT REGISTER 53 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB 53 CIRCUIT DIAGRAM .

rather than on a bit-by bit basis as with the serial output. each bit appears on its respective output line and all the bits are appeared simultaneously. one bit at a time on a single line.DIGITAL ELECTRONICS LAB 54 TRUTH TABLE CLK 1 2 3 4 D0 1 1 1 1 D1 0 1 1 1 D2 0 0 1 1 D3 0 0 0 1 SERIAL-IN PARALLEL OUT THEORY This type of Shift Register enters data serially that is. CIRCUIT DIAGRAM TRUTH TABLE CLK 1 2 3 4 54 INPUT 1 1 1 1 D0 1 1 1 1 D1 0 1 1 1 D2 0 0 1 1 D3 0 0 0 1 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Once the data are stored.

DIGITAL ELECTRONICS LAB PARALPARALLEL IN –SERIAL OUT THEORY 55 For a register with parallel data inputs.G6 G1.G2. the bits are entered simultaneously into their respective stages on Parallel lines rather than on a bit-by-bit basis on one line as with Serial data inputs .G3 OPERATION SHIFT DATA ENTRY 55 VIDYAA VIKAS COLLEGE OF ENGG & TECH .G5.The Serial output is executed once the data are completely stored in the Register CIRCUIT DIAGRAM SHIFT/ A LOAD 1 B 2 1 C D 1 2 1 2 4 5 4 5 10 9 10 9 8 3 1 3 2 6 4 5 6 8 10 9 3 2 QA > 3 FF2 5 QA 12 QB > 9 QB 6 2 QC FF2 11 FF1 >3 FF2 5 QC 8 12 QD >11 FF1 9 QD SERIAL DATA OUT CP SHIFT/LOAD 1 0 ENABLED GATES G4.

DIGITAL ELECTRONICS LAB 56 TRUTH TABLE CP 1 2 3 4 SHIFT/ LOAD 0 1 1 1 A 1 1 1 1 B 0 1 1 1 C 1 0 1 1 D 0 1 0 1 SERIAL OUT 0 1 0 1 PIN DIAGRAM VCC 2Q' 2D 2CLK 2S' 2Q 2Q' 14 13 I C 12 7 3 1CLK 11 4 4 1S' 10 7 4 5 1Q 9 8 1 1R' 2 1D 6 1Q' 7 GND PARALLEL IN PARALLEL OUT REGISTERS THEORY The Parallel in Parallel out register employs both the methods : Immediately following the simultaneous entry of all data bits .the bits appear on the parallel outputs TRUTH TABLE CLK 1 2 3 4 ABCD 000 1 0011 0111 1111 QA 0 0 0 1 QB 0 0 1 1 QC 0 1 1 1 QD 1 1 1 1 56 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

Define a register. The clock pulse is given and it is checked whether the bits shifts. RESULT: QUESTIONS: 1. 2. Define a shift register. 2.DIGITAL ELECTRONICS LAB CIRCUIT DIAGRAM 57 PROCEDURE: 1. 3. What changes should be made in the circuit to roll the data’s? 4 What is difference between Counter and Shift Register? 57 VIDYAA VIKAS COLLEGE OF ENGG & TECH . The components are connected as shown in the circuit diagram.

APPARATUS REQUIRED: S.NO 1 2 COMPONENTS IC 7474 DIGITAL TRAINER KIT SPECIFICATION/RANGE - QUANTITY 2 (0-12) V 1 CIRCUIT DIAGRAM: TRUTH TABLE: CLK QA QB 0 0 1 2 1 0 3 0 1 4 1 1 5 0 0 6 1 0 7 0 1 QC 0 0 0 1 0 0 0 QD 0 0 0 0 1 1 0 58 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB EX NO: 11 Date : 58 FOUR-BIT RING COUNTER AIM: To study and construct a Four bit ring counter using Flip-Flops.

Check for the output as given in the characteristics table RESULT: 59 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Apply the bits as per the truth table. Connect the components as per the given circuit. 3. 2.DIGITAL ELECTRONICS LAB 59 PIN DIAGRAM VCC R2' D2 CLK2 S2' Q2 Q2' 14 13 12 11 10 I 1 2 C 3 7 4 4 5 7 6 9 4 7 8 R1' D1 CLK1 S1' Q1 Q1' GND PROCEDURE: 1.

Each of the four input lines I0 to I3 is applied to one input of an AND gate Selection lines S1 and S0 are decoded to select a particular AND Gate • Consider the case S1 S0=10 . Demultipexer. APPARATUS REQUIRED: Sl.the AND Gate associated with input I2 has two of its inputs equal to 1 and third input connected to I2 he other three AND Gates have at least one input equal to 0. thus providing a path from the selected input to to the output 60 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB Ex.12 Date: AIM: 60 MULTIPLEXERS AND DEMULTIPLEXER AND EXTENSIONS To design and construct a combinational circuit for Multiplexer. Encoder and Decoder using Logic gates. which makes their outputs equal to 0 The OR Gate output is now equal to the value of I2.No.No. 1 2 3 4 5 6 COMPONENTS OR GATE 3 INPUT AND GATE 2 INPUT AND GATE NOT GATE Digital Trainer Kit Digital Power Supply SPECIFICATION/ RANGE IC7432 IC7411 IC7408 IC7404 (0 – 12) V (0 – 5) V Qty 1 2 1 1 1 1 MULTIPLEXER THEORY • Multiplexing means transmitting a large number of information units over a smaller number of channels or lines • A Digital Multiplexer is a combinational circuit that selects binary information from one of the many input lines and directs it to a single output line • • The selection of a particular input line is controlled by a set of selection lines Normally there are 2 n input lines and n selection lines whose bit combinations determine which input is selected • A 4-to-1-line Multiplexer is shown in the fig.

Don’t care) I0=X I1=X I2=X I3=X 0 0 1 1 0 1 0 1 I0=X I1=X I2=X I3=X 61 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB • 61 A Multiplexer is also called Data Selector. since it selects one of many inputs and steers the binary information to the output line CIRCUIT DIAGRAM TRUTH TABLE: Data Input Select Line S1 S0 Output ( X.

62 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB PINDIAGRAM 62 DEMULTIPLEXER: THEORY • A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2 n possible output line • • A decoder with an Enable input can function as a Demuxtiplexer The selection of a specific output line is controlled by a bit value of n selection lines.

DIGITAL ELECTRONICS LAB • 63 The Decoder can function as a Demuxtiplexer if I line is taken as a data input line and lines S1 and S0 are taken as a selection lines. but the input information is directed to only one of the output lines. as specified by the binary values of the two-selection linesS1 and S0. • The single input variable I have a path to all 4 outputs. CIRCUIT DIAGRAM: 63 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

3. Connect the components as per the given circuit. RESULT: 64 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Verification of glowing LED confirms the required data in the truth table.DIGITAL ELECTRONICS LAB TRUTH TABLE Data Input (I) Select Line S1 S0 Output 64 ( X. Apply the bits as per the truth table. 2.Don’t care) X X X X 0 0 1 1 0 1 0 1 D0=X D1=X D2=X D3=X PROCEDURE: 1.

No. C4. C0. GATE IC7400 Digital Trainer Kit (0 – 12) V Digital Power Supply (0 – 5) V Sl. The binary sum appears on the sum outputs (S0 – S3) and outgoing carry (C4) output. NAND IC7486. The circuit adds the two 4 bit binary words (A and B) plus the incoming carry. They generate the binary sum outputs. NO: 13 DATE: AIM: DESIGN OF 4 BIT ADDERS / SUBTRACTORS To design and verify the operations of 4-bit binary adder/Subtractor and BCD adder using IC 7483. IC7411. S0 – S3 and a carry output.DIGITAL ELECTRONICS LAB 65 EX. COMPONENTS 1 2 3 4 Qty 1 1 1 1 THEORY: The 7483A high speed 4 bit binary full adders with internal carry look ahead accept two 4 bit binary words A0 – A3 & B0 – B3 and a carry input. APPARATUS REQUIRED: SPECIFICATION/ RANGE 4 BIT BINARY ADDER IC7483A EXOR. 3 Input AND. C0 + (A0 + B0) + 2(A1 + B1) + 4(A2 + B2) + 8(A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4 65 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

DIGITAL ELECTRONICS LAB 66 PIN DIAGRAM LOGICAL SYMBOL CIRCUIT DIAGRAM: 4 BIT ADDER: 66 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

DIGITAL ELECTRONICS LAB 67 TRUTH TABLE: 4 BIT ADDER / SUBTRACTOR: TRUTH TABLE: A 3 0 1 1 1 A Input A A 2 1 0 0 0 0 0 0 0 0 A 0 1 1 1 1 B 3 0 0 0 1 B Input B B 2 1 1 1 1 1 1 1 0 1 Mode Input B 0 1 1 1 0 M 0 0 1 1 (Addition) (Subtraction) S 3 1 0 0 1 Sum S2 0 0 0 1 S1 0 0 1 1 S0 0 0 0 1 Carry Cout 0 1 0 1 67 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

3.DIGITAL ELECTRONICS LAB BCD ADDER: 68 PROCEDURE: 1. Check for the output as given in the characteristics table by the glowing of LED. Connect the components as per the given circuit. 2. RESULT: 68 VIDYAA VIKAS COLLEGE OF ENGG & TECH . Apply the bits as per the truth table.

7). 3 product terms and 2 outputs with the function of F1=∑m(3.No.7). F2=∑m(4. 1 2 3 4 5 COMPONENTS AND Gate OR Gate NOT Gate Digital IC Trainer Digital Power Supply SPECIFICATION/ RANGE IC7408 IC7432 IC7404 IC 7486 IC 7400 Qty 10 3 4 1 1 PLA-Progammable Logic Array Aim: To implement the circuit with a PLA having 3 inputs.5.5. PLA And ROM memories MEMORIES 69 APPARATUS REQUIRED: Sl. TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F1 0 0 0 1 0 1 0 1 F2 0 0 0 0 1 1 0 1 69 VIDYAA VIKAS COLLEGE OF ENGG & TECH .DIGITAL ELECTRONICS LAB Ex:NO:14 DATE: AIM: To implement the circuit with a PAL .

DIGITAL ELECTRONICS LAB PLA Program Table: Protuct Term 1 2 3 70 A 1 1 Inputs B 1 0 Outputs C 1 1 F1 1 1 T F2 1 1 T CIRCUIT DIAGRAM: 70 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

DIGITAL ELECTRONICS LAB PAL-Progammable Array Logic AIM: To implement the circuit using PAL CIRCUIT DIAGRAM 71 71 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

DIGITAL ELECTRONICS LAB TRUTH TABLE: A 0 1 2 3 4 5 0 0 0 0 0 0 B 0 0 0 0 1 1 C 0 0 1 1 0 0 D 0 1 0 1 0 1 W 1 0 1 0 0 0 X 1 0 1 0 0 0 Y 0 0 1 1 0 0 Z 0 1 0 1 1 72 0 6 7 8 9 10 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 1 0 11 12 13 14 15 72 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

RESULT 73 VIDYAA VIKAS COLLEGE OF ENGG & TECH . 3. Check for the output as given in the characteristics table by the glowing of LED. F1(A1.DIGITAL ELECTRONICS LAB 73 ROM-Memories: AIM: To implement the following Boolean function using ROM. Apply the bits as per the truth table.3) ROM MEMORIES PROCEDURE: 1.1.A0)= ∑m(0. 2. Connect the components as per the given circuit.A0)=∑m(1.2) F2(A1.

DIGITAL ELECTRONICS LAB 74 74 VIDYAA VIKAS COLLEGE OF ENGG & TECH .

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