Fabrication of CMOS ICs

ECE6130 Jeff Davis

*Images taken from textbook: J. Uymura, “Introduction to VLSI Circuits and Systems,” John Wiley and Sons, 2002.

Outline
• • • • Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow

Integrated Circuits created on Silicon Wafers (100-300mm)

The wafer is subjected to 1000s of individual processing steps to make each IC!!

Fabrication Yield

NG Y= ¥ 100% NT
NG = Number of good working die NT = Total number of die sites

Yield enhancement is complex and time consuming!!

Total # of Die (NT) Estimation
2˙ Í (d - de ) ˙ Íp NT = Í 4Adie ˙ Î ˚
d = wafer diameter de = wasted edge distance

note that this indicates floor function

Rw ) † † Rw= radius of wafer a & b = dimensions of the wafer .( jab .de calculation? More exact calculation. Í 2Rw ˙ Í ˙-1 Î b ˚ NT = Â i =0 2 Rw Í 2b ˙ Í Min(Ri . Ri +1 )˙ Îa ˚ 2 Rj = .

R 2 ˙ w Í w Í A ˙ ˙ Î die ˚ ˙ c =Í Í ˙ 2 Adie Í ˙ Í ˙ Î ˚ † † .1˜ Á A ˜ Adie Ë die ¯ Í ˙ Í ˙ Í 2R .c .Square Die Approximation? Ê ˆ 2 2Rw 2Rw NT = + 4c Á .Í 2Rw ˙ .

6 0.8 Yield Yield and Die Size AMD (180nm) Athlon XP Yield(D=0.06cm^(-2)) Yield(D=0.2 1 0.Y =e .2 0 0 1 2 Chip Area 3 4 .DA 1.4 0.25cm^(-2)) Yield(D=1cm^(-2)) Intel (180nm) P4 0.

ICCAD 1993.”Design for Manufacturability (DFM) in Submicron Domain”. et al.. .Yield over product lifetime W. Maly.

Intel: AMD Athlon XP (180nm) 129mm2 (200mm wafers) Intel’s P4 (180nm) 217mm2 (200mm wafers) AMD Athlon XP (130nm) 80mm2 (200mm wafers) Intel’s P4 (130nm) 116mm2 (300mm wafers) .Lesson for VLSI Designer? Keep die size SMALL!!! Example AMD vs.

Outline • • • • Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow .

46x ox † .Thermal Oxide Growth xsi ª 0.

Dry vs. Wet Oxidation Dry Oxidation : Slow but high quality :Heat accelerates reaction Si + O2 Æ SiO2 Wet Oxidation : Fast but high quality: Heat accelerates reaction † Si + H2O Æ SiO2 + 2H2 † .

clean. 2 min . 60 min ramp down to 800 C in Oxygen pull at 1/2" per sec unload into plastic carriers . rinse. 20 min turn on steam. 4 min RINSE 2. 4 min DRY OXIDIZE 1 hr at 1000 C in Wet Oxygen place wafers in quartz oxidation boat insert into furnace ante-chamber push at 1/2" per sec at 800 C in Oxygen ramp to 1000 C (10 C/min).Wet/Dry Combo Example START (100) p-type 10 ohm cm wafers CLEAN in H2(S0)4-H202 piranha etch. dry RINSE 1.

CVD Oxide Process Deposited SiO2 on a surface where no Si is present Silane SiH4 (gas) + 2O2 (gas) Æ SiO2 (solid ) + 2H2O(gas) LTO = Low Temperature Oxides! .

Silicon Nitride (Si3N4) • Often called nitride only • Strong barrier to most items • Use as an overglass layer to protect chip 3SiH4 (gas) + 4NH3 (gas) Æ Si 3N4 (solid ) + 12H2 (gas) Silane Ammonia Silicon Nitride .

Polysilicon Silicon •Depositing silicon on Silicon Dioxide produces small crystallites areas •Called poly for short •Used for gate eletrotrode in FETs •Even heavily doped this has high sheet resistance • Refractory metals (such Ti) coating on poly to decrease sheet resistance .. this is called a silicide SiH4 Æ Si + 2H2 Silane @ 500-600 oC ..

67e-6 W-cm •Electromigration •Current flow displace metal ions in metals dent High current density High current density high-current density moves the dent! .Metals •Aluminum vs.86e-6 W-cm • copper bulk resistivity = 1. Copper • aluminum bulk resistivity = 2.

Electromigration Design Rules limit current density .

Doping Silicon Layers selective doping is very important!! .

Ion Implantation .

Boron Triflouride (BF3) Ion Implantation magnet Ion Source wafer target .

6 ´ 10-19 joules . annealing) 100-200 KeV Physics 101: One electron-volt is equal to the amount of energy gained by an electron dropping through a potential difference of one volt. which is 1.The Ion Stopping Process •Ion energies control depth •Can penetrate thin oxide layers •Damage can result.e.but is fixed with an moderate heated (i.

Gaussian Implant Profile Nion (x ) = N p e Straggle Ê x-R ˆ 2 1 p ˜ .Á Á DR ˜ 2Ë p ¯ † Projected Range .

Chemical Mechanical Polish (CMP) .

com/journals/ edition.pdf .Epitaxial Layer Growth (EPI) Trichlorosilane (TCS) @ 1000-1180 oC Source: www.pdfs/ft15_215.semiconductorfabtech.15/ft15.

Outline • • • • Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow .

Photo = light! Excimer Laser Sources • (250-130nm)Krypton Fluoride (KrF) 248nm • (90nm) Argon Fluoride ArF (193nm) • (65nm?) Fluorine F2 (157nm) .

Reticle or Mask Definition Remember: During Layout using CAD tools this is what you are designing!!! .

Photoresist Application .

Exposure Step .

Characteristics of positive photoresist Negative photoresist works in opposite way!! .

Etching an Oxide Layer .

atechsystem.pdf .kr/custom/rie.co.Reactive Ion Etching RIE Etching work well with both ion bombardment and chemical reaction etching!!! **Source: www.

co.Reactive Ion Etch (RIE) Anisotropic Etch No undercut! **Source: www.kr/custom/rie.atechsystem.pdf .

Ion Implantation of Doped Si Patterns note: lateral doping .

Step-and-Repeat Process registration targets for alignment between masking steps! .

TSMC Fab 6 (190.Clean Room Definitions •Use HEPA filters that are 99. •Class X clean rooms means that there are less than X particles per cubic foot with diameter greater than 0.g.5microns or larger.1 SMIF minienviroments .97% effective of removing particles that are 0.5 micron •Typical clean room facilities have various class levels •e.000sqft 32.000 wafer-per-month) •Class 100 ballroom has Class 0.

Outline • • • • Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow .

nWell and Active Area Masking Steps nWell Mask nFET and pFET will eventually go here! Active Area Mask Needed to define oxide electrical isolation between devices! .

Field Oxide (FOX) growth Field Oxide needed to define oxide electrical isolation between devices! .

Self-Aligned Gate Process Gate/Drain/Source Regions are automatically aligned Poly Mask .

Self-Aligned Gate Process p+ gate electrode pSelect Mask n+ gate electrode nSelect Mask .

Source/Drain Contacts Active Contact Mask Poly Contact Mask .

Metal Masking Steps Metal 1 Mask Via Mask Metal 2 Mask .

Bonding Pad Structure .

Lightly Doped Drain (LDD) nFET Oxide etch to create sidewall spacers (no additional mask needed) .

Lightly Doped Drain (LDD) nFET Oxide etch to create sidewall spacers (no additional mask needed) .

Pt.g.Ta. etc) coated over silicon or polysilicon •Reduce sheet resistance of gate from 25 W to 10s mW!! Silicide reduces contact resistance of Tungsten Contact . Ti.Silicides •Defined as a refractory metal(e.

TiN) to block diffusion to SiO2! .Copper Interconnect: Damascene Copper needs a barrier layer (e.g.

..Dual-Damascene Process Copper vias . 1) lower resistance than Tungsten 2) Electromigration better! .