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Text: Chapter 5, Digital Integrated Circuits 2nd Ed, Rabaey

1) Consider the CMOS inverter circuit in Figure P1 with the following parameters. Assume long channel transistors and no velocity saturation.

Vin

Vout

Figure P1 Find VOL, VOH, VIL, and VIH on the VTC. Also find the noise margins of this inverter.

1

2 .

2) Consider a CMOS inverter circuit with power supply voltage VDD = 3. 3 . the drain current reaches its saturation level Isat = 2mA.3V. When VGS=3. The I-V characteristic of the NMOS transistor is specified below.3V. for VDS > 2. from 0V to 3.3V.5V. Assume that the input signal applied to the gate is a step pulse that switches instantaneously.

Determine the fall time tfall. others are given below. defined as the time elapsed between 90% to 10% transition of the output voltage.3) Consider a CMOS inverter with supply voltage of VDD = 5V. 4 . Assume kn’ = 20µA/V2. Assume long channel transistors and no velocity saturation.

4) An inverter is simulated in SPICE in the following conditions and characteristics 5 .

For tpHL: First calculate Ron for Vout at 2.0463V Figure P5 a) Calculate tplh. and assume an output load of 3 pF Given: VT0 = 0.27315V At Vout=2.5V. tphl.06 V-1. and tp Solution tpLH=0. 6 .63.5V. λ = 0.5) For the resistive-load inverter in Figure P5. VDSAT=0. VOH = 2. k’n=115µA/V2.69RLCL= 155 nsec. VOL = 0.439mA giving Ron= 5695Ω (VOH – VOL)/2. IDVsat=0.43V.5V and 1.

Solution Static Power: VIN=VOL gives Vout=VOH=2. such that the 50% point is Vdd/2 Αt Vout=1.69RaverageCL=9.41m giving Ron= 3049Ω.3mV.8µA PVDD=82µW Dynamic Power: NOTE: fmax= 1 / tp =1 / 82.372kΩ.25V is Raverage=4.Αt Vout=1. the average resistance between Vout=2. Calculating the current through M1 gives IVDD=32.27315V.4106mA giving Ron= 3100. tp=av{tpLH. IDvsat=0.5V.104nsec. the average resistance between Vout=2.398kΩ. tpHL}=82.5V-46.27315V is Raverage=4.69RaverageCL=9.0nsec b) Are the rising and falling delays equal? Why or why not? Solution tpLH >> tpHL because RL=75kΩ is much larger than the effective linearized on-resistance of M1.5V and Vout=1.25V.05nsec ASIDE: if first-order approximation is considered.85Ω.5V*12. Thus. tpHL=0.2MHz=0. VIN=VOH gives Vout=VOL=46. Circuit A uses only NMOS transistors. tp=av{tpLH. Thus.75/0. IDvsat=0.05nsec.0nsec Pdyn=CL∆V*Vdd*fmax=3pF*(2.3mV)*2. c) Compute the static and dynamic power dissipation assuming the gate is clocked as fast as possible. thus IVDD=0A so PVDD=0W. tpHL=0. tpHL}=82. Circuit B is a static CMOS inverter (NOTE: short-channel transistors and velocity saturated) W/L = 0. which is in the linear region. 6) Figure P6 shows two implementations of MOS inverters.5V and Vout=1.225mW.25 Figure P6 7 .

VOL. VM for each case. 8 .a) Calculate VOH.

e.6V.28V.861V We can increase the noise margins by moving VM closer to the middle of the output voltage swing.0V = 0.e. robustness and regeneration of each inverter. Cgd0. Also the regeneration in the second inverter is greater since it provides rail to rail output and the gain of the inverter is much greater. that the CMOS inverter is more robust.25. and tox = 58A.35V NMH = VOH . b) Find VIH. NML and NMH for each inverter and comment on the results.22V for circuit B. So the assumption that both transistors were velocity saturated holds.765 .VIH = 1. 2|φf|=0.4V. c) Comment on the differences in the VTCs.22V = 1. kp’= -30µA/V2. L=Leff =0. 7) For this problem assume: VDD = 2.095V. VIH = 1.1.4.240V Circuit B VIL = 0. γ = 0. How can you increase the noise margins and reduce the undefined region? Solution Circuit A Based on the VOL and VOH from part (a) VIL = 0. Given that VIL = 0. CL=Cinvgate.25µm (i.5V .415V. Solution It is clear from the two VTCs. VIL. WN/L = 0.1. NML = VIL . NML = VIL .503V and VIH = 1. λ= 0V-1.VIH = 2.503V.VOL = 0.503.25. we get VM = 1.861V. since the low and high noise margins are higher than the first inverter. Use the HSPICE model parameters for parasitic capacitance given below (i. VIH = 1. Cjsw). and VIL = 0.263 = 0.VOL = 0.375/0.22V NMH = VOH .0.Setting ID3 + ID4 = 0.35 = 0.25/0.5V. and assume that VSB=0V. WP/L = 1.35V for circuit A. Cj. Vtn0 = | Vtp0 | = 0.861V and VIH = 1.861V. xd= 0µm). (NOTE: short-channel transistors and velocity saturated) 9 . kn’ = 115µA/V2.

i. That means that the NMOS is velocity saturated and the PMOS is saturated. tPLH assuming CLeff = 6. we set the sum of the currents at Vout equal to 0 using the correct equation for each device: b) Calculate tPHL. where ∆Q 10 .e.25V). Do this part by computing the average current used to charge/discharge CLeff. trise=tfall=0.5fF. To find VM. (Assume an ideal step input.) Solution We can estimate the propagation delay using the approximation ∆t =∆Q/I.Figure P7 a) What is the VM for this inverter? Solution Assume that VM is around midrail (1.

During the low-to-high transition CLeff is charged through the PMOS transistor so I = IavgP.4. 8) Consider the circuit in Figure P8 (which is a low-swing driver.= CLeffVDD and I is the average current used to charge/discharge CLeff. Figure P8 a) What is the voltage swing on the output node (Vout)? Assume γ=0.208 0. not an inverter).65 included channel length modulation. but it is ok if your solution did not (see problem assumptions). 11 . NOTE: short-channel transistors and velocity saturated. During the high-to-low transition CLeff is discharged through the NMOS transistor so I = IavgN.216 37. Given VTn0 = 0.223 0.43 and VTp0 = -0. In summary: IavgP = IavgN = 0.

24 V. For the velocity saturated NMOS: Solving for the current at V=0. Solution When the input is high and the capacitor charges.24 V and averaging yields an average current of 404 uA.Solution The range will be from 0. VOL is the output voltage with the input at 0V and VOH is the output voltage with the input at 2. We can use the average current method to approximate tplh.4 V and V=1. so the midpoint is 1.4 V to 2. since the PMOS is a weak pull down device and the NMOS is a weak pull up device.07 V.5V. the PMOS device is in cutoff and the NMOS is velocity saturated for the duration of the charging. Then: 12 . Assume the input rise time to be 0. The total voltage range is 0.e.4 V to 2. the time to transition from VOL to (VOH + VOL) /2). b) Compute tpLH (i.07 V.

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