Lab 9 Dff module library IEEE; use IEEE.STD_LOGIC_1164.

ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dflipflop is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC); end dflipflop; architecture Behavioral of dflipflop is signal s:std_logic; begin process(clk) begin if(clk'event and clk='1')then s<=d; end if; end process;

q<= s; end Behavioral;

test bench dff LIBRARY ieee; USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL;

ENTITY dflipfloptb IS END dflipfloptb;

ARCHITECTURE behavior OF dflipfloptb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dflipflop PORT( d : IN std_logic; clk : IN std_logic; q : OUT std_logic ); END COMPONENT; --Inputs signal d : std_logic := '0';

signal clk : std_logic := '0'; --Outputs signal q : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: dflipflop PORT MAP ( d => d, clk => clk, q => q ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for clk_period; d<='0';

wait for clk_period; d<='1'; wait for clk_period; d<='0'; wait for clk_period; d<='1'; wait; end process; END;

Ucf d ff : net "d" LOC = "N3"; #bank = 2, signal name = sw7 net "clk" LOC = "E2"; #bank = 3, signal name = sw6 net "q" LOC = "G1"; #bank = 3, signal name = LD7

Jk module: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity jkflipflop is Port ( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC); end jkflipflop; architecture Behavioral of jkflipflop is signal s:std_logic:='0'; begin process(clk,j,k)begin if(clk'event and clk='1')then if(j='1' and k='0')then s<='1'; elsif(j='0' and k='1')then s<='0';

elsif(j='1' and k='1')then s<=not s; end if; end if; end process; q<= s; end Behavioral;

jk test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY jktest IS END jktest; ARCHITECTURE behavior OF jktest IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT jkflipflop PORT( j : IN std_logic; k : IN std_logic; clk : IN std_logic; q : OUT std_logic );

END COMPONENT; --Inputs signal j : std_logic := '0'; signal k : std_logic := '0'; signal clk : std_logic := '0'; --Outputs signal q : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: jkflipflop PORT MAP ( j => j, k => k, clk => clk, q => q ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process;

-- Stimulus process stim_proc: process begin wait for clk_period; j<='0'; k<='0'; wait for clk_period; j<='0'; k<='1'; wait for clk_period; j<='1'; k<='0'; wait for clk_period; j<='1'; k<='1'; wait; end process; END;

Ucf jk: net "j" LOC = "N3"; #bank = 2, signal name = sw7 net "k" LOC = "E2"; #bank = 3, signal name = sw6 net "clk" LOC = "F3"; #bank = 3, signal name = sw5 net "q" LOC = "G1"; #bank = 3, signal name = LD7 NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;

Tflip flip module : library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity tflipflop is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC); end tflipflop; architecture Behavioral of tflipflop is signal s:std_logic:='0'; begin process(clk,t)begin if(clk'event and clk='1'and t='1')then s<=not s; end if; end process; q<= s; end Behavioral;

t ff test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tbtff IS END tbtff; ARCHITECTURE behavior OF tbtff IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT tflipflop PORT( t : IN std_logic; clk : IN std_logic; q : OUT std_logic ); END COMPONENT; --Inputs signal t : std_logic := '0'; signal clk : std_logic := '0'; --Outputs signal q : std_logic; -- Clock period definitions constant clk_period : time := 10 ns;

BEGIN -- Instantiate the Unit Under Test (UUT) uut: tflipflop PORT MAP ( t => t, clk => clk, q => q ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for clk_period; t<='0'; wait for clk_period; t<='1'; wait for clk_period; t<='1'; wait;

end process; END;

Tflip flop ucf:net "t" LOC = "N3"; #bank = 2, signal name = sw7 net "clk" LOC = "E2"; #bank = 3, signal name = sw6

net "q" LOC = "G1"; #bank = 3, signal name = LD7 NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;

Srlatch module:library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity srglatch is Port ( s : in STD_LOGIC; r : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC; qbar: out std_logic); end srglatch; architecture Behavioral of srglatch is signal x:std_logic; signal y:std_logic; signal x1:std_logic; signal y1:std_logic; begin x<=r and clk; y<=s and clk;

x1<=y1 nor y; y1<=x nor x1; q<=y1; qbar<=x1; end Behavioral; sr latch test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tbsrglatch IS END tbsrglatch; ARCHITECTURE behavior OF tbsrglatch IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT srglatch PORT( s : IN std_logic; r : IN std_logic; clk : IN std_logic; q : OUT std_logic; qbar : OUT std_logic ); END COMPONENT --Inputs

signal s : std_logic ; signal r : std_logic ; signal clk : std_logic; --Outputs signal q : std_logic; signal qbar : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: srglatch PORT MAP ( s => s, r => r, clk => clk, q => q, qbar => qbar ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/4; clk <= '1'; wait for clk_period/4; end process;

-- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period; s<='0'; r<='1'; wait for clk_period; s<='1'; r<='0'; wait for clk_period; s<='1'; r<='1'; -- insert stimulus here wait; end process; END; Ucf sr latch :net "s" LOC = "N3"; #bank = 2, signal name = sw7 net "r" LOC = "E2"; #bank = 3, signal name = sw6 net "clk" LOC = "F3"; #bank = 3, signal name = sw5 net "q" LOC = "G1"; #bank = 3, signal name = LD7 net "qbar" LOC = "P4"; #bank = 3, signal name = LD6 NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;