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Lab 5 SDK Lab
Targeting MicroBlaze on the Spartan-3E Starter Kit


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SDK Lab: MicroBlaze
Introduction
This lab guides you through the process of adding timers to an embedded system and writing a software
application that utilizes these timers. The Software Developers Kit (SDK) will be used to create and debug
the software application.
Objectives
After completing this lab, you will be able to:
Utilize the XPS timer with interrupt controller
Assign an interrupt handler to the timer
Develop an interrupt handler function
Use SDK Debugger to set break points and view the content of variables and memory
Procedure
You will extend the hardware design created in lab 5 to include an XPS interrupt controller and XPS Timer
(see Figure 5-1). You will develop an interrupt handler to count the interrupts generated from the timer.
The steps for completing the lab are listed below:

1. Add a timer and interrupt controller
2. Create an SDK software project
3. Write an Interrupt Handler
4. Add a Linker script
5. Verify operation in hardware


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Figure 5-1. Design Updated from Previous Lab
For each procedure within a primary step, there are general instructions (indicated by the
symbol). These general instructions only provide a broad outline for performing the procedure.
Below these general instructions, you will find accompanying step-by-step directions and
illustrated figures that provide more detail for performing the procedure. If you feel confident
about completing a procedure, you can skip the step-by-step directions and move on to the next
general instruction.







LMB
BRAM
CNTLR

LMB
BRAM
CNTLR

BRAM
PLB

MDM

UART

INTC

MicroBlaze

Timer

GPIO

GPIO

PSB
LEDs
LCD MYIP

GPIO
DIP

BRAM
XPS
BRAM
CNTLR
MPMC
CNTLR
DDR


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Add a Timer and Interrupt Controller Step 1
Create a lab5 folder and copy the contents of the lab4 folder into the lab5 folder,
or copy the content of the completed\lab4 folder into the lab5 folder. Launch
Xilinx Platform Studio (XPS) and open the project file.
O Create a lab5 folder in the C:\xup\embedded\labs directory and copy the contents from lab4 to
lab5, or copy the content of the completed\lab4 folder into the lab5 folder
O Open XPS by selecting Start Programs Xilinx ISE Design Suite 10.1i EDK
Xilinx Platform Studio
O Browse to the lab5 directory and open the project system.xmp
Add the XPS timer and XPS Interrupt Controller peripherals to the design from
the IP Catalog, and connect them to the system according to the following table.

xps_intc_0 instance
plb_clk sys_clk_s
Intr timer1
Irq Microblaze_0_INTERRUPT
delay instance
CaptureTrig0 net_gnd
Interrupt timer1
microblaze_0 instance
INTERRUPT Microblaze_0_INTERRUPT
O Add the XPS Timer/Counter peripheral from the DMA and Timer section of the IP Catalog
and change its instance name to delay
O Add the XPS Interrupt Controller peripheral from the Clock, Reset, and Interrupt section
of the IP Catalog
O Connect the timer and interrupt controller as a s (slave) device to the PLB bus (see Figure
5-2)


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Figure 5-2. Add and Connect the Interrupt Controller and Timer Peripherals
O Select size as 64K bytes from drop down box and click Generate Addresses.

O Your results should look similar to that indicated in the figure below.

Figure 5-3. Generate Addresses for Interrupt Controller and Timer peripherals
O In the Ports section, type in timer1 as the Interrupt port connection of the delay instance,
and hit enter.
O Make a new net connection (see Figure 5-4) for the INTERRUPT (external interrupt
request) port on the microblaze_0 instance by selecting New Connection from the drop-down
box. This will create a net called microblaze_0_INTERRUPT.

Figure 5-4. Make a new net connection to connect the MicroBlaze Interrupt port


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O Connect the interrupt controller and timer as follows (refer to Figure 5-6)
Connect interrupt output port Irq of the xps_intc_0 instance to the MicroBlaze interrupt
input port using the microblaze_0_INTERRUPT net.

Click in intr field of xps_intc_0 field to open the Interrupt Connection Dialog. Click
on timer1 on left side, and click on sign to add to the Connected Interrupts field
(right), and then click OK.

Figure 5-5. Connecting the Timer and Interrupt Controller

Change the net name of CaptureTrig0 port of delay instance to net_gnd.


Figure 5-6. Connections Snapshot between Timer and Interrupt Controller
O Double-click on delay to open its parameters box and check Only One Timer is Present.
Click OK to accept the changes and close the dialog box
O Select Hardware Generate Bitstream


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Create an SDK Software Project Step 2
Launch SDK and create a new software application project for the lab5 XPS
project. Import the lab5.c source file.
O Open SDK by selecting Software Launch Platform Studio SDK
O Select Import XPS Application Projects and click Next.

Figure 5-6. Managed Make C Project
O Put a check mark next to TestApp_Memory and click Finish.

This creates the directory SDK_Projects/TestApp_Memory, which is a copy of the
TestApp_Memory software application project that was originally created with Base System
Builder.
O Right-click on lab4.c and select Delete.
O Add lab5.c by selecting File Import. In the Import wizard. Double-click on File System
and browse to the c:\xup\embedded\sources directory. Check the lab5.c source file and click
Finish to add the file to the project. For Into Folder, browse to and select
TestApp_Memory. Click Finish


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Figure 5-7. Importing Source Code
O In the left hand Navigator tab, double click on the lab5.c file to open it in the editor. The file
is built as soon as it is opened, and note that both the Problems and Console tabs on the
bottom report several compilation errors. The project is automatically built each time files in
the project are edited and saved. Note also that the project outline on the right side is updated
to reflect the libraries and routines used in the source file
O In the Problems tab, double-click on the second red x for the parse error. This will bring you
around to the line 88.


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Figure 5-8. First Error
O Add the missing global variable declaration as unsigned int, initialize it to the value of 1, and
save the file. The first error message should disappear.
O Click the next error message to highlight the problem in the source code

Figure 5-9. Second Error
G Add the missing global variable declaration as int, inititalize it to the value of 0, and save the
file. The additional error messages should disappear.













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Write an Interrupt Handler Step 3
Create the interrupt handler for the XPS timer
O Go to where the interrupt handler function has already been stubbed out in the source file (a
fast way to do this is to double-click on the function in the outline view).
O Create new local variable for the timer_int_handler function:
unsigned int csr;

The first step in creating an XPS timer interrupt handler is to verify that the XPS
timer caused the interrupt. This can be determined by looking at the XPS Timer
Control Status Register. Open the API documentation to determine how the
Control Status Register works.
O In the XPS System Assembly View window, right-click the delay instance and select View
PDF Datasheet to open the data sheet
O Go to the Register Description section in the data sheet and study the TCSR0 Register.
Notice that bit 23 has the following description:
Timer0 Interrupt
Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is
capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is
generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1

Read:
0 - No interrupt has occurred
1 - Interrupt has occurred

Write:
0 No change in state of T0INT
1 Clear T0INT (clear to 0)

The level 0 driver for the XPS timer provides two functions that read and write to the Control
Status Register. View the timer API doc by right-clicking on the delay instance in the System
Assembly View and selecting Driver:tmrctr_v1_10_b View API Documentation. In the
API document, click on the File List link at the top of the document, then click on the link
labeled xtmrctr_l.h in the file list. This brings up the document on identifiers and the low-
level driver functions declared in this header file. Scroll down in the document and click on
the link for the XTmrCtr_mGetControlStatusReg( ) function to read more about this
function. Use this function to determine whether an interrupt has occurred. The following is
the pertinent information found in the XPS timer documentation:
XTmrCtr_mGetControlStatusReg ( BaseAddress, TmrCtrNumber )
Get the Control Status Register of a timer counter
O Parameters:
o BaseAddress is the base address of the device.


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o TmrCtrNumber is the specific timer counter within the device, a zero-based
number, 0 -> (XTC_DEVICE_TIMER_COUNT - 1)
O Returns:
o The value read from the register, a 32-bit value
O Add the XTmrCtr_mGetControlStatusReg function call to the code with the associated
parameters. The resulting 32-bit return value should be stored in the variable csr.
csr = XTmrCtr_mGetControlStatusReg(baseaddr, 0);

Note: Substitute baseaddr with the base address for the delay peripheral. Refer to
xparameters.h
O Complete the Interrupt handler (see Figure 5-10) according to the steps below
1. Test to see if bit 23 is set by ANDing csr with the XTC_CSR_INT_OCCURED_MASK
parameter.
2. Increment a counter if an interrupt was taken.
3. Display the count value by using the LEDs_8Bit peripheral and print the value using
xil_printf (same functionality as printf with the exception of floating-point handling)
Hint: You may use the XGpio_DiscreteWrite () function
4. Clear the interrupt by using the following function call:
XTmrCtr_mSetControlStatusReg(baseaddr, 0, csr);
Figure 5-10. Completed Interrupt Handler Code
O Save the file, this should compile the source successully.



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Add Linker Script Step 4
Remove TestApp_Memory_linker_script.ld file. Assign lab5_LinkScr.ld as the
linker script for building the project and compile the application.
O Click on the C/C++ Projects tab on the left side
O Right-click on TestApp_Memory and select Properties to open the Properties dialog box
(or select Project Properties from the menu)

Figure 5-11. Software Project
O In the left hand window of the Properties dialog, select the C/C++ Build item
O Select the Linker Script option and click the delete button ( ) to remove the
TestApp_Memory_linker_script.ld script file.
O Click the Add button ( ) and add the lab5_LinkScr.ld file from embedded\sources\
(Figure 5-12).


Figure 5-12. Adding Linker Script

O Click OK to exit the Properties dialogue which will also recompile the program.

O Look in the console to answer the following question.
Software
project


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1. What is the size of the compiled program?
.text segment:
.data segment:
.bss segment:
Total in decimal:
Total in hexadecimal:
Verify Operation in Hardware Step 5

Generate the bitstream and download to the Spartan-3E starter kit.
O Connect and power the board
O Select Device Configuration Program FPGA
O Select TestApp_Memory.elf the Initialization ELF.

Figure 5-13. Selecting executable for BRAM initialization
O Click Save and Program
This will configure the FPGA and you should observe a message on the hyperterminal
window indicating the count value. The LEDs should be flickering.

Figure 5-14. HyperTerminal Output

?


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Debugging Using SDK Step 7
Configure Target Connection Settings
O On the SDK Menu, select Run Run
This will present a screen summarizing the existing Launch Configurations
O Under Configurations, select Xilinx C/C++ ELF
O Click on New to add a new Launch configuration.


Figure 5-15. Setting Up Run Configuration
O Click on the Run button to establish a connection between the debugger and hardware target
You should see output displayed on hyperterminal since the program is running.
O In the XMD Console view, type stop at the XMD% prompt to stop the running process
(Figure 5-16)


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Figure 5-16. SDKs XMD Console


Launch Debugger and debug.
O On the SDK Menu, select Run Debug
This will present a screen summarizing the existing Launch Configurations
O Click on Debug. If a dialog box appears asking you to confirm whether to switch to the
Debug Perspective, click Yes
This opens the Debug perspective. The debugger is automatically connected to the processor
via XMD. The processor will be suspended automatically (breakpoint) at the first statement in
main()
O Click on the Resume button. The application will run

Figure 5-17. Resuming an Application

O Click on the Thread[0] (Running) line in the Debug window (left) and click the Suspend
button to suspend operation.


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Figure 5-18. Suspending a Running Application
O Right click in the Variables tab and select Add Global Variables All global variables will
be displayed. Select count variableand click OK
O Right click on count and make sure that Enable is selected

Monitor variables and memory content.
O Double-click to set a breakpoint on the line in lab5.c where count is written to LED


Figure 5-19. Setting Breakpoint
O Click on Resume button to continue executing the program up until the breakpoint.
As you do step over, you will notice that the count variable value is changing.
O Click on the memory tab. If you do not see it, go to Window Show View Memory
O Click the + sign to add a Memory Monitor


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Figure 5-20. Add Memory Monitor

O Enter the address for the count variable as follows, and click OK

Figure 5-21. Monitoring a Variable
O Click the Resume button to continue execution of the program.

Notice that the count variables increment every time you click resume.


Figure 5-22. Viewing Memory Content of the count variable

O Terminate the session by clicking on the Terminate button.
Click to add
memory
monitor
Watch count
value increment


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Figure 5-23. Terminating a Debug Session
O Close the SDK application and close the XPS project

Conclusion
This lab led you through adding an XPS timer and interrupt controller, and assigning an interrupt
handler function to the interrupting device via the software platform settings. You developed an
interrupt handler function and tested it in hardware. Additionally, you used the SDK debugger to
view the content of variables and memory.

Answers
1. What is the size of the compiled program?
.text segment: 6418
.data segment: 388
.bss segment: 702
Total in decimal: 7508
Total in hexadecimal: 1d54
Click to terminate
session
A


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Completed MHS File

#
#######################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.01 Build
EDK_K_SP1.3
# Thu Jun 05 12:21:01 2008
# Target Board: Xilinx Spartan-3E Starter Board Rev D
# Family: spartan3e
# Device: XC3S500e
# Package: FG320
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 50.00 MHz
# On Chip Memory : 8 KB
# Total Off Chip Memory : 64 MB
# - DDR_SDRAM = 64 MB
#
#######################################################################
PARAMETER VERSION = 2.1.0


PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I
PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out,
DIR = O, VEC = [0:7]
PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O =
fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IO
PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR
= O
PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR =
O, VEC = [12:0]
PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =
fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR
= O
PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR =
O
PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR
= O
PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR =
O
PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O,
VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO,
VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC
= [15:0]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
PORT push_GPIO_in_pin = push_GPIO_in, DIR = I, VEC = [0:3]
PORT dip_GPIO_in_pin = dip_GPIO_in, DIR = I, VEC = [0:3]
PORT lcd_ip_0_lcd_pin = lcd_ip_0_lcd, DIR = O, VEC = [0:6]
A


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BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER HW_VER = 7.10.b
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_AREA_OPTIMIZED = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
PORT MB_RESET = mb_reset
PORT INTERRUPT = microblaze_0_INTERRUPT
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.02.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END




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BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_DCE_RX
PORT TX = fpga_0_RS232_DCE_TX
END

BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END

BEGIN mpmc
PARAMETER INSTANCE = DDR_SDRAM
PARAMETER HW_VER = 4.01.a
PARAMETER C_NUM_PORTS = 1
PARAMETER C_MEM_PARTNO = MT46V32M16-6
PARAMETER C_SPECIAL_BOARD = S3E_STKIT
PARAMETER C_MEM_BANKADDR_WIDTH = 2
PARAMETER C_MEM_DATA_WIDTH = 16
PARAMETER C_MEM_DQS_WIDTH = 2
PARAMETER C_MEM_DM_WIDTH = 2
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_PIM0_BASETYPE = 2
PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
PARAMETER C_SPLB0_NATIVE_DWIDTH = 32
PARAMETER C_MPMC_BASEADDR = 0x8c000000
PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
BUS_INTERFACE SPLB0 = mb_plb
PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n


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PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
PORT DDR_DQS_Div_O =
fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
PORT DDR_DQS_Div_I =
fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s
PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
PORT MPMC_Rst = sys_periph_reset
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 50000000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = DCM0
PARAMETER C_CLKOUT2_FREQ = 100000000
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT2_PHASE = 90
PARAMETER C_CLKOUT2_GROUP = DCM0
PORT CLKOUT0 = sys_clk_s
PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s
PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END

BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.b
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a


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PARAMETER C_EXT_RESET_HIGH = 1
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_gpio
PARAMETER INSTANCE = dip
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_IS_BIDIR = 0
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = dip_GPIO_in
END

BEGIN xps_gpio
PARAMETER INSTANCE = push
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_IS_BIDIR = 0
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = push_GPIO_in
END

BEGIN lcd_ip
PARAMETER INSTANCE = lcd_ip_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xcf400000
PARAMETER C_HIGHADDR = 0xcf40ffff
BUS_INTERFACE SPLB = mb_plb
PORT lcd = lcd_ip_0_lcd
END

BEGIN xps_bram_if_cntlr
PARAMETER INSTANCE = xps_bram_if_cntlr_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_SPLB_NATIVE_DWIDTH = 32
PARAMETER C_BASEADDR = 0x88208000
PARAMETER C_HIGHADDR = 0x88209fff
BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
BUS_INTERFACE SPLB = mb_plb
END

BEGIN bram_block
PARAMETER INSTANCE = xps_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA


SDK Lab: www.xilinx.com/univ 5-25
MicroBlaze Processor xup@xilinx.com

END

BEGIN xps_timer
PARAMETER INSTANCE = delay
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
PARAMETER C_ONE_TIMER_ONLY = 1
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = timer1
PORT CaptureTrig0 = net_gnd
END

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = mb_plb
PORT Irq = microblaze_0_INTERRUPT
PORT Intr = timer1
END