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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity piso is port(x: in std_logic_vector(3 downto 0); load,res,clk: in std_logic; y: out std_logic); end piso; architecture behavior of piso is begin process (clk) variable q: std_logic_vector(3 downto 0); begin if clk='1'then if res='0' then q:="0000"; elsif load='1' then q:=x; else q:='0' & q(3 downto 1); end if; else null; end if; y<=q(0); end process; end behavior;

Simulation Result

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sipo is port(clk, res_sipo, en_sipo, in_bit: in std_logic; sipo_out : out std_logic_vector (3 downto 0)); end sipo; architecture behavior of sipo is begin process (res_sipo,clk) variable q:std_logic_vector(3 downto 0); begin if res_sipo='0'then q:="0000"; elsif (clk'event and clk='0') then if en_sipo='1' then q := in_bit & q (3 downto 1); else null; end if; else null; end if; sipo_out<=q; end process; end behavior;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity seq_1010 is port(x,clk,res:in std_logic; y: out std_logic); end seq_1010; architecture design of seq_1010 is signal pr_state,nxt_state: integer range 0 to 3; signal q: std_logic; begin p1: process (clk,res) begin if res='0' then pr_state<=0; y<='0'; elsif clk'event and clk='1' then pr_state<=nxt_state; y<=q; else null; end if; end process p1; p2: process(pr_state,x) begin case pr_state is when 0 => if x='0' then nxt_state<=0; else nxt_state<=1; end if; q<='0'; when 1 => if x='0' then nxt_state<=2; else nxt_state<=1; end if; q<='0'; when 2 => if x='0' then nxt_state<=0; else nxt_state<=3; end if; q<='0'; when 3 => if x='0' then nxt_state<=2; q<='1'; else nxt_state<=1; q<='0'; end if; end case; end process p2; end design;

VHDL codes for a 2 bit ALU containing 4 arithmetic & 4 logic operations.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity alu is port ( s:in std_logic_vector(2 downto 0); a,b:in std_logic_vector(3 downto 0); c: out std_logic_vector(3 downto 0) ); end alu;

architecture design of alu is signal c1,c2: std_logic_vector(3 downto 0); begin x0: entity work.arithmetic_unit port map(s(1 downto 0),a,b,c1); x1: entity work.logical_unit port map(s(1 downto 0),a,b,c2); x2: entity work.mux port map(s(2),c1,c2,c); end design;

VHDL codes for an arithmetic Unit library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity arithmetic_unit is port ( s:in std_logic_vector(1 downto 0); a,b:in std_logic_vector(3 downto 0); c: out std_logic_vector(3 downto 0) );

end arithmetic_unit;

architecture design of arithmetic_unit is begin process (a,b,s) begin case s is when "00" => c<=a+b; -- addition when "01" => c<=a+"0001"; -- increment a when "10" => c<=b+"0001"; -- increment b when "11" => c<=a-"0001"; -- decrement a when others => c<="0000"; end case; end process; end design;

VHDL codes for a logical Unit library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logical_unit is port ( s:in std_logic_vector(1 downto 0); a,b:in std_logic_vector(3 downto 0); c: out std_logic_vector(3 downto 0) ); end logical_unit;

architecture design of logical_unit is begin process (a,b,s) begin case s is when "00" => c<= not a; -- complement a when "01" => c<= a and b; -- and operation when "10" => c<= a or b; -- or operation when "11" => c<= a xor b; -- xor operation when others => c<="0000";

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