process variation aware FINFET based sram cell

Ashvinikumar Dongre sumit patel

16 April,2012

Contents

Contents:
1. Introduction 2. Need for Novel devices 3. FinFET models 4. Classification of process variation
What is NBTI/PBTI

5. Variations on stability of 6T FinFET SRAM cells with various surface orientations due to NBTI/PBTI 6. Work progress 7. Reference

Introduction Introduction As dimensions of MOS devices have been scaled down. One of these emerging reliability issues is aging effects which result in device performance degradation over time. . new reliability problems are coming into effect. Thus NBTI (for PFET) and PBTI (for NFET)) have become major long-term reliability concerns as they weaken MOSFETs over time. NBTI (Negative Bias Temperature Instability) and PBTI (Positive Bias Temperature Instability) are well known aging effects which cause the threshold voltage degradation of PMOS and NMOS transistors over time. thus resulting in temporal degradation in the stability of the SRAM cells.

Thus. each transistor is isolated by reverse−biased p−n junctions in a well structure. parasitic effects in a SOI device are very small. . Why there is a need to switch over from cmos to novel devices. Bulk CMOS vs SOI CMOS 1. in a SOI CMOS device. In a bulk CMOS device. each transistor is completely isolated by the Oxide insulator.Why there is a need to switch over from cmos to novel devices. On the other hand.

In PD-SOI. The PD-SOI has a relatively thick SOI Si thickness (100-200 nm). the whole body under the gate will deplete.FDSOI FDSOI There are two kinds of SOI devices. there remains a neutral region in the body. In FD-SOI.while in the FD SOI the SOI thickness is less than 50 nm in the FD-SOI the SOI thickness is less than 50 nm. . Partially Depleted (PD)-SOI and Fully Depleted (FD)SOI.

Scaling challenges Scaling challenges At the device gate length (L) less than 100nm. As the physical thickness of the SiO2 gate dielectric (Tox ) is scaled beyond 1. further. reduction in L has yielded limited improvements in performance due to velocity saturation and source velocity limit. quantum mechanical tunneling current from the gate into the channel becomes signicant. Further reduction in Tox will result in large static leakage current and large power consumption even when the device is turned off. .2nm.

.Scaling challenges contd.. . The multi−gate structure is a promising approach. A new approach is needed to allow future reduction of channel length.

The second advantage is improved on state drive current (Ion)and therefore faster circuit speed. Since the channel is controlled electrostatically by the gate from multiple sides. . Improved gate control also provides lower output conductance. Unwanted leakage components are reduced.Multigate advantages Multigate advantages The main advantage of the multigate devices is the improved short channel effects . the channel is better controlled by the gate than in the conventional transistor structure.

. which is handy for driving a large capacitive load such as long interconnect..) Multigate advantages(contd.) The FinFET. provides a larger channel width with a small footprint in area. The third advantage is the reduced manufacturing variation.. the effect of random dopant uctuation (RDF) is minimized. . In the absence of channel dopants. This raises Ion ..Multigate advantages(contd.

FinFET Variants FinFET Variants .

2. . The front and back gate stacks are allowed to have deferent gate workfunctions. independent multi−gate (IMG) 2. dielectric thicknesses and materials. biases. 3. IMG refers to independent double−gate MOSFETs with two separate gates. BSIM IMG 1. common multi− gate (CMG) MOSFETs. Independent−gate FinFET and the planar double−gate SOI belong to this category.FinFET models FinFET models Multi gate MOSFETs are divided in two main categories: 1.

.) FinFET models(contd. bias and dielectric thickness and material.FinFET models(contd. Regular FinFETs and all around gate MOSFETs fall into to this category... The gate stacks of CMG MOSFETs have identical gate workfunction. 2... CMG refers to a special case where the gates are connected together.) BSIM−CMG 1. 3.

.Small signal model for FinFET(contd...) Small signal model for FinFET(contd.) ..

Small signal model for FinFET Small signal model for FinFET .

..Small signal model for FinFET(contd..) Small signal model for FinFET(contd..) .

Classification on process variation Classification on process variation .

.e. which are induced by positive holes from the channel... diffuses away.. the change in vth due to NBTI can be modelled as .NBTI Mechanism and modelling NBTI Mechanism and modelling NBTI is caused by broken Si-H bonds....(1) and Nit is positive interface trap which can be expressed as . which cause the increase of V th. Then H. positive interface traps (N it ) (i. in a neutral form. from Si + ) are left.(2) .

NBTI Modelling contd....(4) . for V ds =0: ....(3) The dependence of K on Vds can be derived from Eq.... (3) as: .NBTI Modelling contd.. K is the generation rate of Nit and found to be linearly proportional to the hole density and exponentially dependent on temperature (T) and the electric field (Eox)Therefore.

instead... the number of interface traps is reduced during this stage and the NBTI degradation is recovered. the .... V gs =0).e. Assuming the recovery happens at t=t 0 with Nit=Nit0 .no new interface traps are generated. As a result. In Phase II...(5) change of Nit can then be modeled as following figure explains the behaviour of NBTI in more detail . holes are not present in the channel and thus. NBTI modelling contd. H diffuses back and anneals the broken Si-H. when Vg=VDD (i.NBTI Modelling contd..

. These are the effect of NBTI/PBTI on Vth at 32nm node.Effects of NBTI/PBTI on SRAM Effects of NBTI/PBTI on SRAM As we can see the PU(pull up)transistors are effected by NBTI and PD(pull down)PG(pass gate)transistors are affected by PBTI.

But at the same time decrease in Iread may cause read failure. .Effects of NBTI/PBTI on SRAM Effects of NBTI/PBTI on SRAM Surprising we see that SNM increases in presence of NBTI/PBTI.

Vds. An optimal VDD exists to minimise the degradation 2. Reducing the duty cycle . PMOS sizing 3.Duty cycle Keeping these points in mind the techniques available to mitigate the effect of NBTI can be stated as 1.Techniques to mitigate effects of NBTI/PBTI Techniques to mitigate effects of NBTI/PBTI From above discussion we can conclude that NBTI/PBTI depends on Process parameters : Vth.Tox Design parameters : VDD.

A FinFet uses an intrinsic body.??? WHY FinFet in SRAM.WHY FinFET in SRAM. FinFet cell offers superior noise margins and switching speeds as well.whereas Fabrication of conventional planar MOSFETs along any plane other than (100) is difficult due to increased process variations and interface traps .??? FinFet based SRAM is found to be more immune to mismatch induced by process variation.. An added advantage of the FinFet is that it can be easily fabricated along different channel planes in a single die.. FinFet is suitable for future nano scale memory circuits design due to its reduced short channel effects.it greatly suppresses the device-performance variability caused by fluctuations in number of dopant ions.

.Oriented FinFETs Oriented FinFets With the advent of FinFETs. fabrication of transistors along the (110) plane has become feasible. leading to design of circuits using differently oriented transistors. logic gates consisting of p-type FinFETs implemented in the (110) plane and n-type FinFETs in the (100) plane will be the fastest. Thus. Electron mobility is highest in the (100) plane and the hole mobility along the (110) plane.

Effect of NBTI/PBTI on FinFET with different orientation Effect of NBTI/PBTI on FinFET with different orientation The variability of RSNM due to NBTI/PBTI can be shown as The variability of WSNM due to NBTI/PBTI can be shown as .

Effect of NBTI/PBTI on FinFET with different orientation Effect of NBTI/PBTI on FinFET with different orientation The entire analysis can be summarised as .

0.Work progress Work progress Tools used 1. We started from device level We went through the device and process simulation steps and tried to modified the example of FinFET according to our requirement. SILVACO-ICCAD(GATEWAY.0(latest model released on 15th march 2012) for Finfet simulation . ATLAS. Take the model files and work on circuit level.DevEdit3D) We found two ways to implement Finfet based SRAM 1. Still working on how to use BSIM-CMG 106.SMARTSPICE) 2. Start work from device level and then use that device at circuit level. 2. SILVACO-TCAD(ATHENA.

Ming-Long Fan. California.San Francisco State University. Pin Su and Ching-Te Chuang. SISPAD 2010 Rakesh Vattikonda.PROCESS AND TEMPERATURE VARIATIONS IN NANO-SCALE CMOS”. Chien-Yu Hsieh.Reference Reference Vita Pi-Ho Hu.Yu Cao. .”FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation” .”Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design”.Wenping Wang.Thesis on ”ANALYSIS OF SRAM RELIABILITY UNDER COMBINED EFFECT OF TRANSISTOR AGING. USA. San Francisco. Harwinder Singh.DAC 2006. California.

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