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Cyclone IV Device Datasheet

CYIV-53001-1.3

This chapter describes the electrical and switching characteristics for Cyclone IV devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include transceiver specifications, core, and periphery performance. This chapter also describes I/O timing, including programmable I/O element (IOE) delay and programmable output buffer delay. This chapter includes the following sections:

Operating Conditions on page 11 Power Consumption on page 115 Switching Characteristics on page 116 I/O Timing on page 137 Glossary on page 138

Operating Conditions
When Cyclone IV devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Cyclone IV devices, you must consider the operating requirements described in this chapter. Cyclone IV devices are offered in commercial, industrial, and automotive grades. Cyclone IV E devices offer 6 (fastest), 7, 8, 8L, and 9L speed grades for commercial devices, 7 and 8L speed grades for industrial devices, and 7 speed grade for automotive devices. Cyclone IV GX devices offer 6 (fastest), 7, and 8 speed grades for commercial devices and 7 speed grade for industrial devices. f For more information about the supported speed grades for respective Cyclone IV devices, refer to the Cyclone IV FPGA Device Family Overview chapter. Cyclone IV E devices are offered in core voltages of 1.0 and 1.2 V. Cyclone IV E devices with a core voltage of 1.0 V have an L prefix attached to the speed grade. In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with a C prefix, industrial with an I prefix, and automotive with an A prefix. Therefore, commercial devices are indicated as C6, C7, C8, C8L, or C9L per respective speed grade. Industrial devices are indicated as I7, I8, or I8L. Automotive devices are indicated as A7.

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Chapter 1: Cyclone IV Device Datasheet Operating Conditions

Absolute Maximum Ratings


Absolute maximum ratings define the maximum operating conditions for Cyclone IV devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied at these conditions. Table 11 lists the absolute maximum ratings for Cyclone IV devices. c Conditions beyond those listed in Table 11 cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time have adverse effects on the device.
Table 11. Absolute Maximum Ratings for Cyclone IV Devices (Note 1) Preliminary Symbol VCCINT VCCA VCCD_PLL VCCIO VCC_CLKIN VCCH_GXB VCCA_GXB VCCL_GXB VI IOUT TSTG TJ Parameter Core voltage, PCI Express (PCIe ) hard IP block, and transceiver physical coding sublayer (PCS) power supply Phase-locked loop (PLL) analog power supply PLL digital power supply I/O banks power supply Differential clock input pins power supply Transceiver output buffer power supply Transceiver physical medium attachment (PMA) and auxiliary power supply Transceiver PMA and auxiliary power supply DC input voltage DC output current, per pin Storage temperature Operating junction temperature

Min 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 25 65 40

Max 1.8 3.75 1.8 3.9 3.9 2.625 2.625 1.8 3.95 40 150 125

Unit V V V V V V V V V mA C C

Note to Table 11:


(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the power supply.

Maximum Allowed Overshoot or Undershoot Voltage


During transitions, input signals may overshoot to the voltage shown in Table 12 and undershoot to 2.0 V for a magnitude of currents less than 100 mA and for periods shorter than 20 ns. Table 12 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the lifetime of the device. The maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. 1 A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.2 V can only be at 4.2 V for 10.74% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 10.74/10ths of a year.

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Table 12. Maximum Allowed Overshoot During Transitions over a 10-Year Time Frame for Cyclone IV Devices Symbol Parameter Condition (V) VI = 3.95 VI = 4.0 VI = 4.05 VI = 4.10 VI = 4.15 VI = 4.20 Vi AC Input Voltage VI = 4.25 VI = 4.30 VI = 4.35 VI = 4.40 VI = 4.45 VI = 4.50 VI = 4.60 VI = 4.70 Overshoot Duration as % of High Time 100 95.67 55.24 31.97 18.52 10.74 6.23 3.62 2.1 1.22 0.71 0.41 0.14 0.047 Unit % % % % % % % % % % % % % %

Figure 11 shows the methodology to determine the overshoot duration. The overshoot voltage is shown in red and is present on the input pin of the Cyclone IV device at over 4.1 V but below 4.2 V. From Table 12, for an overshoot of 4.1 V, the percentage of high time for the overshoot can be as high as 31.97% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations in which the device is in an idle state, lifetimes are increased.
Figure 11. Cyclone IV Devices Overshoot Duration

4.2 V 4.1 V 3.3 V

T T

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Recommended Operating Conditions


This section lists the functional operation limits for AC and DC parameters for Cyclone IV devices. Table 13 and Table 14 list the steady-state voltage and current values expected from Cyclone IV E and Cyclone IV GX devices. All supplies must be strictly monotonic without plateaus.
Table 13. Recommended Operating Conditions for Cyclone IV E Devices (Note 1), (2) (Part 1 of 2) Symbol Parameter Supply voltage for internal logic, 1.2-V operation Supply voltage for internal logic, 1.0-V operation Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 3.0-V operation Supply voltage for output buffers, 2.5-V operation Supply voltage for output buffers, 1.8-V operation Supply voltage for output buffers, 1.5-V operation Supply voltage for output buffers, 1.2-V operation VCCA (3) Supply (analog) voltage for PLL regulator Supply (digital) voltage for PLL, 1.2-V operation Supply (digital) voltage for PLL, 1.0-V operation Input voltage Output voltage Operating junction temperature Conditions For commercial use TJ For industrial use For automotive use tRAMP Power supply ramp time Standard power-on reset (POR) (5) Fast POR (6) Min 1.15 0.97 3.135 2.85 2.375 1.71 1.425 1.14 2.375 1.15 0.97 0.5 0 0 40 40 50 s 50 s Typ 1.2 1.0 3.3 3 2.5 1.8 1.5 1.2 2.5 1.2 1.0 Max 1.25 1.03 3.465 3.15 2.625 1.89 1.575 1.26 2.625 1.25 1.03 3.6 VCCIO 85 100 125 50 ms 3 ms Unit V V V V V V V V V V V V V C C C

VCCINT (3)

VCCIO (3), (4)

VCCD_PLL (3)

VI VO

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Table 13. Recommended Operating Conditions for Cyclone IV E Devices (Note 1), (2) (Part 2 of 2) Symbol IDiode Parameter Magnitude of DC current across PCI-clamp diode when enable Conditions Min Typ Max 10 Unit mA

Notes to Table 13:


(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. (2) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time. (3) VCC must rise monotonically. (4) VCCIO powers all input buffers. (5) The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range within 50 ms. (6) The POR time for Fast POR ranges between 3 and 9 ms. Each individual power supply must reach the recommended operating range within 3 ms.

Table 14. Recommended Operating Conditions for Cyclone IV GX Devices (Part 1 of 2)Preliminary Symbol VCCINT (3) VCCA (1),(3) VCCD_PLL (2) Parameter Core voltage, PCIe hard IP block, and transceiver PCS power supply PLL analog power supply PLL digital power supply I/O banks power supply for 3.3-V operation I/O banks power supply for 3.0-V operation I/O banks power supply for 2.5-V operation I/O banks power supply for 1.8-V operation I/O banks power supply for 1.5-V operation I/O banks power supply for 1.2-V operation Differential clock input pins power supply for 3.3-V operation Differential clock input pins power supply for 3.0-V operation VCC_CLKIN (3),(5), (6) Differential clock input pins power supply for 2.5-V operation Differential clock input pins power supply for 1.8-V operation Differential clock input pins power supply for 1.5-V operation Differential clock input pins power supply for 1.2-V operation VCCH_GXB VCCA_GXB Transceiver output buffer power supply Transceiver PMA and auxiliary power supply Conditions Min 1.16 2.375 1.16 3.135 2.85 2.375 1.71 1.425 1.14 3.135 2.85 2.375 1.71 1.425 1.14 2.375 2.375 Typ 1.2 2.5 1.2 3.3 3 2.5 1.8 1.5 1.2 3.3 3 2.5 1.8 1.5 1.2 2.5 2.5 Max 1.24 2.625 1.24 3.465 3.15 2.625 1.89 1.575 1.26 3.465 3.15 2.625 1.89 1.575 1.26 2.625 2.625 Unit V V V V V V V V V V V V V V V V V

VCCIO (3), (4)

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Table 14. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2)Preliminary Symbol VCCL_GXB VI VO TJ Parameter Transceiver PMA and auxiliary power supply DC input voltage DC output voltage Operating junction temperature Conditions For commercial use For industrial use Standard power-on reset (POR) (7) Fast POR (8) IDiode Magnitude of DC current across PCI-clamp diode when enabled Min 1.16 0.5 0 0 40 50 s 50 s Typ 1.2 Max 1.24 3.6 VCCIO 85 100 50 ms 3 ms 10 Unit V V V C C mA

tRAMP

Power supply ramp time

Notes to Table 14:


(1) All VCCA pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time. (2) You must connect VCCD_PLL to VCCINT through a decoupling capacitor and ferrite bead. (3) Power supplies must rise monotonically. (4) VCCIO for all I/O banks must be powered up during device operation. Configurations pins are powered up by VCCIO of I/O Banks 3, 8, and 9 where I/O Banks 3 and 9 only support VCCIO of 1.5, 1.8, 2.5, 3.0, and 3.3 V. For fast passive parallel (FPP) configuration mode, the VCCIO level of I/O Bank 8 must be powered up to 1.5, 1.8, 2.5, 3.0, and 3.3 V. (5) You must set VCC_CLKIN to 2.5 V if you use CLKIN as a high-speed serial interface (HSSI) refclk. VCC_CLKIN located at I/O Banks 3B and 8B only support a nominal voltage level of 2.5 V for LVDS input function because they are dedicated for HSSI refclk. (6) The CLKIN pins in I/O Banks 3B and 8B can support single-ended I/O standard. (7) The POR time for Standard POR ranges between 50 and 200 ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended operating range within 50 ms. (8) The POR time for Fast POR ranges between 3 and 9 ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended operating range within 3 ms.

ESD Performance
This section lists the electrostatic discharge (ESD) voltages using the human body model (HBM) and charged device model (CDM) for Cyclone IV devices general purpose I/Os (GPIOs) and high-speed serial interface (HSSI) I/Os. Table 16 lists the ESD for Cyclone IV devices GPIOs and HSSI I/Os.
Table 15. ESD for Cyclone IV Devices GPIOs and HSSI I/Os Symbol VESDHBM VESDCDM
Note to Table 15:
(1) This value is applicable only to Cyclone IV GX devices.

Parameter ESD voltage using the HBM (GPIOs) ESD using the HBM (HSSI I/Os) (1) ESD using the CDM (GPIOs) ESD using the CDM (HSSI I/Os) (1)

Passing Voltage 2000 1000 500 250

Unit V V V V

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DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT) tolerance, and bus hold specifications for Cyclone IV devices.

Supply Current
The device supply current requirement is the minimum current drawn from the power supply pins that can be used as a reference for power size planning. Use the Excel-based early power estimator (EPE) to get the supply current estimates for your design because these currents vary greatly with the resources used. Table 16 lists the I/O pin leakage current for Cyclone IV devices.
Table 16. I/O Pin Leakage Current for Cyclone IV Devices (Note 1), (2) Symbol II IOZ Parameter Input pin leakage current Tristated I/O pin leakage current Conditions VI = 0 V to VCCIOMAX VO = 0 V to VCCIOMAX Device Min 10 10 Typ Max 10 10 Unit A A

Notes to Table 16:


(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V). (2) The 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on.

Bus Hold
The bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode. Table 17 lists bus hold specifications for Cyclone IV devices.
Table 17. Bus Hold Parameter for Cyclone IV Devices (Part 1 of 2) (Note 1)Preliminary VCCIO (V) Parameter Condition Min Bus hold low, sustaining current Bus hold high, sustaining current Bus hold low, overdrive current Bus hold high, overdrive current VIN > VIL (maximum) 1.2 Max Min 1.5 Max Min 1.8 Max Min 2.5 Max 3.0 Min Max 3.3 Min Max A Unit

12

30

50

70

70

VIN < VIL (minimum)

12

30

50

70

70

0 V < VIN < VCCIO

125

175

200

300

500

500

0 V < VIN < VCCIO

125

175

200

300

500

500

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Table 17. Bus Hold Parameter for Cyclone IV Devices (Part 2 of 2) (Note 1)Preliminary VCCIO (V) Parameter Condition Min Bus hold trip point
Note to Table 17:
(1) Bus hold trip points are based on the calculated input voltages from the JEDEC standard.

1.2 Max 0.9 Min

1.5 Max Min

1.8 Max 1.07 Min 0.7

2.5 Max 1.7

3.0 Min 0.8 Max 2

3.3 Min 0.8 Max 2

Unit

0.3

0.375 1.125

0.68

OCT Specifications
Table 18 lists the variation of OCT without calibration across process, temperature, and voltage (PVT).
Table 18. Series OCT Without Calibration Specifications for Cyclone IV DevicesPreliminary Resistance Tolerance Description VCCIO (V) 3.0 2.5 Series OCT without calibration 1.8 1.5 1.2 Commercial Max 30 30 40 50 50 Industrial and Automotive Max 40 40 50 50 50 Unit % % % % %

OCT calibration is automatically performed at device power-up for OCT-enabled I/Os. Table 19 lists the OCT calibration accuracy at device power-up.
Table 19. Series OCT with Calibration at Device Power-Up Specifications for Cyclone IV Devices Preliminary Calibration Accuracy Description VCCIO (V) Commercial Max 3.0 Series OCT with calibration at device power-up 2.5 1.8 1.5 1.2 10 10 10 10 10 Industrial and Automotive Max 10 10 10 10 10 Unit % % % % %

The OCT resistance may vary with the variation of temperature and voltage after calibration at device power-up. Use Table 110 and Equation 11 to determine the final OCT resistance considering the variations after calibration at device power-up. Table 110 lists the change percentage of the OCT resistance with voltage and temperature.

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Table 110. OCT Variation After Calibration at Device Power-Up for Cyclone IV DevicesPreliminary Nominal Voltage 3.0 2.5 1.8 1.5 1.2 dR/dT (%/C) 0.262 0.234 0.219 0.199 0.161 dR/dV (%/mV) 0.026 0.039 0.086 0.136 0.288

Equation 11. Final OCT Resistance (Note 1), (2), (3), (4), (5), (6) RV = (V2 V1) 1000 dR/dV (7) RT = (T2 T1) dR/dT (8) For Rx < 0; MFx = 1/ (|Rx|/100 + 1) (9) For Rx > 0; MFx = Rx/100 + 1 (10) MF = MFV MFT (11) Rfinal = Rinitial MF (12)
Notes to Equation 11:
(1) T2 is the final temperature. (2) T1 is the initial temperature. (3) MF is multiplication factor. (4) Rfinal is final resistance. (5) Rinitial is initial resistance. (6) Subscript x refers to both V and T. (7) RV is a variation of resistance with voltage. (8) RT is a variation of resistance with temperature. (9) dR/dT is the change percentage of resistance with temperature after calibration at device power-up. (10) dR/dV is the change percentage of resistance with voltage after calibration at device power-up. (11) V2 is final voltage. (12) V1 is the initial voltage.

Example 11 shows how to calculate the change of 50-I/O impedance from 25C at 3.0 V to 85C at 3.15 V.
Example 11. Impedance Change RV = (3.15 3) 1000 0.026 = 3.83 RT = (85 25) 0.262 = 15.72 Because RV is negative, MFV = 1 / (3.83/100 + 1) = 0.963 Because RT is positive, MFT = 15.72/100 + 1 = 1.157 MF = 0.963 1.157 = 1.114 Rfinal = 50 1.114 = 55.71

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Pin Capacitance
Table 111 lists the pin capacitance for Cyclone IV devices.
Table 111. Pin Capacitance for Cyclone IV Devices Preliminary Typical Quad Flat Pack (QFP) 7 7 8 21 23 7 6 Typical Quad Flat No Leads (QFN) 7 7 8 21 23 7 6 Typical Fineline BGA (FBGA) 6 5 7 21 23 6 5

Symbol CIOTB CIOLR CLVDSLR CVREFLR (1) CVREFTB (1) CCLKTB CCLKLR

Parameter Input capacitance on top and bottom I/O pins Input capacitance on right I/O pins Input capacitance on right I/O pins with dedicated LVDS output Input capacitance on right dual-purpose VREF pin when used as VREF or user I/O pin Input capacitance on top and bottom dual-purpose VREF pin when used as VREF or user I/O pin Input capacitance on top and bottom dedicated clock input pins Input capacitance on right dedicated clock input pins

Unit pF pF pF pF pF pF pF

Note to Table 111:


(1) When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and tCO because of higher pin capacitance.

Internal Weak Pull-Up and Weak Pull-Down Resistor


Table 112 lists the weak pull-up and pull-down resistor values for Cyclone IV devices.
Table 112. Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Cyclone IV Devices (Note 1) (Part 1 of 2) Preliminary Symbol Parameter Conditions VCCIO = 3.3 V 5% (2), (3) Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you enable the programmable pull-up resistor option VCCIO = 3.0 V 5% (2), (3) VCCIO = 2.5 V 5% (2), (3) VCCIO = 1.8 V 5% (2), (3) VCCIO = 1.5 V 5% (2), (3) VCCIO = 1.2 V 5% (2), (3) Min 7 7 8 10 13 19 Typ 25 28 35 57 82 143 Max 41 47 61 108 163 351 Unit k k k k k k

R_PU

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Table 112. Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Cyclone IV Devices (Note 1) (Part 2 of 2) Preliminary Symbol Parameter Conditions VCCIO = 3.3 V 5% (4) VCCIO = 3.0 V 5% (4) R_PD Value of the I/O pin pull-down resistor before and during configuration VCCIO = 2.5 V 5% (4) VCCIO = 1.8 V 5% (4) VCCIO = 1.5 V 5% (4)
Notes to Table 112:
(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (3) R_PU = (VCCIO VI)/IR_PU Minimum condition: 40C; VCCIO = VCC + 5%, VI = VCC + 5% 50 mV; Typical condition: 25C; VCCIO = VCC, VI = 0 V; Maximum condition: 100C; VCCIO = VCC 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin. (4) R_PD = VI/IR_PD Minimum condition: 40C; VCCIO = VCC + 5%, VI = 50 mV; Typical condition: 25C; VCCIO = VCC, VI = VCC 5%; Maximum condition: 100C; VCCIO = VCC 5%, VI = VCC 5%; in which VI refers to the input voltage at the I/O pin.

Min 6 6 6 7 8

Typ 19 22 25 35 50

Max 30 36 43 71 112

Unit k k k k k

Hot-Socketing
Table 113 lists the hot-socketing specifications for Cyclone IV devices.
Table 113. Hot-Socketing Specifications for Cyclone IV Devices Preliminary Symbol IIOPIN(DC) IIOPIN(AC) IXCVRTX(DC) IXCVRRX(DC)
Note to Table 113:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate.

Parameter DC current per I/O pin AC current per I/O pin DC current per transceiver TX pin DC current per transceiver RX pin

Maximum 300 A 8 mA (1) 100 mA 50 mA

During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF.

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Schmitt Trigger Input


Cyclone IV devices support Schmitt trigger input on the TDI, TMS, TCK, nSTATUS, nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rate. Table 114 lists the hysteresis specifications across the supported VCCIO range for Schmitt trigger inputs in Cyclone IV devices.
Table 114. Hysteresis Specifications for Schmitt Trigger Input in Cyclone IV Devices Preliminary Symbol Parameter Conditions (V) VCCIO = 3.3 VSCHMITT Hysteresis for Schmitt trigger input VCCIO = 2.5 VCCIO = 1.8 VCCIO = 1.5 Minimum 200 200 140 110 Unit mV mV mV mV

I/O Standard Specifications


The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL), for various I/O standards supported by Cyclone IV devices. Table 115 through Table 120 provide the I/O standard specifications for Cyclone IV devices.
Table 115. Single-Ended I/O Standard Specifications for Cyclone IV Devices (Note 1), (2) Preliminary VCCIO (V) I/O Standard Min 3.3-V LVTTL (3) 3.3-V LVCMOS (3) 3.0-V LVTTL (3) 3.0-V LVCMOS (3) 2.5-V LVTTL and LVCMOS (3) 1.8-V LVTTL and LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.0-V PCI 3.0-V PCI-X
Notes to Table 115:
(1) For voltage-referenced receiver input waveform and explanation of terms used in Table 115, refer to Glossary on page 138. (2) AC load CL = 10 pF (3) For more information about interfacing Cyclone IV devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

VIL (V) Max 3.465 3.465 3.15 3.15 2.625 1.89 1.575 1.26 3.15 3.15 Min 0.3 0.3 0.3 0.3 0.3 0.3 Max 0.8 0.8 0.8 0.8 0.7 0.35 * VCCIO 0.35 * VCCIO 0.35 * VCCIO 0.3 * VCCIO 0.35* VCCIO Min 1.7 1.7 1.7 1.7 1.7 0.65 * VCCIO 0.65 * VCCIO 0.65 * VCCIO 0.5 * VCCIO 0.5 * VCCIO

VIH (V) Max 3.6 3.6 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 2.25 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3

VOL (V) Max 0.45 0.2 0.45 0.2 0.4 0.45

VOH (V) Min 2.4 VCCIO 0.2 2.4 VCCIO 0.2 2.0 VCCIO 0.45

Typ 3.3 3.3 3.0 3.0 2.5 1.8 1.5 1.2 3.0 3.0

IOL (mA) 4 2 4 0.1 1 2 2 2 1.5 1.5

IOH (mA) 4 2 4 0.1 1 2 2 2 0.5 0.5

3.135 3.135 2.85 2.85 2.375 1.71 1.425 1.14 2.85 2.85

0.25 * VCCIO 0.75 * VCCIO 0.25 * VCCIO 0.75 * VCCIO 0.1 * VCCIO 0.1 * VCCIO 0.9 * VCCIO 0.9 * VCCIO

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Table 116. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Cyclone IV Devices (Note 1) Preliminary I/O Standard SSTL-2 Class I, II SSTL-18 Class I, II HSTL-18 Class I, II HSTL-15 Class I, II HSTL-12 Class I, II VCCIO (V) Min 2.375 1.7 1.71 1.425 1.14 Typ 2.5 1.8 1.8 1.5 1.2 Max 2.625 1.9 1.89 1.575 1.26 Min 1.19 0.833 0.85 0.71 0.48 * VCCIO (3) 0.47 * VCCIO (4) VREF (V) Typ 1.25 0.9 0.9 0.75 0.5 * VCCIO (3) 0.5 * VCCIO (4) Max 1.31 0.969 0.95 0.79 0.52 * VCCIO (3) 0.53 * VCCIO (4) Min VREF 0.04 VREF 0.04 0.85 0.71 VTT (V) (2) Typ VREF VREF 0.9 0.75 0.5 * VCCIO Max VREF + 0.04 VREF + 0.04 0.95 0.79

Notes to Table 116:


(1) For an explanation of terms used in Table 116, refer to Glossary on page 138. (2) VTT of the transmitting device must track VREF of the receiving device. (3) Value shown refers to DC input reference voltage, VREF(DC). (4) Value shown refers to AC input reference voltage, VREF(AC).

Table 117. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Cyclone IV DevicesPreliminary I/O Standard SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I HSTL-12 Class II VIL(DC) (V) Min 0.15 0.15 Max VREF 0.18 VREF 0.18 VREF 0.125 VREF 0.125 VREF 0.1 VREF 0.1 VREF 0.1 VREF 0.1 VREF 0.08 VREF 0.08 Min VREF + 0.18 VREF + 0.18 VREF + 0.125 VREF + 0.125 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.08 VREF + 0.08 VIH(DC) (V) Max VCCIO + 0.15 VCCIO + 0.15 VIL(AC) (V) Min 0.24 0.24 Max VREF 0.35 VREF 0.35 VREF 0.25 VREF 0.25 VREF 0.2 VREF 0.2 VREF 0.2 VREF 0.2 VREF 0.15 VREF 0.15 Min VREF + 0.35 VREF + 0.35 VREF + 0.25 VREF + 0.25 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.15 VREF + 0.15 VIH(AC) (V) Max VCCIO + 0.24 VCCIO + 0.24 VOL (V) Max VTT 0.57 VTT 0.76 VTT 0.475 0.28 0.4 0.4 0.4 0.4 0.25 VCCIO 0.25 VCCIO VOH (V) Min VTT + 0.57 VTT + 0.76 VTT + 0.475 VCCIO 0.28 VCCIO 0.4 VCCIO 0.4 VCCIO 0.4 VCCIO 0.4 0.75 VCCIO 0.75 VCCIO IOL (mA) 8.1 16.4 6.7 13.4 8 16 8 16 8 14 IOH (mA) 8.1 16.4 6.7 13.4 8 16 8 16 8 14

For more information about receiver input and transmitter output waveforms, and for other differential I/O standards, refer to the I/O Features in Cyclone IV Devices chapter.

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Table 118. Differential SSTL I/O Standard Specifications for Cyclone IV DevicesPreliminary VCCIO (V) I/O Standard Min SSTL-2 Class I, II SSTL-18 Class I, II 2.375 1.7 Typ 2.5 1.8 Max Min Max VCCIO VCCIO Min VCCIO/2 0.2 VCCIO/2 0.175 Typ Max VCCIO/2 + 0.2 VCCIO/2 + 0.175 Min Max 0.7 0.5 VCCIO VCCIO Min VCCIO/2 0.125 VCCIO/2 0.125 Typ Max VCCIO/2 + 0.125 VCCIO/2 + 0.125 2.625 0.36 1.90 0.25 VSwing(DC) (V) VX(AC) (V) VSwing(AC) (V) VOX(AC) (V)

Table 119. Differential HSTL I/O Standard Specifications for Cyclone IV DevicesPreliminary VCCIO (V) I/O Standard Min HSTL-18 Class I, II HSTL-15 Class I, II HSTL-12 Class I, II 1.71 1.425 1.14 Typ 1.8 1.5 1.2 Max 1.89 1.575 1.26 Min 0.2 0.2 0.16 Max VCCIO Min 0.85 0.71 0.48 * VCCIO Typ Max 0.95 0.79 0.52 * VCCIO Min 0.85 0.71 0.48 * VCCIO Typ Max 0.95 0.79 0.52 * VCCIO VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V) Mi n 0.4 0.4 0.3 Max 0.48 * VCCIO

Table 120. Differential I/O Standard Specifications for Cyclone IV Devices (Note 1) (Part 1 of 2)Preliminary VCCIO (V) I/O Standard Min LVPECL (Row I/Os) (6) Typ Max Min Max Min 0.05 2.375 2.5 2.625 100 0.55 1.05 0.05 LVPECL (Column I/Os) (6) 2.375 2.5 2.625 100 0.55 1.05 0.05 LVDS (Row I/Os) 2.375 2.5 2.625 100 0.55 1.05 0.05 LVDS (Column I/Os) BLVDS (Row I/Os) (4) BLVDS (Column I/Os) (4) 2.375 2.5 2.625 100 0.55 1.05 2.375 2.5 2.625 100 VID (mV) VIcM (V) (2) Condition DMAX500 Mbps 500 Mbps DMAX 700 Mbps DMAX > 700 Mbps DMAX 500 Mbps 500 Mbps DMAX 700 Mbps DMAX > 700 Mbps DMAX 500 Mbps 500 Mbps DMAX 700 Mbps DMAX > 700 Mbps DMAX 500 Mbps 500 Mbps DMAX 700 Mbps DMAX > 700 Mbps Max 1.80 1.80 1.55 1.80 1.80 1.55 1.80 1.80 1.55 1.80 1.80 1.55 247 600 1.125 1.25 1.375 247 600 1.125 1.25 1.375 VOD (mV) (3) Min Typ Max Min VOS (V) (3) Typ Max

2.375

2.5

2.625

100

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Table 120. Differential I/O Standard Specifications for Cyclone IV Devices (Note 1) (Part 2 of 2)Preliminary VCCIO (V) I/O Standard Min mini-LVDS (Row I/Os) (5) mini-LVDS (Column I/Os) (5) RSDS (Row I/Os)(5) RSDS (Column I/Os) (5) PPDS (Row I/Os) (5) PPDS (Column I/Os) (5) 2.375 Typ 2.5 Max 2.625 Min Max Min VID (mV) VIcM (V) (2) Condition Max VOD (mV) (3) Min 300 Typ Max 600 Min 1.0 VOS (V) (3) Typ 1.2 Max 1.4

2.375

2.5

2.625

300

600

1.0

1.2

1.4

2.375

2.5

2.625

100

200

600

0.5

1.2

1.5

2.375

2.5

2.625

100

200

600

0.5

1.2

1.5

2.375

2.5

2.625

100

200

600

0.5

1.2

1.4

2.375

2.5

2.625

100

200

600

0.5

1.2

1.4

Notes to Table 120:


(1) For an explanation of terms used in Table 120, refer to Glossary on page 138. (2) VIN range: 0 V VIN 1.85 V. (3) RL range: 90 RL 110 . (4) There are no fixed VIN , VOD , and VOS specifications for BLVDS. They depend on the system topology. (5) The Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins. (6) The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported for output pins.

Power Consumption
Use the following methods to estimate power for a design:

the Excel-based EPE the Quartus II PowerPlay power analyzer feature

The interactive Excel-based EPE is used prior to designing the device to get a magnitude estimate of the device power. The Quartus II PowerPlay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The PowerPlay power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, combined with detailed circuit models, can yield very accurate power estimates. f For more information about power estimation tools, refer to the Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook.

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Switching Characteristics
This section provides performance characteristics of Cyclone IV core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary or Final.

Preliminary characteristics are created using simulation results, process data, and other known parameters. The upper-right hand corner of these tables show the designation as Preliminary. Final numbers are based on actual silicon characterization and testing. The numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. There are no designations on finalized tables.

Transceiver Performance Specifications


Table 121 lists the Cyclone IV GX transceiver specifications.
Table 121. Transceiver Specification for Cyclone IV GX Devices (Part 1 of 4)Preliminary Symbol/ Description Reference Clock Supported I/O Standards Input frequency from REFCLK input pins Spread-spectrum modulating clock frequency Spread-spectrum downspread Rref Transceiver Clock Calibration block clock frequency fixedclk clock frequency reconfig_clk clock frequency Delta time between reconfig_clk PCIe Receiver Detect Dynamic reconfiguration clock frequency 10 2.5/ 37.5 (1) 125 125 10 2.5/ 37.5 (1) 125 125 10 2.5/ 37.5 (1) 125 125 MHz MHz Physical interface for PCI Express (PIPE) mode PIPE mode 1.2 V PCML, 1.5 V PCML, 3.3 V PCML, Differential LVPECL, LVDS, HCSL C6 Conditions Min Typ Max Min Typ Max Min Typ Max C7 C8 Unit

156.25

156.25

156.25

MHz

30

33

30

33

30

33

kHz

0 to 0.5% 2000 1%

0 to 0.5% 2000 1%

0 to 0.5% 2000 1%

50

50

50

MHz

ms

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Table 121. Transceiver Specification for Cyclone IV GX Devices (Part 2 of 4)Preliminary Symbol/ Description Transceiver block minimum power-down pulse width Receiver Supported I/O Standards Data rate (F324 and smaller package) Data rate (F484 and larger package) Absolute VMAX for a receiver pin (2) Operational VMAX for a receiver pin Absolute VMIN for a receiver pin Peak-to-peak differential input voltage VID (diff p-p) VICM Differential on-chip termination resistors Differential and common mode return loss Programmable PPM detector (3) Run length VICM = 0.82 V setting, Data Rate = 600 Mbps to 3.125 Gbps VICM = 0.82 V setting 100 setting 150 setting PIPE, Serial Rapid I/O SR, SATA, CPRI LV, SDI, XAUI No Equalization Programmable equalization Medium Low Medium High High Signal detect/loss threshold tLTR (4) tLTR-LTD_Manual (5) tLTD (6) PIPE mode 65 15 0 80 100 1.5 4.5 5.5 7 175 75 4000 600 600 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS 2500 3125 1.6 1.5 600 600 2500 3125 1.6 1.5 600 600 2500 2500 1.6 1.5 Mbps Mbps V V V C6 Conditions Min Typ Max Min Typ Max Min Typ Max C7 C8 Unit

0.4

0.4

0.4

0.1

2.7

0.1

2.7

0.1

2.7

820 100 150

820 100 150

820 100 150

mV

Compliant

62.5, 100, 125, 200, 250, 300, 500, 1000 65 15 0 80 100 1.5 4.5 5.5 7 175 75 4000 65 15 0 80 100 1.5 4.5 5.5 7 175 75 4000

PPM UI dB dB dB dB mV s s ns

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Table 121. Transceiver Specification for Cyclone IV GX Devices (Part 3 of 4)Preliminary Symbol/ Description tLTD_Manual (7) tLTD_Auto (8) Receiver buffer and CDR offset cancellation time (per channel) C6 Conditions Min Typ Max 4000 4000 Min Typ Max 4000 4000 Min Typ Max 4000 4000 ns ns reconfig _clk cycles C7 C8 Unit

17000

17000

17000

DC Gain Setting =0 Programmable DC gain DC Gain Setting =1 DC Gain Setting =2 Transmitter Supported I/O Standards Data rate (F324 and smaller package) Data rate (F484 and larger package) VOCM Differential on-chip termination resistors Differential and common mode return loss Rise time Fall time Intra-differential pair skew Intra-transceiver block skew 0.65 V setting 100 setting 150 setting PIPE, CPRI LV, Serial Rapid I/O SR, SDI, XAUI, SATA

0 3 6

0 3 6

0 3 6

dB dB dB

1.5 V PCML 600 600 650 100 150 2500 3125 600 600 650 100 150 2500 3125 600 600 650 100 150 2500 2500 Mbps Mbps mV

Compliant

50 50

200 200 15 120

50 50

200 200 15 120

50 50

200 200 15 120

ps ps ps ps

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Table 121. Transceiver Specification for Cyclone IV GX Devices (Part 4 of 4)Preliminary Symbol/ Description C6 Conditions Min Typ Max Min Typ Max Min Typ Max C7 C8 Unit

PLD-Transceiver Interface Interface speed (F324 and smaller package) Interface speed (F484 and larger package) Digital reset pulse width
Notes to Table 121:
(1) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is configured in Receiver Only or Receiver and Transmitter mode. (2) The device cannot tolerate prolonged operation at this absolute maximum. (3) The rate matcher supports only up to 300 parts per million (PPM). (4) Time taken until pll_locked goes high after pll_powerdown deasserts. (5) Time that the CDR must be kept in lock-to-reference mode after rx_analogreset deasserts and before rx_locktodata is asserted in manual mode. (6) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode (Figure 12), or after rx_freqlocked signal goes high in automatic mode (Figure 13). (7) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. (8) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode.

25

125

25

125

25

125

MHz

25

156.25

25

156.25

25

156.25

MHz

Minimum is 2 parallel clock cycles

Figure 12 shows the lock time parameters in manual mode. 1 LTD = lock-to-data. LTR = lock-to-reference.

Figure 12. Lock Time Parameters for Manual Mode


Reset Signals

2
rx _ analogreset

4
rx _ digitalreset

t LTD_Manual (2)
CDR Control Signals

3
rx _ locktorefclk

t LTR_LTD_Manual (1)
rx _ locktodata

Two parallel clock cycles

Output Status Signals

1
busy

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Figure 13 shows the lock time parameters in automatic mode.


Figure 13. Lock Time Parameters for Automatic Mode
Reset Signals

2
rx _ analogreset

4
rx _ digitalreset
Two parallel clock cycles

Output Status Signals busy

3
rx _ freqlocked

t LTD_Auto (1)

Figure 14 shows the differential receiver input waveform.


Figure 14. Receiver Input Waveform
Single-Ended Waveform Positive Channel (p) VID Negative Channel (n) VCM Ground

Differential Waveform

VID (diff peak-peak) = 2 x VID (single-ended) VID pn=0V VID

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Figure 15 shows the transmitter output waveform.


Figure 15. Transmitter Output WaveformPreliminary
Single-Ended Waveform Positive Channel (p) VOD Negative Channel (n) VCM Ground

Differential Waveform

VOD (diff peak-peak) = 2 x VOD (single-ended) VOD pn=0V VOD

Table 122 lists the typical VOD for Tx term that equals 100 .
Table 122. Typical VOD Setting, Tx Term = 100 Preliminary VOD Setting (mV) Symbol 1 VOD Typical (mV)
Note to Table 122:
(1) This setting is required for compliance with the PCIe protocol.

2 600

3 800

4 (1) 900

5 1000

6 1200

400

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Table 123 lists the Cyclone IV GX transceiver block AC specifications.


Table 123. Transceiver Block AC Specification for Cyclone IV GX Devices (Note 1), (2) Preliminary Symbol/ Description C6 Conditions Min Typ Max Min Typ Max Min Typ Max C7, I7 C8 Unit

PCIe Transmit Jitter Generation (3) Total jitter at 2.5 Gbps (Gen1) Compliance pattern 0.25 0.25 0.25 UI

PCIe Receiver Jitter Tolerance (3) Total jitter at 2.5 Gbps (Gen1) Compliance pattern > 0.6 > 0.6 > 0.6 UI

GIGE Transmit Jitter Generation (4) Deterministic jitter (peak-to-peak) Total jitter (peak-to-peak) Pattern = CRPAT Pattern = CRPAT 0.14 0.279 0.14 0.279 0.14 0.279 UI UI

GIGE Receiver Jitter Tolerance (4) Deterministic jitter tolerance (peak-to-peak) Combined deterministic and random jitter tolerance (peak-to-peak)
Notes to Table 123:
(1) Dedicated refclk pins were used to drive the input reference clocks. (2) The jitter numbers specified are valid for the stated conditions only. (3) The jitter numbers for PIPE are compliant to the PCIe Base Specification 2.0. (4) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.

Pattern = CJPAT

> 0.4

> 0.4

> 0.4

UI

Pattern = CJPAT

> 0.66

> 0.66

> 0.66

UI

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Core Performance Specifications


The following sections describe the clock tree specifications, PLLs, embedded multiplier, memory block, and configuration specifications for Cyclone IV Devices.

Clock Tree Specifications


Table 124 lists the clock tree specifications for Cyclone IV devices.
Table 124. Clock Tree Performance for Cyclone IV Devices Preliminary Performance Device C6 EP4CE6 EP4CE10 EP4CE15 EP4CE22 EP4CE30 EP4CE40 EP4CE55 EP4CE75 EP4CE115 EP4CGX15 EP4CGX22 EP4CGX30 EP4CGX50 EP4CGX75 EP4CGX110 EP4CGX150
Note to Table 124:
(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades.

Unit C7 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 C8 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 C8L (1) 362 362 362 362 362 362 362 362 362 C9L (1) 265 265 265 265 265 265 265 265 265 I7 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 437.5 I8L (1) 362 362 362 362 362 362 362 362 362 A7 402 402 402 402 402 402 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500

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PLL Specifications
Table 125 lists the PLL specifications for Cyclone IV devices when operating in the commercial junction temperature range (0C to 85C), the industrial junction temperature range (40C to 100C), and the automotive junction temperature range (40C to 125C). For more information about the PLL block, refer to Glossary on page 138.
Table 125. PLL Specifications for Cyclone IV Devices (Note 1), (2) (Part 1 of 2)Preliminary Symbol fIN (3) fINPFD fVCO (4) fINDUTY tINJITTER_CCJ (5) fOUT_EXT (external clock output) (3) Parameter Input clock frequency (6, 7, 8 speed grades) Input clock frequency (8L speed grade) Input clock frequency (9L speed grade) PFD input frequency PLL internal VCO operating range Input clock duty cycle Input clock cycle-to-cycle jitter FREF 100 MHz FREF < 100 MHz PLL output frequency PLL output frequency (6 speed grade) PLL output frequency (7 speed grade) fOUT (to global clock) PLL output frequency (8 speed grade) PLL output frequency (8L speed grade) PLL output frequency (9L speed grade) tOUTDUTY tLOCK tDLOCK Duty cycle for external clock output (when set to 50%) Time required to lock from end of device configuration Time required to lock dynamically (after switchover, reconfiguring any non-post-scale counters/delays or areset is deasserted) Dedicated clock output period jitter FOUT 100 MHz FOUT < 100 MHz tOUTJITTER_CCJ_DEDCLK (6) Dedicated clock output cycle-to-cycle jitter FOUT 100 MHz FOUT < 100 MHz tOUTJITTER_PERIOD_IO (6) Regular I/O period jitter FOUT 100 MHz FOUT < 100 MHz tOUTJITTER_CCJ_IO (6) tPLL_PSERR tARESET Regular I/O cycle-to-cycle jitter FOUT 100 MHz FOUT < 100 MHz Accuracy of PLL phase shift Minimum pulse width on areset signal. Min 5 5 5 5 600 40 45 Typ 50 Max 472.5 362 265 325 1300 60 0.15 750 472.5 472.5 450 402.5 362 265 55 1 1 Unit MHz MHz MHz MHz MHz % UI ps MHz MHz MHz MHz MHz MHz % ms ms

tOUTJITTER_PERIOD_DEDCLK (6)

10

300 30 300 30 650 75 650 75 50

ps mUI ps mUI ps mUI ps mUI ps ns

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Table 125. PLL Specifications for Cyclone IV Devices (Note 1), (2) (Part 2 of 2)Preliminary Symbol tCONFIGPLL fSCANCLK
Notes to Table 125:
(1) This table is applicable for general purpose PLLs and multipurpose PLLs. (2) You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead. (3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (4) The VCO frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. (5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less than 200 ps. (6) Peak-to-peak jitter with a probability level of 1012 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied. (7) With 100-MHz scanclk frequency.

Parameter Time required to reconfigure scan chains for PLLs scanclk frequency

Min

Typ 3.5 (7)

Max 100

Unit SCANCLK cycles MHz

Embedded Multiplier Specifications


Table 126 lists the embedded multiplier specifications for Cyclone IV devices.
Table 126. Embedded Multiplier Specifications for Cyclone IV Devices Preliminary Resources Used Mode Number of Multipliers 9 9-bit multiplier 18 18-bit multiplier 1 1 C6 340 287 C7, I7, A7 300 250 C8 260 200 C8L, I8L 240 185 C9L 175 135 MHz MHz Performance Unit

Memory Block Specifications


Table 127 lists the M9K memory block specifications for Cyclone IV devices.
Table 127. Memory Block Performance Specifications for Cyclone IV Devices Preliminary Resources Used Memory FIFO 256 36 M9K Block Single-port 256 36 Simple dual-port 256 36 CLK True dual port 512 18 single CLK Mode LEs 47 0 0 0 M9K Memory 1 1 1 1 C6 315 315 315 315 Performance Unit C7, I7, A7 274 274 274 274 C8 238 238 238 238 C8L, I8L 200 200 200 200 C9L 157 157 157 157 MHz MHz MHz MHz

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Configuration and JTAG Specifications


Table 128 lists the configuration mode specifications for Cyclone IV devices.
Table 128. Passive Configuration Mode Specifications for Cyclone IV Devices (Note 1) Programming Mode Passive Serial (PS) Fast Passive Parallel (FPP) (2)
Notes to Table 128:
(1) For more information about PS and FPP configuration timing parameters, refer to the Configuration and Remote System Upgrades in Cyclone IV Devices chapter. (2) FPP configuration mode supports all Cyclone IV E devices (except for E144 package devices) and EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 only. (3) VCCINT = 1.0 V is only supported for Cyclone IV E 1.0 V core voltage devices. (4) Cyclone IV E devices support 1.2 V VCCINT. Cyclone IV E 1.2 V core voltage devices support 133 MHz DCLK fMAX for EP4CE6, EP4CE10, EP4CE15, EP4CE22, EP4CE30, and EP4CE40 only.

VCCINT Voltage Level (V) 1.0 (3) 1.2 1.0 (3) 1.2 (4)

DCLK fMAX 66 133 66 100

Unit MHz MHz MHz MHz

Table 129 lists the active configuration mode specifications for Cyclone IV devices.
Table 129. Active Configuration Mode Specifications for Cyclone IV Devices Preliminary Programming Mode Active Parallel (AP) (1) Active Serial (AS)
Note to Table 129:
(1) AP configuration mode is only supported for Cyclone IV E devices.

DCLK Range 20 to 40 20 to 40

Unit MHz MHz

Table 130 lists the JTAG timing parameters and values for Cyclone IV devices.
Table 130. JTAG Timing Parameters for Cyclone IV Devices (Note 1) (Part 1 of 2)Preliminary Symbol tJCP tJCH tJCL tJPSU_TDI tJPSU_TMS tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX TCK clock period TCK clock high time TCK clock low time JTAG port setup time for TDI JTAG port setup time for TMS JTAG port hold time JTAG port clock to output (2), (3) JTAG port high impedance to valid output (2), (3) JTAG port valid output to high impedance (2), (3) Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Parameter Min 40 19 19 1 3 10 5 10 Max 15 15 15 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

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Table 130. JTAG Timing Parameters for Cyclone IV Devices (Note 1) (Part 2 of 2)Preliminary Symbol tJSXZ Parameter Update register valid output to high impedance Min Max 25 Unit ns

Notes to Table 130:


(1) For more information about JTAG waveforms, refer to JTAG Waveform in Glossary on page 138. (2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns. (3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 18 ns.

Periphery Performance
This section describes periphery performance, including high-speed I/O and external memory interface. I/O performance supports several system interfaces, such as the high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load. f For more information about the supported maximum clock rate, device and pin planning, IP implementation, and device termination, refer to Section III: System Performance Specifications of the External Memory Interfaces Handbook. Actual achievable frequency depends on design- and system-specific factors. Perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

High-Speed I/O Specifications


Table 131 through Table 136 list the high-speed I/O timing for Cyclone IV devices. For definitions of high-speed timing specifications, refer to Glossary on page 138.
Table 131. RSDS Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (2), (4) (Part 1 of 2)Preliminary C6 Symbol Modes Min 10 8 fHSCLK (input clock frequency) 7 4 2 1 10 10 10 10 10 10 Typ Max Min 180 180 180 180 180 360 10 10 10 10 10 10 Typ Max 155.5 155.5 155.5 155.5 155.5 311 Min 10 10 10 10 10 10 Typ Max 155.5 155.5 155.5 155.5 155.5 311 Min 10 10 10 10 10 10 Typ Max 155.5 155.5 155.5 155.5 155.5 311 Min 10 10 10 10 10 10 Typ Max 132.5 132.5 132.5 132.5 132.5 265 MHz MHz MHz MHz MHz MHz C7, I7 C8, A7 C8L, I8L C9L Unit

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Table 131. RSDS Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (2), (4) (Part 2 of 2)Preliminary C6 Symbol Modes Min 10 8 Device operation in Mbps 7 4 2 1 tDUTY Transmitter channel-tochannel skew (TCCS) Output jitter (peak to peak) tRISE tFALL tLOCK (3)
Notes to Table 131:
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter. (2) Cyclone IV E devicestrue RSDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated RSDS transmitter is supported at the output pin of all I/O Banks. Cyclone IV GX devicestrue RSDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated RSDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9. (3) tLOCK is the time required for the PLL to lock from the end-of-device configuration. (4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

C7, I7 Max Min 360 360 360 360 360 360 55 100 80 70 40 20 10 45 Typ Max 311 311 311 311 311 311 55 Min 100 80 70 40 20 10 45

C8, A7 Typ Max 311 311 311 311 311 311 55 Min 100 80 70 40 20 10 45

C8L, I8L Typ Max 311 311 311 311 311 311 55 Min 100 80 70 40 20 10 45

C9L Unit Typ Max 265 265 265 265 265 265 55 Mbps Mbps Mbps Mbps Mbps Mbps %

Typ

100 80 70 40 20 10 45

200

200

200

200

200

ps

20 80%, CLOAD = 5 pF 20 80%, CLOAD = 5 pF

500 500

500 1

500 500

500 1

500 500

550 1

500 500

600 1

500 500

700 1

ps ps ps ms

Table 132. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (3) (Part 1 of 2) Preliminary C6 Symbol Modes Min 10 8 fHSCLK (input clock frequency) 7 4 2 1 10 10 10 10 10 10 Typ Max Min 85 85 85 85 85 170 10 10 10 10 10 10 Typ Max Min 85 85 85 85 85 170 10 10 10 10 10 10 Typ Max Min 85 85 85 85 85 170 10 10 10 10 10 10 Typ Max Min 85 85 85 85 85 170 10 10 10 10 10 10 Typ Max 72.5 72.5 72.5 72.5 72.5 145 MHz MHz MHz MHz MHz MHz C7, I7 C8, A7 C8L, I8L C9L Unit

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Table 132. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (3) (Part 2 of 2) Preliminary C6 Symbol Modes Min 10 8 Device operation in Mbps 7 4 2 1 tDUTY TCCS Output jitter (peak to peak) tRISE tFALL tLOCK (2)
Notes to Table 132:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks of Cyclone IV E devices and I/O Banks 3, 4, 5, 6, 7, 8, and 9 of Cyclone IV GX devices. (2) tLOCK is the time required for the PLL to lock from the end-of-device configuration. (3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

C7, I7 Max Min 170 170 170 170 170 170 55 200 500 1 100 80 70 40 20 10 45 Typ 500 500 Max Min 170 170 170 170 170 170 55 200 500 1 100 80 70 40 20 10 45

C8, A7 Typ 500 500 Max Min 170 170 170 170 170 170 55 200 550 1 100 80 70 40 20 10 45

C8L, I8L Typ 500 500 Max Min 170 170 170 170 170 170 55 200 600 1 100 80 70 40 20 10 45

C9L Unit Typ 500 500 Max 145 145 145 145 145 145 55 200 700 1 Mbps Mbps Mbps Mbps Mbps Mbps % ps ps ps ps ms

Typ 500 500

100 80 70 40 20 10 45

20 80%, CLOAD = 5 pF 20 80%, CLOAD = 5 pF

Table 133. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (2), (4) (Part 1 of 2) Preliminary C6 Symbol Modes Min 10 8 fHSCLK (input clock frequency) 7 4 2 1 10 8 Device operation in Mbps 7 4 2 1 10 10 10 10 10 10 100 80 70 40 20 10 Typ Max Min 200 200 200 200 200 400 400 400 400 400 400 400 10 10 10 10 10 10 100 80 70 40 20 10 Typ Max 155.5 155.5 155.5 155.5 155.5 311 311 311 311 311 311 311 Min 10 10 10 10 10 10 100 80 70 40 20 10 Typ Max 155.5 155.5 155.5 155.5 155.5 311 311 311 311 311 311 311 Min 10 10 10 10 10 10 100 80 70 40 20 10 Typ Max 155.5 155.5 155.5 155.5 155.5 311 311 311 311 311 311 311 C7, I7 C8, A7 C8L, I8L
Mi n

C9L Unit
Typ Max

10 10 10 10 10 10 100 80 70 40 20 10

132.5 132.5 132.5 132.5 132.5 265 265 265 265 265 265 265

MHz MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps

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Table 133. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (2), (4) (Part 2 of 2) Preliminary C6 Symbol tDUTY TCCS Output jitter (peak to peak) tRISE tFALL tLOCK (3)
Notes to Table 133:
(1) Applicable for true and emulated mini-LVDS transmitter. (2) Cyclone IV Etrue mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at the output pin of all I/O banks. Cyclone IV GXtrue mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9. (3) tLOCK is the time required for the PLL to lock from the end-of-device configuration. (4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

C7, I7 Max Min 55 200 500 1 45 Typ 500 500 Max 55 200 500 1 Min 45

C8, A7 Typ 500 500 Max 55 200 550 1 Min 45

C8L, I8L Typ 500 500 Max 55 200 600 1


Mi n

C9L Unit
Typ Max

Modes Min 20 80%, CLOAD = 5 pF 20 80%, CLOAD = 5 pF 45 Typ 500 500

45

500 500

55 200 700 1

% ps ps ps ps ms

Table 134. True LVDS Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (3) (Part 1 of 2) Preliminary C6 Symbol Modes Min 10 8 fHSCLK (input clock frequency) 7 4 2 1 10 8 HSIODR 7 4 2 1 tDUTY TCCS Output jitter (peak to peak) 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 420 420 420 420 420 420 840 840 840 840 840 420 55 200 500 Min 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 370 370 370 370 370 402.5 740 740 740 740 740 402.5 55 200 500 Min 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 320 320 320 320 320 402.5 640 640 640 640 640 402.5 55 200 550 Min 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 320 320 320 320 320 362 640 640 640 640 640 362 55 200 600 Min 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 250 250 250 250 250 265 500 500 500 500 500 265 55 200 700 MHz MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps % ps ps C7, I7 C8, A7 C8L, I8L C9L Unit

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Table 134. True LVDS Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (3) (Part 2 of 2) Preliminary C6 Symbol tLOCK (2) Modes Min Max 1 Min Max 1 Min Max 1 Min Max 1 Min Max 1 ms C7, I7 C8, A7 C8L, I8L C9L Unit

Notes to Table 134:


(1) Cyclone IV Etrue LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Cyclone IV GXtrue LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. (2) tLOCK is the time required for the PLL to lock from the end-of-device configuration. (3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

Table 135. Emulated LVDS Transmitter Timing Specifications for Cyclone IV Devices (Note 1), (3) Preliminary C6 Symbol Modes Min 10 8 fHSCLK (input clock frequency) 7 4 2 1 10 8 HSIODR 7 4 2 1 tDUTY TCCS Output jitter (peak to peak) tLOCK (2) 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 320 320 320 320 320 402.5 640 640 640 640 640 402.5 55 200 500 1 Min 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 320 320 320 320 320 402.5 640 640 640 640 640 402.5 55 200 500 1 Min 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 275 275 275 275 275 402.5 550 550 550 550 550 402.5 55 200 550 1 Min 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 275 275 275 275 275 362 550 550 550 550 550 362 55 200 600 1 Min 10 10 10 10 10 10 100 80 70 40 20 10 45 Max 250 250 250 250 250 265 500 500 500 500 500 265 55 200 700 1 MHz MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps % ps ps ms C7, I7 C8, A7 C8L, I8L C9L Unit

Notes to Table 135:


(1) Cyclone IV Eemulated LVDS transmitter is supported at the output pin of all I/O Banks. Cyclone IV GXemulated LVDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9. (2) tLOCK is the time required for the PLL to lock from the end-of-device configuration. (3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

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Table 136. LVDS Receiver Timing Specifications for Cyclone IV Devices (Note 1), (3) Preliminary C6 Symbol Modes Min 10 8 fHSCLK (input clock frequency) 7 4 2 1 10 8 HSIODR 7 4 2 1 SW Input jitter tolerance tLOCK (2) 10 10 10 10 10 10 100 80 70 40 20 10 Max 437.5 437.5 437.5 437.5 437.5 437.5 875 875 875 875 875 437.5 400 500 1 Min 10 10 10 10 10 10 100 80 70 40 20 10 Max 370 370 370 370 370 402.5 740 740 740 740 740 402.5 400 500 1 Min 10 10 10 10 10 10 100 80 70 40 20 10 Max 320 320 320 320 320 402.5 640 640 640 640 640 402.5 400 550 1 Min 10 10 10 10 10 10 100 80 70 40 20 10 Max 320 320 320 320 320 362 640 640 640 640 640 362 550 600 1 Min 10 10 10 10 10 10 100 80 70 40 20 10 Max 250 250 250 250 250 265 500 500 500 500 500 265 640 700 1 MHz MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps ps ps ms C7, I7 C8, A7 C8L, I8L C9L Unit

Notes to Table 136:


(1) Cyclone IV ELVDS receiver is supported at all I/O Banks. Cyclone IV GXLVDS receiver is supported at I/O Banks 3, 4, 5, 6, 7, 8, and 9. (2) tLOCK is the time required for the PLL to lock from the end-of-device configuration. (3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

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External Memory Interface Specifications


The external memory interfaces for Cyclone IV devices are auto-calibrating and easy to implement. f For more information about the supported maximum clock rate, device and pin planning, IP implementation, and device termination, refer to Section III: System Performance Specifications of the External Memory Interface Handbook. Table 137 lists the memory output clock jitter specifications for Cyclone IV devices.
Table 137. Memory Output Clock Jitter Specifications for Cyclone IV Devices (Note 1), (2) Preliminary Parameter Clock period jitter Cycle-to-cycle period jitter Duty cycle jitter
Notes to Table 137:
(1) Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard. (2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global clock (GCLK) network.

Symbol tJIT(per) tJIT(cc) tJIT(duty)

Min 125 200 150

Max 125 200 150

Unit ps ps ps

Duty Cycle Distortion Specifications


Table 138 lists the worst case duty cycle distortion for Cyclone IV devices.
Table 138. Duty Cycle Distortion on Cyclone IV Devices I/O Pins (Note 1), (2), (3)Preliminary C6 Symbol Min Output Duty Cycle
Notes to Table 138:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general purpose I/O pins. (2) Cyclone IV devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current strength. (3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

C7, I7 Max 55 Min 45 Max 55

C8, I8L, A7 Min 45 Max 55 Min 45

C9L Unit Max 55 %

45

OCT Calibration Timing Specification


Table 139 lists the duration of calibration for series OCT with calibration at device power-up for Cyclone IV devices.
Table 139. Timing Specification for Series OCT with Calibration at Device Power-Up for Cyclone IV Devices (Note 1)Preliminary Symbol tOCTCAL
Note to Table 139:
(1) OCT calibration takes place after device configuration and before entering user mode.

Description Duration of series OCT with calibration at device power-up

Maximum

Units s

20

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IOE Programmable Delay


Table 140 and Table 141 list the IOE programmable delay for Cyclone IV E 1.0 V core voltage devices.
Table 140. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices (Note 1), (2) Preliminary Max Offset Parameter Paths Affected Number of Setting 7 8 2 Min Offset Fast Corner C8L Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Input delay from dual-purpose clock pin to fan-out destinations
Notes to Table 140:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Slow Corner C8L 3.387 3.341 1.111 C9L 4.017 4.252 1.377 I8L 3.411 3.367 1.124

Unit

I8L 1.924 1.875 0.631

Pad to I/O dataout to core Pad to I/O input register I/O output register to pad Pad to global clock network

0 0 0

2.054 2.010 0.641

ns ns ns

12

0.971

0.931

1.684

2.298

1.684

ns

Table 141. IOE Programmable Delay on Row Pins for Cyclone IV E 1.0 V Core Voltage Devices (Note 1), (2)Preliminary Max Offset Parameter Paths Affected Number of Setting 7 8 2 Min Offset Fast Corner C8L Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Input delay from dual-purpose clock pin to fan-out destinations
Notes to Table 141:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Slow Corner C8L 3.389 3.420 1.160 C9L 4.146 4.374 1.420 I8L 3.412 3.441 1.168

Unit

I8L 1.921 1.919 0.623

Pad to I/O dataout to core Pad to I/O input register I/O output register to pad Pad to global clock network

0 0 0

2.057 2.059 0.670

ns ns ns

12

0.960

0.919

1.656

2.258

1.656

ns

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Table 142 and Table 143 list the IOE programmable delay for Cyclone IV E 1.2 V core voltage devices.
Table 142. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices (Note 1), (2) Preliminary Max Offset Parameter Paths Affected Pad to I/O dataout to core Pad to I/O input register I/O output register to pad Pad to global clock network Number of Setting Min Offset C6 Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Input delay from dual-purpose clock pin to fan-out destinations
Notes to Table 142:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Fast Corner I7 A7 C6 C7

Slow Corner C8 I7 A7 2.508

Unit

1.314

1.211 1.211 2.177

2.340

2.433 2.388

ns

1.307

1.203 1.203

2.19

2.387

2.540 2.430

2.545

ns

0.437

0.402 0.402 0.747

0.820

0.880 0.834

0.873

ns

12

0.693

0.665 0.665 1.200

1.379

1.532 1.393

1.441

ns

Table 143. IOE Programmable Delay on Row Pins for Cyclone IV E 1.2 V Core Voltage Devices (Note 1), (2)Preliminary Max Offset Parameter Paths Affected Pad to I/O dataout to core Pad to I/O input register I/O output register to pad Pad to global clock network Number of Setting Min Offset C6 Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Input delay from dual-purpose clock pin to fan-out destinations
Notes to Table 143:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Fast Corner I7 A7 C6 C7

Slow Corner C8 I7 A7 2.548

Unit

1.314

1.209 1.209 2.201

2.386

2.510 2.429

ns

1.312

1.207 1.207 2.202

2.402

2.558 2.447

2.557

ns

0.458

0.419 0.419 0.783

0.861

0.924 0.875

0.915

ns

12

0.686

0.657 0.657 1.185

1.360

1.506 1.376

1.422

ns

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Table 144 and Table 145 list the IOE programmable delay for Cyclone IV GX devices.
Table 144. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices (Note 1), (2)Preliminary Max Offset Parameter Paths Affected Pad to I/O dataout to core Pad to I/O input register I/O output register to pad Pad to global clock network Number of Settings Min Offset Fast Corner C6 Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Input delay from dual-purpose clock pin to fan-out destinations
Notes to Table 144:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Slow Corner C6 2.184 C7 2.336 C8 2.451 I7 2.387

Unit

I7 1.209

1.313

ns

1.312

1.208

2.200

2.399

2.554

2.446

ns

0.438

0.404

0.751

0.825

0.886

0.839

ns

12

0.713

0.682

1.228

1.41

1.566

1.424

ns

Table 145. IOE Programmable Delay on Row Pins for Cyclone IV GX Devices (Note 1), (2) Preliminary Max Offset Parameter Paths Affected Pad to I/O dataout to core Pad to I/O input register I/O output register to pad Number of Settings Min Offset Fast Corner C6 Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin 7 0 1.314 I7 1.210 C6 2.209 Slow Corner C7 2.398 C8 2.526 I7 2.443 ns Unit

1.313

1.208

2.205

2.406

2.563

2.450

ns

0.461

0.421

0.789

0.869

0.933

0.884

ns

Input delay from Pad to global dual-purpose clock pin clock network to fan-out destinations
Notes to Table 145:

12

0.712

0.682

1.225

1.407

1.562

1.421

ns

(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software

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I/O Timing
Use the following methods to determine I/O timing:

the Excel-based I/O Timing the Quartus II timing analyzer

The Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get a timing budget estimation as part of the link timing analysis. The Quartus II timing analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after place-and-route is complete. f The Excel-based I/O Timing spreadsheet is downloadable from Cyclone IV Devices Literature website.

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Glossary
Table 146 lists the glossary for this chapter.
Table 146. Glossary (Part 1 of 5) Letter A B C D E F G H fHSCLK GCLK GCLK PLL HSIODR Term Input pin directly to Global Clock network. Input pin to Global Clock network through the PLL. High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI). Definitions High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.

Input Waveforms for the SSTL Differential I/O Standard

VIH VSWING VREF VIL

TMS

TDI t JCP t JCH TCK t JCL t JPSU_TDI t JPSU_TMS

t JPH

JTAG Waveform
tJPZX TDO tJSSU Signal to be Captured Signal to be Driven t JSH t JPCO t JPXZ

tJSZX

t JSCO

t JSXZ

K L M N O

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Table 146. Glossary (Part 2 of 5) Letter Term Definitions The following highlights the PLL specification parameters:
Switchover
CLK CLKOUT Pins

fOUT _EXT

fIN
Core Clock

fINPFD
PFD CP LF VCO fVCO

PLL Block

Counters C0..C4

fOUT

GCLK

Phase tap M

Key Reconfigurable in User Mode

Q RL

Receiver differential input discrete resistor (external to Cyclone IV devices). Receiver input waveform for LVDS and LVPECL differential standards:
Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground

Receiver Input Waveform

Differential Waveform (Mathematical Function of Positive & Negative Channel)

VID 0V VID p -n

Receiver input skew margin (RSKM)

High-speed I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI SW TCCS) / 2.

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Table 146. Glossary (Part 3 of 5) Letter Term Definitions

VCCIO
VOH

VIH (AC )

VIH(DC) VREF
Single-ended voltagereferenced I/O Standard
VIL(DC) VIL(AC ) VOL

VSS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing.

SW (Sampling Window) tC Channel-tochannel-skew (TCCS) tcin tCO tcout tDUTY T tFALL tH Timing Unit Interval (TUI) tINJITTER tOUTJITTER_DEDCLK tOUTJITTER_IO tpllcin tpllcout

High-speed I/O block: The period of time during which the data must be valid to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window. High-speed receiver and transmitter input and output clock period. High-speed I/O block: The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. Delay from the clock pad to the I/O input register. Delay from the clock pad to the I/O output. Delay from the clock pad to the I/O output register. High-speed I/O block: Duty cycle on high-speed transmitter output clock. Signal high-to-low transition time (8020%). Input register hold time. High-speed I/O block: The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w). Period jitter on the PLL clock input. Period jitter on the dedicated clock output driven by a PLL. Period jitter on the general purpose I/O driven by a PLL. Delay from the PLL inclk pad to the I/O input register. Delay from the PLL inclk pad to the I/O output register.

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Table 146. Glossary (Part 4 of 5) Letter Term Definitions Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O Standards:
Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL Vos

Transmitter Output Waveform

Ground

Differential Waveform (Mathematical Function of Positive & Negative Channel)

VOD 0V VOD p -n

tRISE tSU U

Signal low-to-high transition time (2080%). Input register setup time.

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Table 146. Glossary (Part 5 of 5) Letter VCM(DC) VDIF(AC) VDIF(DC) VICM VID VIH VIH(AC) VIH(DC) VIL VIL (AC) VIL (DC) VIN VOCM V VOD VOH VOL VOS VOX (AC) VREF VREF (AC) VREF (DC) VSWING (AC) VSWING (DC) VTT VX (AC) W X Y Z Term DC common mode input voltage. AC differential input voltage: The minimum AC input differential voltage required for switching. DC differential input voltage: The minimum DC input differential voltage required for switching. Input common mode voltage: The common mode of the differential signal at the receiver. Input differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. Voltage input high: The minimum positive voltage applied to the input that is accepted by the device as a logic high. High-level AC input voltage. High-level DC input voltage. Voltage input low: The maximum positive voltage applied to the input that is accepted by the device as a logic low. Low-level AC input voltage. Low-level DC input voltage. DC input voltage. Output common mode voltage: The common mode of the differential signal at the transmitter. Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. VOD = VOH VOL. Voltage output high: The maximum positive voltage from an output that the device considers is accepted as the minimum positive high level. Voltage output low: The maximum positive voltage from an output that the device considers is accepted as the maximum positive low level. Output offset voltage: VOS = (VOH + VOL) / 2. AC differential output cross point voltage: the voltage at which the differential output signals must cross. Reference voltage for the SSTL and HSTL I/O standards. AC input reference voltage for the SSTL and HSTL I/O standards. VREF(AC) = VREF(DC) + noise. The peak-to-peak AC noise on VREF must not exceed 2% of VREF(DC). DC input reference voltage for the SSTL and HSTL I/O standards. AC differential input voltage: AC input differential voltage required for switching. For the SSTL differential I/O standard, refer to Input Waveforms. DC differential input voltage: DC input differential voltage required for switching. For the SSTL differential I/O standard, refer to Input Waveforms. Termination voltage for the SSTL and HSTL I/O standards. AC differential input cross point voltage: The voltage at which the differential input signals must cross. Definitions

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Document Revision History


Table 147 lists the revision history for this chapter.
Table 147. Document Revision History Date Version Changes Made Updated for the Quartus II software version 10.0 release:

Updated Table 13, Table 14, Table 121, Table 125, Table 128, Table 130, Table 140, Table 141, Table 142, Table 143, Table 144, and Table 145. Updated Figure 12 and Figure 13. Removed SW Requirement and TCCS for Cyclone IV Devices tables. Minor text edits. Updated the Operating Conditions and PLL Specifications sections. Updated Table 11, Table 18, Table 19, Table 121, Table 126, Table 127, Table 131, Table 132, Table 133, Table 134, Table 135, Table 136, Table 137, Table 138, Table 140, Table 142, and Table 143. Added Table 15 to include ESD for Cyclone IV devices GPIOs and HSSI I/Os. Added Table 144 and Table 145 to include IOE programmable delay for Cyclone IV E 1.2 V core voltage devices. Minor text edits. Updated Table 13 through Table 144 to include information for Cyclone IV E devices and Cyclone IV GX devices for Quartus II software version 9.1 SP1 release. Minor text edits.

July 2010

1.3

Updated to include automotive devices:


March 2010

1.2

February 2010 November 2009

1.1

1.0

Initial release.

July 2010

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Chapter 1: Cyclone IV Device Datasheet Document Revision History

Cyclone IV Device Handbook, Volume 3

July 2010 Altera Corporation