# EE3102 LAB REPORT EXP#1 FEB

2007
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Feedback Amplifiers
Matt xxxxx
Student ID : xxxxxxx
1/16/07 – 2/26/07
Abstract:
Experiment one dealt with feedback amplifiers and the four negative
feedback topologies associated with them. We investigated the
frequency response of the amplifiers using these feedback topologies
and addressed the issues associated with feedback stability. Then
additionally, positive feedback was employed to create a sinusoidal
oscillator.
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EE3102 LAB REPORT EXP#1 FEB
2007
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Introduction:
Feedback in circuit analysis is one of the most important concepts in electrical engineering, whether
positive or negative. It can be used to create a wide variety of circuits, from amplifiers to oscillators. In
this experiment we used the concept of feedback to investigate the frequency response of the four negative
feedback topologies, as well as a positive feedback application, the Wein Bridge. We observed for each
topology, the behavior of the circuit as it relates to various frequency and load changes. Additionally, we
used many circuit concepts to study each topology in detail and to observe its effects given external
changes.
Experiment
Open Loop Voltage Gain
The first section of the experiment asked us to determine and record the open loop voltage gain for three
different 741 Op Amps. To do so we constructed the circuit shown in Figure 1.1.1 using the specified
values.
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EE3102 LAB REPORT EXP#1 FEB
2007
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-
+
U 2
L M 7 4 1
3
2
6
7 1
4 5
R 1
2 K
R 2
1 0 K
R 3
1 0 K
R 4
1 0
R 5
1 0 K
0
V 1
1 5 V d c 0
0
V 2
1 5 V d c
V 1 I n p u t
V o
Fig 1.1.1
Since the input voltage of the Op Amp is obtained by a simple voltage division we had to choose as
accurate resistance values as possible. As it turns out these resistance values were provided to us so
everyone would obtain as consistent of data as possible.
The procedure of finding the DC open loop voltage gain is identical for all three Op Amps. To do so we set
our input voltage
g
V to some arbitrary value, then proceeded to measure
1 i
V and
01
V . With these values
recorded we then changed the input voltage
g
V to a different voltage level and proceeded to find
2 i
V and
2 o
V . Using these values we were then able to able to calculate the DC open loop voltage gain using the
following formula.
01 2
1 2
*1000
o
v
i i
V V
A
V V
| `
=
÷

. ,
The collected values and calculations for the three Op Amps using the procedure outlined above are shown
below.
For Op Amp 1:
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EE3102 LAB REPORT EXP#1 FEB
2007
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1
1
1.35
2.64
i
o
V V
V V
·
·
For
104
g
V mV ·
2
2
1.36
3.91
i
o
V V
V V
·
·
For
95
g
V mV ·
2.64 3.91
*1000
1.35 1.36
126000
v
v
A
A
+ | `
=
÷
+
. ,
=
For Op Amp 2:
1
1
1.34
4.14
i
o
V V
V V
·
·
For
106.2
g
V mV ·
2
2
1.35
5.08
i
o
V V
V V
·
·
For
1.21
g
V V ·
4.14 5.08
*1000
1.34 1.35
235000
v
v
A
A
+ | `
=
÷
+
. ,
=
For Op Amp 3:
1
1
1.26
3.87
i
o
V V
V V
·
·
For
87.3
g
V mV ·
2
2
1.26
4.89
i
o
V V
V V
·
·
For
1.092
g
V V ·
3.87 4.89
*1000
1.26 1.26
165000
v
v
A
A
+ | `
=
÷
+
. ,
=
From the analysis of the DC open loop voltage gain we are able to see that the gains for the three different
Op Amps were 126000, 235000, and 165000 respectively.
The Four Topologies
Section 1.2 Series/Shunt
The second section of the experiment asked us to design for a no-load voltage gain of 15 for the respective
Series/Shunt feedback circuit shown in figure 1.2.1. We were then to measure the midband voltage gain for
various resistive loads. With this completed we determined the low frequency small-signal input resistance
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EE3102 LAB REPORT EXP#1 FEB
2007
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and found the dominant pole for the sinusoidal steady state response. Finally we determined the location of
the dominant pole in the open loop response of the Op Amp itself.
-
+
U 1
U A 7 4 1
3
2
6
7 1
4 5
R 1
1 4 K
R 2
1 K
R 3
R
R 4
L o a d
0
0
0
V 2
1 5 V d c
V 3
1 5 V d c
0
0
V 2 V 1
V o
V 4
1 V a c
0 V d c
Fig 1.2.1
In order to determine the necessary values of the resistors to achieve a gain of 15 we used the following
two port network equivalent shown in figure 1.2.2.
R 1
R
R 2
R
+ +
- -
V 1
I 2 I 1
V 2
Fig 1.2.2
Proceeding we know the gain for a series/shunt amplifier is:
1
o
f
i
f
V
A
V
A
A

·
·
+
Here we assumed 1 Aþ >>
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EE3102 LAB REPORT EXP#1 FEB
2007
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Therefore
1
f
A
þ
·
,
Where
1
15
þ
·
Solving for beta yields:
1
0.06667
15
þ · ·
Now using H parameters for our two port circuit we were able to determine the resistor values as follows.
2 2
12
1 2
6.667*10
R
h
R R
þ

· · ·
+
Choosing
2
1 R k · O arbitrarily and solving for
1
R yielded
1
14.015 R k · O.
With the circuit design completed and the circuit built we were able to determine the voltage gain as a
0 0.505 7.69 15.168
10 0.502 0.2 0.409
50 0.499 1.036 2.076
100 0.498 2.06 4.37
500 0.487 7.45 15.29
1000 0.494 7.58 15.35
10000 0.488 7.46 15.413
100000 0.488 7.46 15.415
1000000 0.494 7.56 15.3
Fig 1.2.3
A plot of Gain vs. Load Resistance is shown below.
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EE3102 LAB REPORT EXP#1 FEB
2007
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0
2
4
6
8
10
12
14
16
18
1 10 100 1000 10000 100000 1000000
Gain
Series1
Fig 1.2.4
Next we found the low frequency small signal input resistance and the location of the dominant pole of the
To determine this we placed a 100k ohm resister between the input and V+ so we could determine the
current flowing into the terminal as shown in figure 1.2.5.
-
+
U 1
U A 7 4 1
3
2
6
7 1
4 5
R 1
1 4 K
R 2
1 K
R 3
1 0 0 k
0
0
V 2
1 5 V d c
V 3
1 5 V d c
0
0
V 2 V 1
V 4
1 V a c
0 V d c
V o
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EE3102 LAB REPORT EXP#1 FEB
2007
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Fig 1.2.5
In order to determine the current flowing into V+ we measured the voltage values at V1, V2 and then used
Ohm’s Law to compute the current.
1
2
1
0.98
V V
V V
·
·
Then using Ohm’s Law.
1 2
1 0.98
100
V V
I
R k

· ·
200 I nA ·
With this current found we could then calculate
if
R
.
2
0.98
280
4.9
s
if
s
if
if
V V
R
I I
V
R
nA
R M
· ·
·
· O
To determine the dominant pole we needed to find the closed loop gain for the circuit. We accomplished
this by collecting following data:
Gain vs Frequency
Freq (Hz) Vi (V) Vo (V) Gain
500 0.5 6.94 13.88
1000 0.5 7 14.12
2000 0.5 7.7 15.3
5000 0.5 8 16
10000 0.5 7.8 15.6
15000 0.5 7.8 15.6
20000 0.5 7.7 15.4
25000 0.48 7.3 15.2
30000 0.48 7 14.58
40000 0.48 6.6 13.75
50000 0.48 5.8 12.08
57000 0.48 5 10.35
60000 0.48 4.5 10.41
70000 0.48 5.5 9.375
Fig 1.2.6
A plot of Gain vs. Frequency is shown below.
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EE3102 LAB REPORT EXP#1 FEB
2007
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0
2
4
6
8
10
12
14
16
18
100 1000 10000 100000
Gain
Frequency (Hz)
Gain vs. Frequency
Series1
Fig 1.2.7
Using this data we are able to see that our midband gain is about 15.3V/V. Using this we could then
calculate our closed loop gain.
15.3*.707 10.8
CL
A · ·
This can be seen to occur at about 57 KHz.
Thus
3
57
dB
F KHz ·
With this information we were than able to calculate our dominant pole location.
3
3
* *
*
CL dB D OL
CL dB
D
OL
A F F A
A F
F
A
·
·
Since Op Amp 1 was used for this experiment,
CL
A was equal to 126000.
10.35*57
126000
4.68
D
D
K
F
F
·
·
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EE3102 LAB REPORT EXP#1 FEB
2007
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Section 1.3 Shunt/Series
The third section of the experiment asked us to design for a midband short circuit gain of 100 for the
respective Series/Shunt feedback circuit shown in figure 1.3.1. Using this circuit we were to measure the
midband gain for various resistive loads.
-
+
U 1
U A 7 4 1
3
2
6
7 1
4 5
R 1
L o a d
R 2
1 0 1
0
0
V 2
1 5 V d c
V 3
1 5 V d c
0
0
V A
V 2
V 4
1 V a c
0 V d c
0
R 1
1 0 K
V 2 V 1
V B
R 4
1 M
Fig 1.3.1
In this circuit we approximated the necessary current source as a voltage source in series with a large
resistor. We used a 1M ohm resistor that was chosen arbitrarily.
Once again we used two port circuit analyses to determine the necessary resistor values to obtain a midband
short circuit gain of 100 (See figure 1.3.1 for the two port network.).
R 2
R
R 1
R
+ +
- -
V 1 V 2
I 2 I 1
Fig 1.3.2
Proceeding we know the gain for a Shunt/Series amplifier is:
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EE3102 LAB REPORT EXP#1 FEB
2007
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o
f
s
I
A
I
·
1
f
A
A

·
+
Here we assumed 1 Aþ >>
Therefore
1
f
A
þ
·
,
Where
1
100
þ
·
Solving for beta yields:
1
0.01
100
þ · ·
Now using G parameters for our two port circuit we were able to determine the resistor values as follows.
2
12
1 2
0.01
R
g
R R
þ

· · ·
+
Choosing
1
10 R k · O arbitrarily and solving for
2
R yielded
2
101.01 R · O.
With the circuit design completed and the circuit built we were able to determine the current gain as a
function of various resistive loads as follows:
V1 (V) V2(mV) Va (mV) V (mV) Rl (Ohms) I (uA) Io (uA) Gain
2.31 300 300 300m 0 1.827 0 0
2.31 300 300 340m 220 1.827 181.8 99.5
2.31 300 300 410m 500 1.827 220 120.4
2.31 280 280 530m 1000 1.845 250 135.5
2.31 270 270 780m 2000 1.855 255 137.5
2.31 250 250 1.45 5100 1.872 235 125.6
2.31 250 250 2.52 10000 1.872 227 121.2
2.31 250 250 4.69 20000 1.872 222 118
2.5 220 220 19.1 100000 2.072 188.8 91.08
Fig 1.3.3
A plot of Current Gain vs. Load Resistance is shown below.
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EE3102 LAB REPORT EXP#1 FEB
2007
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0
20
40
60
80
100
120
140
160
0 220 500 1000 2000 5100 10000 20000 100000
Current Gain
Series1
Fig 1.3.4
Viewing the table and graph we are able to see that the gain is slightly lower for very low and high
frequency values. This is acceptable and follows closely with what is expected in circuit theory.
Section 1.4 Series/Series
The fourth section of the experiment asked us to design for a midband short circuit transconductance of
1ma/V for the respective Series/Series feedback circuit shown in figure 1.4.1 and to measure the midband
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EE3102 LAB REPORT EXP#1 FEB
2007
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-
+
U 1
U A 7 4 1
3
2
6
7 1
4 5
R 1
L o a d
R 2
1 K
R 3
R
0
0
V 2
1 5 V d c
V 3
1 5 V d c
0
0
V o
V 2 V 1
V 4
1 V a c
0 V d c
V l
Fig 1.4.1
Once again we used two port circuit analysis to determine the necessary resistor values to obtain a midband
short circuit transconductance of 1mA/V (See figure 1.4.2 for two port network.).
R 1
R
+ +
- -
V 1
I 2 I 1
V 2
Fig 1.4.2
Proceeding we know the gain for a shunt/series amplifier is:
s P N
o o f
o s o f
V V V
V I R
V V I R
· ·
·
· ·
Solving for Is
o
o
f
V
I
R
·
Now using Z parameters for our two port circuit we were able to determine the resistor values as follows.
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EE3102 LAB REPORT EXP#1 FEB
2007
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12
1
s
f
o
s s f
V
R
I
Z gm
V V R
· · · ·
,
1
1
1
1
f
f
gm
R
R k
m
· ·
· · O
With the circuit design completed and circuit built we were able to determine the transconductance as a
Vs (V) Vl (V) Vo (V) Rl (Ohms) Io (mA)
Gmf
(mA/V)
1 1.11 1.11 0 0 0
1 1.11 1.34 220 1.04 0.962
1.03 1.11 1.61 500 1 0.971
1 1.11 2.1 1000 0.99 0.99
1.02 1.11 3.1 2000 0.995 0.975
1.02 1.11 6.07 5100 0.973 0.954
1 1.11 11.3 10000 1.019 1.02
1.02 1.1 20.6 20000 9.75 0.952
0.3 0.325 22.2 100000 0.219 0.731
Fig 1.4.3
To determine Io and gmf we used the following.
o L
o
L
o
mf
s
V V
I
R
I
g
V

·
These values can be seen in figure 1.4.3.
A plot of Transconductance vs. Load Resistance is shown below.
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EE3102 LAB REPORT EXP#1 FEB
2007
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0
0.2
0.4
0.6
0.8
1
1.2
0 220 500 1000 2000 5100 10000 20000 100000
Transconductance
Resistance (Ohms)
Series1
Fig 1.4.4
Form the table and graph we are able to see that the gmf remained relatively constant until
L
R became
very large. ( 100 ) k = O .
Section 1.5 Shunt/Shunt
The fifth section of the experiment asked us to design for a midband open circuit gain of 100K for the
respective Shunt/Shunt feedback circuit shown in figure 1.5.1 and then to measure the midband
In this circuit we once again approximated the necessary current source as a voltage source in series with a
large resistor. We used a 1M ohm resistor that was chosen arbitrarily.
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EE3102 LAB REPORT EXP#1 FEB
2007
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-
+
U 1
U A 7 4 1
3
2
6
7 1
4 5
R 1
L o a d
0 0
V 2
1 5 V d c
V 3
1 5 V d c
0
0
V o
V 2
V 4
1 V a c
0 V d c
0
R 3
1 0 0 K
V n V 1
R 4
1 M
Fig 1.5.1
We then proceeded to determine the necessary value of
f
R
.
0
100
o
s
f
s
f
s
f
V
I
R
V
R
I
R k
·
·
· ·
With the circuit design completed and the circuit built we were able to determine the transresistance as a
function of various resistive loads as follows:
V1 (V) Vn (V) Vo (V) Is (A) Rl (Ohms) Rf (Ohms)
2.25 9m 0.2171 2u 0 96876.4
2.207 8.2m 0.2171 2u 10 98690.2
2.201 5m 0.2172 2u 50 98907.1
2.201 5m 0.2174 2u 100 98998.2
2.203 4m 0.2174 2u 1000 98863.1
2.2 2.1m 0.2174 2u 10000 98912.6
2.2 4m 0.2176 2u 100000 99089.3
Fig 1.5.2
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Here we calculated
s
I and R using the following. Where 1 R M · O.
1 n
s
V V
I
R

·
o
f
s
V
R
I
·
These values are then displayed in figure 1.5.2
A plot of Transresistance vs., Load Resistance is shown below.
95500
96000
96500
97000
97500
98000
98500
99000
99500
0 10 50 100 1000 10000 100000
Transresistance
Resistance (Ohms)
Series1
Fig 1.5.3
From the table and graph we are able to see that the transresistance vs. load remains relatively constant and
is indeed consistent with results form circuit theory.
Section 1.6 Frequency Response
The sixth section of the experiment asked us to take two Series/Shunt amplifiers and cascade to provide an
overall feedback to make the overall voltage gain about 15 at the midband. See figure 1.6.1.
This was very similar to the design process of section two only here we cascaded two Series/Shunt
amplifiers together. Here the specified gain of the individual amplifiers was to be 15. This meant that the
same resistance values we used for the Series/Shunt amplifier in part two could be used here as well.
Additionally, the overall gain was to also be 15. This meant that the same resistor values could be used for
the overall gain control as the individual stages. Thus, each stage of this amplifier was to have the same
gain.
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EE3102 LAB REPORT EXP#1 FEB
2007
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-
+
U 1
U A 7 4 1
3
2
6
7 1
4 5
-
+
U 2
U A 7 4 1
3
2
6
7 1
4 5
R 1
1 K
R 5
1 4 K
R 6
1 K
R 4
1 K
R 2
1 4 K
0
0
R 3
1 4 K
V 1
1 5 V d c
V 2
1 5 V d c
V 3
1 5 V d c
V 4
1 5 V d c
0 0
0 0
V o
V i
Fig 1.6.1
Once we had the circuit constructed we could then investigate the voltage gain vs. frequency relationship.
Gain vs Frequency
Frequency (Hz) Vi (V) Vo (V) Gain
1000 0.0455 0.72 15.82
5000 0.0461 0.732 15.87
10000 0.0461 0.73 15.83
25000 0.0471 0.729 15.47
50000 0.0477 0.745 15.62
100000 0.0488 0.837 17.15
125000 0.0495 0.89 17.98
125000 0.0498 0.904 18.15
140000 0.0499 0.981 19.66
160000 0.0512 1.09 21.29
170000 0.0518 1.189 22.99
180000 0.0518 1.308 25.25
190000 0.0527 1.423 27.6
200000 0.0533 1.428 26.79
210000 0.0535 1.376 25.72
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EE3102 LAB REPORT EXP#1 FEB
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220000 0.0539 1.31 24.3
240000 0.0529 1.17 22.12
260000 0.0525 1.029 19.6
280000 0.0504 0.91 18.05
300000 0.0492 0.8 16.26
320000 0.0482 0.705 14.62
340000 0.0471 0.613 13.01
400000 0.0445 0.415 9.33
500000 0.0425 0.239 5.63
Fig 1.6.2
A plot of Voltage Gain vs. Frequency is shown below.
0
5
10
15
20
25
30
1000 10000 100000 1000000
Voltage Gain
Frequency (Hz)
Voltage Gain Vs. Frequency
Series1
Fig 1.6.3
In addition to investigating the overall feedback of the amplifier we were also to determine the quality
factor for the circuit. This was done by determining the bandwidth and resonance frequencies and then
solving for Q.
109
(280 125 )
R
f
Q
Bw
k
Q
k k
·
·

1.2258 Q ·
The final part of this section asked us to observe the output, given a square wave input, as a function of
frequency. This was quite simple and the results were as expected. We observed that as frequency
increased the output transformed from a square wave into a sine wave.
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EE3102 LAB REPORT EXP#1 FEB
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Stability
The seventh section of the experiment asked us to place three Series/Shunt amplifiers in series and then to
provide an overall feedback to generate an overall midband voltage gain variable from 10 to 100. We were
to then investigate the stability of the amplifier as a function of the gain.
To accomplish this we had to make calculations similar to those in part seven of the experiment, only now
Here, once again, the gains of the individual stages remained the same as two.
We were told to design for a midband variable voltage gain from 10 to 100. To accomplish this we placed a
potentiometer in place of resistor R9 so we could adjust the feedback of the circuit and thus the gain. The
calculations for this were actually quite simple.
9
8 9
@ 10 0.1
0.1
f
A
R
R R
þ · ÷ ·
· ·
+
Letting
8
100 R K · O and solving for the necessary sized potentiometer yielded
9
10 R K · O
The resultant circuit design can be seen in figure 1.7.1.
-
+
U 1
U A 7 4 1
3
2
6
7 1
4 5
-
+
U 2
U A 7 4 1
3
2
6
7 1
4 5
R 1
1 K
R 4
1 K
R 2
1 4 K
0 0
R 3
1 4 K
V 1
1 5 V d c
V 2
1 5 V d c
V 3
1 5 V d c
V 4
1 5 V d c
0
0
0 0
V i
-
+
U 3
U A 7 4 1
3
2
6
7 1
4 5
V 5
1 5 V d c
V 6
1 5 V d c
R 7
R
R 8
1 0 0 K
R 9
1 K
R 1 0
1 4 K
0 0
0
V o
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EE3102 LAB REPORT EXP#1 FEB
2007
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Fig 1.7.1
The goal of this part of the experiment was to ultimately investigate the stability of the cascaded amplifiers.
When a square wave was inputted to the circuit the output was clearly unstable. It could be seen that the
output was not a perfect square wave and that continuous ringing was occurring. This instability was
indeed a problem and needed to be eliminated in order for the circuit to have any practical use.
Compensation
The eighth section of the experiment dealt with dominant pole compensation and asked us to design the
circuit to be stabile with a phase margin between 45 and 90 degrees.
Here we needed to determine where to place the dominant pole. To accomplish this we determined the
following values at resonance.
34 KHz, Av=29,
1
°
4 ·
Next we found the 45 degree phase margin and determined the same information as previous.
124.83 KHz, Av 7.9,
135
°
4 ·
Now using this information we could plug into the following equation and solve for the dominant pole
D
F .
1 2
20log
v v
D
f
A A
F
| `
·
÷
. ,
Plugging in the appropriate values and solving for
D
F yields.
124.83
29 7.9 20log
10.98
D
D
k
F
F Hz
| `
·
÷
. ,
· ·
With the dominant pole found we could then calculate our capacitor and resistor values necessary to give us
our dominant pole compensation.
1
2
D
F
RC r
·
Choosing uF C 7 . 4 · arbitrarily we can then solve for R.
O =
·
·
K R
R
C F
R
D
3
98 . 10 * 7 . 4 * 2
1
2
1
µ π
π
-21-
EE3102 LAB REPORT EXP#1 FEB
2007
___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
With the appropriate values determined we were then able to insert the new pole between Op Amps two
and three as shown in figure 1.8.1.
Fig 1.8.1
With the dominant pole compensation completed and inserted into the circuit we were able to determine the
bandwidth of our new compensated amplifier.
Gain & Phase vs Frequency
Frequency (Hz) Vi (mV) Vo (V) Gain
Phase
(degrees)
1 256 25.3 98.8 0
10 256 25.3 98.8 1
100 256 25.3 98.8 2
500 256 25.3 98.8 3
1000 256 25.3 98.8 6
2000 256 25.3 98.8 18
3000 256 25.3 98.8 22
5000 256 25.3 95.8 35
10000 256 22.1 86.31 58
15000 250 14.4 56.25 100
30000 250 8 31 133
-
+
U1
UA741
3
2
6
7 1
4 5 -
+
U2
UA741
3
2
6
7 1
4 5
R1
1K
R4
1K
R2
14K
0 0
R3
14K
V1
15Vdc
V2
15Vdc
V3
15Vdc
V4
15Vdc
0
0
0
0
Vi
-
+
U3
UA741
3
2
6
7 1
4 5
V5
15Vdc
V6
15Vdc
R7
R
R8
100K
R9
1K
R10
14K
0
0
0
Vo
R11
11
C1
4.7uF
0
-22-
EE3102 LAB REPORT EXP#1 FEB
2007
___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
Fig 1.8.2
Plots of Frequency vs. Gain and Phase Shift are shown below.
0
20
40
60
80
100
120
1 10 100 1000 10000 100000
Gain
Frequency (Hz)
Frequncy Vs. Gain
Series3
Fig 1.8.3
0
20
40
60
80
100
120
140
1 10 100 1000 10000 100000
Phi (Degrees)
Frequency (Hz)
Phase Shift
Series1
Fig 1.8.4
Viewing the graphs we can easily see that the amplifier with compensation was indeed stable while
maintaining good bandwidth.
-23-
EE3102 LAB REPORT EXP#1 FEB
2007
___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
Oscillators
The final circuit was to design and construct a 500 Hz Sinusoidal oscillator (see Figure 1.9.1). This was to
be powered by 15 volt supplies and have an output of 5V. With these design criteria in mind we designed
and built the following circuit:
Fig 1.9.1
To design for 500 Hz we made the following calculations.
1
500
2
f
RC π
· ·
Choosing C=10nF
1 1
2 2 500*20
R
fC n r r
· ·

O = k R 32
-24-
-
+
U1
UA741
3
2
6
7 1
4 5
10K
POT
D1
D2
C1
10nF
C2
10nF
R2 10K
R3
32K
R4
32K
Vo
0
0
V1
15Vdc
V2
15Vdc
0
0
EE3102 LAB REPORT EXP#1 FEB
2007
___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
Therefore the values used were as follows.
nF C C 10
2 1
· ·
O · · K R R 32
2 1
To provide the stabilization we added the two diodes in parallel with a 10K resistor. The last requirement
was to have an output amplitude of 5 V. This was achieved by placing a 10K potentiometer in the circuit as
shown in figure 1.9.1 to control the feedback and therefore the gain of the circuit. The potentiometer was
then adjusted until the circuit was operating at the desired 5 V.
The actual frequency of the Wein Bridge was not exactly 500 Hz, but rather 522 Hz. This was due largely
to the tolerances of the parts used and the inherent mismatches that resulted. This was the only flaw with
the Wein Bridge the circuit performed as expected producing a near perfect sine wave.

Conclusion:

Throughout this experiment we investigated various forms of feedback and its effects. We observed, that
all forms of negative feedback, were relatively unaffected by changes in load resistance. In other words the
gains for the different amplifiers remained constant. This can be seen through the various plots of Gain vs.
Load Resistance. Next we studied cascaded amplifiers. Here we observed gain peaking in a double
cascaded Series/Shunt amplifier and demonstrated that it has a very low quality factor of 1.2. Next we
studied the stability of triple cascaded Series/Shunt amplifiers. Here we observed that the amplifier was
highly unstable, thus requiring dominant pole compensation to stabilize the amplifier. Finally, we designed
and constructed a Wein Bridge sinusoidal oscillator. This was an application of positive feedback where as
all of the previous implementations had been negative feedback. Overall the concept of feedback for
differential amplifiers is crucial in designing many of today’s electronics. Without it many designs would
not be possible or would require far more complicated and expensive circuitry. Thus, this experiment
hereby demonstrated the functionality and effectiveness of the feedback network in circuit design.
-25-