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# Analysis and comparison of Full Adder Block in 180 nm Technology

INTRODUCTION: In this work main goal was to design and implement one of the most popular adder circuit (one bit full adder) known as MIRROR ADDER and compare its performance with an adder designed in complementary cmos logic. SIMPLE CMOS FULL ADDER: One way to implement full adder is to take the logic equation and translate them directly into complement cmos circuitry. Some logic manipulation was done to reduce the transistor count. It is advantageous to share some logic between the carry and sum generation sub-circuits until this does not slow down the carry generation process, which is the most critical path in adder circuit. Following is our reduced logic expressions =AB+BCin+ACin And S= ABCin+ (A+B+Cin)

## Figure: Implemented full adder circuit in CMOS logic

Some observation about the circuit: 1.The pmos transistor stacks are present in both sum and carry generation circuits. 2.The intrinsic load capacitance of the carry_out signal is large and it consist of two diffusion and 6 gate capacitances plus the wiring capacitance.So the signal propagation delay is not optimum for this adder circuit.

A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Cin 0 1 1 0 1 0 0 1

S 0 0 0 1 0 1 1 1

Co

Carry Status Delete Delete Propagate Propagate Propagate Propagate Generate/propagate Generate/propagate

Figure: TRUTH TABLE OF FULL ADDER Circuit has been designed by realizing the fact that SUM(S) and Cout are functions of some intermediate signals known as 1. GENERATE (G) 2. PROPAGATE (P) 3. DELETE (D) The logic expression for the above three signals are as bellows G=AB D= P=A XOR B Now using these above three intermediate signals SUM and Cout expression can be written as (G,P)=G+PCin S(G,P)=P XOR Cin.

Figure: FULL MIRROR ADDER Some observation about this circuit: 1. The transistors connected to the Cin are placed closest to the output. 2. Only the transistors in carry stage have to be optimized for speed. All the transistors in the sum side can be of minimum size. So effective load capacitance of the carry stage can be reduced to some extent.

## Delay and power consumption calculation of the above two circuits:

Name of the architecture. CMOS Full Adder Dynamic power consumption(after layout)( w) 4.6 Static power consumption(after layout)(pw) 53.45 Worst case delay(ps)