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Inter Integrated Circuit (I2C) Technical Data Sheet

Technical Data Sheet

Part Number:
Document Number: May 2011

T-CS-PE-0007-100
I-IPA01-0045-TDS Rev 14

Inter Integrated Circuit (I2C)


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Licensing
Licensing this product does not imply a right under the Philips I C Patents to make, use or sell any integrated circuit or other electronic device implementing the product. To implement this product in an integrated circuit or other electronic device, a patent licence must first be obtained from Philips Electronics N.V.
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Document No: I-IPA01-0045-TDS Rev 14, May 2011 2005-2011 Cadence Design Systems, Inc.

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I2C Technical Data Sheet

Inter Integrated Circuit (I2C)

Features
Uses the AMBA APB protocol, version 2.0 Uses I2C bus specification version 2.0 (100Khz and 400KHz) Programmable for both normal (100 kHz) and fast bus data rates (400 kHz) Programmable as either a master or slave interface Programmable to use normal or extended addressing Capable of clock synchronization and bus arbitration Fully programmable slave response address Optional reversible FIFO with parameterizable depth (same register array for receive and transmit) Slave monitor mode when set up as master Supports I2C bus hold for slow host service Supports combined format transfers both as master and slave Slave time out detection with programmable period Transfer status interrupts and flags System clock speed over 200 MHz (0.13 m technology)

Description
The I C module is a bus controller that can function as a master or slave in a multi-master, 2 2 two-wire serial I C bus. In master mode, the I C interface can transmit data to a slave and initiate a transfer to receive data from a slave.
Clock Enable Generator
2

Control Register APB I/F TX Data Register RX Data Register Status Register Interrupt Controller RX Shift Register Control FSM SCL/SDA Interface

When embedded as a master in a multi-master bus, the I2C performs arbitration for bus ownership and clock synchronization with other bus masters. This prevents any corruption of data when more than one master tries to transmit or receive data at the same time. Also, it can use both normal (7 bit) addressing or extended (10 bit) addressing modes. This option is programmable in master mode and automatic in slave mode by detecting a specific code in bits [7:3] of the first address byte. When configured in slave mode, the response address is fully programmable. General call addresses are not acknowledged.

Document No: I-IPA01-0045-TDS Rev 14, May 2011 2005-2011 Cadence Design Systems, Inc.

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I2C Technical Data Sheet A register type FIFO can be implemented in the design as an option. This FIFO is reversible to keep the gate count of the module low with the same FIFO used both for transmit and receive. It is accessed by the host through a single APB register. In master mode, the FIFO allows the host to load a request for multiple data bytes transfer 2 and receive notification when this request is serviced by the I C interface, or if the transfer is terminated prematurely due to error or time out. The host can determine the reasons and the outstanding amount of data by reading the interrupt status register and transfer size register. In slave mode, the FIFO allows for buffering the received data or storing transmit data in 2 advance in the FIFO to reduce the load on the host servicing the I C interface. The I C interface is capable of holding the I C bus by keeping the sclk line low until the host provides more data to allow transfer to continue, or until the host allows the transfer to be 2 terminated. If bus hold mode is not activated by the host, the I C interface terminates the transfer, if acting as master, or allows it to be terminated, if acting as a slave, after the amount of data provided by the host is transferred. In either master or slave mode, the I C interface is capable of detecting excessively long periods of the sclk signal being low on the bus which is signified by a maskable interrupt. The time out period is programmable by the host. When set up as master, the I C module can be driven in slave monitor mode. In this mode, an attempt is made to access a slave to check if that slave is ready to respond and perform a transfer. In this mode, when an address is sent to a slave, an interrupt is generated if the slave responds with ACK without any data to be transferred. If the slave does not respond 2 with ACK, the I C module waits for a back-off time before repeating to address the slave and continues to do this until the slave responds with ACK to its address. The I2C module has a single clock domain operating on a single clock edge.
2 2 2 2

Signal Interfaces
The I C has two sets of signals, one to deal with I/O and another to interface with the AMBA APB bus as detailed below.
n_p_reset pclk psel penable pwrite paddr[11:0] pwdata[15:0] prdata[15:0] i2c_irq
2

I2C I/F

sda_out sda_oen sda_input scl_out scl_oen scl_input

Interface and Bus Signal Descriptions


Signal Name n_p_reset pclk I/O I I Description Active low reset for entire block Peripheral bus clock, rising edge used throughout.

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I2C Technical Data Sheet psel I I I I I O O APB signal. Selects this specific APB interface for data transfer. Used along with penable to perform data transfers. APB signal. When set high indicates that data transfers are enabled. APB signal. When set high and psel is active, it indicates that 2 data is to be written to the I C interface. APB address bus of selected master APB write data APB read data Interrupt request to host. When active high indicates that the I C requires host intervention. Actual state of the external SCL signal Actual state of the external SDA signal Clock to be placed on external SCL signal. Output enable for the SCL output buffer Data to be placed on external SDA signal. Output enable for the SDA output buffer
2

penable pwrite

paddr[11:0 ] pwdata[15: 0] prdata[15: 0] i2c_irq

scl_input sda_input scl_out scl_oen sda_out sda_oen

I I O O O O

APB Timing Characteristics


Tclk pclk Tihnres n_p_reset Tispen penable psel paddr Tispw pwrite Tispwd pwdata Tohprd prdata Tovprd Tihpwd Tihpw Tispe l Tispa Tihpel Tihpa Tihpen Tisnre s

Parameter Tclk Clock period

Description

Min 5

Max DC

Unit ns

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I2C Technical Data Sheet Tihnres Tisnres Tihpen Tispen Tihpsel Tispsel Tihpa Tispa Tihpw Tispw Tihpwd Tispwd Tohprd Tovprd Note n_p_reset hold after pclk n_p_reset setup before pclk penable hold after pclk penable setup before pclk psel hold after pclk psel setup before pclk paddr hold after pclk paddr setup before pclk pwrite hold after pclk pwrite setup before pclk pwdata hold after pclk pwdata setup before pclk prdata hold after pclk prdata valid after pclk Timing achieved using trial layout with 0.13 m technology. N/A N/A 0 50 % 0 50 % 0 50 % 0 50 % 0 50 % 0 N/A N/A 30 % ns Tclk ns Tclk ns Tclk ns Tclk ns Tclk ns Tclk

Programming Interface
Register Map
The following registers can be configured to determine the functionality of the interface. Offset Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C R/W R/W RO R/W R/W RO R/W R/W R/W Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1F Control register Status register I2C address register I2C data register Interrupt status register Transfer size register Slave monitor pause register Time out register Function

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I2C Technical Data Sheet 0x20 0x24 0x28 RO WO WO 0x2FF 0x0 0x0 Interrupt mask register Interrupt enable register Interrupt disable register

Control Register
The main control register which defines in which mode the interface operates. Bit Func Bit Func 7 15 14 divisor_a 6 5 4 HOLD 13 12 11 divisor_b 3 ACKEN 2 NEA 1 MS 0 RW 10 9 8

CLR_FIFO SLVMON

Function
RW

Signal Name
read_write

Description
Direction of transfer: 1 - master receiver 0 - master transmitter. This bit is used in master mode only. Overall interface mode: 1 - master 0 - slave Addressing mode: 1 - normal (7-bit) address 0 - extended (10-bit) address. This bit is used in master mode only. Enable transmission of ACK when master-receiver: 1 acknowledge enabled, ACK transmitted 0 acknowledge disabled, NACK transmitted. This bit must always be set if FIFO is implemented. Hold I2C sclk low until host services the data resources or clears this bit. 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. This bit has the same meaning in both master and slave modes. Slave monitor mode. 1 - monitor mode. I2C master transmits slave address and terminate if ACK. Repeat if NACK. 2 0 - normal operation. I C master transmits slave address and transfers data if ACK. This bit is used in master mode only.

MS

master_slave

NEA

normal_extended

ACKEN

ackn_enabled

HOLD

hold_bus

SLVMO N

slave_monitor

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I2C Technical Data Sheet


CLR_FIF O clear_fifo This bit is implemented only if FIFO is implemented. Setting this bit to 1 automatically initializes the FIFO to all zeros and clears the transfer size register. This flag is used in both master and slave modes and is automatically cleared on the next APB clock after being set. Always read zero Divisor for stage A clock divider. Divides the input pclk frequency by divisor_a + 1. Divisor for stage B clock divider. Divides the output frequency from divisor_a by divisor_b + 1.

-divisor_a

Reserved

divisor_b

Status Register
Bit Func Bit 15 7 14 6 TXDV 13 5 RXDV 12 4 11 3 RXRW 10 2 9 1 8 BA 0

Func RXOVF

Functio n RXRW RXDV TXDV RXOV F BA

Signal Name Reserved RX read_write Receiver Data Valid Transmit Data Valid Receiver Overflow Always reads zero

Description

Indicates the mode of the transmission received from a master. Indicates that there is valid, new data to be read from the interface. Indicates that there is still a byte of data to be transmitted by the interface. This flag is set when the receiver receives a byte of data before the previous byte has been read by the host. Indicates there is an ongoing transfer on the I2C bus. The I2C controller is not necessarily involved in it.

Bus Active

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I2C Technical Data Sheet

Address Register
Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. 2 APB write access to this register always initiates a transfer if the I C is in master mode. Reserved bits always read as zeros. Bit Func Bit 15 7 14 6 ADD(6) 13 5 ADD(5) 12 4 ADD(4) 11 3 ADD(3) 10 2 ADD(2) 9 ADD(9) 1 ADD(1) 8 ADD(8) 0 ADD(0)

Func ADD(7)

Data Register
When written to, the data register sets data to transmit. When read from, the data register reads the last received byte of data. Reserved bits always read as zeros.
Bit Func Bit Func 15 7 DATA(7) 14 6 DATA(6) 13 5 DATA(5) 12 4 DATA(4) 11 3 DATA(3) 10 2 DATA(2) 9 1 DATA(1) 8 0 DATA(0)

Interrupt Status Register


All bits of this register are cleared upon read.
Bit Func Bit Func

15 7 RX_UNF

14 6 TX_OVF

13 5 RX_OVF

12 4 SLV_RDY

11 3 TO

10 2 NACK

9 ARB_LOST 1 DATA

8 0 COMP

Function

Signal Name

Description

Document No: I-IPA01-0045-TDS Rev 14, May 2011 2005-2011 Cadence Design Systems, Inc.

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I2C Technical Data Sheet COMP Transfer complete Master Mode In master write, this bit is always set when all the supplied data is successfully written to the slave and transfer is about to be terminated with STOP sequence. If FIFO is implemented and hold bit is set, COMP bit is also set as soon as the data is successfully written to the slave, but transfer is not terminated at this point. This allows for combined transfers to be performed even when FIFO is implemented. If the host clears the HOLD bit instead of continuing the transfer, COMP bit is set again during the STOP sequence generation. In master read, this bit is set when all the requested data has been successfully read from a slave and transfer is to be terminated with STOP sequence. Slave Mode In slave receive, this bit is set whenever the master terminates the transfer by generating STOP sequence. In slave transmit, this bit is set whenever all the data supplied by the host is transmitted and the last byte was not acknowledged by the master which terminates the transfer with STOP sequence. Master Write or Slave Transmitter If FIFO not implemented, this bit is set as soon as 2 the I C data register is loaded in the output shift 2 register of the I C interface. If FIFO is implemented, this bit is set whenever there are only 2 bytes left in the FIFO. In slave transmitter mode, this bit is also set if the FIFO is emptied but 2 I C master returned ACK on the last byte transmitted by the slave. Master Read or Slave Receiver If FIFO is not implemented in the design, this bit is set whenever a byte is received and stored in the 2 I C register. If FIFO is implemented, this bit is set whenever there are only 2 free locations in the FIFO. Master Mode This bit is set whenever the accessed slave responds with a NACK during address or data byte transfer. Slave Mode This bit is set if FIFO is implemented and is in slave transmitter mode when a master terminates the transfer before all data supplied by the host is transmitted. Master and Slave Mode 2 This bit is set whenever the I C sclk line is kept low for longer time than the value that is specified by the time out register.

DATA

More data

NACK

Transfer not acknowledged

TO

Transfer time out

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I2C Technical Data Sheet SLV_RD Y Monitored slave ready This bit is set only if I C interface is in master mode, SLVMON bit in the control register is set and the addressed slave returns ACK. Master Read or Slave Receiver If FIFO is not implemented, this bit is set whenever 2 there is valid data in the I C data register and a new byte is received. The second byte is not 2 acknowledged and contents of I C data register remains unchanged. If FIFO is implemented, this bit is set whenever FIFO is full and a new byte is received. The new byte is not acknowledged and contents of the FIFO remains unchanged. This bit is available only if FIFO implemented in the 2 design. Set if the host attempts to write to the I C data register more times than the FIFO depth. This bit is available only if FIFO implemented in the 2 design. Set if the host attempts to read from the I C data register more times than the value of the transfer size register plus one. Always reads zero. Master Mode This bit is set if a master loses bus ownership during a transfer due to ongoing arbitration. Always reads zero.
2

RX_OVF

Receive overflow

TX_OVF

FIFO transmit overflow

RX_UNF

FIFO receive underflow

ARB_LO ST Bits [15:10]

Reserved arbitration lost

reserved

Transfer Size Register


This register is available only if FIFO is implemented in the design. Its meaning varies according to the operating mode as follows: Master transmitter mode: number of data bytes still not transmitted minus one Master receiver mode: number of data bytes that are still expected to be received Slave transmitter mode: number of bytes remaining in the FIFO after the master terminates the transfer Slave receiver mode: number of valid data bytes in the FIFO This register is cleared if CLR_FIFO bit in the control register is set. Bit 7 6 5 4 3 2 1 0

Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer Func Size (7) * Size (6) * Size (5) * Size (4)* Size (3) Size (2) Size (1) Size (0) * - The presence of these bits depends on the setting of `define p_xfer_size_width.

Slave Monitor Pause Register


This register is associated with the slave monitor mode of the I C interface. It is meaningful only when the module is in master mode and bit SLVMON in the control register is set.
2

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I2C Technical Data Sheet This register defines the pause interval between consecutive attempts to address the slave 2 once a write to an I C address register is done by the host. It represents the number of sclk cycles minus one between two attempts. The reset value of the register is 0, which results in the master again trying to access the slave immediately after unsuccessful attempt. Bit Func 7 6 5 4 3 Pause (3) 2 Pause (2) 1 Pause (1) 0 Pause (0)

Time Out Register


The value of time out register represents the time out interval in number of sclk cycles minus one. When the accessed slave holds the sclk line low for longer than the time out period, thus 2 prohibiting the I C interface in master mode to complete the current transfer, an interrupt is generated and TO interrupt flag is set. The reset value of the register is 0x1f. Bit Func 7 TO(7) 6 TO(6) 5 TO(5) 4 TO (4) 3 TO (3) 2 TO (2) 1 TO (1) 0 TO (0)

Note - the Time Out register is active in slave mode as well as master mode. In slave mode when sclk is slow enough the timeout register will cause the timeout interrupt to fire. In this case the timeout interrupt should be masked.

Interrupt Mask Register


Each bit in this register corresponds to a bit in the interrupt status register. If bit i in the interrupt mask register is set, the corresponding bit in the interrupt status register is ignored. Otherwise, an interrupt is generated whenever bit i in the interrupt status register is set. Bits in this register are set through a write to the interrupt disable register and are cleared through a write to the interrupt enable register. All mask bits are set and all interrupts are disabled after reset. Interrupt mask register has the same format as the interrupt status register.
Bit Func Bit Func 15 14 13 12 11 10 9 ARB_LOS T 1 DATA 8

7 RX_UNF

6 TX_OVF

3 TO

2 NACK

0 COMP

RX_OVF SLV_RDY

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I2C Technical Data Sheet

Interrupt Enable Register


This register has the same format as the interrupt status register. Setting a bit in the interrupt enable register clears the corresponding mask bit in the interrupt mask register, effectively enabling corresponding interrupt to be generated.
Bit Func Bit Func 15 7 RX_UNF 14 6 TX_OVF 13 5 12 4 11 3 TO 10 2 NACK 9 ARB_LOST 1 DATA 8 0 COMP

RX_OVF SLV_RDY

Interrupt Disable Register


This register has the same format as the interrupt status register. Setting a bit in the interrupt disable register sets the corresponding mask bit in the interrupt mask register, effectively disabling corresponding interrupt to be generated.
Bit Func Bit Func 15 14 13 12 11 10 9 ARB_LOS T 1 DATA 8

7 RX_UNF

6 TX_OVF

3 TO

2 NACK

0 COMP

RX_OVF SLV_RDY

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I2C Technical Data Sheet

Physical Estimates
Gate count FF count Power estimate (0.13 m @ 200 MHz) SOC-Internal pins (in) SOC-Internal pins (out) SOC-External pins (in) SOC-External pins (out) SOC-External pins (bi-directional) 4200 with 8 byte FIFO 3000 without FIFO 245 with FIFO 183 without FIFO 1.2 mW with FIFO 750 W without FIFO 33 17 2 4 0

Verification
All our IP modules are verified to one of the following levels. Gold IP has been to target silicon. Silver IP has been to silicon in FPGA. Bronze IP has been verified in simulation with logical timing closure. In development IP has not yet been verified. Please contact the IPGallery (ipgallery@cadence.com) for the latest verification information.

Deliverables
The full IP package comes complete with: Verilog HDL Cadence RTL Compiler synthesis scripts and SDC constraints Verilog testbench I2C Users Guide with full programming interface, parameterization instructions and synthesis instructions.

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