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Code No: RR410505 Set No.

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IV B.Tech I Semester Supplementary Examinations, March 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. Implement the following gates with p-MOS transistors only and explain its working

(a) 2 Input AND gate.
(b) 4 Input NOR gate. [8+8]

2. Define different voltage parameters of digital IC and Explain their significance.[16]

3. Explain about different spice - parameters of MOS transistor and their significance.
[16]

4. Compute the high-to-low delay of a two-input static complementary NOR gate with
minimum-sized transistor driving these loads.

(a) An inverter with minimum-sized pull up and pull down.
(b) An inverter whose pull up and pull down are both of size W = 10λ L = 10λ.
[8+8]

5. How cross-talk appears in ICs and explain how this cross-talk can be minimized in
ICs. [16]

6. Draw the Architecture of PLA and explain how different logic functions can be
implemented using PLA. [16]

7. How would you translate a register - transfer structure into a legal two - phase
latched sequential machine? [16]

8. Explain about switch - level simulation and give rules for evaluating switch - level
simulation. [16]

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[8+8] 2. [16] 5. Explain clearly the detailed routing phase of the floor planning of the chip with few examples by considering all constraints.Tech I Semester Supplementary Examinations. With suitable example explain any one of the partitioning algorithm [16] ⋆⋆⋆⋆⋆ 1 of 1 . [16] 3. [16] 8. [16] 6. Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following gates with p-MOS transistors only and explain its working (a) 3 Input NAND gate. An p-MOS transistor is operating in the triode region with the following parameters µn Cox = 95 µ A/V 2 W/L ( ratio) = 90 V gs = −4V.delay measurement of the combinational logic circuits. Design a layout for CMOS 2-input NOR gate. Design a logic gate network for full adder (a) Using Two-level logic (b) Using multi-level logic [8+8] 7. Find its drain current & drain -Source resistance. 2 IV B. Explain in detail the path . Vds = −2V .1V.Code No: RR410505 Set No.parameters of MOS transistor and their significance. [16] 4. (b) Inverter. Explain about different spice . March 2006 VLSI SYSTEMS DESIGN ( Common to Computer Science & Engineering. Vtn = −1.

(b) An inverter whose pull up and pull down are both of size W = 10λ L = 10λ. Explain with suitable example how to design the layout of a gate to maximize performance and minimize area. [8+8] 2. [8+8] 5. Clearly explain about block placement and channel definition with respect to floor planning of the chip. 3 IV B. [16] 4.Tech I Semester Supplementary Examinations. What are the key advantages of ICs? And explain how these advantages of ICs translate in to advantages at the system level. [16] 6. (a) Pipelining (b) Data-paths [8+8] 7. (b) Inverter. Design a stick diagram for two-input P-MOS NAND and NOR gates. Explain about different types in the register file based data-path. (a) An inverter with minimum-sized pull up and pull down. [16] 3. Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. [16] ⋆⋆⋆⋆⋆ 1 of 1 . Compute the high-to-low delay of a two-input static complementary NOR gate with minimum-sized transistor driving these loads. March 2006 VLSI SYSTEMS DESIGN ( Common to Computer Science & Engineering. Implement the following gates with CMOS Logic and explain its working (a) 3 Input NAND gate.Code No: RR410505 Set No. [16] 8. Discuss clearly about the following system Design principles.

Code No: RR410505 Set No. [16] 6. Clearly explain about the generic integrated circuit design flow. March 2006 VLSI SYSTEMS DESIGN ( Common to Computer Science & Engineering. [16] 3. [8+8] 5. Implement the following gates with p-MOS transistors only and explain its working (a) 3 Input NAND gate. [16] 8. Compute the high-to-low delay of a two-input static complementary NOR gate with minimum-sized transistor driving these loads. 4 IV B. (b) Inverter. (a) An inverter with minimum-sized pull up and pull down. [16] ⋆⋆⋆⋆⋆ 1 of 1 . [16] 4. (b) An inverter whose pull up and pull down are both of size W = 10λ L = 10λ. [8+8] 2. How cross-talk appears in ICs and explain how this cross-talk can be minimized in ICs. Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. [16] 7. Explain about pad design procedure to design input and output pads. Draw the Architecture of PLA and explain how different logic functions can be implemented using PLA.Tech I Semester Supplementary Examinations. Name different IC fabrication technologies with suitable examples. Explain details about level-1 modeling of MOS transistor.