FPGA Physical Description

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1 1. VGA (HD-15) Monitor Port 2 2. 9-pin (DB-9) 3 3. Power Connector 4 4. A1 Expansion Port 5 5. A2 Expansion Port 6 6. B1 Expansion Port 7 7. PS/2 Port 8 8. Seven Segment Displays 9 9. Switches (8) 10 10. Buttons (4) 1 11. LEDs (8) 2 12. Power LED 3 13. Spartan 3 FPGA Core 4 14. Program LED (Lit when the FPGA is programmed) 5 15. JTAG Port (used to program the FPGA)


Programming Xilinx Board (Spartan 3) Tutorial Using ISE 8.1i Tutorial prepared by Oluwayomi Adamo Introduction This tutorial shows you how to program Spartan 3 FPGA board using Xilinx ISE 8.1i. As an example, a half adder circuit will be implemented on the Spartan 3 board. The tutorial begins by showing you how to create a new project and how to describe the digital circuit in VHDL. After the circuit’s functionality has been verified, it is then downloaded to the Spartan 3 board for implementation. You are encouraged to try out the examples before embarking on any exercise. Creating a new Project and Source Start the Xilinx ISE 8.1i project navigator by double clicking the Xilinx ISE 8.1i icon on your desktop.

Xilinx ISE 8.1i.lnk

Click on File and select New Project


Select a project location and type the name you would like to call your project “HalfAdder”: Click Next 3 .

device. and speed grade as shown below: Click Next Click New Source 4 . package.Select the device family.

Select VHDL Module in the New Source Wizard window: Click Next 5 .

This is used to generate a template for your VHDL code.Specify the inputs and outputs of your design (HalfAdder). Click Next 6 .

Click Finish if you are satisfied your specifications shown in the summary page Click Next 7 .

8 .Click Next Verify the information on the Project Summary window: Click Finish.

Double-click on “HalfAdder-Behavioral(HalfAdder. 9 . Include an “enable” input in your entity and it should be 1 bit wide.vhd)” tab in the “Sources” pane. Complete the architectural part of your VHDL code.

Specify the pins you would like the inputs and outputs to be connected to. Double-click on “Assign Package Pins” in the “Process” pane in the left of the window. 10 .

Click Yes. If you have any error. The Pace editor is loaded. Your design will be checked for syntax error. 11 . Click Yes.Note: You may be asked to save your VHDL code. make sure you fix them before proceeding.

The package view gives a better view of the physical FPGA package). Type in the desired pin names for each signal in the “Design Object List” at the left in the “Loc” column 12 .You can select “Package View” tab at the bottom of the right pane.

Click File and Exit. Click Ok. 13 . Note: The following dialog may appear when saving the file: Click on “Don’t show this dialog again”.Click File and Save. View the UCF file by double-clicking “Edit Constraints (Text)” in the project Navigator window.

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double-click on “HalfAdder-Behavioral (HalfAdder)” tab in the “Sources” pane. 15 .Programming the Board In the Project Navigator window.

Right-click on “Generate Programming File” in the “Processes” pane. Change “FPGA Start-UP Clock” to “JTAG Clock” 16 . Select “Startup Options” tab. In the Process Properties windows. Select “Properties”.

Click Ok. Double-click on “Configure Device (iMPACT)”. This opens the iMPACT tool and a wizard for creating a new configuration. In the “Processes” window.Click Apply. 17 . click on the + sign by “Generate programming file”.

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bit). “Assign New Configuration File” window opens.Click Finish.bit” file (HalfAdder. click Bypass. 19 . Select the name of your select the “. Click Open.

select “Program”. 20 .You will now be at the main iMPACT window: Right-click on the FPGA (“xc3s200”).

21 .Make sure that “Verify” is not checked.

Click Ok. The FPGA is now being programmed as shown: 22 .Click Apply.

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