ST164 – Elementos Básicos de Computação Professor: Vladimir Barbosa Curso: Tecnologia em Informática Período: Noturno Aluno: Christian Hartung

RA: 070461

Memória
Memórias são componentes, dispositivos ou mídias de armazenamento capazes de guardar dados temporariamente ou permanentemente. As memórias podem ser:

Primárias: estão conectadas diretamente à CPU e devem estar presentes para que esta funcione corretamente. Podem ser divididas em três tipos:

Registradores: são internos à CPU e guardam informações para as operações aritméticas e lógicas sendo realizadas no momento. São a forma de armazenamento mais veloz. Cache: um tipo especial de memória usada para aumentar o desempenho das CPUs. Informação da memória principal é copiada para a memória cache, que é mais veloz (menos que os registradores), apesar de ser menor (maior que os registradores). Normalmente são usadas em níveis, sendo o primário menor e mais veloz (mais próximo à CPU) e o secundário, maior e menos veloz. Principal (ou primária): armazena os programas sendo executados no momento. É a memória RAM. Está conectada à CPU por um barramento de memória e um barramento de dados, que conseguem transferir rapidamente as informações dela para os registradores.

Secundárias: precisam que o computador utilize os recursos de entrada e saída para acessá-las, e são usadas para armazenar informações por um longo período de tempo, mas os sistemas operacionais também podem usá-la como memória virtual. Normalmente possuem maior capacidade que as memórias primárias, mas são mais lentas. Exemplos de memórias secundárias são CD, DVD, Dispositivos USB, HD, etc. Terciárias: são mídias removíveis que o computador insere e remove automaticamente (através de braços robóticos). Primeiramente o computador verifica no banco de dados onde está a informação desejada, solicita que o braço insira em um drive, lê a informação e o braço recoloca a mídia em seu lugar. Exemplos disso são fitas magnéticas e bibliotecas de discos óticos (como um jukebox). Rede: qualquer tipo de armazenamento onde os dados são transferidos por uma rede. Isso permite que a informação seja centralizada e evita duplicidade dos dados.

RAM

A Memória de Acesso Aleatório (Random Access Memory) é usada como memória principal e permite que a informação seja acessada em qualquer ordem e sem movimento físico. O termo “aleatório” vem do fato de qualquer dado ser retornado rapidamente e em velocidade constante, não importando a posição na memória.

A principal vantagem da RAM em relação à memória secundária é que o acesso aos dados é rápido e consistente, pois não depende de onde está a informação e não é necessário nenhum tipo de movimento físico para que ela seja acessada. A desvantagem é o custo e o fato de os dados serem perdidos quando é cessada a alimentação elétrica. Mas atualmente estão sendo desenvolvidas NVRAMs (Non-Volatile RAM – RAM não volátil), ou seja, memórias que não perdem a informação mesmo quando é cessada a alimentação elétrica. Dois tipos de memória que merecem ser citados são:

DDR SDRAM: Memória de Acesso Aleatório de Taxa de Transferência Dobrada (Double-Data-Rate Synchronous Dynamic Random Access Memory) é um tipo de memória que utiliza tanto o ciclo de subida como o de descida do clock para transferir dados. Assim, é capaz de transferir duas vezes mais dados por ciclo de clock (que pode ser de 100 até 300 Mhz). Já foi lançado o padrão DDR2, que pode ter clock de 200 até 533 Mhz e a DDR3, que tem clock de 400 até 800MHz, além de ter um consumo de energia 40% menor que sua antecessora. Para se obter a velocidade de transferência, utiliza-se a equação: (clock * 2 * n) / 8, onde n é o número de bits transferido por ciclo de clock (tipicamente 64). XDR DRAM: Memória de Acesso Aleatório com Taxa de Transferência Extrema (Extreme Data-Rate Dynamic Random Access Memory) é um tipo de memória desenvolvido pela Rambus como concorrente das memórias DDR. Possuem clock de 400, 600 e 800MHz, com 1GHz já planejado. Podem transferir dados a 6,4GB/s em 400MHz. A XDR2 já está em desenvolvimento e agendado para este ano (2007).

Disco Rígido

O Disco Rígido (Hard Disk) é uma mídia de armazenamento não-volátil. São usados para armazenar as informações no computador, já que a memória principal é apagada quando ele é desligado. Também são usados como memória virtual, i.e. o sistema operacional joga os dados da memória RAM para o HD para simular uma memória maior e vai trocando os dados conforme for necessário. Possuem uma capacidade de armazenamento maior que a memória principal, porém com uma velocidade menor. As interfaces para a conexão com o computador são:

ATA: Advanced Technology Attachment é um padrão de interface para conectar dispositivos de armazenamento criado em 1986. O padrão permite cabos com até 46 centímetros de comprimento. É uma interface paralela, normalmente usada internamente à CPU, onde dois dispositivos podem ser conectados por cabo, com velocidades que veriam de 16MB/s até 133MB/s. SATA: Serial ATA é um padrão criado em 2003 desenvolvido para substituir o padrão ATA paralelo. Utiliza um cabo de até 1m com sete fios e que pode conectar apenas um dispositivo com velocidade de 1.5Gb/s e 3Gb/s e 6Gb/s está em desenvolvimento (lembrando que estes valores estão em bits e devem ser divididos por 8 para conversão para byte). SCSI: Small Computer System Interface é um conjunto de padrões para conectar e transferir dados entre computadores e periféricos criado em 1986. É mais usado para conectar Hds e drives de fita, mas pode ser usado para conectar scanners e drives óticos. É mais comumente usado em estações de trabalho e servidores e possuem velocidades que variam de 5 até 640MB/s.

Discos Ópticos
São discos onde os dados são armazenados na forma de “vales” em uma superfície. Esses dados são acessados quando o disco é iluminado por um laser. Os “vales” destorcem a luz refletida.

Compact Disc

O CD é um disco óptico usado para armazenar dados digitais, originalmente projetado para armazenar áudio digital, lançado em 1982 e desenvolvido pela Sony e Philips. Normalmente são discos de 120mm de diâmetro que podem armazenar até 80min de áudio. A tecnologia foi adaptada para armazenar dados (CD-ROM) e para poder ser gravado uma (CD-R) ou mais (CD-RW) vezes. São capazes de armazenar entre 650 e 703MB.

Digital Versatile Disc

Também conhecido como Digital Video Disc, o DVD é um disco óptico que pode ser usado para armazenar dados e filmes. Assim como os Cds, possuem 120mm de diâmetro, porém são codificados de maneira diferente, permitindo uma maior densidade. São capazes de armazenar 4,7GB em camada simples e 9,4GB em camada dupla. Pode ser DVD+R, DVD-R, DVD+R/RW, DVD-R/RW ou DVD-RAM.

DataPlay

É um disco óptico desenvolvido e lançado pela DataPlay, Inc em 2002. É um disco de 32mm de diâmetro envolvido por uma capa de proteção. É capaz de armazenar 250MB/lado.

Graças aos algoritmos utilizados, teoricamente é capaz de armazenar até 11h de música com qualidade.

Universal Media Disc

É um disco óptico desenvolvido pela Sony para ser usado no PSP. É uma mídia com cerca de 65mm de diâmetro, capaz de armazenar até 1,8GB (camada dupla) de dados, que podem incluir jogos, vídeos, música, etc.

Blu-ray Disc

É um disco óptico de alta densidade de armazenamento. Diferentemente dos Cds e DVDs, o Blu-ray utiliza laser azul para ler e gravar os dados. Por este laser ser menor (405nm) que o dos DVDs (650nm), é capaz de armazenar mais dados. Um disco de 120mm de diâmetro consegue armazenar 25GB com comada simples e 50GB com camada dupla.

High-Definition DVD

Ou HD DVD, é um formato desenvolvido para competir com o Blu-ray. Assim como o Blu-ray, também utiliza laser azul. É capaz de armazenar 15GB em camada simples e 30GB em camada dupla.

Ultra Density Optical

É uma mídia óptica capaz de armazenar até 30GB de dados. Mas versões de 60 e 120GB estão em desenvolvimento. Há especulações de que é possível fazer um disco de até 500GB. Também utiliza um laser azul de 405nm, mas possui 130mm de diâmetro.

Holographic Versatile Disc

O HVD é uma mídia óptica que ainda está em fase de desenvolvimento. O comitê está trabalhando em versões de até 200GB de armazenamento, apesar de, teoricamente, ser possível muito mais (3,9TB). Ultimamente, referente ao HD DVD, Blu-ray, DVD, e ao CD, andamos tentando compactar memória com lasers menores, linhas de leitura em verticais, e tambem com camadas e duplas-faces. A vantagem da Tecnologia Holográfica, é que ao contrário da mídias citadas anteriormentes, que marcam cada ponto como um bit, é que ela pode marcar vários bits no mesmo ponto, através de "queima por angulos". Quando se grava um CD, por exemplo, nós "imprimimos" os dados na superfície do produto, como se fossem "marcas de fogo", não que isso signifique que você tenha que acender um isqueiro para gravar um CD. Agora, quando se grava em uma mídia holográfica, como o HVD, o laser lança uma "luz", um holograma, a mídia "fotografa" o holograma, registrando a informação. E já que a holografia é uma forma de se registrar ou apresentar imagens em dimensões, significa que podemos marcar holohramas em uma mídia várias vezes no mesmo ponto. E já que a longitude dos laseres são bem menores que os das mídias de hoje em dia, podemos associar essa tecnologia com mídias holográficas em várias camadas, como 6, 12 camadas.

1. Laser verde de leitura/escrita (532nm) 2. Laser vermelho de endereçamento (650nm) 3. Holograma dos dados 4. Camada de Policarbonato 5. Camada holográfica de dados 6. Camadas de distanciamento 7. Camada refletora (reflete a luz verde) 8. Camada refletora de alumínio (reflete a luz vermelha) 9. Camada transparente P. Camada de endereçamento (por depressões binárias).

USB Mass storage device

É um conjunto de protocolos sobre o Universal Serial Bus (USB) para dispositivos de armazenamento, tais como Hds, memórias flash, câmeras digitais, MP3 players, etc.

Cartões de Memória

Dispositivos de armazenamento que oferecem boa velocidade de leitura e gravação, armazenamento sem consumo de energia. Existem vários tipos de cartões de memória, usados para diferentes propósitos. Alguns usos comuns incluem câmeras, consoles e celulares.

Processadores
O processador é o componente do computador que interpreta instruções e processa dados. Obs.: Dados retirados da Wikipedia.

Process or

Series

Code Name

Speed

Socket

Fab

TDP

Core FSB

L2 Cache

Pentiu 8xx/9xx m D/EE

Smithfield, Presler

2.66– 3.73 LGA 775 GHz

2 × 1024 533/80 65/9 95-130 dual KiB/2 × 0/1066 0 nm W core 2048 MT/s KiB 65/9 400/53 256– 0/13 20.8– 3/800/ single 2048 0/18 115 W 1066 KiB 0 nm MT/s

Pentiu 5xx/6xx m 41

1.3– Willamette, Northwood, Gallatin, 3.8 Prescott, Cedar Mill GHz

Socket 478/LGA 775/Socket 423

Covington, Mendocino, Coppermine-128, Tualatin-256, Intel 2xx/1xxx/ Willamette-128, Prescott-256, Celeron 1.x/2.x Cedar Mill-512, Northwood-256, Banias-512, Dothan-1024, Yonah-1024 Drake, Tanner, Cascades, Foster, Prestonia, Gallatin, Nocona, Irwindale, Cranford, Potomac, Paxville, Sossaman, Dempsey, Woodcrest, Tulsa Banias, Dothan

Slot 1, Socket 370, 266 Socket 478, LGA 65Mhz66-533 0-1024 775, Socket 615, 250 5-86 W single 3.3 MT/s KiB Socket 495, Socket nm Ghz 479, Socket M 400 Slot 2, Socket 603, 65– single 100– 256– MHz– 16–165 Socket 604, Socket 250 /dual/ 1333 4096 3.8 W M, LGA771 nm quad MT/s KiB GHz 0.8– 2.26 GHz 90/1 400/53 1024– 30 5–27 W single 3 2048 nm MT/s KiB 65 nm 25–49 W/ 15– 24 W / <14 W mostl 533/66 y 2048 7 dual KiB MT/s core

Intel Xeon

5xxx/ 7xxx

Pentiu 7xx mM Txxxx/ Lxxxx/ Uxxxx

Socket 479

Intel Core

Yonah

1.06– 2.33 Socket M GHz

Exxxx/ 3xxx/ Intel Txxxx/ Core 2 Xxxxx/ Qxxxx/ QXxxxx

Allendale, Conroe, Merom

1.6– 3.0 GHz

LGA 775/Socket M

65 nm

>65 W dual/ 667/10 2048/ 24-49 quad 66 8192 W core MT/s KiB

Tabela 1: Comparação de Processadores Intel

The 4-bit processors Intel 4004: first single-chip microprocessor
• • • • • • • • •

Introduced November 15-16, 1971 Clock speed 740 kHz 0.06 MIPS Bus Width 4 bits (multiplexed address/data due to limited pins) PMOS Number of Transistors 2,300 at 10 µm Addressable Memory 640 bytes Program Memory 4 KiB One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)

Originally designed to be used in Busicom calculator

4040
• • • • • • • • • •

Introduced 4th Qtr, 1974 Clock speed of 500 kHz to 740 kHz using 4 to 5.185 MHz crystals 0.06 MIPS Bus Width 4 bits (multiplexed address/data due to limited pins) PMOS Number of Transistors 3,000 at 10 µm Addressable Memory 640 bytes Program Memory 8 KiB Interrupts Enhanced version of 4004

The 8-bit processors 8008
• • • • • • • • • •

Introduced April 1, 1972 Clock speed 500 kHz (8008-1: 800 kHz) 0.05 MIPS Bus Width 8 bits (multiplexed address/data due to limited pins) PMOS Number of Transistors 3,500 at 10 µm Addressable memory 16 KiB Typical in dumb terminals, general calculators, bottling machines Developed in tandem with 4004 Originally intended for use in the Datapoint 2200 terminal

8080
• • • • • • • •

Introduced April 1, 1974 0.64 MIPS Bus Width 8 bits data, 16 bits address NMOS Addressable memory 64 KiB 10X the performance of the 8008 Used in the Altair 8800, Traffic light controller, cruise missile Required six support chips versus 20 for the 8008

8085
• • • • • • • • •

Introduced March 1976 Clock speed 5 MHz 0.37 MIPS Bus Width 8 bits data, 16 bits address Number of Transistors 6,500 at 3 µm Assembly language downwards compatible with 8080. Used in Toledo scale. Also was used as a computer peripheral controller - modems, harddisks, etc... CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable. High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured two serial I/O connection,3 maskable interupts,1 Non-maskable,1 programmable,status,DMA.

The bit-slice processor 3000 Family
• • • • • • • •

Introduced 3rd Qtr, 1974 Members of the family • 3001 (Microcontrol Unit) 3002 (2-bit Arithmetic Logic Unit slice) 3003 (Look-ahead Carry Generator) 3212 (Multimode Latch Buffer) 3214 (Interrupt Control Unit) 3216 (Parallel Bi-directional Bus Driver) Bus Width 2-n bits data/address (depending on number of slices used)

The 16-bit processors: origin of x86 8086
• • • • • • • • • • •

Introduced June 8, 1978 Clock speeds: • 5 MHz with 0.33 MIPS 8 MHz with 0.66 MIPS 10 MHz with 0.75 MIPS The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle. Bus Width 16 bits data, 20 bits address Number of Transistors 29,000 at 3 µm Addressable memory 1 megabyte 10X the performance of 8080 Used in portable computing Used segment registers to access more than 64 KiB of data at once, bane of programmers' existence for years to come

8088
• • • • • • • • •

Introduced June 1, 1979 Clock speeds: • 5 MHz with 0.33 MIPS 8 MHz with 0.75 MIPS Internal architecture 16 bits External bus Width 8 bits data, 20 bits address Number of Transistors 29,000 at 3 µm Addressable memory 1 megabyte Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end) Used in IBM PCs and PC clones

iAPX 432 (chronological entry)
• • •

Introduced January 1, 1981 Multi-chip CPU; Intel's first 32-bit microprocessor See main entry

80186
• •

Introduced 1982 Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like

• •

Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor Later renamed the iAPX 186

80188
• •

A version of the 80186 with an 8-bit external data bus Later renamed the iAPX 188

80286
• • • • • • • • • • • • •

Introduced February 1, 1982 Clock speeds: • 6 MHz with 0.9 MIPS 8 MHz, 10 MHz with 1.5 MIPS 12.5 MHz with 2.66 MIPS 16 MHZ, 20MHz and 25MHz available. Bus Width 16 bits Included memory protection hardware to support multitasking operating systems with per-process address space Number of Transistors 134,000 at 1.5 µm Addressable memory 16 mebibytes Added protected-mode features to 8086 with essentially the same instruction set 3-6X the performance of the 8086 Widely used in PC clones at the time Can scan the Encyclopædia Britannica in 45 seconds

32-bit processors: the non-x86 microprocessors iAPX 432
• • • • • • • • • • • • •

Introduced January 1, 1981 as Intel's first 32-bit microprocessor Object/capability architecture Microcoded operating system primitives One tebibyte virtual address space Hardware support for fault tolerance Two-chip General Data Processor (GDP), consists of 43201 and 43202 43203 Interface Processor (IP) interfaces to I/O subsystem 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems 43205 Memory Control Unit (MCU) Architecture and execution unit internal data paths 32 bit Clock speeds: • 5 MHz 7 MHz 8 MHz

i960 aka 80960
• • • • •

Introduced April 5, 1988 RISC-like 32-bit architecture predominantly used in embedded systems Evolved from the capability processor developed for the BiiN joint venture with Siemens Many variants identified by two-letter suffixes.

80386SX (chronological entry)
• •

Introduced June 16, 1988 See main entry

80376 (chronological entry)
• •

Introduced January 16, 1989 See main entry

i860 aka 80860
• • • •

Introduced February 27, 1989 Intel's first superscalar processor RISC 32/64-bit architecture, with pipeline characteristics very visible to programmer Used in Intel Paragon massively parallel supercomputer

XScale
• • •

Introduced August 23, 2000 32-bit RISC microprocessor based on the ARM architecture Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.

32-bit processors: the 80386 range 80386DX
• • • • • • • • • • • • • •

Introduced October 17, 1985 Clock speeds: • 16 MHz with 5 to 6 MIPS 20 MHz with 6 to 7 MIPS, introduced 16 February 1987 25 MHz with 8.5 MIPS, introduced 4 April 1988 33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced 10 April 1989 Bus Width 32 bits Number of Transistors 275,000 at 1 µm Addressable memory 4 gibibytes Virtual memory 64 tebibytes First x86 chip to handle 32-bit data sets Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp Used in Desktop computing Can address enough memory to manage an eight-page history of every person on earth Can scan the Encyclopædia Britannica in 12.5 seconds

80960 (i960) (chronological entry)
• •

Introduced April 5, 1988 See main entry

80386SX
• • • • • • • •

Introduced June 16, 1988 Clock speeds: • 16 MHz with 2.5 MIPS 20 MHz with 2.5 MIPS, 25 MHz with 2.7 MIPS, introduced 25 January 1989 33 MHz with 2.9 MIPS, introduced 26 October 1992 Internal architecture 32 bits External data bus width 16 bits External address bus width 24 bits Number of Transistors 275,000 at 1 µm

• • • •

Addressable memory 16 MiB Virtual memory 1 tebibyte Narrower buses enable low-cost 32-bit processing Used in entry-level desktop and portable computing

80376
• • • •

Introduced January 16, 1989; Discontinued June 15, 2001 Variant of 386 intended for embedded systems No "real mode", starts up directly in "protected mode" Replaced by much more successful 80386EX from 1994

80860 (i860) (chronological entry)
• •

Introduced February 27, 1989 See main entry

80486DX (chronological entry)
• •

Introduced April 10, 1989 See main entry

80386SL
• • • • • • • • • •

Introduced October 15, 1990 Clock speeds: • 20 MHz with 4.21 MIPS 25 MHz with 5.3 MIPS, introduced 30 September 1991 Internal architecture 32 bits External bus width 16 bits Number of Transistors 855,000 at 1 µm Addressable memory 4 gibibytes Virtual memory 1 tebibyte First chip specifically made for portable computers because of low power consumption of chip Highly integrated, includes cache, bus, and memory controllers

80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)
• •

Introduced 1991–1994 See main entries

80386EX
• • • • • • • • • • • • •

Introduced August 1994 Variant of 80386SX intended for embedded systems Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt On-chip peripherals: • Clock and power mgmt Timers/counters Watchdog timer Serial I/O units (sync and async) and parallel I/O DMA RAM refresh JTAG test logic Significantly more successful than the 80376 Used aboard several orbiting satellites and microsatellites Used in NASA's FlightLinux project

32-bit processors: the 80486 range 80486DX
• • • • • • • • • • • • •

Introduced April 10, 1989 Clock speeds: • 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92) 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KiB L2), introduced 7 May 1990 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KiB L2), introduced 24 June 1991 Bus Width 32 bits Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm Addressable memory 4 gibibytes Virtual memory 1 tebibyte Level 1 cache on chip Math coprocessor on chip 50X performance of the 8088 Used in Desktop computing and servers Family 4 model 3

80386SL (chronological entry)
• •

Introduced October 15, 1990 See main entry

80486SX
• • • • • • • • • • • • •

Introduced April 22, 1991 Clock speeds: • 16 MHz with 13 MIPS 20 MHz with 16.5 MIPS, introduced 16 September 1991 25 MHz with 20 MIPS (12 SPECint92), introduced 16 September 1991 33 MHz with 27 MIPS (15.86 SPECint92), introduced 21 September 1992 Bus Width 32 bits Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm Addressable memory 4 gibibytes Virtual memory 1 tebibyte Identical in design to 486DX but without math coprocessor Used in low-cost entry to 486 CPU desktop computing Upgradable with the Intel OverDrive processor Family 4 model 2

80486DX2
• • • • • •

Introduced March 3, 1992 Clock speeds: • 20 MHz 40 MHz 50 MHz 66 MHz 100 MHz

80486SL
• • •

Introduced November 9, 1992 Clock speeds: • 20 MHz with 15.4MIPS 25 MHz with 19 MIPS

• • • • • • •

33 MHz with 25 MIPS Bus Width 32 bits Number of Transistors 1.4 million at 0.8 µm Addressable memory 4 GiB Virtual memory 1 tebibyte Used in notebook computers Family 4 model 3

Pentium (chronological entry)
• •

Introduced March 22, 1993 See main entry

80486DX4
• • • • • • • • • • •

Introduced March 7, 1994 Clock speeds: • 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KiB L2) 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KiB L2) Number of Transistors 1.6 million at 0.6 µm Bus width 32 bits Addressable memory 4 gibibytes Virtual memory 64 tebibytes Pin count 168 PGA Package, 208 sq ftP Package Die size 345 mm² Used in high performance entry-level desktops and value notebooks Family 4 model 8

32-bit processors: the Pentium ("I") Pentium ("Classic")
• • • • • • • • • • • • • • • • • • • •

Bus width 64 bits System bus speed 60 or 66 MHz Address bus 32 bits Addressable Memory 4 gibibytes Virtual Memory 64 tebibytes Superscalar architecture brought 5X the performance of the 33 MHz 486DX processor Runs on 5 volts Used in desktops 16 KiB of L1 cache P5 - 0.8 µm process technology • Introduced March 22, 1993 Number of transistors 3.1 million Socket 4 273 pin PGA processor package Package dimensions 2.16" x 2.16" Family 5 model 1 Variants • 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KiB L2) 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KiB L2) P54 - 0.6 µm process technology • Socket 7 296/321 pin PGA package Number of transistors 3.2 million Variants • 75 MHz Introduced October 10, 1994 90 MHz Introduced March 7, 1994

• • • • • • • • • •

100 MHz Introduced March 7, 1994 120 MHz Introduced March 27, 1995 P54C - 0.35 µm process technology • Number of transistors 3.3 million 90 mm² die size Family 5 model 2 Variants • 120 MHz Introduced March, 1995 133 MHz Introduced June, 1995 150 MHz Introduced January 4, 1996 166 MHz Introduced January 4, 1996 200 MHz Introduced June 10, 1996

80486DX4 (chronological entry)
• •

Introduced March 7, 1994 See main entry

80386EX (Intel386 EX) (chronological entry)
• •

Introduced August 1994 See main entry

Pentium Pro (chronological entry)
• •

Introduced November 1995 See main entry

Pentium MMX
• • • • • • • • • • • • • • •

P55C - 0.35 µm process technology • Introduced January 8, 1997 Intel MMX instructions Socket 7 296/321 pin PGA (pin grid array) package 32 KiB L1 cache Number of transistors 4.5 million System bus speed 66 MHz Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8 Variants • 166 MHz Introduced January 8, 1997 200 MHz Introduced January 8, 1997 233 MHz Introduced June 2, 1997 166 MHz (Mobile) Introduced January 12, 1998 200 MHz (Mobile) Introduced September 8, 1997 233 MHz (Mobile) Introduced September 8, 1997 266 MHz (Mobile) Introduced January 12, 1998 300 MHz (Mobile) Introduced January 7, 1999

32-bit processors: P6/Pentium M microarchitecture Pentium Pro
• • • •

Introduced November 1, 1995 Precursor to Pentium II and III Primarily used in server systems Socket 8 processor package (387 pins) (Dual SPGA)

• • • • • • • • • • • • • •

Number of transistors 5.5 million Family 6 model 1 0.6 µm process technology • 16 KiB L1 cache 256 KiB integrated L2 cache 60 MHz system bus speed Variants • 150 MHz 0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache • Number of transistors 5.5 million 512 KiB or 256 KiB integrated L2 cache 60 or 66 MHz system bus speed Variants • 166 MHz (66 MHz bus speed, 512 KiB 0.35 µm cache) Introduced November 1, 1995 180 MHz (60 MHz bus speed, 256 KiB 0.6 µm cache) Introduced November 1, 1995 200 MHz (66 MHz bus speed, 256 KiB 0.6 µm cache) Introduced November 1, 1995 200 MHz (66 MHz bus speed, 512 KiB 0.35 µm cache) Introduced November 1, 1995 200 MHz (66 MHz bus speed, 1 MiB 0.35 µm cache) Introduced August 18, 1997

Pentium II
• • • • • • • • • • • • • • • • • • • • • • • •

Introduced May 7, 1997 Pentium Pro with MMX and improved 16-bit performance 242-pin Slot 1 (SEC) processor package Number of transistors 7.5 million 32 KiB L1 cache 512 KiB ½ speed external L2 cache The only Pentium II that did not have the cache at ½ speed of the core was the Pentium II 450 PE. Klamath - 0.35 µm process technology (233, 266, 300 MHz) • 66 MHz system bus speed Family 6 model 3 Variants • 233 MHz Introduced May 7, 1997 266 MHz Introduced May 7, 1997 300 MHz Introduced May 7, 1997 Deschutes - 0.25 µm process technology (333, 350, 400, 450 MHz) • Introduced January 26, 1998 66 MHz system bus speed (333 MHz variant), 100 MHz system bus speed for all models after Family 6 model 5 Variants • 333 MHz Introduced January 26, 1998 350 MHz Introduced April 15, 1998 400 MHz Introduced April 15, 1998 450 MHz Introduced August 24, 1998 233 MHz (Mobile) Introduced April 2, 1998 266 MHz (Mobile) Introduced April 2, 1998 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998; Engineering Sample Photo 300 MHz (Mobile) Introduced September 9, 1998 333 MHz (Mobile)

Celeron (Pentium II-based)
• • • •

Covington - 0.25 µm process technology • Introduced April 15, 1998 242-pin Slot 1 SEPP (Single Edge Processor Package) Number of transistors 7.5 million 66 MHz system bus speed

• • • • • • • • • • • • • • • • • • • • • • • • • • • •

32 KiB L1 cache No L2 cache Variants • 266 MHz Introduced April 15, 1998 300 MHz Introduced June 9, 1998 Mendocino - 0.25 µm process technology • Introduced August 24, 1998 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package Number of transistors 19 million 66 MHz system bus speed 32 KiB L1 cache 128 KiB integrated cache Family 6 model 6 Variants • 300 A MHz Introduced August 24, 1998 333 MHz Introduced August 24, 1998 366 MHz Introduced January 4, 1999 400 MHz Introduced January 4, 1999 433 MHz Introduced March 22, 1999 466 MHz 500 MHz Introduced August 2, 1999 533 MHz Introduced January 4, 2000 266 MHz (Mobile) 300 MHz (Mobile) 333 MHz (Mobile) Introduced April 5, 1999 366 MHz (Mobile) 400 MHz (Mobile) 433 MHz (Mobile) 450 MHz (Mobile) Introduced February 14, 2000 466 MHz (Mobile) 500 MHz (Mobile) Introduced February 14, 2000

Pentium II Xeon (chronological entry)
• •

Introduced June 29, 1998 See main entry

Pentium III
• • • • • • • • • • • • • • •

Katmai - 0.25 µm process technology • Introduced February 26, 1999 Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE) Number of transistors 9.5 million 512 KiB ½ speed L2 External cache 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package System Bus Speed 100 MHz, 133 MHz (B-models) Family 6 model 7 Variants • 450 MHz Introduced February 26, 1999 500 MHz Introduced February 26, 1999 550 MHz Introduced May 17, 1999 600 MHz Introduced August 2, 1999 533 MHz Introduced (133 MHz bus speed) September 27, 1999 600 MHz Introduced (133 MHz bus speed) September 27, 1999 Coppermine - 0.18 µm process technology • Introduced October 25, 1999 Number of transistors 28.1 million

• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

256 KiB Advanced Transfer L2 Cache (Integrated) 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package System Bus Speed 100 MHz (E-models), 133 MHz (EB models) Family 6 model 8 Variants • 500 MHz (100 MHz bus speed) 533 MHz 550 MHz (100 MHz bus speed) 600 MHz 600 MHz (100 MHz bus speed) 650 MHz (100 MHz bus speed) Introduced October 25, 1999 667 MHz Introduced October 25, 1999 700 MHz (100 MHz bus speed) Introduced October 25, 1999 733 MHz Introduced October 25, 1999 750 MHz (100 MHz bus speed) Introduced December 20, 1999 800 MHz (100 MHz bus speed) Introduced December 20, 1999 800 MHz Introduced December 20, 1999 850 MHz (100 MHz bus speed) Introduced March 20, 2000 866 MHz Introduced March 20, 2000 933 MHz Introduced May 24, 2000 1000 MHz Introduced March 8, 2000 (Not widely available at time of release) 1100 MHz 1133 MHz (first version recalled, later re-released) 400 MHz (Mobile) Introduced October 25, 1999 450 MHz (Mobile) Introduced October 25, 1999 500 MHz (Mobile) Introduced October 25, 1999 600 MHz (Mobile) Introduced January 18, 2000 650 MHz (Mobile) Introduced January 18, 2000 700 MHz (Mobile) Introduced April 24, 2000 750 MHz (Mobile) Introduced June 19, 2000 800 MHz (Mobile) Introduced September 25, 2000 850 MHz (Mobile) Introduced September 25, 2000 900 MHz (Mobile) Introduced March 19, 2001 1000 MHz (Mobile) Introduced March 19, 2001 Tualatin - 0.13 µm process technology • Introduced July 2001 Number of transistors 28.1 million 32 KiB L1 cache 256 KiB or 512 KiB Advanced Transfer L2 cache (Integrated) 370-pin FC-PGA (Flip-chip pin grid array) package 133 MHz system bus speed Family 6 model 11 Variants • 1133 MHz (256 KiB L2) 1133 MHz (512 KiB L2) 1200 MHz 1266 MHz (512 KiB L2) 1333 MHz 1400 MHz (512 KiB L2)

Pentium II and III Xeon

PII Xeon • Variants • 400 MHz Introduced June 29, 1998 450 MHz (512 KiB L2 Cache) Introduced October 6, 1998

• • • • • • • • • • • • • • • • • • • •

450 MHz (1 MiB and 2 MiB L2 Cache) Introduced January 5, 1999 PIII Xeon • Introduced October 25, 1999 Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm) L2 cache is 256 KiB, 1 MiB, or 2 MiB Advanced Transfer Cache (Integrated) Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330 System Bus Speed 133 MHz (256 KiB L2 cache) or 100 MHz (1 - 2 MiB L2 cache) System Bus Width 64 bit Addressable memory 64 gibibytes Used in two-way servers and workstations (256 KiB L2) or 4- and 8-way servers (1 - 2 MiB L2) Family 6 model 10 Variants • 500 MHz (0.25 µm process) Introduced March 17, 1999 550 MHz (0.25 µm process) Introduced August 23, 1999 600 MHz (0.18 µm process, 256 KiB L2 cache) Introduced October 25, 1999 667 MHz (0.18 µm process, 256 KiB L2 cache) Introduced October 25, 1999 733 MHz (0.18 µm process, 256 KiB L2 cache) Introduced October 25, 1999 800 MHz (0.18 µm process, 256 KiB L2 cache) Introduced January 12, 2000 866 MHz (0.18 µm process, 256 KiB L2 cache) Introduced April 10, 2000 933 MHz (0.18 µm process, 256 KiB L2 cache) 1000 MHz (0.18 µm process, 256 KiB L2 cache) Introduced August 22, 2000 700 MHz (0.18 µm process, 1 - 2 MiB L2 cache) Introduced May 22, 2000

Celeron (Pentium III Coppermine-based)
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

Coppermine-128 - 0.18 µm process technology • Introduced March,2000 Streaming SIMD Extensions (SSE) Socket 370 PPGA processor package Number of transistors 28.1 million 66 MHz system bus speed, 100 MHz system bus speed on January 3, 2001 32 KiB L1 cache 128 KiB Advanced Transfer L2 cache Family 6 model 8 Variants • 533 MHz 566 MHz 600 MHz 633 MHz Introduced June 26, 2000 667 MHz Introduced June 26, 2000 700 MHz Introduced June 26, 2000 733 MHz Introduced November 13, 2000 766 MHz Introduced November 13, 2000 800 MHz 850 MHz Introduced April 9, 2001 900 MHz Introduced July 2, 2001 950 MHz Introduced August 31, 2001 1000 MHz Introduced August 31, 2001 1100 MHz Introduced August 31, 2001 1200 MHz Introduced October 2, 2001 1300 MHz Introduced January 3, 2002 550 MHz (Mobile) 600 MHz (Mobile) Introduced June 19, 2000 650 MHz (Mobile) Introduced June 19, 2000 700 MHz (Mobile) Introduced September 25, 2000 750 MHz (Mobile) Introduced March 19, 2001 800 MHz (Mobile)

• • • •

850 MHz (Mobile) Introduced July 2, 2001 600 MHz (LV Mobile) 500 MHz (ULV Mobile) Introduced January 30, 2001 600 MHz (ULV Mobile)

XScale (chronological entry)
• •

Introduced August 23, 2000 See main entry

Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)
• •

Introduced April 2000 – July 2002 See main entries

Celeron (Pentium III Tualatin-based)
• • • • • • • • •

Tualatin Celeron - 0.13 µm process technology • 32 KiB L1 cache 256 KiB Advanced Transfer L2 cache 100 MHz system bus speed Family 6 model 11 Variants • 1.0 GHz 1.1 GHz 1.2 GHz 1.3 GHz 1.4 GHz

Pentium M
• • • • • • • • • • • • • • • • • • • • • • •

Banias 0.13 µm process technology • Introduced March 2003 64 KiB L1 cache 1 MiB L2 cache (integrated) Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline Number of transistors 77 million Micro-FCPGA, Micro-FCBGA processor package Heart of the Intel mobile "Centrino" system 400 MHz Netburst-style system bus Family 6 model 9 Variants • 900 MHz (Ultra low voltage) 1.0 GHz (Ultra low voltage) 1.1 GHz (Low voltage) 1.2 GHz (Low voltage) 1.3 GHz 1.4 GHz 1.5 GHz 1.6 GHz 1.7 GHz Dothan 0.09 µm (90 nm) process technology • Introduced May 2004 2 MiB L2 cache Revised data prefetch unit 400 MHz Netburst-style system bus 21W TDP

• • • • • • • • • • • • • • • • • • • • • •

Variants
• 1.00 GHz (Pentium M 723) (Ultra low voltage, 5W TDP) 1.10 GHz (Pentium M 733) (Ultra low voltage, 5W TDP) 1.20 GHz (Pentium M 753) (Ultra low voltage, 5W TDP) 1.30 GHz (Pentium M 718) (Low voltage, 10W TDP) 1.40 GHz (Pentium M 738) (Low voltage, 10W TDP) 1.50 GHz (Pentium M 758) (Low voltage, 10W TDP) 1.60 GHz (Pentium M 778) (Low voltage, 10W TDP) 1.40 GHz (Pentium M 710) 1.50 GHz (Pentium M 715) 1.60 GHz (Pentium M 725) 1.70 GHz (Pentium M 735) 1.80 GHz (Pentium M 745) 2.00 GHz (Pentium M 755) 2.10 GHz (Pentium M 765) Dothan 533 0.09 µm (90 nm) process technology • Introduced Q1 2005 Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP Variants • 1.60 GHz (Pentium M 730) 1.73 GHz (Pentium M 740) 1.86 GHz (Pentium M 750) 2.00 GHz (Pentium M 760) 2.13 GHz (Pentium M 770) 2.26 GHz (Pentium M 780)

Celeron M
• • • • • • • • • • • • • • • • • • •

• • •

Banias-512 0.13 µm process technology • Introduced March 2003 64 KiB L1 cache 512 KiB L2 cache (integrated) SSE2 SIMD instructions No SpeedStep technology, is not part of the 'Centrino' package Family 6 model 9 Variants • 310 - 1.20 GHz 320 - 1.30 GHz 330 - 1.40 GHz 340 - 1.50 GHz Dothan-1024 90 nm process technology • 64 KiB L1 cache 1 MiB L2 cache (integrated) SSE2 SIMD instructions No SpeedStep technology, is not part of the 'Centrino' package Variants • 350 - 1.30 GHz 350J - 1.30 GHz, with Execute Disable bit 360 - 1.40 GHz 360J - 1.40 GHz, with Execute Disable bit 370 - 1.50 GHz, with Execute Disable bit • Family 6, Model 13, Stepping 8[1] • 380 - 1.60 GHz, with Execute Disable bit 390 - 1.70 GHz, with Execute Disable bit Yonah-1024 65 nm process technology • 64 KiB L1 cache 1 MiB L2 cache (integrated)

• • • • • • • • • • • • • •

SSE3 SIMD instructions, 533MHz front-side bus, execute-disable bit No SpeedStep technology, is not part of the 'Centrino' package Variants • 410 - 1.46 GHz 420 - 1.60 GHz, 423 - 1.06 GHz (ultra low voltage) 430 - 1.73 GHz 440 - 1.86 GHz 443 - 1.20 GHz (ultra low voltage) 450 - 2.00 GHz Merom-1024 65 nm process technology • 64 KiB L1 cache 1 MiB L2 cache (integrated) SSE3 SIMD instructions, 533MHz front-side bus, execute-disable bit, 64-bit No SpeedStep technology, is not part of the 'Centrino' package Variants • 520 - 1.60 GHz

Intel Core
• • • • • • • • • • • • • • •

Yonah 0.065 µm (65 nm) process technology • Introduced January 2006 667 MHz frontside bus 2 MiB (Shared on Duo) L2 cache SSE3 SIMD instructions Variants: • Intel Core Duo T2700 2.33 GHz Intel Core Duo T2600 2.16 GHz Intel Core Duo T2500 2.00 GHz Intel Core Duo T2400 1.83 GHz Intel Core Duo T2300 1.66 GHz Intel Core Duo T2050 1.60 GHz Pentium dual-core T2080 1.73 GHz - 1024 KiB L2-cache Pentium dual-core T2060 1.60 GHz - 1024 KiB L2-cache Intel Core Solo T1350 1.86 GHz Intel Core Solo T1300 1.66 GHz Intel Core Solo T1200 1.50 GHz [2]

Dual-Core Xeon LV
• • • • •

Sossaman 0.065 µm (65 nm) process technology • Introduced March 2006 Based on Yonah core, with SSE3 SIMD instructions 667 MHz frontside bus 2 MiB Shared L2 cache Variants • 2.0 GHz

32-bit processors: NetBurst microarchitecture Pentium 4
• • •

0.18 µm process technology (1.40 and 1.50 GHz) • Introduced November 20, 2000 L2 cache was 256 KiB Advanced Transfer Cache (Integrated) Processor Package Style was PGA423, PGA478

• • • • • • • • • • • • • • • • • • • • • • • •

System Bus Speed 400 MHz SSE2 SIMD Extensions Number of Transistors 42 million Used in desktops and entry-level workstations 0.18 µm process technology (1.7 GHz) • Introduced April 23, 2001 See the 1.4 and 1.5 chips for details 0.18 µm process technology (1.6 and 1.8 GHz) • Introduced July 2, 2001 See 1.4 and 1.5 chips for details Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode Power <1 watt in Battery Optimized Mode Used in full-size and then light mobile PCs 0.18 µm process technology Willamette (1.9 and 2.0 GHz) • Introduced August 27, 2001 See 1.4 and 1.5 chips for details Family 15 model 1 Pentium 4 (2 GHz, 2.20 GHz) • Introduced January 7, 2002 Pentium 4 (2.4 GHz) • Introduced April 2, 2002 0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6 GHz) • Improved branch prediction and other microcodes tweaks 512 KiB integrated L2 cache Number of transistors 55 million 400 MHz system bus. Family 15 model 2 0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz) • 533 MHz system bus. (3.06 includes Intel's hyper threading technology). 0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz) • 800 MHz system bus (all versions include Hyper Threading) 6500 to 10000 MIPS

Itanium (chronological entry)
• •

Introduced 2001 See main entry

Xeon
• • • • • • • •

Official designation now Xeon, i.e. not "Pentium 4 Xeon" Xeon 1.4, 1.5, 1.7 GHz • Introduced May 21, 2001 L2 cache was 256 KiB Advanced Transfer Cache (Integrated) Processor Package Style was Organic Lan Grid Array 603 (OLGA 603) System Bus Speed 400 MHz SSE2 SIMD Extensions Used in high-performance and mid-range dual processor enabled workstations Xeon 2.0 GHz and up to 3.6 GHz • Introduced September 25, 2001

Itanium 2 (chronological entry)
• •

Introduced July 2002 See main entry

Mobile Pentium 4-M
• • • • • • • • • •

0.13 µm process technology 55 million transistors cache L2 512 KiB BUS a 400 MHz Supports up to 1 GiB of DDR 266 MHz Memory Supports ACPI 2.0 and APM 1.2 System Power Management 1.3 V - 1.2 V (SpeedStep) Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W Sleep Power 5 W (1.2 V) Deeper Sleep Power = 2.9 W (1.0 V)
• 1.40 GHz - 23 April 2002 1.50 GHz - 23 April 2002 1.60 GHz - 4 March 2002 1.70 GHz - 4 March 2002 1.80 GHz - 23 April 2002 1.90 GHz - 24 June 2002 2.00 GHz - 24 June 2002 2.20 GHz - 16 September 2002 2.40 GHz - 14 January 2003 2.40 GHz - 14 January 2003 2.50 GHz - 16 April 2003 2.60 GHz - 11 June 2003

• • • • • • • • • • •

Pentium 4 EE
• • •

Introduced September 2003 EE = "Extreme Edition" Built from the Xeon's "Gallatin" core, but with 2MiB cache

Pentium 4E
• • • • • • • • • • •

Introduced February 2004 built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MiB L2 cache 533 MHz system bus (2.4A and 2.8A only) Number of Transistors 125 million on 1 MiB Models Number of Transistors 169 million on 2 MiB Models 800 MHz system bus (all other models) Hyper-Threading support is only available on CPUs using the 800 MHz system bus. The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater clock speeds. 7500 to 11000 MIPS LGA-775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64) The 6xx series has 2 MiB L2 cache and Intel 64

Pentium 4F
• • • •

Introduced Spring 2004 same core as 4E, "Prescott" 3.2–3.6 GHz starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated

64-bit processors: IA-64
• •

New instruction set, not at all related to x86. Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but

slowly.

Itanium
• •

Released May 29, 2001 733 MHz and 800 MHz

Itanium 2
• •

Released July 2002 900 MHz and 1 GHz

Pentium M (chronological entry)
• •

Introduced March 2003 See main entry

Pentium 4EE, 4E (chronological entries)
• •

Introduced September 2003, February 2004, respectively See main entries

64-bit processors: Intel64 - NetBurst
• • •

Intel® Extended Memory 64 Technology Mostly compatible with AMD's AMD64 architecture Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)

Pentium 4F, D0 and later steppings

Starting with the D0 stepping of this processor, x86-64 extensions are supported

Pentium D
Main article: List of Intel Pentium D microprocessors
• • • • • • • • • • • • • •

Dual-core microprocessor No Hyper-Threading 800(4x200) MHz front side bus Smithfield - 90 nm process technology (2.8–3.4 GHz) • Introduced May 26, 2005 2.8–3.4 GHz (model numbers 820-840) Number of Transistors 230 million 1 MiB x 2 (non-shared, 2 MiB total) L2 cache Cache coherency between cores requires communication over the FSB Performance increase of 60% over similarly clocked Prescott 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005 Presler - 65 nm process technology (2.8–3.6 GHz) • Introduced January 16, 2006 2.8–3.6 GHz (model numbers 920-960) Number of Transistors 376 million 2 MiB x 2 (non-shared, 4 MiB total) L2 cache

Pentium Extreme Edition

Dual-core microprocessor

• • •

Enabled Hyper-Threading 1066(4x266) MHz front side bus Smithfield - 90 nm process technology (3.2 GHz) • Variants • Pentium 840 EE - 3.20 GHz (2 x 1 MiB L2) Presler - 65 nm process technology (3.46, 3.73) • 2 MiB x 2 (non-shared, 4 MiB total) L2 cache Variants • Pentium 955 EE - 3.46 GHz Pentium 965 EE - 3.73 GHz

• • •

Xeon

Nocona • Introduced 2004 Irwindale • Introduced 2004 Cranford • Introduced April 2005 MP version of Nocona Potomac • Introduced April 2005 Cranford with 8 MiB of L3 cache Paxville DP (2.8 GHz) • Introduced October 10, 2005 Dual-core version of Irwindale, with 4 MiB of L2 Cache (2 MiB per core) 2.8 GHz 800 MT/s front side bus Paxville MP - 90 nm process (2.67 - 3.0 GHz) • Introduced November 1, 2005 Dual-Core Xeon 7000 series MP-capable version of Paxville DP 2 MiB of L2 Cache (1 MiB per core) or 4 MiB of L2 (2 MiB per core) 667 MT/s FSB or 800 MT/s FSB Dempsey - 65 nm process (2.67 - 3.73 GHz) • Introduced May 23, 2006 Dual-Core Xeon 5000 series MP version of Presler 667 MT/s or 1066 MT/s FSB 4 MiB of L2 Cache (2 MiB per core) Socket J, also known as LGA 771. Tulsa - 65 nm process (2.5 - 3.4 GHz) • Introduced August 29, 2006 Dual-Core Xeon 7100-series Improved version of Paxville MP 667 MT/s or 800 MT/s FSB

• • • • • • • • • • • • • • • • • • • • • • •

64-bit processors: Intel64 - Intel Core microarchitecture (P6E Based) Xeon

Woodcrest - 65 nm process technology

• • • • • • • • • • • • • • •

Server and Workstation CPU (SMP support for dual CPU system) Introduced June 26, 2006 Dual-Core Intel Virtualization Technology, multiple OS support EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160 Execute Disable Bit LaGrande Technology, enhanced security hardware extensions SSSE3 SIMD instructions iAMT2 (Intel Active Management Technology), remotely manage computers Variants • Xeon 5160 - 3.00 GHz (4 MiB L2, 1333 MHz FSB, 80 W) Xeon 5150 - 2.66 GHz (4 MiB L2, 1333 MHz FSB, 65 W) Xeon 5140 - 2.33 GHz (4 MiB L2, 1333 MHz FSB, 65 W) Xeon 5130 - 2.00 GHz (4 MiB L2, 1333 MHz FSB, 65 W) Xeon 5120 - 1.86 GHz (4 MiB L2, 1066 MHz FSB, 65 W) Xeon 5110 - 1.60 GHz (4 MiB L2, 1066 MHz FSB, 65 W) Xeon 5148LV - 2.33 GHz (4 MiB L2, 1333 MHz FSB, 40 W) -- Low Voltage Edition

• • • • • • • • • • • • • • •

Clovertown - 65 nm process technology • Server and Workstation CPU (SMP support for dual CPU system) Introduced Dec 13th 2006 Quad-Core Intel Virtualization Technology, multiple OS support EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160 Execute Disable Bit LaGrande Technology, enhanced security hardware extensions SSSE3 SIMD instructions iAMT2 (Intel Active Management Technology), remotely manage computers Variants • Xeon X5355 - 2.66 GHz (2x4 MiB L2, 1333 MHz FSB, 105 W) Xeon E5345 - 2.33 GHz (2x4 MiB L2, 1333 MHz FSB, 80 W) Xeon E5335 - 2.00 GHz (2x4 MiB L2, 1333 MHz FSB, 80 W) Xeon E5320 - 1.86 GHz (2x4 MiB L2, 1066 MHz FSB, 65 W) Xeon E5310 - 1.60 GHz (2x4 MiB L2, 1066 MHz FSB, 65 W) Xeon L5320 - 1.86 GHz (2x4 MiB L2, 1066 MHz FSB, 40 W)-- Low Voltage Edition

Intel Core 2
• • • • • • • • • • • • • • • •

Conroe - 65 nm process technology • Desktop CPU (SMP support restricted to 2 CPUs) Two CPUs in one package Introduced July 27, 2006 SSSE3 SIMD instructions Number of Transistors 291 Million on 4 MiB Models Number of Transistors 167 Million on 2 MiB Models Intel Virtualization Technology, multiple OS support LaGrande Technology, enhanced security hardware extensions Execute Disable Bit EIST (Enhanced Intel SpeedStep Technology) iAMT2 (Intel Active Management Technology), remotely manage computers LGA775 Variants • Core 2 Duo E6850 - 3.00 Ghz (4 MiB L2, 1333 MHz FSB) Core 2 Duo E6800 - 2.93 Ghz (4 MiB L2, 1066 MHz FSB) Core 2 Duo E6750 - 2.67 GHz (4 MiB L2, 1333 MHz FSB) Core 2 Duo E6700 - 2.67 GHz (4 MiB L2, 1066 MHz FSB)

• • • • • • • •

Core 2 Duo E6650 - 2.33 GHz (4 MiB L2, 1333 MHz FSB) Core 2 Duo E6600 - 2.40 GHz (4 MiB L2, 1066 MHz FSB) Core 2 Duo E6420 - 2.13 GHz (4 MiB L2, 1066 MHz FSB) Core 2 Duo E6400 - 2.13 GHz (2 MiB L2, 1066 MHz FSB) Core 2 Duo E6320 - 1.86 GHz (4 MiB L2, 1066 MHz FSB) Core 2 Duo E6300 - 1.86 GHz (2 MiB L2, 1066 MHz FSB) Core 2 Duo E4400 - 2.0 GHz (2 MiB L2, 800 MHz FSB) Core 2 Duo E4300 - 1.80 GHz (2 MiB L2, 800 MHz FSB) Conroe XE - 65 nm process technology • Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs) Introduced July 27, 2006 same features as Conroe LGA775 Variants • Core 2 Extreme X6800 - 2.93 GHz (4 MiB L2, 1066 MHz FSB) Merom - 65 nm process technology • Mobile CPU (SMP support restricted to 2 CPUs) Introduced July 27, 2006 same features as Conroe Socket M Variants • Core 2 Duo T7700 - 2.40 GHz (4 MiB L2, 800 MHz FSB) (Santa Rosa platform) Core 2 Duo L7400 - 1.50 GHz (4 MiB L2, 667 MHz FSB) (Low Voltage) Core 2 Duo L7200 - 1.33 GHz (4 MiB L2, 667 MHz FSB) (Low Voltage) Core 2 Duo T7600 - 2.33 GHz (4 MiB L2, 667 MHz FSB) Core 2 Duo T7400 - 2.16 GHz (4 MiB L2, 667 MHz FSB) Core 2 Duo T7200 - 2.00 GHz (4 MiB L2, 667 MHz FSB) Core 2 Duo T5600 - 1.83 GHz (2 MiB L2, 667 MHz FSB) Core 2 Duo T5500 - 1.66 GHz (2 MiB L2, 667 MHz FSB) Core 2 Duo T5200 - 1.60 GHz (2 MiB L2, 533 MHz FSB) Kentsfield - 65 nm process technology • Desktop CPU Quad Core (SMP support restricted to 4 CPUs) Introduced December 13, 2006 same features as Conroe but with 4 CPU Cores Socket 775 Variants • Core 2 Extreme QX6800 - 2.93 GHz (2x4 MiB L2, 1066 MHz FSB) (Apr 9th 07) Core 2 Extreme QX6700 - 2.66 GHz (2x4 MiB L2, 1066 MHz FSB) (Nov 14th 06) Core 2 Quad Q6600 - 2.40 GHz (2x4 MiB L2, 1066 MHz FSB) (Jan 7th 07)

• • • • •

• • • • • • • • • • • • •

• • • • • • •

Intel 805xx product codes
Intel discontinued the use of part numbers such as 80486 in the marketing of mainstream x86-architecture microprocessors with the introduction of the Pentium brand in 1993. However, numerical codes, in the 805xx range, continued to be assigned to these processors for internal and part numbering uses. The following is a list of such product codes in numerical order: Product code 80500 80501 Pentium Pentium Marketing name(s) P5 (A-step) P5 Codename(s)

80502 80503 80521 80522 80523 80524 80525 80526 80528 80530 80531 80532 80535 80536 80537 80538 80539 80541 80546 80547 80550 80551 80552 80553 80555 80556 80557 80560 80562 80563

Pentium Pentium MMX Pentium Pro Pentium II Pentium II, Celeron, Pentium II Xeon Pentium II, Celeron Pentium III, Pentium III Xeon Pentium III, Celeron, Pentium III Xeon Pentium 4, Xeon Pentium III, Celeron Pentium 4, Celeron Pentium 4, Celeron, Xeon Pentium M, Celeron M Pentium M, Celeron M Core 2 Duo T-series Core Solo, Celeron M 4xx Core Duo Itanium Pentium 4, Celeron D, Xeon Pentium 4, Celeron D Dual-Core Xeon 71xx Pentium D, Pentium EE, Dual-Core Xeon Pentium 4, Celeron D Pentium D, Pentium EE Dual-Core Xeon 50xx Dual-Core Xeon 51xx Core 2 Duo E-series, Dual-Core Xeon 30xx Dual-Core Xeon 70xx Core 2 Quad, Core 2 Extreme QX-series, Quad-Core Xeon 32xx Quad-Core Xeon 53xx

P54C, P54CS P55C, Tillamook P6 Klamath Deschutes, Covington, Drake Dixon, Mendocino Katmai, Tanner Coppermine, Cascades Willamette (Socket 423), Foster Tualatin Willamette (Socket 478) Northwood, Prestonia, Gallatin Banias Dothan Merom Yonah Yonah Merced

Prescott (Socket 478), Nocona, Irwindale, C Potomac Prescott (LGA775) Tulsa Smithfield, Paxville DP Cedar Mill Presler Dempsey Woodcrest Conroe Paxville MP Kentsfield Clovertown

Core Palomino

Model Name Clock Speed Athlon XP 1800+ 1533 Mhz (133*11.5)

Year

Fabrication process FSB Speed Supported Max Memory Speed, (nm) (Range) Bus (Range) 266 333 266 333 400 400 400 DDR266 DDR400 DDR266 DDR333 DDR400 DDR400 DDR400

2001 180 133

Thoroughbred Athlon A Palomino Barton Barton Barton Barton AthlonXP 2000+ AthlonXP 3000+ AthlonXP 3000+ AthlonXP 3200+ AthlonXP 3400+ 1662Mhz (133*12.5) 2158Mhz (166*13) 2000Mhz (200*10) 2200Mhz (200*11) 2400Mhz (200*12)

130 2003 130 130 130 130

Tabela 2: Comparação de Processadores AMD - Athlon XP

Core Sledgehammer

Model Name Opteron 125

Clock Speed 1800

Year

Fabrication process FSB Speed Supported Max Memory Speed, **(nm) (Range) Bus (Range) 800 DDR400

L1 C (I+D

2003 130

64K+

Tabela 3: Comparação de Processadores AMD - Opteron

Core

Model Name

Clock Speed 1800 2000 2200 2200 2.2Ghz 2.4Ghz

Year

Fabrication process FSB Speed Supported Max Memory Speed, (nm) (Range) Bus (Range) 800 800 800 800 800 800 DDR400 DDR400 DDR400 DDR400 DDR400 DDR400

L1 C (I+D

ClawHamme Athlon 64 r 2800+ ClawHamme Athlon 64 r 3000+ ClawHamme Athlon 64 r 3200+ ClawHamme Athlon 64 r 3400+ ClawHamme Athlon 64 r 3500+ ClawHamme Athlon 64 r 3700+

2003 130 2003 130 2003 130 2003 130 2003 130 2003 130

64K+

64K+

64K+

64K+

64K+

64K+

Tabela 4: Comparação de Processadores AMD - Athlon 64 Core Sledgehammer Sledgehammer Sledgehammer Sledgehammer Sledgehammer Windsor Model Name Athlon 64 FX-51 Athlon 64 FX-53 Athlon 64 FX-55 Athlon 64 FX-57 Athlon 64 FX-60 Athlon 64 FX-62 Clock Speed 2200 2400 2600 2800 2600 2800 Year Fabrication process (nm) FSB Speed Supported Max Memory Speed, (Range) Bus (Range) 800 1000 1000 1000 1000 1000 DDR400 DDR400 DDR400 DDR400 DDR400 DDR400

L1 Cac (I+D)

2002 130 2003 90 2004 90 2005 90 2005 90 2006 90

64K+64

64K+64

64K+64

64K+64

64K+64

64K+64

Tabela 5: Comparação de Processadores AMD - Athlon 64 FX

Core

Model Name

Clock Speed

Year

Fabrication process (nm) 90 90 90

FSB Speed Supported Max Memory Speed, (Range) Bus (Range) 1000 1000 1000 DDR400 DDR400 DDR400

L1 Ca (I+D)

ClawHamme Athlon 64 X2 2000 r 3600+ ClawHamme Athlon 64 X2 2000 r 3800+ Manchester Athlon 64 X2 2200 4200+

64K+

64K+

64K+

Tabela 6: Comparação de Processadores AMD - Athlon 64 X2

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